CML Semiconductor Products
AN/Telecom/868/REF/ 1 December 2000
Programmers' Quick Reference to the CMX868
With modern fabrication techniques it is becoming increasing common to see more peripheral circuits added to the
basic functionality of integrated circuits. This trend toward increasingly complex devices is good for the user in that it
simplifies the overall design, reduces external hardware and lowers cost whilst giving increased flexibility. The trade-off
is that the device becomes more difficult to understand and manage as previously separate functions become inter-
related and inter-dependent.
The CMX868 is a good example of such complexity. As a V.22 modem with a C-Bus interface the device is fairly
simple to use despite the rigours of trying to manage full duplex data transmission over a media intended for medium-
quality analogue voice. The CMX868 integrates Ring Detection, Tone Generation and Tone Detection but extends this
functionality by permitting the Tone Detectors, a complex filtering system in itself, to be programmable. Add to this the
different powersave modes allowing a complex powersave strategy; the generation and detection of dual tones
permitting encoding and decoding of DTMF and Global Call Progress Tones; makes the CMX868 a powerful peripheral
for PSTN modem products.
To use this rich functionality, the programmer must understand the registers that control each function block and the
effects on other function blocks. This quick reference is intended to ‘pull’ as much information on each register into a
single page and cross-reference the content as much as possible.
It is recommended that this quick reference be used in conjunction with the Data Sheet where the names of registers
and function block used will provide cross-referencing. A short description of the layout follows.
Each register description starts and ends on the same page.
General information about the register is given in a paragraph at the beginning of the description.
The register bit layout is given in the left hand margin and a description of those bits is given to the right. The bit
descriptions are tabulated and aligned, as closely as possible, with the bit layout.
Some bits have a function that is mode dependent. This is shown by splitting the bit layout and then splitting the bit
description in a similar manner. Thus, the left hand table of the bit layout will be described in the left hand table of the
bit description.
Some table entries are expanded. These are shown given ‘3D’ view with two lines showing the origin of the expansion.
Status register bits affected, where appropriate, are shown in an isolated table on the same page.
Register bits, other than those being described, have the format:
<Register Name> <Register location in Hex> <bit(s)>
The register location may be omitted.
Key
SR Status Register
bBit (bits are subscripted 0 through 15. E.g. b1 b2 b3)
b10 .. 8 Bits 10, 9 and 8
mask IRQ Mask Bit in the General Control Register. E.g. mask 1, mask 2, mask 3
mask 1 IRQ Mask Bit 1.
IRQN Interrupt pin on the CMX868
General Reset $01 Clears all bits of the General Control, Transmit Mode and
Receive Mode Registers. Clears b15 and b13..0 of the Status Register.
The device will be in powersave following General Reset.
General Control $E0 All bits cleared to 0 following a General Reset $01
000Xtal
Frequency LB Equ Rly
Drv Pwr Rst Irqn
En IRQ Mask Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX Modem Modes Rx Tones Detect Modes
Rx Data Overflow (SR b5)
Rx Data Ready (SR b6) 1st Programmable tone detected (SR b6)
2225 Hz Detect Mask (SR b6)
DTMF Detect Mask (SR b5)
See Table to right
Rx Data Ready (SR b6)
2nd Programmable Tone Detected (SR b6)
2100 Hz Detected (SR b7)S1 (DPSK, QAM) Detected (SR b9)
1010..(FSK) Detected (SR b9)
In Band Energy Detected
(SR b10)
In Band Energy Detected (SR b10)
Both Programmable Tones Detected
(SR b10)
Tx Data Underflow (SR b11)
Tx Data Ready (SR b12)
Programme Register Contents Written (SR b13)
Ring Detected (SR b14)
IRQNEN Enable IRQN Output. IrqnEn = 1: IRQN Output = 0 if IRQ (SR bit 15) = 1
IrqnEn = 0: IRQN Output = Tristate
Reset Rst = 1: Internal Circuits Reset. Transmit and Receive Mode Registers,
SR b15 and b13..0 Cleared
Rst = 0: Normal Operation
Powerup Pwr = 1: Switch from Powersave to Normal Operation. Transmit and
Receive Mode Registers, SR b15 and b13..0 Cleared. Follow with Reset =1
Pwr = 0: Powersave Mode. All circuits except Ring Detect, RDRVN, and
C-Bus Disabled
Relay Drive RlyDrv = 1: RDRVN output pulled to Vss
RlyDrv = 0: RDRVN output pulled to Vdd
Tx and Rx Fixed Compromise Equalisers Equ = 1: Equalisers Disabled
Equ = 0: Equalisers Enabled (600, 1200
and 2400 bps modem modes)
Analogue Loopback Test Mode LB = 1: Local Analogue Loopback. Make Transmit
and Receive Mode Registers to the same type, band
and bit rate
LB = 0: No Loopback
XTAL Frequency XtalFreq = 1: 11.0592MHz
XtalFreq = 0: 12.2880MHz
IRQ Mask Bit 1. RX Modem
Mode only
Descrambler
Disabled Descrambler Enabled
(DPSK, QAM)
Unscrambled 1s
Detected
(SR b7)
Unscrambled 0s
Detected
(SR b8)
Unscrambled 1s
Detected (SR b7)
Scrambled 0s Detected
(SR b8)
Scrambled 1s Detected
(SR b8, b7)
b3..0 = tone or tone pair to transmit
Status Register bits affected
on Transmit
Tx Data Source (QAM, DPSK, FSK)
Synchronous Modes
b4..3 = 1
Tx Data and Stop Bits (QAM, DPSK, FSK)
Stop-Start Modes
For Parity and Mode setting see table 'Tx Data Format' below
b2..0 Tx Data Source
Stop BitsTx Data
b2..b0
Stop Bits
b2..0 Tx Data
SR b11, mask b3 = Tx Data
Underflow
b11..9 Tx Level
b4..3
1XXData Bytes from Tx Data Buffer $E3 or $E4
2
1
2
1
8
8
7
7
1
1
1
1
2
1
2
1
Transmit Mode $E1 All bits cleared to zero following General Reset $01, or
General Control Register $E0 Reset (b7) = 1 or General Control Register $E0
Powerup (b8) = 0 (Powersave Mode).
1
Tx Data and Stop Bits
Tx Data Source
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Tx data FormatTx Guard Tone
Tx LevelTx Mode 0
Tx Scrambler Mode
000 DTMF / Tones (See DTMF / Tones Mode table at bottom right)
011V.22 600bps DPSK High Band
1010V.22 600bps DPSK Low Band
1001V.21 300bps FSK High Band
0000V.21 300bps FSK Low Band
0111Bell 103 300bps FSK High Band
0110Bell 103 300bps FSK Low Band
0101V.23 FSK 1200bps
0100V.23 FSK 75bps
0011Bell 202 FSK 1200bps
0010Bell 202 FSK 150bps
0001DTMF / Tones Mode see table to right
0000Transmitter Disabled
1111V.22 Bis 2400bps QAM High Band
1110V.22 Bis 2400bps QAM Low Band
1101V.22 / Bell 212A 1200bps DPSK High Band
1100V.22 / Bell 212A 1200bps DPSK Low Band
b15..12 Tx Mode
1110dB
110-1.5dB
101-3.0dB
100-4.5dB
011-6.0dB
010-7.5dB
001-9dB
000-10.5dB
1 0
0X
b8..7 Tx Guard Tone (QAM, DPSK)
1 1
Tx 1800Hz Guard Tone
No Tx Guard Tone
Tx 550Hz Guard Tone
1 0
0X
b6..5 Tx Scrambler Mode (QAM, DPSK)
1 1
Scrambler Enabled. Scrambler Unlock Disabled
Scrambler Disabled
Scrambler Enabled. Scrambler Unlock Enabled
1 1
1 0
0 1
0 0
0 1 1 6
0 1 0 6
0 0 1 5
0 0 0 5
1 1 Synchronous Mode
1 0 Start-Stop Mode. No Parity
0 1 Start-Stop Mode. Even Parity
0 0 Start--Stop Mode. Odd Parity
Tx Data Format (QAM, DPSK, FSK)
011Continuous 1s
010Continuous 0s
00XContinuous S1 (QAM, DPSK) or 1010.. in all
other modes
Tx Level
b11..b9
DTMF / Tones Mode
b4 = 0: Tx Fixed Tone or
Programmed Tone Pair
b4 = 1: Tx DTMF
b8..5 = 0000
b15..12 = 0001
SR b15 = IRQ
SR b12, mask b3 = Tx Data
Ready
b11..9
Status Register bits affected on Receive
1 1 1
Rx Data Bits and Parity. Start-Stop Modes (QAM, DPSK,
FSK) only.
Bits 2..0 ignored in synchronous mode.
See b5..4 in Rx USART Settings table below for stop bits.
Parity check (SR 3, no int) = 0: Odd Parity Ok
1: Even Parity Ok
Framing check (SR b4, no int) = 1 on error Parity
Tx Data
b2..0Parity
Tx Data
b2..0
DTMF bit 3
SR b3, no int = 0: Odd Parity
Even Parity
DTMF bit 2
SR b2, no int = Signal Quality b2
DTMF bit 1
SR b1, no int = Signal Quality b1
DTMF bit 0
SR b0, no int = Signal Quality b0
0
Rx Synchronous Mode
Not Valid. Do Not Select
Not Valid. Do Not Select
Not Valid. Do Not Select
Programmable Tone Pair Detect Mode (SR b6
/ b7 / b10, mask b0 / b1 / b2) See table above
Call Progress Tone Detect Mode (SR b10,
mask b2)
2100Hz (SR b7, mask b1) or 2225Hz (SR b6,
mask b0) Answer Tone Detect Mode
DTMF Detect Mode (SR b5, mask b0)
Disabled
Rx Data Format
11
1
1
1
1
0
0
1
01
b2..0
0
0
0
0
0
Rx Data Bits and Parity
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Rx USART SettingRx Scrambler
Rx LevelRx Mode Tones Detect Mode
Receive Mode $E2 All bits cleared to zero following General Reset $01, or
General Control Register $E0 Reset (b7) = 1 or General Control Register
$E0 Powerup (b8) = 0 (Powersave Mode).
Rx Auto
Equalise
00000
b11..9 Rx Level
b5..3
Yes
No
Yes
No
8
8
7
7
1
1
1
1
Yes
No
Yes
No
1011V.22 600bps DPSK High Band
1010V.22 600bps DPSK Low Band
1001V.21 300bps FSK High Band
0000V.21 300bps FSK Low Band
0111Bell 103 300bps FSK High Band
0110Bell 103 300bps FSK Low Band
0101V.23 FSK 1200bps
0100V.23 FSK 75bps
0011Bell 202 FSK 1200bps
0010Bell 202 FSK 150bps
0001DTMF / Tones Detect see table at right
0000Receiver Disabled
1111V.22 Bis 2400bps QAM High Band
1110V.22 Bis 2400bps QAM Low Band
1101V.22 / Bell 212A 1200bps DPSK High Band
1100V.22 / Bell 212A 1200bps DPSK Low Band
b15..12 Rx Mode
1110dB
110-1.5dB
101-3.0dB
100-4.5dB
011-6.0dB
010-7.5dB
001-9dB
000-10.5dB
1
0
b8 Rx Auto Equalise (QAM, DPSK)
Enabled
QAM: Freeze Settings DPSK: Disabled
1 0
0X
b7..6 Rx Descrambler Mode (QAM, DPSK)
1 1
Descrambler Enabled. Descrambler Unlock Disabled
Descrambler Disabled
Descrambler Enabled. Descrambler Unlock Enabled
1 1
1 0
0 1
0 0
0 1 1 6
0 1 0 6
0 0 1 5
0 0 0 5
1 1 Rx Start-stop Mode. No Overspeed
1 0 Rx Start-stop Mode. +1% Overspeed
1 0 Rx Start-stop Mode. +2.3% Overspeed
0XRx USART Disabled
Rx USART Settings (QAM, DPSK, FSK)
Rx Level
DTMF / Tones Detect Mode
b8..3 = 000000
b15..12 = 0001
1
1
0
0
1
0
1
0
0
1
0
X
0
SR b15 = IRQ
Rx Modem Modes DTMF/Tone Detect Modes
In-Band Energy or both
programmable tones
detected In-Band Energy Detected
SR b10, mask b2
SR b9, mask b1 = S1 (QAM, DPSK) or 1010... pattern (FSK)
detected SR b8..7, mask b1
- -
Continuous Unscrambled 1s Continuous Unscrambled 1s
Continuous Unscrambled 0s Continuous Scrambled 0s
Continuous Scrambled 1s
0 0
0 1
1 0
1 1
Descrambler Disabled Descrambler Enabled
(DPSK/QAM)
b8..7
SR b6, mask b0
Rx Modem Modes DTMF/Tone Detect Modes
Rx Data Ready 2225Hz Detected or
1st Programmable Tone Det
SR b5, mask b0
Rx Data Overflow DTMF Detected
SR b4, no int = Rx Framing Error
Tones Detect Mode
See table at bottom of pag e
b7 b6
76543210
b5 b4 b3 b2 b1 b0
Rx Data $E5 Indeterminate following power-on, powerup and reset
Start-Stop and Synchronous Modes (Receive Mode Register $E2, b15..12 and b5..0)
The receive register is double buffered. b0 is the first received bit.
Data is read when Rx Data Ready flag is set (SR b6, mask b0) and the flag will be cleared when
a read of the Status Register $E6 occurs.
A receive overflow is indicated when the Rx overflow flag is set (SR b5, mask b0) and the flag
will be cleared when a read of the Rx Data Register $E5 occurs.
Stop-Start Mode only (Receive Mode Register $E2, b15..12 and b5..0)
The required number of bits, Rx Mode Register $E2 b2..0 are loaded into the Rx Data Register $E5
up to the MSB of the data. The remaining (upper) bits of the Rx Data Register should be ignored.
Start bit automatically detected and deleted.
The parity bit will be automatically detected and deleted. The Status Register Parity bit will be
updated b3 = 1(Even Parity) or 0 (Odd Parity). There is no Rx Parity setting.
Stop bits will be detected and deleted automatically. Receive Mode Register $E1, b5..3. A missing
stop bit (no V.14) will flag a framing error (SR b4) but data will still be available.
V14 mode selection Rx Mode Register $E2 b5..3 automatically checks stop bits. Missing bits
beyond those permitted will flag a framing error (SR b4) but data will still be available.'
Break' signals, all zeroes including the parity and stop bits, will flag a framing error (SR b4) and the
modem will re-sync on the next 1->0 transition.
Synchronous Mode only (Transmit Mode Register $E2, b15..12 and b5..3)
b0 transmitted first. All eight bits will be transmitted.
S1 pattern (DPSK or QAM) and 1010.. pattern (FSK) indicated by SR b9, mask b1.
Continuous 0s or continuous 1s are indicated by SR b8..7, mask b1.
See General Control Register $E0 for loopback modes, equalisation, hook switch (relay drive) IRQ
pin enable and interrupt mask bits.
See Rx Mode Register $E2 for Rx mode, level, auto-equlise, scrambler, data format (data bits, parity
and stop bits) + V.14 protocol, tones and DTMF.
See Status Register $E6 for Interrupt flag, Tx buffer empty flag, Tx underflow flag and interrupt mask
bits.
b7 b6
7 6 5 4 3 2 1 0
b5 b4 b3 b2 b1 b0
Tx Data $E3 ($E4)Indeterminate following power-on, powerup and reset. $E3 normally used. $E4 is for V.14
The transmit register is double buffered.
Data is loaded when Tx Data Ready flag is set SR b12, mask b3 and the flag will be cleared
when a write to Tx Data register $E3 or $E4 occurs.
A transmit underflow is indicated when the Tx Underflow flag is set SR b11, mask b3 and
cleared by a write to the Tx Data $E3 or $E4.
Start-Stop and Synchronous Modes (Transmit Mode Register $E1, b15..12 and b3..4)
Stop-Start Mode only (Transmit Mode Register $E1, b15..12 and b3..4)
Synchronous Mode only (Transmit Mode Register $E1, b15..12 and b3..4)
Bit b0 transmitted first. If the number of bits in the frame are less than 8 then bits above the MSB will
be ignored. Number of Data bits: Transmit Mode Register $E, b2..0
Start bit automatically added.
A parity bit will be added automatically. Transmit Mode Register $E1, b3..4.
Stop bits will be added automatically. Transmit Mode Register $E1, b2..0.
If a transmit underflow occurs then a continuous Stop (1) is transmitted.
b0 transmitted first. All eight bits will be transmitted.
If a transmit underflow occurs then Tx Data will be re-transmitted.
S1 pattern, 1010.. pattern, continuous 0s or continuous 1s can be transmitted in this mode Tx
Mode register $E1 b2..0
Tx Data $E4 used for V14. Data should be normally written to $E3.
QAM and DPSK start-stop modes. A write to $E4 will cause one less stop bit to be transmitted.
FSK start-stop modes. The period of the stop bit at the end of the character is reduced by 12.5%.
Stop bit insertion occurrs automatically. see start-stop mode above.
If synchronous mode is selected then data written to $E4 will be treated as if written to $E3.
See General Control Register $E0 for loopback modes, equalisation, hook switch (relay drive) IRQ
pin enable and interrupt mask bits.
See Tx Mode Register $E1 for Tx mode, level, guard tones, scrambler, data format (data bits, parity
and stop bits), pattern sending, tones and DTMF.
See Status Register $E6 for Interrupt flag, Tx buffer empty flag, Tx underflow flag and interrupt mask
bits.
2225Hz or first
Programmable
Tone Detected
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRQ Programming
flag Tx Data
Ready
Rx Energy
Detect
S1, 1010..
Pattern
Detected
Scrambled or unscrambled
0s or 1s Rx Data
Ready Rx Data
Overflow
Ring Detect
Rx Framing
Error Rx Parity Rx Signal
Quality b2
Rx
Signal
Quality
b1
Rx Signal
Quality b0 or
FSKdemod
Output
Call Progress
or both
Programmabed
Tones Detected 0DTMF
Detected 0DTMF b3 DTMF b2 DTMF b1 DTMF b0
Rx Signal Quality bit b0 (QAM, DPSK - Rx Mode $E2
b15..12) or Output of FSK demodulator (FSK - Rx
Mode $E2 b15..12) This bit is updated at 8 times the
nominal data rate.
No Mask. Does not assert IRQN.
Rx Modem modes Rx Tones Detect modes
Received DTMF b0. Rx Mode $E2 b15..12
No Mask. Does not assert IRQN.
Received DTMF b1. Rx Mode $E2 b15..12
No Mask. Does not assert IRQN.
Received DTMF b2. Rx Mode $E2 b15..12
No Mask. Does not assert IRQN.
Received DTMF b3. Rx Mode $E2 b15..12
No Mask. Does not assert IRQN.
Rx Signal Quality bit b1 QAM DPSK
No Mask. Does not assert IRQN.
Rx Signal Quality bit b2 QAM DPSK
No Mask. Does not assert IRQN.
Rx Parity Check: 0 = Odd Parity Ok
1 = Even Parity Ok (Rx Mode $E2 b2..0)
No Mask. Does not assert IRQN.
Rx Framing Error (Rx Mode $E2 b15..12, b5..0)
No Mask. Does not assert IRQN. 0
DTMF code detected
Mask bo (General Control $E0). Asserts IRQN.
2225Hz Answer tone detected (Rx Mode $E2
b15..12) or 1st Programmable Tone detected (Rx
Mode $E2 b15..12 and Programming Register $E8)
Mask bo (General Control $E0). Asserts IRQN.
Rx Data Overflow
Cleared on reading Rx Data $E5
Mask b0 (General Control $E0). Asserts IRQN.
Rx Data Ready
Cleared on reading Rx Data Register $E5
Mask b0 (General Control $E0). Asserts IRQN.
b7
2100Hz Answer tone detected (Rx Mode $E2 b15..12)
or 2nd Programmable Tone Detected (Rx Mode $E2
b15..12 and Programming Register $E8)
Mask b1 (General Control $E0)
0
0
S1 detected QAM or DPSK mode or
1010... detected FSK mode (Rx Mode $E2 b15..12)
Mask b1 (General Control $E0). Asserts IRQN.
Rx Energy Detected in Modem Signal Band
Mask bit b2 (General Control $E0). Asserts IRQN. Rx Energy Detected in Call Progress Signal Band or
1st and 2nd Programmable Tones Detected (Rx
Mode $E2 b15..12 and Programming Register $E8)
Mask bit b2 (General Control $E0). Asserts IRQN.
Tx Data Underflow - Start-Stop Mode. If a transmit underflow occurs then a continuous Stop (1) is
transmitted.
Synchronous Mode. If a transmit underflow occurs then Tx Data will be re-transmitted.
(Tx Mode $E1 b15..12, b4..3)
Mask bit b3 (General Control $E0). Asserts IRQN.
Tx Data Ready - Set to 1 when the Tx Data $E3 or $E4 is ready to receive a new byte for transmission.
Cleared by a write to Tx Data $E3 or $E4.
Mask bit b3 (General Control $E0). Asserts IRQN.
Set when the Programming action is completed.
Cleared by a write to the Programming register $E8.
Mask bit b4 (General Control $E0). Asserts IRQN.
Set when the voltage at RD exceeds the threshold level.
Cleared by a read of Status register $E6.
Mask bit b5 (General Control $E0). Asserts IRQN.
Set when a valid interrupt is generated.
Cleared by a read of the Status register $E6.
Mask bit b5 (General Control $E0).
Descrambler Disabled Descrambler Enabled
0- -
1Unscrambled 1s Unscrambled 1s
0Unscrambled 0s Scrambled 0s. see below
1-Scrambled 1s
b8
0
0
1
1
Scrambler Rx Mode $E3 b7..6.
Mask bo1 (General Control $E0). Asserts IRQN.
Status $E6 Bits b15, b13..0 cleared to zero following General Reset $01, or
General Control Register $E0 Reset (b7) = 1 or General Control Register $E0
Powerup (b8) = 0 (Powersave Mode).
2100Hz or
second
Programmabl
Tone
Detected
0
Tx Data
Underflow
