MCM63Z736
D
MCM63Z818
1
MOTOROLA FAST SRAM
Advance Information
128K x 36 and 256K x 18 Bit
Pipelined ZBT RAM
Synchronous Fast Static RAM
The ZBT RAM is a 4M–bit synchronous fast static RAM designed to provide
zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during
back–to–back read/write and write/read cycles. The MCM63Z736 is organized
as 128K words of 36 bits each and the MCM63Z818 is organized as 256K words
of 18 bits each, fabricated with high performance silicon gate CMOS
technology. This device integrates input registers, an output register, a 2–bit
address counter, and high speed SRAM onto a single monolithic circuit for
reduced parts count in communication applications. Synchronous design
allows precise cycle control with the use of an external clock (CK). CMOS
circuitry reduces the overall power consumption of the integrated functions for
greater reliability.
Addresses (SA), data inputs (DQ), and all control signals except output enable
(G) and linear burst order (LBO) are clock (CK) controlled through positive–
edge–triggered noninverting registers.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (CK) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily stored by an edge–
triggered output register and then released to the output buffers at the next rising
edge of clock (CK).
•3.3 V LVTTL and LVCMOS Compatible
•MCM63Z736/MCM63Z818–133 = 4.2 ns Access/7.5 ns Cycle (133 MHz)
MCM63Z736/MCM63Z818–100 = 5 ns Access/10 ns Cycle (100 MHz)
•Selectable Burst Sequencing Order (Linear/Interleaved)
•Internally Self–T imed W rite Cycle
•Two–Cycle Deselect
•Byte Write Control
•ADV Controlled Burst
•100–Pin TQFP Package
ZBT and Zero Bus T urnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by
Micron Technology, Inc. and Motorola, Inc.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Order this document
by MCM63Z736/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM63Z736
MCM63Z818
TQ PACKAGE
TQFP
CASE 983A–01
REV 1
2/6/98
Motorola, Inc. 1998
MCM63Z736
D
MCM63Z818
2MOTOROLA FAST SRAM
PIN ASSIGNMENT
71
72
DQc
VDDQ
DQb
69
70
66
67
68
64
65
61
62
63
3738343536 42433940 41 454644
60
59
58
57
56
55
54
53
52
51
31 3233
74
75
76
77
78
79
80
50494847
DQb
DQb
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VDDQ
VSS
VSS
VDDQ
DQc
DQc
DQc
DQc
DQc
DQc
DQc
SA
SA
SE1
SBd
CK
SBc
NC
G
SA0
SA
SA
SA
SA
NC
NC
NC
LBO
SA1
VDD
VDD
DQa
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
VDDQ
DQa
DQa
DQd
VDD
VSS
VSS
VDDQ
DQd
DQd
DQd
DQd
DQd
73
DQc 94 93979695 89 889291 90 86858710099 98 81828384
10
9
12
11
15
14
13
17
16
20
19
18
21
22
23
24
25
26
27
28
29
30
7
6
5
4
3
2
1
8
SA
SA
CKE
SE2
SE3
VSS
VDD
VDDQ
VSS
DQd
DQd
DQd
SA
SA
SA
SA
SA
SA
SA
NC
VSS
NC
ADV
SW
SBa
SBb
VDD
VDD VSS
VDD
TOP VIEW
MCM63Z736
MCM63Z736
D
MCM63Z818
3
MOTOROLA FAST SRAM
PIN ASSIGNMENT
71
72
NC
VDDQ
SA
69
70
66
67
68
64
65
61
62
63
3738343536 42433940 41 454644
60
59
58
57
56
55
54
53
52
51
31 3233
74
75
76
77
78
79
80
50494847
NC
NC
VSS
DQa
NC
DQa
DQa
VSS
VDDQ
DQa
DQa
VDDQ
VSS
VSS
VDDQ
NC
NC
NC
DQb
DQb
DQb
DQb
SA
SA
SE1
NC
CK
NC
NC
G
SA0
SA
SA
SA
SA
NC
NC
NC
SA1
VDD
VDD
DQa
VSS
DQa
DQa
NC
DQa
VSS
VDDQ
NC
NC
VSS
VDDQ
NC
NC
DQb
VDD
VSS
VSS
VDDQ
DQb
DQb
DQb
DQb
NC
73
NC 94 93979695 89 889291 90 86858710099 98 81828384
10
9
12
11
15
14
13
17
16
20
19
18
21
22
23
24
25
26
27
28
29
30
7
6
5
4
3
2
1
8
SA
SA
CKE
SE2
SE3
VSS
VDD
VDDQ
VSS
NC
NC
NC
SA
SA
SA
SA
SA
SA
SA
NC
VSS
NC
ADV
SW
SBa
SBb
VDD
VDD VSS
VDD
TOP VIEW
MCM63Z818
LBO
MCM63Z736
D
MCM63Z818
4MOTOROLA FAST SRAM
MCM63Z736 PIN DESCRIPTIONS
Pin Locations Symbol Type Description
85 ADV Input Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
89 CK Input Clock: This signal registers the address, data in, and all control signals
except G and LBO.
87 CKE Input Clock Enable: Disables the CK input when CKE is high.
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30
DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
86 G Input Asynchronous Output Enable.
31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low – linear burst counter.
High – interleaved burst counter.
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 50, 81, 82, 99, 100 SA Input Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37 SA0, SA1 Input Synchronous Burst Address Inputs: The two LSB’s of the address field.
These pins must preset the burst address counter values. These inputs
are registered and must meet setup and hold times.
93, 94, 95, 96
(a) (b) (c) (d) SBx Input Synchronous Byte Write Inputs: Enables write to byte “x”
(byte a, b, c, d) in conjunction with SW. Has no effect on read cycles.
98 SE1 Input Synchronous Chip Enable: Active low to enable chip.
97 SE2 Input Synchronous Chip Enable: Active high for depth expansion.
92 SE3 Input Synchronous Chip Enable: Active low for depth expansion.
88 SW Input Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
14, 15, 16, 41, 65, 66, 91 VDD Supply Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77 VDDQ Supply I/O Power Supply.
5, 10, 17, 21, 26, 40,
55, 60, 64, 67, 71, 76, 90 VSS Supply Ground.
38, 39, 42, 43, 83, 84 NC — No Connection: There is no connection to the chip.
MCM63Z736
D
MCM63Z818
5
MOTOROLA FAST SRAM
MCM63Z818 PIN DESCRIPTIONS
Pin Locations Symbol Type Description
85 ADV Input Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
89 CK Input Clock: This signal registers the address, data in, and all control signals
except G and LBO.
87 CKE Input Clock Enable: Disables the CK input when CKE is high.
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74
(b) 8, 9, 12, 13, 18, 19, 22, 23, 24 DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
86 G Input Asynchronous Output Enable.
31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low – linear burst counter.
High – interleaved burst counter.
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 50, 80, 81, 82, 99, 100 SA Input Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37 SA0, SA1 Input Synchronous Burst Address Inputs: The two LSB’s of the address field.
These pins must preset the burst address counter values. These inputs
are registered and must meet setup and hold times.
93, 94
(a) (b) SBx Input Synchronous Byte Write Inputs: Enables write to byte “x”
(byte a, b) in conjunction with SW. Has no effect on read cycles.
98 SE1 Input Synchronous Chip Enable: Active low to enable chip.
97 SE2 Input Synchronous Chip Enable: Active high for depth expansion.
92 SE3 Input Synchronous Chip Enable: Active low for depth expansion.
88 SW Input Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
14, 15, 16, 41, 65, 66, 91 VDD Supply Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77 VDDQ Supply I/O Power Supply.
5, 10, 17, 21, 26, 40,
55, 60, 64, 67, 71, 76, 90 VSS Supply Ground.
1, 2, 3, 6, 7, 25, 28, 29, 30,
38, 39, 42, 43, 51, 52, 53, 56, 57,
75, 78, 79, 83, 84, 95, 96
NC — No Connection: There is no connection to the chip.
MCM63Z736
D
MCM63Z818
6MOTOROLA FAST SRAM
TRUTH TABLE
CK CKE E SW SBx ADV SA0 –
SAx Next Operation Input Command
Code Notes
L–H 1 X X X X X Hold H 1, 2
L–H 0 False X X 0 X Deselect D 1, 2
L–H 0 True 0 V 0 V Load Address, New Write W 1, 2, 3,
4, 5
L–H 0 True 1 X 0 V Load Address, New Read R 1, 2
L–H 0 X X V (W) 1 X Burst B1, 2, 4,
67
X (R, D) Continue 6, 7
NOTES:
1. X = don‘t care, 1 = logic high, 0 = logic low, V = valid signal, according to AC Operating Conditions and Characteristics.
2. E = true if SE1 and SE3 = 0, and SE2 = 1.
3. Byte write enables, SBx are evaluated only as new write addresses are loaded.
4. No control inputs except CKE, SBx, and ADV are recognized in a clock cycle where ADV is sampled high.
5. A write with SBx not valid does load addresses.
6. A burst write with SBx not valid does increment address.
7. ADV controls whether the RAM enters burst mode. If the previous cycle was a write, then ADV = 1 results in a burst write. If the previous
cycle is a read, then ADV = 1 results in a burst read. ADV = 1 will also continue a deslect cycle.
WRITE TRUTH TABLE
Cycle Type SW SBa SBb SBc
(See Note 1) SBd
(See Note 1)
Read H X X X X
Write Byte a L L H H H
Write Byte b L H L H H
Write Byte c (See Note 1) L H H L H
Write Byte d (See Note 1) L H H H L
Write All Bytes L L L L L
NOTE:
1. Valid only for MCM63Z736.
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X10 X . . . X11 X . . . X00
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X00 X . . . X01 X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X00 X . . . X11 X . . . X10
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X10 X . . . X01 X . . . X00
MCM63Z736
D
MCM63Z818
7
MOTOROLA FAST SRAM
INPUT COMMAND CODE AND STATE NAME DEFINITION DIAGRAM
FALSEE
CK
CKE
TRUE TRUE
SA0 – SAx VALID VALID
SW
ADV
VALID VALIDSBX
DBW BRBH
DESELECT CONTINUE
DESELECT NEW WRITE BURST
WRITE NEW READ BURST
READ HOLD
INPUT
COMMAND
CODE
NOTE: Cycles are named for their control inputs, not for data I/O state.
MCM63Z736
D
MCM63Z818
8MOTOROLA FAST SRAM
Figure 1. ZBT RAM State Diagram
DESELECT
BURST
WRITE
BURST
READ
W
R
D
NEW
WRITE
NEW
READ
B
W
R
WRW
B
B
B
R
B
R
D
D
W
D
D
CURRENT
STATE (n) NEXT
STATE (n + 1)
TRANSITION
ƒ
INPUT
COMMAND
CODE
KEY:
NOTES:
1. Input command codes (D, W, R, and B) represent control pin inputs
as indicated in the T ruth Table.
2. Hold (i.e., CKE sampled high) is not shown simply because
CKE = 1 blocks clock input and therefore, blocks any state change.
CK
COMMAND
CODE
STATE
ƒ
DQ
n n + 1 n + 2 n + 3
CURRENT
STATE NEXT
STATE
Figure 2. State Definitions for ZBT RAM State Diagram
MCM63Z736
D
MCM63Z818
9
MOTOROLA FAST SRAM
Figure 3. Data I/O State Diagram
HIGH–Z
HIGH–Z
(DATA IN)
DATA OUT
(Q VALID)
W
R
BW
CURRENT
STATE (n) NEXT STATE
(n + 2)
TRANSITION
ƒ
INPUT
COMMAND
CODE
KEY:
INTERMEDIATE INTERMEDIATE
INTERMEDIATE INTERMEDIATE
INTERMEDIATE
B
R
DD
W
R
INTERMEDIATE
D
B
NOTES:
1. Input command codes (D, W , R, and B) represent control pin
inputs as indicated in the Truth Table.
2. Hold (i.e., CKE sampled high) is not shown simply because
CKE = 1 blocks clock input and therefore, blocks any state
change.
INTERMEDIATE
STATE (n + 1)
TRANSITION
CK
COMMAND
CODE
STATE
STATE NAME
ƒ
DQ
n n + 1 n + 2 n + 3
CURRENT
STATE INTERMEDIATE
STATE NEXT
STATE
Figure 4. State Definitions for I/O State Diagrams
MCM63Z736
D
MCM63Z818
10 MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating Symbol Value Unit Notes
Power Supply Voltage VDD – 0.5 to + 4.6 V
I/O Supply Voltage VDDQ VSS – 0.5 to VDD V 2
Input Voltage Relative to VSS for
Any Pin Except VDD Vin, Vout – 0.5 to VDD + 0.5 V 2
Input Voltage (Three State I/O) VIT VSS – 0.5 to
VDDQ + 0.5 V 2
Output Current (per I/O) Iout ± 20 mA
Package Power Dissipation PD1.3 W 3
Temperature Under Bias Tbias – 10 to 85 °C
Storage Temperature Tstg – 55 to 125 °C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could af fect device reliability.
2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing is not necessary.
3. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance Symbol Max Unit Notes
Junction to Ambient (@ 200 lfm) Single–Layer Board
Four–Layer Board RθJA 40
25 °C/W 1, 2
Junction to Board (Bottom) RθJB 17 °C/W 3
Junction to Case (Top) RθJC 9°C/W 4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883
Method 1012.1).
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
MCM63Z736
D
MCM63Z818
11
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 5%, TA = 0 to 70°C Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter Symbol Min Typ Max Unit
Supply Voltage VDD 3.135 3.3 3.465 V
I/O Supply Voltage VDDQ*3.135 3.3 VDD V
Input Low Voltage VIL – 0.3 — 0.8 V
Input High Voltage VIH 2 — VDD + 0.3 V
Input High Voltage I/O Pins VIH2 2 — VDDQ + 0.3 V
*VDD and VDDQ are shorted together on the device and must be supplied with identical voltage levels.
VIH
20% tKHKH (MIN)
VSS
VSS – 1.0 V
Figure 5. Undershoot Voltage
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Symbol Min Typ Max Unit Notes
Input Leakage Current (0 V ≤ Vin ≤ VDD) Ilkg(I) — — ± 1 µA 1
Output Leakage Current (0 V ≤ Vin ≤ VDDQ) Ilkg(O) — — ± 1 µA
AC Supply Current (Device Selected, All Outputs Open,
Freq = Max) Includes Supply Current for Both VDD and VDDQ IDDA — — 350 mA 2, 3, 4
CMOS Standby Supply Current (Device Deselected,
Freq = 0, VDD = Max, VDDQ = Max, All Inputs Static at CMOS
Levels)
ISB2 — — 5 mA 5, 6
TTL Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, VDDQ = Max, All Inputs Static at TTL Levels) ISB3 — — 25 mA 5, 7
Hold Supply Current (Device Selected, Freq = Max,
VDD = Max, VDDQ = Max, CKE ≥ VDD – 0.2 V, All Inputs Static at
CMOS Levels)
IDD1 — — 15 mA 6
Output Low Voltage (IOL = 8 mA) VOL — — 0.4 V
Output High Voltage (IOH = – 8 mA) VOH 2.4 — — V
NOTES:
1. LBO has an internal pullup and will exhibit leakage currents of ± 5 µA.
2. Reference AC Operating Conditions and Characteristics for Input and T iming.
3. All addresses transition simultaneously low (LSB) then high (MSB).
4. Data states are all zero.
5. Device in deselected mode as defined by the T ruth Table.
6. CMOS levels for I/Os are VIT ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V.
7. TTL levels for I/O’s are VIT ≤ VIL or ≥ VIH2. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)
Parameter Symbol Min Typ Max Unit
Input Capacitance Cin — 4 5 pF
Input/Output Capacitance CI/O — 7 8 pF
MCM63Z736
D
MCM63Z818
12 MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 5%, TA = 0 to 70°C Unless Otherwise Noted)
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Input Pulse Levels 0 to 3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 1 V/ns (20% to 80%). . . . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .
Output Load See Figure 6 Unless Otherwise Noted. . . . . . . . . . . . . .
RθJA Under Test TBD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
P
Sbl
MCM63Z736–133
MCM63Z818–133
133 MHz
MCM63Z736–100
MCM63Z818–100
100 MHz
Ui
N
Parameter Symbol Min Max Min Max Unit Notes
Cycle Time tKHKH 7.5 — 10 — ns
Clock High Pulse Width tKHKL 3 — 4 — ns 3
Clock Low Pulse Width tKLKH 3 — 4 — ns 3
Clock Access Time tKHQV —4.2 — 5 ns
Output Enable to Output Valid tGLQV —4.2 — 5 ns
Clock High to Output Active tKHQX1 1.5 — 1.5 — ns 4, 5
Output Hold T ime tKHQX 1.5 — 1.5 — ns 4
Output Enable to Output Active tGLQX 0 — 0 — ns 4, 5
Output Disable to Q High–Z tGHQZ —3.5 — 3.5 ns 4, 5
Clock High to Q High–Z tKHQZ 1.5 3.5 1.5 3.5 ns 4, 5
Setup T imes: Address
ADV
Data In
Write
Chip Enable
Clock Enable
tADKH
tLVKH
tDVKH
tWVKH
tEVKH
tCVKH
2
2
1.7
2
2
2
— 2.2
2.2
2
2.2
2.2
2.2
— ns
Hold T imes: Address
ADV
Data In
Write
Chip Enable
Clock Enable
tKHAX
tKHLX
tKHDX
tKHWX
tKHEX
tKHCX
0.5 — 0.5 — ns
NOTES:
1. Write is defined as any SBx and SW low. Chip Enable is defined as SE1 low , SE2 high, and SB3 low whenever ADV is low.
2. All read and write cycle timings are referenced from CK or G.
3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some de-
sign exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given
in the AC test conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
4. This parameter is sampled and not 100% tested.
5. Measured at ± 200 mV from steady state.
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
1.5 V
Figure 6. AC Test Load
MCM63Z736
D
MCM63Z818
13
MOTOROLA FAST SRAM
CK
SA0 – SAx
Figure 7. AC Timing Parameter Definitions
tKHKH
tKHKL tKLKH
tAVKH tKHAX
SW
tWVKH tKHWX
SBx
tWVKH tKHWX
E
tEVKH tKHEX
ADV
tLVKH tKHLX
CKE
tCVKH tKHCX
G
DQ Q
DQ
DQ
tKHQX1
Q
tKHQZ
Q
tKHQV
tGHQZ
tGLQX
tGLQV
tKHQX
tDVKH tKHDX
D
MCM63Z736
D
MCM63Z818
14 MOTOROLA FAST SRAM
READ/WRITE CYCLES WITH HOLD AND DESELECT CYCLES
CK
COMMAND
AB CD E FG HIJ
RWHRW
D
RHWRDWRD
Q(A0) D(B0) Q(C0) D(D0) Q(E0) D(F0) Q(G0) D(H0) Q(I0)
ADDRESS
CODE
DQ
NOTE: Command code definitions are shown in Truth Table.
MCM63Z736
D
MCM63Z818
15
MOTOROLA FAST SRAM
READ CYCLES (SINGLE, BURST, AND BURST WRAP–AROUND)
CK
COMMAND
AB C
RRBBBR
BBBB
ADDRESS
CODE
DQ Q(A0) Q(B0) Q(B1) Q(B2) Q(B3) Q(C0) Q(C1) Q(C2) Q(C3) Q(C0)
NOTE: Command code definitions are shown in Truth Table.
MCM63Z736
D
MCM63Z818
16 MOTOROLA FAST SRAM
WRITE CYCLES (SINGLE, BURST, AND BURST WRAP–AROUND)
CK
COMMAND
AB C
WWBBB
W
BBBB
ADDRESS
CODE
DQ D(A0) D(B0) D(B1) D(B2) D(B3) D(C0) D(C1) D(C2) D(C3) D(C0)
NOTE: Command code definitions are shown in Truth Table.
MCM63Z736
D
MCM63Z818
17
MOTOROLA FAST SRAM
READ, WRITE, READ COHERENCY WITH HOLD, AND DESELECT CYCLES
CK
COMMAND
AB C
RWRWB R
BDWH
ADDRESS
CODE
DQ Q(A0) D(B0) Q(B0) D(C0) D(C1) Q(C0) Q(C1) D(D0)
BC D DE
RR
Q(D0) Q(E0)
NOTE: Command code definitions are shown in Truth Table.
MCM63Z736
D
MCM63Z818
18 MOTOROLA FAST SRAM
MCM 63Z818 XX X X
Motorola Memory Prefix
Part Number
Full Part Numbers — MCM63Z736TQ133 MCM63Z736TQ100
MCM63Z736TQ133R MCM63Z736TQ100R
MCM63Z818TQ133 MCM63Z818TQ100
MCM63Z818TQ133R MCM63Z818TQ100R
Package (TQ = TQFP)
Blank = T rays, R = Tape and Reel
Speed (133 = 133 MHz, 100 = 100 MHz)
ORDERING INFORMATION
(Order by Full Part Number)
63Z736
MCM63Z736
D
MCM63Z818
19
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
TQ PACKAGE
100–PIN TQFP
CASE 983A–01
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A––– 1.60 ––– 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.45 0.053 0.057
b0.22 0.38 0.009 0.015
b1 0.22 0.33 0.009 0.013
c0.09 0.20 0.004 0.008
c1 0.09 0.16 0.004 0.006
D22.00 BSC 0.866 BSC
E16.00 BSC 0.630 BSC
E1 14.00 BSC 0.551 BSC
e0.65 BSC 0.026 BSC
L0.45 0.75 0.018 0.030
L1 1.00 REF 0.039 REF
L2 0.50 REF
S0.20 ––– 0.008 –––
R1 0.08 ––– 0.003 –––
R2 0.08 0.20 0.003 0.008
q
0 7 0 7
q
0 ––– 0 –––
q
11 13 11 13
q
11 13 11 13
1
2
3
D1 20.00 BSC 0.787 BSC
0.020 REF
_
_
_
_
_
_
_
_
_
_
_
_
_
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT
DATUM PLANE –H–.
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018).
A–B0.20 (0.008) H
e
D
A–B0.20 (0.008) C D
A–B0.20 (0.008) C D
0.10 (0.004) C
0.25 (0.010)
S
0.05 (0.002)
S
A–B
M
0.13 (0.005) D S
C
e/2
D/2
E
E1
D1
D
D1/2
E1/2
E/2
4X
2X 30 TIPS
2X 20 TIPS
–D–
–B–
–A–
–C–
–H–
q
1
q
3
q
2
q
100
81
80 51
50
31
301
PLATING
SECTION B–B
c1
c
b
b1
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
BASE
METAL
A
SEATING
PLANE
VIEW AB
S
VIEW AB
A2
A1 R1 L2
L
L1
R2
GAGE PLANE
–X–
VIEW Y
B
BX=A, B, OR D
MCM63Z736
D
MCM63Z818
20 MOTOROLA FAST SRAM
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Af firmative Action Employer .
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141,
P.O . Bo x 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488
Mfax: RMFAX0@email.sps.mot.com – TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
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– http://sps.motorola.com/mfax/
HOME PAGE: http://motorola.com/sps/ CUSTOMER FOCUS CENTER: 1-800-521-6274
MCM63Z736/D
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