5-1
FAST AND LS TTL DATA
8-BIT SHIFT/STORAGE REGISTER
WITH 3-STATE OUTPUTS
The SN54/74LS323 is an 8-Bit Universal Shift/Storage Register with
3-state outputs. Its function is similar to the SN54/74LS299 with the exception
of Synchronous Reset. Parallel load inputs and flip-flop outputs are
multiplexed to minimize pin count. Separate inputs and outputs are provided
for flip-flops Q0 and Q7 to allow easy cascading.
Four operation modes are possible: hold (store), shift left, shift right, and
parallel load. All modes are activated on the LOW-to-HIGH transition of the
Clock.
•Common I/O for Reduced Pin Count
•Four Operation Modes: Shift Left, Shift Right, Parallel Load and Store
•Separate Continuous Inputs and Outputs from Q0 and Q7 Allow Easy
Cascading
•Fully Synchronous Reset
•3-State Outputs for Bus Oriented Applications
•Input Clamp Diodes Limit High-Speed Termination Effects
•ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
18 17 16 15 14 13
1234567
20 19
8
VCC
S0
S1DS7Q7I/O7I/O3
I/O5I/O1
OE1OE2I/O6I/O4I/O2I/O0Q0910
SR GND
12 11
CP DS0
PIN NAMES LOADING (Note a)
HIGH LOW
CP Clock Pulse (active positive going edge) Input 0.5 U.L. 0.25 U.L.
DS0Serial Data Input for Right Shift 0.5 U.L. 0.25 U.L.
DS7Serial Data Input for Left Shift 0.5 U.L. 0.25 U.L.
I/OnParallel Data Input or
Parallel Output (3-State) (Note c) 1.0 U.L.
65 (25) U.L. 0.5 U.L.
15 (7.5) U.L.
OE1, OE23-State Output Enable (active LOW) Inputs 0.5 U.L. 0.25 U.L.
Q0, Q7
S0, S1Serial Outputs (Note b)
Mode Select Inputs 10 U.L.
1 U.L. 5 (2.5) U.L.
SR Synchronous Reset (active LOW) Input 0.5 U.L. 0.25 U.L.
NOTES:
a) 1 TTL LOAD = 40 µA HIGH/1.6 mA LOW.
b) The output LOW drive factor is 2.5 U.L for Military (54) and 5 U.L. for Commercial Temperature Ranges.
c) The output LOW drive factor is 7.5 U.L for Military (54) and 15 U.L. for Commercial Temperature Ranges.
The output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for Commercial Temperature Ranges.
SN54/74LS323
8-BIT SHIFT/STORAGE REGISTER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
20
1
J SUFFIX
CERAMIC
CASE 732-03
20 1
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
5-2
FAST AND LS TTL DATA
SN54/74LS323
LOGIC DIAGRAM
S1S0
DS0
SR
Q0
OE1
OE2
DQCP
I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7
DS7
Q7
14
1
2
67
3
8
45
9
11
12
13 15 16
17
18
19
DQCP DQCP DQCP DQCP DQCP DQCP DQCP
CP
FUNCTIONAL DESCRIPTION
The logic diagram and truth table indicate the functional
characteristics of the SN54/74LS323 Universal Shift/Storage
Register. This device is similar in operation to the
SN54/74LS299 except for synchronous reset. A partial list of
the common features are described below:
1. They use eight D-type edge-triggered flip-flops that re-
spond only to the LOW-to-HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control (S0, S1) and data inputs (DS0, DS7, I/O0–I/O7) may
be stable at least a setup time prior to the positive transition
of the Clock Pulse.
2. When S0 = S1 = 1, I/O0–I/O7 are parallel inputs to flip-flops
Q0–Q7 respectively, and the outputs of Q0–Q7 are in the
high impedance state regardless of the state of OE1 or
OE2.
An important unique feature of the SN54/74LS323 is a fully
Synchronous Reset that requires only to be stable at least one
setup time prior to the positive transition of the Clock Pulse.
TRUTH TABLE
INPUTS RESPONSE
SR S1S0OE1OE2CP DS0DS7
L X X H X X X
Synchronous Reset; Q0
=
Q7
=
LOW
L X X X H X X
Synchronous
Reset;
Q0
=
Q7
=
LOW
I/O voltage undetermined
L H H X X X X
I/O
voltage
undetermined
L L X L L X X Synchronous Reset; Q0 = Q7 = LOW
L X L L L X X I/O voltage LOW
H L H X X D X Shift Right; D→Q0; Q0→Q1; etc.
H L H L L D X Shift Right; D→Q0 & I/O0; Q0→Q1 & I/O1; etc.
H H L X X X D Shift Left; D→Q7; Q7→Q6; etc.
H H L L L X D Shift Left; D→Q7 & I/O7; Q7→Q6 & I/O6; etc.
H H H X X X X Parallel Load I/On→Qn
H L L H X X X X
Hold; I/O Voltage Undetermined
H L L X H X X X
Hold;
I/O
Voltage
Undetermined
H L L L L X X X Hold; I/On = Qn
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
5-3
FAST AND LS TTL DATA
SN54/74LS323
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54
74 4.5
4.75 5.0
5.0 5.5
5.25 V
TAOperating Ambient Temperature Range 54
74 –55
025
25 125
70 °C
IOH Output Current — High Q0, Q754, 74 –0.4 mA
IOL Output Current — Low Q0, Q7
Q0, Q754
74 4.0
8.0 mA
IOH Output Current — High I/O0–I/O7
I/O0–I/O754
74 –1.0
–2.6 mA
IOL Output Current — Low I/O0–I/O7
I/O0–I/O754
74 12
24 mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54 0.7
V
Guaranteed Input LOW Voltage for
V
IL
I
npu
t
LOW
V
o
lt
age 74 0.8
V
pg
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage 54 2.4 3.2 V
VCC = MIN IOH = MAX
V
OH
pg
I/O0–I/O774 2.4 3.1 V
V
CC =
MIN
,
I
OH =
MAX
VOH
Output HIGH Voltage 54 2.5 3.4 V
VCC = MIN IOH = MAX
V
OH
pg
Q0, Q774 2.7 3.4 V
V
CC =
MIN
,
I
OH =
MAX
VOL
Output LOW Voltage 54, 74 0.25 0.4 V IOL = 12 mA VCC = VCC MIN,
VIN =V
IL or VIH
V
OL
pg
I/O0–I/O774 0.35 0.5 V IOL = 24 mA
V
IN =
V
IL or
V
IH
per T ruth Table
VOL
Output LOW Voltage 54, 74 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN =V
IL or VIH
V
OL
pg
Q0–Q774 0.5 V IOL = 8.0 mA
V
IN =
V
IL or
V
IH
per T ruth Table
IOZH Output Off Current HIGH
I/O0–I/O740 µA VCC = MAX, VOUT = 2.7 V
IOZL Output Off Current LOW
I/O0–I/O7–400 µA VCC = MAX, VOUT = 0.4 V
I
I HIGH C
Others 20 µA
V MAX V 2 7 V
I
Input HIGH Current
S0, S1,
I/O0–I/O740 µAVCC = MAX, VIN = 2.7 V
IIH Input HIGH Current Others 0.1 mA
VCC = MAX VIN =70V
S0, S10.2 mA
V
CC =
MAX
,
V
IN =
7
.
0
V
I/O0–I/O70.1 mA VCC = MAX, VIN = 5.5 V
IIL
Input LOW Current Others –0.4 mA
VCC = MAX VIN =04V
I
IL S0, S1–0.8 mA
V
CC =
MAX
,
V
IN =
0
.
4
V
IOS Short Circuit Current Qo, Q7–20 –100 mA VCC = MAX
(Note 1) I/O0–I/O7–30 –130 mA VCC = MAX
ICC Power Supply Current 53 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
5-4
FAST AND LS TTL DATA
SN54/74LS323
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit T est Conditions
fMAX Maximum Clock Frequency 25 35 MHz
C15F
tPHL
tPLH Propagation Delay, Clock
to Q0 or Q726
22 39
33 ns CL = 15 pF
tPHL
tPLH Propagation Delay, Clock
to I/O0–I/O725
17 39
25 ns CL = 45 pF,
tPZH
tPZL Output Enable T ime 14
20 21
30 ns
Lp,
RL = 667 Ω
tPHZ
tPLZ Output Disable T ime 10
10 15
15 ns CL = 5.0 pF
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit T est Conditions
tWClock Pulse Width HIGH 25 ns
V50V
tWClock Pulse Width LOW 15 ns
V50V
tWClear Pulse Width LOW 20 ns
V50V
tsData Setup T ime 20 ns
VCC =50V
tsSelect Setup T ime 35 ns
V
CC =
5
.
0
V
thData Hold T ime 0 ns
thSelect Hold T ime 10 ns
trec Recovery Time 20 ns
1.3 V
1.3 V 1.3 V
1.3 V
VIN
VOUT
tPLH tPHL
1.3 V
1.3 V
VIN
VOUT 1.3 V
tPLH tPHL
1.3 V
Figure 1 Figure 2
Figure 5
Figure 3 Figure 4
1.5 V 1.5 V
1.5 V
≈
1.5 V
1.5 V 1.5 V
1.5 V
≈
1.5 V
VE
VE
VOUT tPZL tPLZ
VOL
0.5 V
VE
VE
VOUT
tPZH tPHZ
0.5 V
≥
VOH
3-STATE WAVEFORMS
AC LOAD CIRCUIT
SWITCH POSITIONS
SW2CL*
5 k
Ω
SW1
VCC
RL
TO OUTPUT
UNDER TEST
* Includes Jig and Probe Capacitance.
5-5
FAST AND LS TTL DATA
SN54/74LS323
SYMBOL SW1 SW2
tPZH Open Closed
tPZL Closed Open
tPLZ Closed Closed
tPHZ Closed Closed
