Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCIMX35SR2CEC
Rev. 10, 06/2012
© Freescale Semiconductor, Inc., 2010. All rights reserved.
IMX35
Ordering Information
See Ta b l e 1 on page 3 for ordering information.
Package Information
Plastic Package
Case 5284 17 x 17 mm, 0.8 mm Pitch
1 Introduction
The i.MX353 and the i.MX357 multimedia applications
processors represent the next generation of ARM11
products with the right performance and integration to
address applications within the industrial and consumer
markets for applications such as HMI and display
controllers. Unless otherwise specified, the material in
this data sheet is applicable to both the i.MX353 and
i.MX357 devices and referred to singularly throughout
this document as i.MX35 or MCIMX35. The i.MX353
devices do not include a graphics processing unit
(GPU). For information on i.MX35 devices for
automotive applications, please refer to document
number, MCIMX35SR2AEC.
The i.MX35 processor takes advantage of the
ARM1136JF-S™ core running at 532 MHz that is
boosted by a multi-level cache system and integrated
features such as LCD controller, Ethernet, and graphics
acceleration for creating rich user interfaces.
The i.MX35 supports connections to various types of
external memories, such as SDRAM, mobile DDR, and
DDR2, SLC and MCL NAND Flash, NOR Flash and
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Functional Description and Application Information. . . . . . 4
2.1. Application Processor Domain Overview. . . . . . . . . 5
2.2. Shared Domain Overview . . . . . . . . . . . . . . . . . . . . 6
2.3. Advanced Power Management Overview . . . . . . . . 6
2.4. ARM11 Microprocessor Core. . . . . . . . . . . . . . . . . . 6
2.5. Module Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Signal Descriptions: Special Function Related Pins . . . . 12
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1. i.MX35 Chip-Level Conditions . . . . . . . . . . . . . . . . 12
4.2. Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3. Supply Power-Up/Power-Down Requirements and
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4. Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . 18
4.6. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . 19
4.7. I/O Pin DC Electrical Characteristics . . . . . . . . . . . 20
4.8. I/O Pin AC Electrical Characteristics . . . . . . . . . . . 23
4.9. Module-Level AC Electrical Specifications. . . . . . . 29
5. Package Information and Pinout . . . . . . . . . . . . . . . . . . 130
5.1. MAPBGA Production Package 1568-01, 17 ×17 mm,
0.8 Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.2. MAPBGA Signal Assignments . . . . . . . . . . . . . . . 132
6. Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . 144
7. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
i.MX35 Applications
Processors for
Industrial and
Consumer Products
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor2
SRAM. The devices can be connected to a variety of external devices such as USB 2.0 OTG, ATA,
MMC/SDIO, and Compact Flash.
1.1 Features
It provides low-power solutions for applications demanding high-performance multimedia and graphics.
The i.MX35 is based on the ARM1136 platform, which has the following features:
• ARM1136JF-S processor, version r1p3
• 16-Kbyte L1 instruction cache
• 16-Kbyte L1 data cache
• 128-Kbyte L2 cache, version r0p4
• 128 Kbytes of internal SRAM
• Vector floating point unit (VFP11)
To boost multimedia performance, the following hardware accelerators are integrated:
• Image processing unit (IPU)
• OpenVG 1.1 graphics processing unit (GPU) (not available for the MCIMX351)
The MCIMX35 provides the following interfaces to external devices (some of these interfaces are muxed
and not available simultaneously):
• 2 controller area network (CAN) interfaces
• 2 SDIO/MMC interfaces, 1 SDIO/CE-ATA interface (CE-ATA is not available for the MCIMX351)
• 32-bit mobile DDR, DDR2 (4-bank architecture), and SDRAM (up to 133 MHz)
• 2 configurable serial peripheral interfaces (CSPI) (up to 52 Mbps each)
• Enhanced serial audio interface (ESAI)
• 2 synchronous serial interfaces (SSI)
• Ethernet MAC 10/100 Mbps
• 1 USB 2.0 host with ULPI interface or internal full-speed PHY. Up to 480 Mbps if external HS
PHY is used.
• 1 USB 2.0 OTG (up to 480 Mbps) controller with internal high-speed OTG PHY
• Flash controller—MLC/SLC NAND and NOR
• GPIO with interrupt capabilities
•3 I
2C modules (up to 400 Kbytes each)
•JTAG
• Key pin port
• Asynchronous sample rate converter (ASRC)
•1-Wire
• Parallel camera sensor (4/8/10/16-bit data port for video color models: YCC, YUV, 30 Mpixels/s)
• Parallel display (primary up to 24-bit, 1024 x 1024)
• Parallel ATA (up to 66 Mbytes) (not available for the MCIMX351)
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•PWM
• SPDIF transceiver
• 3 UART (up to 4.0 Mbps each)
1.2 Ordering Information
Table 1 provides the ordering information for the i.MX35 processors for consumer and industrial
applications.
The ball map for silicon revision 2.1 is different than the ballmap for silicon revision 2.0. The layout for
each revision is not compatible, so it is important that the correct ballmap be used to implement the layout.
See Section 5, “Package Information and Pinout.”
Table 2 shows the functional differences between the different parts in the i.MX35 family.
Table 1. Ordering Information
Description Part Number Silicon
Revision Package1
1Case 5284 is RoHS-compliant, lead-free, MSL = 3, 1.
Speed
Operating
Temperature
Range (°C)
Signal Ball
Map
Locations
Ball Map
i.MX353 MCIMX353CVM5B 2.0 5284 532 MHz –40 to 85 Table 94 Table 96
i.MX353 MCIMX353DVM5B 2.0 5284 532 MHz –20 to 70 Table 94 Table 96
i.MX357 MCIMX357CVM5B 2.0 5284 532 MHz –40 to 85 Table 94 Table 96
i.MX357 MCIMX357DVM5B 2.0 5284 532 MHz –20 to 70 Table 94 Table 96
i.MX353 MCIMX353CJQ5C 2.1 5284 532MHz -40 to 85 Table 95 Table 97
i.MX353 MCIMX353DJQ5C 2.1 5284 532MHz -20 to 70 Table 95 Table 97
i.MX357 MCIMX357CJQ5C 2.1 5284 532MHz -40 to 85 Table 95 Table 97
i.MX357 MCIMX357DJQ5C 2.1 5284 532MHz -20 to 70 Table 95 Table 97
Table 2. Functional Differences in the i.MX35 Parts
Module MCIMX351 MCIMX353 MCIMX355 MCIMX356 MCIMX357
I 2C ( 3 ) Ye s Ye s Ye s Ye s Ye s
C SP I ( 2 ) Ye s Ye s Ye s Ye s Ye s
SSI/I2S (2) Yes Yes Yes Yes Yes
ESAI Yes Yes Yes Yes Yes
SPDIF I/O Yes Yes Yes Yes Yes
U SB H S H o s t Ye s Ye s Ye s Ye s Ye s
U SB OT G Ye s Ye s Ye s Ye s Ye s
FlexCAN (2) Yes Yes Yes Yes Yes
M L B Ye s Ye s Ye s Ye s Ye s
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Ethernet Yes Yes Yes Yes Yes
1 - W i r e Ye s Ye s Ye s Ye s Ye s
K P P Ye s Ye s Ye s Ye s Ye s
SDIO/MMC (2) Yes Yes Yes Yes Yes
SDIO/Memory Stick Yes Yes Yes Yes Yes
External Memory Controller (EMC) Yes Yes Yes Yes Yes
J TA G Ye s Ye s Ye s Ye s Ye s
PATA — Ye s Ye s Ye s Ye s
C E - ATA — Ye s Ye s Ye s Ye s
Image Processing Unit (IPU) (inversion
and rotation, pre- and post-processing,
camera interface, blending, display
controller)
— Ye s Ye s Ye s Ye s
Open VG graphics acceleration (GPU) — Yes — Yes Yes
Table 2. Functional Differences in the i.MX35 Parts (continued)
Module MCIMX351 MCIMX353 MCIMX355 MCIMX356 MCIMX357
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1.3 Block Diagram
Figure 1 is the i.MX35 simplified interface block diagram.
Figure 1. i.MX35 Simplified Interface Block Diagram
2 Functional Description and Application Information
The i.MX35 consists of the following major subsystems:
• ARM1136 Platform—AP domain
• SDMA Platform and EMI—Shared domain
2.1 Application Processor Domain Overview
The applications processor (AP) and its domain are responsible for running the operating system and
applications software, providing the user interface, and supplying access to integrated and external
peripherals. The AP domain is built around an ARM1136JF-S core with 16-Kbyte instruction and data L1
caches, an MMU, a 128-Kbyte L2 cache, a multiported crossbar switch, and advanced debug and trace
interfaces.
External Memory
Interface (EMI)
Smart
DMA
Peripherals
ARM11
Internal
Memory
DDR2/SDDR
RAM
NOR
Flash/ NAND
Flash
Audio/Power
Management
ARM1136JF-S
ESAI
SPBA
CSPI
UART
Camera
Image
Processing Unit
(IPU)
Platform
Bluetooth MMC/SDIO Keypin
VFP
L2 cache
MAX
AIPS (2)
JTAG
LCD Display 2
LCD Display 1
Sensor External Graphics
Accelerator
Timers
GPT
RTC
GPIO(3)
WDOG
OWIRE
I2C(3)
PWM
KPP
UART(2)
3 FuseBox
PSRAM
or WLAN
SCC
CAN(2)
SPDIF
HS USBOTG
ATA IIM
CSPI
RTICv3
eSDHC(3)
MSHC
ASRC
AUDMUX
L1 I/D cache
ETM
AVIC
RNGC
EPIT
ECT
IOMUX
FEC
HS USBOTGPHY
HS USBHost
FS USBPHY
SSI
SSI
GPIO(3)
ECT
GPU 2D
Connectivity
Access
ARM1136 Platform Peripherals
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The i.MX35 core is intended to operate at a maximum frequency of 532 MHz to support the required
multimedia use cases. Furthermore, an image processing unit (IPU) is integrated into the AP domain to
offload the ARM11 core from performing functions such as color space conversion, image rotation and
scaling, graphics overlay, and pre- and post-processing.
The functionality of AP Domain peripherals includes the user interface; the connectivity, display, security,
and memory interfaces; and 128 Kbytes of multipurpose SRAM.
2.2 Shared Domain Overview
The shared domain is composed of the shared peripherals, a smart DMA engine (SDMA) and a number of
miscellaneous modules. For maximum flexibility, some peripherals are directly accessible by the SDMA
engine.
The i.MX35 has a hierarchical memory architecture including L1 caches and a unified L2 cache. This
reduces the bandwidth demands for the external bus and external memory. The external memory
subsystem supports a flexible external memory system, including support for SDRAM (SDR, DDR2 and
mobile DDR) and NAND Flash.
2.3 Advanced Power Management Overview
To address the continuing need to reduce power consumption, the following techniques are incorporated
in the i.MX35:
• Clock gating
• Power gating
• Power-optimized synthesis
• Well biasing
The insertion of gating into the clock paths allows unused portions of the chip to be disabled. Because
static CMOS logic consumes only leakage power, significant power savings can be realized.
“Well biasing” is applying a voltage that is greater than VDD to the nwells, and one that is lower than VSS
to the pwells. The effect of applying this well back bias voltage reduces the subthreshold channel leakage.
For the 90-nm digital process, it is estimated that the subthreshold leakage is reduced by a factor of ten
over the nominal leakage. Additionally, the supply voltage for internal logic can be reduced from 1.4 V to
1.22 V.
2.4 ARM11 Microprocessor Core
The CPU of the i.MX35 is the ARM1136JF-S core, based on the ARM v6 architecture. This core supports
the ARM Thumb® instruction sets, features Jazelle® technology (which enables direct execution of Java
byte codes) and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit
registers.
The ARM1136JF-S processor core features are as follows:
• Integer unit with integral EmbeddedICE™ logic
• Eight-stage pipeline
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• Branch prediction with return stack
• Low-interrupt latency
• Instruction and data memory management units (MMUs), managed using micro TLB structures
backed by a unified main TLB
• Instruction and data L1 caches, including a non-blocking data cache with hit-under-miss
• Virtually indexed/physically addressed L1 caches
• 64-bit interface to both L1 caches
• Write buffer (bypassable)
• High-speed Advanced Micro Bus Architecture (AMBA)™ L2 interface
• Vector floating point co-processor (VFP) for 3D graphics and hardware acceleration of other
floating-point applications
• ETM™ and JTAG-based debug support
Table 3 summarizes information about the i.MX35 core.
2.5 Module Inventory
Table 4 shows an alphabetical listing of the modules in the MCIMX35. For extended descriptions of the
modules, see the MCIMX35 reference manual.
Table 3. i.MX35 Core
Core
Acronym
Core
Name Brief Description Integrated Memory
Features
ARM11 or
ARM1136
ARM1136
Platform
The ARM1136™ platform consists of the ARM1136JF-S core, the ETM
real-time debug modules, a 6 ×5 multi-layer AHB crossbar switch (MAX), and
a vector floating processor (VFP).
The i.MX35 provides a high-performance ARM11 microprocessor core and
highly integrated system functions. The ARM Application Processor (AP) and
other subsystems address the needs of the personal, wireless, and portable
product market with integrated peripherals, advanced processor core, and
power management capabilities.
• 16-Kbyte
instruction cache
• 16-Kbyte data
cache
• 128-Kbyte L2
cache
• 32-Kbyte ROM
• 128-Kbyte RAM
Table 4. Digital and Analog Modules
Block
Mnemonic Block Name Domain1Subsystem Brief Description
1-WIRE 1-Wire
interface
ARM ARM1136
platform
peripherals
1-Wire provides the communication line to a 1-Kbit add-only
memory. the interface can send or receive 1 bit at a time.
ASRC Asynchronous
sample rate
converter
SDMA Connectivity
peripherals
The ASRC is designed to convert the sampling rate of a signal
associated to an input clock into a signal associated to a different
output clock. It supports a concurrent sample rate conversion of
about –120 dB THD+N. The sample rate conversion of each
channel is associated to a pair of incoming and outgoing sampling
rates.
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ATA ATA module SDMA Connectivity
peripherals
The ATA block is an AT attachment host interface. Its main use is to
interface with IDE hard disk drives and ATAPI optical disk drives. It
interfaces with the ATA device over a number of ATA signals.
AUDMUX Digital audio
mux
ARM Multimedia
peripherals
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (SSIs) and
peripheral serial interfaces (audio codecs). The AUDMUX has two
sets of interfaces: internal ports to on-chip peripherals and external
ports to off-chip audio devices. Data is routed by configuring the
appropriate internal and external ports.
CAN(2) CAN module ARM Connectivity
peripherals
The CAN protocol is primarily designed to be used as a vehicle
serial data bus running at 1 Mbps.
CCM Clock control
module
ARM Clocks This block generates all clocks for the peripherals in the SDMA
platform. The CCM also manages ARM1136 platform low-power
modes (WAIT, STOP), disabling peripheral clocks appropriately for
power conservation, and provides alternate clock sources for the
ARM1136 and SDMA platforms.
CSPI(2) Configurable
serial
peripheral
interface
SDMA,
ARM
Connectivity
peripherals
This module is a serial interface equipped with data FIFOs; each
master/slave-configurable SPI module is capable of interfacing to
both serial port interface master and slave devices. The CSPI ready
(SPI_RDY) and slave select (SS) control signals enable fast data
communication with fewer software interrupts.
ECT Embedded
cross trigger
SDMA,
ARM
Debug ECT (embedded cross trigger) is an IP for real-time debug
purposes. It is a programmable matrix allowing several subsystems
to interact with each other. ECT receives signals required for
debugging purposes (from cores, peripherals, buses, external
inputs, and so on) and propagates them (propagation programmed
through software) to the different debug resources available within
the SoC.
EMI External
memory
interface
SDMA External
memory
interface
The EMI module provides access to external memory for the ARM
and other masters. It is composed of the following main
submodules:
M3IF—provides arbitration between multiple masters requesting
access to the external memory.
SDRAM CTRL—interfaces to mDDR, DDR2 (4-bank architecture
type), and SDR interfaces.
NANDFC—provides an interface to NAND Flash memories.
WEIM—interfaces to NOR Flash and PSRAM.
EPIT(2) Enhanced
periodic
interrupt timer
ARM Timer
peripherals
Each EPIT is a 32-bit “set-and-forget” timer that starts counting after
the EPIT is enabled by software. It is capable of providing precise
interrupts at regular intervals with minimal processor intervention. It
has a 12-bit prescaler to adjust the input clock frequency to the
required time setting for the interrupts, and the counter value can be
programmed on the fly.
Table 4. Digital and Analog Modules (continued)
Block
Mnemonic Block Name Domain1Subsystem Brief Description
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ESAI Enhanced
serial audio
interface
SDMA Connectivity
peripherals
The enhanced serial audio interface (ESAI) provides a full-duplex
serial port for serial communication with a variety of serial devices,
including industry-standard codecs, SPDIF transceivers, and other
DSPs. The ESAI consists of independent transmitter and receiver
sections, each section with its own clock generator.
eSDHCv2
(3)
Enhanced
secure digital
host controller
ARM Connectivity
peripherals
The eSDHCv2 consists of four main modules: CE-ATA, MMC, SD
and SDIO. CE-ATA is a hard drive interface that is optimized for
embedded applications of storage. The MultiMediaCard (MMC) is a
universal, low-cost, data storage and communication media to
applications such as electronic toys, organizers, PDAs, and smart
phones. The secure digital (SD) card is an evolution of MMC and is
specifically designed to meet the security, capacity, performance,
and environment requirements inherent in emerging audio and
video consumer electronic devices. SD cards are categorized into
Memory and I/O. A memory card enables a copyright protection
mechanism that complies with the SDMI security standard. SDIO
cards provide high-speed data I/O (such as wireless LAN via SDIO
interface) with low power consumption.
Note: CE-ATA is not available for the MCIMX351.
FEC Ethernet SDMA Connectivity
peripherals
The Ethernet media access controller (MAC) is designed to support
both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external
transceiver interface and transceiver function are required to
complete the interface to the media
GPIO(3) General
purpose I/O
modules
ARM Pins Used for general purpose input/output to external ICs. Each GPIO
module supports 32 bits of I/O.
GPT General
purpose timers
ARM Timer
peripherals
Each GPT is a 32-bit free-running or set-and-forget mode timer with
a programmable prescaler and compare and capture registers. A
timer counter value can be captured using an external event and can
be configured to trigger a capture event on either the leading or
trailing edges of an input pulse. When the timer is configured to
operate in set-and-forget mode, it is capable of providing precise
interrupts at regular intervals with minimal processor intervention.
The counter has output compare logic to provide the status and
interrupt at comparison. This timer can be configured to run either
on an external clock or on an internal clock.
GPU2D Graphics
processing unit
2Dv1
ARM Multimedia
peripherals
This module accelerates OpenVG and GDI graphics.
Note: Not available for the MCIMX351.
Table 4. Digital and Analog Modules (continued)
Block
Mnemonic Block Name Domain1Subsystem Brief Description
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I2C(3) I2C module ARM ARM1136
platform
peripherals
Inter-integrated circuit (I2C) is an industry-standard, bidirectional
serial bus that provides a simple, efficient method of data exchange,
minimizing the interconnection between devices. I2C is suitable for
applications requiring occasional communications over a short
distance among many devices. The interface operates at up to
100 kbps with maximum bus loading and timing. The I2C system is
a true multiple-master bus, with arbitration and collision detection
that prevent data corruption if multiple devices attempt to control the
bus simultaneously. This feature supports complex applications with
multiprocessor control and can be used for rapid testing and
alignment of end products through external connections to an
assembly-line computer.
IIM IC
identification
module
ARM Security
modules
The IIM provides the primary user-visible mechanism for interfacing
with on-chip fuse elements. Among the uses for the fuses are
unique chip identifiers, mask revision numbers, cryptographic keys,
and various control signals requiring a fixed value.
IOMUX External
signals and pin
multiplexing
ARM Pins Each I/O multiplexer provides a flexible, scalable multiplexing
solution with the following features:
• Up to eight output sources multiplexed per pin
• Up to four destinations for each input pin
• Unselected input paths held at constant levels for reduced power
consumption
IPUv1 Image
processing unit
ARM Multimedia
peripherals
The IPU supports video and graphics processing functions. It also
provides the interface for image sensors and displays. The IPU
performs the following main functions:
• Preprocessing of data from the sensor or from the external
system memory
• Postprocessing of data from the external system memory
• Post-filtering of data from the system memory with support of the
MPEG-4 (both deblocking and deringing) and H.264 post-filtering
algorithms
• Displaying video and graphics on a synchronous (dumb or
memory-less) display
• Displaying video and graphics on an asynchronous (smart)
display
• Transferring data between IPU sub-modules and to/from the
system memory with flexible pixel reformatting
KPP Keypin port ARM Connectivity
peripherals
Can be used for either keypin matrix scanning or general purpose
I/O.
OSCAUD OSC audio
reference
oscillator
Analog Clock The OSCAUDIO oscillator provides a stable frequency reference for
the PLLs. This oscillator is designed to work in conjunction with an
external 24.576-MHz crystal.
OSC24M OSC24M
24-MHz
reference
oscillator
Analog Clock The signal from the external 24-MHz crystal is the source of the
CLK24M signal fed into USB PHY as the reference clock and to the
real time clock (RTC).
Table 4. Digital and Analog Modules (continued)
Block
Mnemonic Block Name Domain1Subsystem Brief Description
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MPLL
PPLL
Digital
phase-locked
loops
SDMA Clocks DPLLs are used to generate the clocks:
MCU PLL (MPLL)—programmable
Peripheral PLL (PPLL)—programmable
PWM Pulse-width
modulator
ARM ARM1136
platform
peripherals
The pulse-width modulator (PWM) is optimized to generate sound
from stored sample audio images; it can also generate tones.
RTC Real-time
clock
ARM Clocks Provides the ARM1136 platform with a clock function (days, hours,
minutes, seconds) and includes alarm, sampling timer, and minute
stopwatch capabilities.
SDMA Smart DMA
engine
SDMA System
controls
The SDMA provides DMA capabilities inside the processor. It is a
shared module that implements 32 DMA channels and has an
interface to connect to the ARM1136 platform subsystem, EMI
interface, and the peripherals.
SJC Secure JTAG
controller
ARM Pins The secure JTAG controller (SJC) provides debug and test control
with maximum security.
SPBA SDMA
peripheral bus
arbiter
SDMA System
controls
The SPBA controls access to the SDMA peripherals. It supports
shared peripheral ownership and access rights to an owned
peripheral.
S/PDIF Serial audio
interface
SDMA Connectivity
peripherals
Sony/Philips digital transceiver interface
SSI(2) Synchronous
serial interface
SDMA,
ARM(2)
Connectivity
peripherals
The SSI is a full-duplex serial port that allows the processor
connected to it to communicate with a variety of serial protocols,
including the Freescale Semiconductor SPI standard and the I2C
sound (I2S) bus standard. The SSIs interface to the AUDMUX for
flexible audio routing.
UART(3) Universal
asynchronous
receiver/trans
mitters
ARM
(UART1,2)
SDMA
(UART3)
Connectivity
peripherals
Each UART provides serial communication capability with external
devices through an RS-232 cable using the standard RS-232
non-return-to-zero (NRZ) encoding format. Each module transmits
and receives characters containing either 7 or 8 bits
(program-selectable). Each UART can also provide low-speed IrDA
compatibility through the use of external circuitry that converts
infrared signals to electrical signals (for reception) or transforms
electrical signals to signals that drive an infrared LED (for
transmission).
USBOH High-speed
USB on-the-go
SDMA Connectivity
peripherals
The USB module provides high performance USB on-the-go (OTG)
functionality (up to 480 Mbps), compliant with the USB 2.0
specification, the OTG supplement, and the ULPI 1.0 low pin count
specification. The module has DMA capabilities handling data
transfer between internal buffers and system memory.
WDOG Watchdog
modules
ARM Timer
peripherals
Each module protects against system failures by providing a method
of escaping from unexpected events or programming errors. Once
activated, the timer must be serviced by software on a periodic
basis. If servicing does not take place, the watchdog times out and
then either asserts a system reset signal or an interrupt request
signal, depending on the software configuration.
Table 4. Digital and Analog Modules (continued)
Block
Mnemonic Block Name Domain1Subsystem Brief Description
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3 Signal Descriptions: Special Function Related Pins
Some special functional requirements are supported in the device. The details about these special functions
and the corresponding pin names are listed in Table 5.
4 Electrical Characteristics
The following sections provide the device-level and module-level electrical characteristics for the i.MX35
processor.
4.1 i.MX35 Chip-Level Conditions
This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference
to the individual tables and sections.
1ARM = ARM1136 platform, SDMA = SDMA platform
Table 5. Special Function Related Pins
Function Name Pin Name Mux Mode Detailed Description
External ARM Clock EXT_ARMCLK ALT0 External clock input for ARM clock.
External Peripheral Clock I2C1_CLK ALT6 External peripheral clock source.
External 32-kHz Clock CAPTURE ALT4 External clock input of 32 kHz, used when the internal
24M Oscillator is powered off, which could be
configured either from CAPTURE or CSPI1_SS1.
CSPI1_SS1 ALT2
Clock Out CLKO ALT0 Clock-out pin from CCM, clock source is controllable
and can also be used for debug.
Power Ready GPIO1_0 ALT1 PMIC power-ready signal, which can be configured
either from GPIO1_0 or TX1.
TX1 ALT1
Tamper Detect GPIO1_1 ALT6 Tamper-detect logic is used to issue a security
violation. This logic is activated if the tamper-detect
input is asserted. Tamper-detect logic is enabled by the
bit of IOMUXC_GPRA[2]. After enabling the logic, it is
impossible to disable it until the next reset.
Table 6. i.MX35 Chip-Level Conditions
Characteristics Table/Location
Absolute Maximum Ratings Table 7 on page 13
i.MX35 Operating Ranges Table 8 on page 13
Interface Frequency Table 9 on page 14
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 13
CAUTION
Stresses beyond those listed in Table 7 may cause permanent damage to the
device. These are stress ratings only. Functional operation of the device at
these or any other conditions beyond those indicated in Table 8 is not
implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
4.1.1 i.MX35 Operating Ranges
Table 8 provides the recommended operating ranges. The term NVCC in this section refers to the
associated supply rail of an input or output.
Table 7. Absolute Maximum Ratings
Parameter Symbol Min. Max. Units
Supply voltage (core) VDDmax1
1VDD is also known as QVCC.
–0.5 1.47 V
Supply voltage (I/O) NVCCmax –0.5 3.6 V
Input voltage range VImax –0.5 3.6 V
Storage temperature Tstorage –40 125 oC
ESD damage immunity: Vesd V
Human Body Model (HBM) — 20002
2HBM ESD classification level according to the AEC-Q100-002 standard
Charge Device Model (CDM) — 5003
3Corner pins max. 750 V
Table 8. i.MX35 Operating Ranges
Parameter Symbol Min. Typical Max. Units
Core Operating Voltage
0 < fARM < 400 MHz
VDD 1.22 — 1.47 V
Core Operating Voltage
0 < fARM < 532 MHz
1.33 — 1.47 V
State Retention Voltage 1 — — V
EMI1NVCC_EMI1,2,3 1.7 — 3.6 V
WTDG, Timer, CCM, CSPI1 NVCC_CRM 1.75 — 3.6 V
NANDF NVCC_NANDF 1.75 — 3.6 V
ATA, USB generic NVCC_ATA 1.75 — 3.6 V
eSDHC1 NVCC_SDIO 1.75 — 3.6 V
CSI, SDIO2 NVCC_CSI 1.75 — 3.6 V
JTAG NVCC_JTAG 1.75 — 3.6 V
LCDC, TTM, I2C1 NVCC_LCDC 1.75 — 3.6 V
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor14
4.1.2 Interface Frequency Limits
Table 9 provides information on interface frequency limits.
I2Sx2,ESAI, I2C2, UART2, UART1, FEC NVCC_MISC 1.75 — 3.6 V
MLB NVCC_MLB21.75 — 3.6 V
USB OTG PHY PHY1_VDDA 3.17 3.3 3.43 V
USB OTG PHY USBPHY1_VDDA_BIAS 3.17 3.3 3.43 V
USB OTG PHY USBPHY1_UPLLVDD 3.17 3.3 3.43 V
USB HOST PHY PHY2_VDD 3.0 3.3 3.6 V
OSC24M OSC24M_VDD 3.0 3.3 3.6 V
OSC_AUDIO OSC_AUDIO_VDD 3.0 3.3 3.6 V
MPLL MVDD 1.4 — 1.65 V
PPLL PVDD 1.4 — 1.65 V
Fusebox program supply voltage FUSE_VDD33.0 3.6 3.6 V
Operating Ambient Temperature Range TA–20 — 70 oC
Operating Ambient Temperature Range TA–40 — 85 oC
1EMI I/O interface power supply should be set up according to external memory. For example, if using SDRAM then
NVCC_EMI1,2,3 should all be set at 3.3 V (typ.). If using MDDR or DDR2, NVC_EMI1,2,3 must be set at 1.8 V (typ.).
2MLB Interface I/O pins can be programmed to function as GPIO for the consumer and industrial parts by setting NVCC_MLB
to 1.8 or 3.3 V. NVCC_MLB can be left floating.
3The Fusebox read supply is connected to supply of the full speed USB PHY. FUSE_VDD is only used for programming. It is
recommended that FUSE_VDD be connected to ground when not being used for programming. FUSE_VDD should be
supplied by following the power up sequence given in Section 4.3.1, “Powering Up.”
Table 9. Interface Frequency
ID Parameter Symbol Min. Typ. Max. Units
1 JTAG TCK Frequency fJTAG DC 5 10 MHz
Table 8. i.MX35 Operating Ranges (continued)
Parameter Symbol Min. Typical Max. Units
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 15
4.2 Power Modes
Table 10 provides descriptions of the power modes of the i.MX35 processor.
Table 10. i.MX35 Power Modes
Power
Mode Description
QVCC (ARM/L2
Peripheral) MVDD/PVDD OSC24M_VDD
OSC_AUDO_VDD
Typ. Max. Typ. Max. Typ. Max.
Wait VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is active.
L2 cache is kept powered.
MCU PLL is on (400 MHz)
PER PLL is off (can be configured)
(default: 300 MHz)
Module clocks are gated off (can be
configured by CGR register).
OSC 24M is ON.
OSC audio is off (can be configured).
RNGC internal osc is off.
16 mA — 7.2 mA —1.2 mA —
Doze VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted.
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is on(400 MHz)
PER PLL is off (can be configured).
(300 Mhz).
Module clocks are gated off (can be
configured by CGR register).
OSC 24M is ON.
OSC audio is off (can be configured)
RNGC internal osc is off
12.4mA — 7.2mA — 1.2mA —
Stop VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is off.
PER PLL is off.
All clocks are gated off.
OSC 24 MHz is on
OSC audio is off
RNGC internal osc is off
1.1 mA — 400 µA — 1.2 mA —
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor16
4.3 Supply Power-Up/Power-Down Requirements and Restrictions
This section provides power-up and power-down sequence guidelines for the i.MX35 processor.
CAUTION
Any i.MX35 board design must comply with the power-up and power-down
sequence guidelines as described in this section to guarantee reliable
operation of the device. Any deviation from these sequences can result in
irreversible damage to the i.MX35 processor (worst-case scenario).
NOTE
Deviation from these sequences may also result in one or more of the
following:
• Excessive current during power-up phase
• Prevent the device from booting
• Programming of unprogrammed fuses
4.3.1 Powering Up
The power-up sequence should be completed as follows:
1. Assert Power on Reset (POR).
2. Turn on digital logic domain and IO power supply: VDDn, NVCCx
3. Wait until VDDn and NVCCx power supplies are stable + 32 μs.
Static VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is off.
PER PLL is off.
All clocks are gated off.
OSC 24MHz is on
OSC audio is off
RNGC internal osc is off
820 µA — 50 µA — 24 µA —
Note: Typical column: TA = 25 °C
Table 10. i.MX35 Power Modes (continued)
Power
Mode Description
QVCC (ARM/L2
Peripheral) MVDD/PVDD OSC24M_VDD
OSC_AUDO_VDD
Typ. Max. Typ. Max. Typ. Max.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 17
4. Turn on all other power supplies: PHY1_VDDA, USBPHY1_VDDA_BIAS, PHY2_VDD,
USBPHY1_UPLLVDD, OSC24M_VDD, OSC_AUDIO_VDD, MVDD, PVDD, FUSEVDD.
(Always FUSE_VDD should be connected to ground, except when eFuses are to be
programmed.)
5. Wait until PHY1_VDDA, USBPHY1_VDDA_BIAS, PHY2_VDD, USBPHY1_UPLLVDD,
OSC24M_VDD, OSC_AUDIO_VDD, MVDD, PVDD, (FUSEVDD, optional). Power supplies
are stable + 100 μs.
6. Deassert the POR signal.
Figure 2 shows the power-up sequence and timing.
Figure 2. i.MX35 Power-Up Sequence and Timing
4.3.2 Powering Down
The power-up sequence in reverse order is recommended for powering down. However, all power supplies
can be shut down at the same time.
4.4 Reset Timing
There are two ways of resetting the i.MX35 using external pins:
• Power On Reset (using the POR_B pin)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor18
• System Reset (using the RESET_IN_B pin)
4.4.1 Power On Reset
POR_B is normally connected to a power management integrated circuit (PMIC). The PMIC asserts
POR_B while the power supplies are turned on and negates POR_B after the power up sequence is
finished. See Figure 2.
Assuming the i.MX35 chip is already fully powered; it is still possible to reset all of the modules to their
default reset by asserting POR_B for at least 4 CKIL cycles and later de-asserting POR_B. This method
of resetting the i.MX35 can also be supported by tying the POR_B and RESET_IN_B pins together.
Figure 3. Timing Between POR_B and CKIL for Complete Reset of i.MX35
4.4.2 System Reset
System reset can be achieved by asserting RESET_IN_B for at least 4 CKIL cycles and later negating
RESET_IN_B. The following modules are not reset upon system reset: RTC, PLLs, CCM, and IIM.
POR_B pin must be deasserted all the time.
Figure 4. Timing Between RESET_IN_B and CKIL for i.MX35 System Reboot
4.5 Power Characteristics
The table shows values representing maximum current numbers for the i.MX35 under worst case voltage
and temperature conditions. These values are derived from the i.MX35 with core clock speeds up to
POR_B
CKIL
At leas t 4 CKIL cycles
RESET_IN_B
CKIL
At least 4 CKIL cycles
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 19
532 MHz. Common supplies have been bundled according to the i.MX35 power-up sequence
requirements. Peak numbers are provided for system designers so that the i.MX35 power supply
requirements will be satisfied during startup and transient conditions. Freescale recommends that system
current measurements be taken with customer-specific use-cases to reflect normal operating conditions in
the end system.
The method for obtaining max current is as follows:
1. Measure worst case power consumption on individual rails using directed test on i.MX35.
2. Correlate worst case power consumption power measurements with worst case power
consumption simulations.
3. Combine common voltage rails based on power supply sequencing requirements
4. Guard band worst case numbers for temperature and process variation. Guard band is based on
process data and correlated with actual data measured on i.MX35.
5. The sum of individual rails is greater than real world power consumption, as a real system does
not typically maximize power consumption on all peripherals simultaneously.
4.6 Thermal Characteristics
The thermal resistance characteristics for the device are given in Table 12. These values were measured
under the following conditions:
• Two-layer substrate
• Substrate solder mask thickness: 0.025 mm
• Substrate metal thicknesses: 0.016 mm
• Substrate core thickness: 0.200 mm
• Core via I.D: 0.168 mm, Core via plating 0.016 mm.
• Full array map design, but nearly all balls under die are power or ground.
• Die Attach: 0.033 mm non-conductive die attach, k = 0.3 W/m K
• Mold compound: k = 0.9 W/m K
Table 11. Power Consumption
Power Supply Voltage (V) Max Current (mA)
QVCC 1.47 400
MVDD, PVDD 1.65 20
NVCC_EMI1, NVCC_EMI2, NVCC_EMI3, NVCC_LCDC, NVCC_NFC 1.9 90
FUSE_VDD1
1This rail is connected to ground; it only needs a voltage if eFuses are to be programmed. FUSE_VDD should be supplied by
following the power up sequence given in Section 4.3.1, “Powering Up.”
3.6 62
NVCC_MISC, NVCC_CSI, NVCC_SDIO, NVCC_CRM, NVCC_ATA, NVCC_MLB,
NVCC_JTAG
3.6 60
OSC24M_VDD, OSC_AUDIO_VDD, PHY1_VDDA, PHY2_VDD,
USBPHY1_UPLLVDD, USBPHY1_VDDA_BIAS
3.6 25
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor20
4.7 I/O Pin DC Electrical Characteristics
I/O pins are of two types: GPIO and DDR. DDR pins can be configured in three different drive strength
modes: mobile DDR, SDRAM, and DDR2. The SDRAM and mobile DDR modes can be further
customized at three drive strength levels: normal, high, and max.
Table 13 shows currents for the different DDR pin drive strength modes.
Table 12. Thermal Resistance Data
Rating Condition Symbol Value Unit
Junction to ambient1 natural convection
1Junction-to-ambient thermal resistance determined per JEDC JESD51-3 and JESD51-6. Thermal test board meets JEDEC
specification for this package.
Single layer board (1s) ReJA 53 ºC/W
Junction to ambient1 natural convection Four layer board (2s2p) ReJA 30 ºC/W
Junction to ambient1 (at 200 ft/min) Single layer board (1s) ReJMA 44 ºC/W
Junction to ambient1 (at 200 ft/min) Four layer board (2s2p) ReJMA 27 ºC/W
Junction to boards2
2Junction-to-board thermal resistance determined per JEDC JESD51-8. Thermal test board meets JEDEC specification for this
package.
—R
eJB 19 ºC/W
Junction to case (top)3
3Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used
for the case temperature. Reported value includes the thermal resistance of the interface layer.
—R
eJCtop 10 ºC/W
Junction to package top4
4Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, this thermal characterization parameter is written
as Psi-JT.
Natural convection ΨJT 2ºC/W
Table 13. DDR Pin Drive Strength Mode Current Levels
Drive Mode Normal High Max.
Mobile DDR (1.8 V) 3.6 mA 7.2 mA 10.8 mA
SDRAM (1.8 V) — — 6.5 mA
SDRAM (3.3 V) 4 mA 8 mA 12 mA
DDR2 (1.8 V) — — 13.4 mA
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 21
Table 14 shows the DC electrical characteristics for GPIO, DDR2, mobile DDR, and SDRAM pins. The
term NVCC refers to the power supply voltage that feeds the I/O of the module in question. For example,
NVCC for the SD/MMC interface refers to NVCC_SDIO.
Table 14. I/O Pin DC Electrical Characteristics
Pin DC Electrical Characteristics Symbol Test Condition Min. Typ. Max. Unit
GPIO High-level output voltage Voh Ioh = –1 mA
Ioh = specified drive
NVCC – 0.15
0.8 ×NVCC
—— V
Low-level output voltage Vol Iol = 1 mA
Iol = specified drive
——0.15
0.2 ×NVCC
V
High-level output current for
slow mode
(Voh = 0.8 ×NVCC)
Ioh Standard drive
High drive
Max. drive
–2.0
–4.0
–8.0
——mA
High-level output current
for fast mode
(Voh = 0.8 ×NVCC)
Ioh Standard drive
High drive
Max. drive
–4.0
–6.0
–8.0
——mA
Low-level output current
for slow mode
(Voh = 0.2 ×NVCC)
Iol Standard drive
High drive
Max. drive
2.0
4.0
8.0
——mA
Low-level output current
for fast mode
(Voh = 0.2 ×NVCC)
Iol Standard drive
High drive
Max. drive
4.0
6.0
8.0
——mA
High-level DC Input
Voltage with 1.8 V,
3.3 V NVCC (for digital
cells in input mode)
VIH — 0.7 ×NVCC — NVCC V
Low-level DC Input
Voltage with 1.8 V,
3.3 V NVCC (for digital
cells in input mode
VIL — –0.3 V — 0.3 ×NVCC V
Input Hysteresis VHYS OVDD = 3.3 V
OVDD = 1.8 V
—410
330
—mV
Schmitt trigger VT+ VT+ — 0.5 ×NVCC — V
Schmitt trigger VT– VT– — — — 0.5 ×NVCC V
Pull-up resistor
(22 kΩ PU)
Rpu Vi = 0 — 22 — kΩ
Pull-up resistor
(47 kΩ PU)
Rpu Vi = 0 — 47 — kΩ
Pull-up resistor
(100 kΩPU)
Rpu Vi = 0 — 100 — kΩ
Pull-down resistor (100 kΩPD) Rpd Vi = NVCC — 100 — kΩ
External resistance to pull
keeper up when enabled
Rkpu Ipu > 620 μA
@ min Vddio = 3.0 V
——4.8kΩ
External resistance to pull
keeper down when enabled
Rkpd Ipu > 510 μA
@min Vddio = 3.0 V
——5.9kΩ
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor22
DDR2 High-level output voltage Voh — NVCC – 0.28 — — V
Low-level output voltage Vol — — 0.28 V
Output min. source current Ioh — –13.4 — — mA
Output min. sink current Iol — 13.4 — — mA
DC input logic high VIH(dc) — NVCC ÷2+
0.125
—NVCC+0.3 V
DC input logic low VIL(dc) — –0.3 V — NVCC ÷2–
0.125
V
DC input signal voltage
(for differential signal)
Vin(dc) — –0.3 — NVCC + 0.3 V
DC differential input voltage Vid(dc) — 0.25 — NVCC + 0.6 V
Termination voltage Vtt — NVCC ÷2–
0.04
NV
CC
÷2
NVCC ÷2+
0.04
V
Input current (no
pull-up/down)
IIN — — — ±1 μA
Tri-state I/O supply current Icc – N
VCC
———±1μA
Mobile
DDR
High-level output voltage — IOH = –1mA
IOH = specified drive
NVCC – 0.08
0.8 ×NVCC
—— V
Low-level output voltage — IOL = 1mA
IOL = specified drive
——0.08
0.2 ×NVCC
V
High-level output current
(Voh = 0.8 ×NVCCV)
— Standard drive
High drive
Max. drive
–3.6
–7.2
–10.8
——mA
Low-level output current
(Vol = 0.2 ×NVCCV)
— Standard Drive
High Drive
Max. Drive
3.6
7.2
10.8
——mA
High-Level DC CMOS
input voltage
VIH — 0.7 ×NVCC — NVCC + 0.3 V
Low-Level DC CMOS
input voltage
VIL — –0.3 — 0.2 ×NVCC V
Differential receiver VTH+ VTH+ — — — 100 mV
Differential receiver VTH– VTH– — –100 — mV
Input current (no
pull-up/down)
IIN VI = 0
VI = NVCC
——±1μA
Tri-state I/O supply current Icc – N
VCC
VI = NVCC or 0 — — ±1 μA
Table 14. I/O Pin DC Electrical Characteristics (continued)
Pin DC Electrical Characteristics Symbol Test Condition Min. Typ. Max. Unit
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 23
4.8 I/O Pin AC Electrical Characteristics
Figure 5 shows the load circuit for output pins.
Figure 5. Load Circuit for Output Pin
SDR
(1.8 V)
High-level output voltage Voh loh = 5.7 mA OVDD – 0.28 — — V
Low-level output voltage Vol loh = 5.7 mA — — 0.4 V
High-level output current Ioh Max. drive 5.7 — — mA
Low-level output current Iol Max. drive 7.3 — — mA
High-level DC Input Voltage VIH — 1.4 — 1.98 V
Low-level DC Input Voltage VIL — –0.3 — 0.8 V
Input current (no
pull-up/down)
IIN VI = 0
VI=NVCC
——150
80
μA
Tri-state I/O supply current Icc
(NVCC)
VI = OVDD or 0 — — 1180 μA
Tri-state core supply current Icc
(NVCC)
VI = VDD or 0 — — 1220 μA
SDR
(3.3 V)
High-level output voltage Voh Ioh=specified drive
(Ioh = –4, –8, –12,
–16 mA)
2.4 — — V
Low-level output voltage Vol Ioh=specified drive (Ioh = 4,
8, 12, 16 mA)
——0.4V
High-level output current Ioh Standard drive
High drive
Max. drive
–4.0
–8.0
–12.0
——mA
Low-level output current Iol Standard drive
High drive
Max. drive
4.0
8.0
12.0
——mA
High-level DC Input Voltage VIH — 2.0 — 3.6 V
Low-level DC Input Voltage VIL — –0.3V — 0.8 V
Input current (no
pull-up/down)
IIN VI = 0
VI = NVCC
——±1μA
Tri-state I/O supply current Icc
(NVCC)
VI = NVCC or 0 — — ±1 μA
Table 14. I/O Pin DC Electrical Characteristics (continued)
Pin DC Electrical Characteristics Symbol Test Condition Min. Typ. Max. Unit
Test Point
From Output
Under Test CL
CL includes package, probe and jig capacitance
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor24
Figure 6 shows the output pin transition time waveform.
Figure 6. Output Pin Transition Time Waveform
4.8.1 AC Electrical Test Parameter Definitions
AC electrical characteristics in Table 16 through Table 21 are not applicable for the output open drain
pull-down driver.
The dI/dt parameters are measured with the following methodology:
• The zero voltage source is connected between pin and load capacitance.
• The current (through this source) derivative is calculated during output transitions.
Table 15. AC Requirements of I/O Pins
Parameter Symbol Min. Max. Units
AC input logic high VIH(ac) NVCC ÷2 + 0.25 NVCC + 0.3 V
AC input logic low VIL(ac) –0.3 NVCC ÷2 – 0.25 V
Table 16. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode
[NVCC = 3.0 V–3.6 V]
Parameter Symbol Test
Condition
Min.
Rise/Fall Typ. Rise/Fall Max.
Rise/Fall Units
Duty cycle Fduty — 40 — 60 %
Output pin slew rate (max. drive) tps 25 pF
50 pF
0.79/1.12
0.49/0.73
1.30/1.77
0.84/1.23
2.02/2.58
1.19/1.58
V/ns
Output pin slew rate (high drive) tps 25 pF
50 pF
0.48/0.72
0.27/0.42
0.76/1.10
0.41/0.62
1.17/1.56
0.63/0.86
V/ns
Output pin slew rate (standard
drive)
tps 25 pF
50 pF
0.25/0.40
0.14/0.21
0.40/0.59
0.21/0.32
0.60/0.83
0.32/0.44
V/ns
Output pin di/dt (max. drive) tdit 25 pF
50 pF
15
16
36
38
76
80
mA/ns
Output pin di/dt (high drive) tdit 25 pF
50 pF
8
9
20
21
45
47
mA/ns
Output pin di/dt (standard
drive)
tdit 25 pF
50 pF
4
4
10
10
22
23
mA/ns
0V
NVCC
20%
80% 80%
20%
PA 1 PA 1
Output (at pin)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 25
Table 17. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode
[NVCC = 1.65 V–1.95 V]
Parameter Symbol Test Condition Min.
Rise/Fall Typ. Max.
Rise/Fall Units
Duty cycle Fduty — 40 — 60 %
Output pin slew rate (max. drive) tps 25 pF
50 pF
0.30/0.42
0.20/0.29
0.54/0.73
0.35/0.50
0.91/1.20
0.60/0.80
V/ns
Output pin slew rate (high drive) tps 25 pF
50 pF
0.19/0.28
0.12/0.18
0.34/0.49
0.34/0.49
0.58/0/79
0.36/0.49
V/ns
Output pin slew rate (standard drive) tps 25 pF
50 pF
0.12/0.18
0.07/0.11
0.20/0.30
0.11/0.17
0.34/0.47
0.20/0.27
V/ns
Output pin di/dt (max. drive) tdit 25 pF
50 pF
7
7
21
22
56
58
mA/ns
Output pin di/dt (high drive) tdit 25 pF
50 pF
5
5
14
15
38
40
mA/ns
Output pin di/dt (standard
drive)
tdit 25 pF
50 pF
2
2
7
7
18
19
mA/ns
Table 18. AC Electrical Characteristics of GPIO Pins in Fast Slew Rate Mode for
[NVCC = 3.0 V–3.6 V]
Parameter Symbol Test Condition Min.
rise/fall Typ. Max.
Rise/Fall Units
Duty cycle Fduty — 40 — 60 %
Output pin slew rate (max. drive) tps 25 pF
50 pF
0.96/1.40
0.54/0.83
1.54/2.10
0.85/1.24
2.30/3.00
1.26/1.70
V/ns
Output pin slew rate (high drive) tps 25 pF
50 pF
0.76/1.10
0.41/0.64
1.19/1.71
0.63/0.95
1.78/2.39
0.95/1.30
V/ns
Output pin slew rate (standard drive) tps 25 pF
50 pF
0.52/0.78
0.28/0.44
0.80/1.19
0.43/0.64
1.20/1.60
0.63/0.87
V/ns
Output pin di/dt (max. drive) tdit 25 pF
50 pF
46
49
108
113
250
262
mA/ns
Output pin di/dt (high drive) tdit 25 pF
50 pF
35
37
82
86
197
207
mA/ns
Output pin di/dt (standard
drive)
tdit 25 pF
50 pF
22
23
52
55
116
121
mA/ns
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor26
Table 19. AC Electrical Characteristics, GPIO Pins in Fast Slew Rate Mode
[NVCC = 1.65 V–1.95 V]
Parameter Symbol Test Condition Min.
Rise/Fall Typ. Max.
Rise/Fall Units
Duty cycle Fduty — 40 — 60 %
Output pin slew rate (max. drive) tps 25 pF
50 pF
0.40/0.57
0.25/0.36
0.72/0.97
0.43/0.61
1.2/1.5
0.72/0.95
V/ns
Output pin slew rate (high drive) tps 25 pF
50 pF
0.38/0.48
0.20/0.30
0.59/0.81
0.34/0.50
0.98/1.27
0.56/0.72
V/ns
Output pin slew rate (standard drive) tps 25 pF
50 pF
0.23/0.32
0.13/0.20
0.40/0.55
0.23/0.34
0.66/0.87
0.38/0.52
V/ns
Output pin di/dt (max. drive) tdit 25 pF
50 pF
7
7
43
46
112
118
mA/ns
Output pin di/dt (high drive) tdit 25 pF
50 pF
11
12
31
33
81
85
mA/ns
Output pin di/dt (standard
drive)
tdit 25 pF
50 pF
9
10
27
28
71
74
mA/ns
Table 20. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode
[NVCC = 2.25 V–2.75 V]
Parameter Symbol Test Condition Min.
Rise/Fall Typ. Max.
Rise/Fall Units
Duty cycle Fduty — 40 — 60 %
Output pin slew rate (max. drive) tps 25 pF
40 pF
50 pF
0.63/0.85
0.52/0.67
0.41/0.59
1.10/1.40
0.90/1.10
0.73/0.99
1.86/2.20
1.53/1.73
1.20/1.50
V/ns
Output pin slew rate (high drive) tps 25 pF
40 pF
50 pF
0.40/0.58
0.33/0.43
0.25/0.37
0.71/0.98
0.56/0.70
0.43/0.60
1.16/1.40
0.93/1.07
0.68/0.90
V/ns
Output pin slew rate (standard drive) tps 25 pF
40 pF
50 pF
0.24/0.36
0.19/0.25
0.13/0.21
0.41/0.59
0.32/0.35
0.23/0.33
0.66/0.87
0.51/0.59
0.36/0.48
V/ns
Output pin di/dt (max. drive) tdit 25 pF
50 pF
22
23
62
65
148
151
mA/ns
Output pin di/dt (high drive) tdit 25 pF
50 pF
15
16
42
44
102
107
mA/ns
Output pin di/dt (standard
drive)
tdit 25 pF
50 pF
7
8
21
22
52
54
mA/ns
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 27
4.8.2 AC Electrical Characteristics for DDR Pins (DDR2, Mobile DDR, and
SDRAM Modes)
Table 21. AC Electrical Characteristics of GPIO Pins in Fast Slew Rate Mode
[NVCC = 2.25 V–2.75 V]
Parameter Symbol Test
Condition
Min.
Rise/Fall Typ. Max.
Rise/Fall Units Notes
Duty cycle Fduty — 40 — 60 % —
Output pin slew rate (max. drive) tps 25 pF
40 pF
50 pF
0.84/1.10
0.68/0.83
0.58/0.72
1.45/1.80
1.14/1.34
0.86/1.10
2.40/2.80
1.88/2.06
1.40/1.70
V/ns 2
Output pin slew rate (high drive) tps 25 pF
40 pF
50 pF
0.69/0.96
0.55/0.69
0.40/0.59
1.18/1.50
0.92/1.10
0.67/0.95
1.90/2.30
1.49/1.67
1.10/1.30
V/ns
Output pin slew rate (standard drive) tps 25 pF
40 pF
50 pF
0.24/0.36
0.37/0.47
0.13/0.21
0.80/1.00
0.62/0.76
0.45/0.65
1.30/1.60
1.00/1.14
0.70/0.95
V/ns
Output pin di/dt (max. drive) tdit 25 pF
50 pF
46
49
124
131
310
324
mA/ns 3
Output pin di/dt (high drive) tdit 25 pF
50 pF
33
35
89
94
290
304
mA/ns
Output pin di/dt (standard
drive)
tdit 25 pF
50 pF
28
29
75
79
188
198
mA/ns
Table 22. AC Electrical Characteristics of DDR Type IO Pins in DDR2 Mode
Parameter Symbol Test Condition Min.
Rise/Fall Typ. Max.
Rise/Fall Units
Duty cycle Fduty — 45 50 55 %
Clock frequency f — — 133 — MHz
Output pin slew rate tps 25 pF
50 pF
0.86/0.98
0.46/054
1.35/1.5
0.72/0.81
2.15/2.19
1.12/1.16
V/ns
Output pin di/dt tdit 25 pF
50 pF
65
70
157
167
373
396
mA/ns
Table 23. AC Requirements of DDR2 Pins
Parameter1
1The Jedec SSTL_18 specification (JESD8-15a) for an SSTL interface for class II operation supersedes any specification in this
document.
Symbol Min. Max. Units
AC input logic high VIH(ac) NVCC ÷2 + 0.25 NVCC + 0.3 V
AC input logic low VIL(ac) –0.3 NVCC ÷2 – 0.25 V
AC differential cross point voltage for output2Vox(ac) NVCC ÷2 – 0.125 NVCC ÷2 + 0.125 V
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor28
2The typical value of Vox(ac) is expected to be about 0.5 ×NVCC and Vox(ac) is expected to track variation in NVCC. Vox(ac)
indicates the voltage at which the differential output signal must cross. Cload = 25 pF.
Table 24. AC Electrical Characteristics of DDR Type IO Pins in mDDR Mode
Parameter Symbol Test Condition Min.
Rise/Fall Typ. Max.
Rise/Fall Units
Duty cycle Fduty — 45 50 55 %
Clock frequency f — — 133 — MHz
Output pin slew rate (max. drive) tps 25 pF
50 pF
0.80/0.92
0.43/0.50
1.35/1.50
0.72/0.81
2.23/2.27
1.66/1.68
V/ns
Output pin slew rate (high drive) tps 25 pF
50 pF
0.37/0.43
0.19/0.23
0.62/0.70
0.33/0.37
1.03/1.05
0.75/0.77
V/ns
Output pin slew rate (standard drive) tps 25 pF
50 pF
0.18/0.22
0.10/0.12
0.31/0.35
0.16/0.18
0.51/0.53
0.38/0.39
V/ns
Output pin di/dt (max. drive) tdit 25 pF
50 pF
64
69
171
183
407
432
mA/ns
Output pin di/dt (high drive) tdit 25 pF
50 pF
37
39
100
106
232
246
mA/ns
Output pin di/dt (standard drive) tdit 25 pF
50 pF
18
20
50
52
116
123
mA/ns
Table 25. AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode
Parameter Symbol Test Condition Min.
Rise/Fall
Min. Clock
Frequency
Max.
Rise/Fall Units
Clock frequency f — — 125 — MHz
Output pin slew rate (max. drive) tps 25 pF
50 pF
1.11/1.20
0.97/0.65
1.74/1.75
0.92/0.94
2.42/2.46
1.39/1.30
V/ns
Output pin slew rate (high drive) tps 25 pF
50 pF
0.76/0.80
0.40/0.43
1.16/1.19
0.61/0.63
1.76/1.66
0.93/0.87
V/ns
Output pin slew rate (standard drive) tps 25 pF
50 pF
0.38/0.41
0.20/0.22
0.59/0.60
0.31/0.32
0.89/0.82
0.47/0.43
V/ns
Output pin di/dt (max. drive) tdit 25 pF
50 pF
89
94
198
209
398
421
mA/ns
Output pin di/dt (high drive) tdit 25 pF
50 pF
59
62
132
139
265
279
mA/ns
Output pin di/dt (standard drive) tdit 25 pF
50 pF
29
31
65
69
132
139
mA/ns
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 29
4.9 Module-Level AC Electrical Specifications
This section contains the AC electrical information (including timing specifications) for the modules of
the i.MX35. The modules are listed in alphabetical order.
4.9.1 AUDMUX Electrical Specifications
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between
internal serial interfaces (SSI) and external serial interfaces (audio and voice codecs). The AC timing of
AUDMUX external pins is hence governed by the SSI module. See the electrical specification for SSI.
4.9.2 CSPI AC Electrical Specifications
The i.MX35 provides two CSPI modules. CSPI ports are multiplexed in the i.MX35 with other pins. See
the “External Signals and Multiplexing” chapter of the reference manual for more details.
Table 26. AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive (1.8 V)
Parameter Symbol Test Condition Min.
Rise/Fall Typ. Max.
Rise/Fall Units
Clock frequency f — 125 — — MHz
Output pin slew rate (max. drive)1
1Min. condition for tps: wcs model, 1.1 V, IO 1.65 V, and 105 °C. tps is measured between VIL to VIH for rising edge and between
VIH to VIL for falling edge.
tps 25 pF
50 pF
2.83/2.68
1.59/1.49
1.84/1.85
1.03/1.05
1.21/1.40
0.70/0.75
V/ns
Output pin di/dt (max. drive)2
2Max. condition for tdit: bcs model, 1.3 V, IO 1.95 V, and –40 °C.
didt 25 pF
50 pF
89
95
202
213
435
456
mA/ns
Input pin transition times3
3Max. condition for tpi and trfi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Min. condition for tpi and trfi: bcs model, 1.3 V, IO 1.95V
and –40 °C. Input transition time from pad is 5 ns (20%–80%).
trfi 1.0 pF 0.07/0.08 0.11/0.12 0.16/0.20 ns
Input pin propagation delay, 50%–50% tpi 1.0 pF 0.35/1.17 0.63/1.53 1.16/2.04 ns
Input pin propagation delay, 40%–60% tpi 1.0 pF 1.18/1.99 1.45/2.35 1.97/2.85 ns
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor30
Figure 7 and Figure 8 depict the master mode and slave mode timings of the CSPI, and Table 27 lists the
timing parameters.
Figure 7. CSPI Master Mode Timing Diagram
Figure 8. CSPI Slave Mode Timing Diagram
Table 27. CSPI Interface Timing Parameters
ID Parameter Symbol Min. Max. Units
CS1 SCLK cycle time tclk 60 — ns
CS2 SCLK high or low time tSW 30 — ns
CS3 SCLK rise or fall tRISE/FALL —7.6ns
CS4 SSn[3:0] pulse width tCSLH 30 — ns
CS5 SSn[3:0] lead time (CS setup time) tSCS 30 — ns
CS6 SSn[3:0] lag time (CS hold time) tHCS 30 — ns
CS7 MOSI setup time tSmosi 5—ns
CS8 MOSI hold time tHmosi 5—ns
CS9 MISO setup time tSmiso 5—ns
CS1
CS7 CS8
CS2
CS2
CS4
CS6 CS5
CS9 CS10
SCLK
SSn[3:0]
MOSI
MISO
SPI_RDY CS11
CS3 CS3
CS7 CS8
CS2
CS2
CS4
CS6
CS9 CS10
SCLK
SSn[3:0]
MISO
MOSI
CS1 CS3
CS3
CS5
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 31
4.9.3 DPLL Electrical Specifications
There are three PLLs inside the i.MX35, all based on the same PLL design. The reference clock for these
PLLs is normally generated from an external 24-MHz crystal connected to an internal oscillator via
EXTAL24M and XTAL24 pins. It is also possible to connect an external 24-MHz clock directly to
EXTAL24M, bypassing the internal oscillator.
DPLL specifications are listed in Table 28.
If crystals are used instead of external oscillators, they should meed the following specifications:
CS10 MISO hold time tHmiso 5—ns
CS11 SPI_RDY setup time tSDRY 5—ns
Table 28. DPLL Specifications
Parameter Min. Typ. Max. Unit Comments
Reference clock frequency 10 24 100 MHz
Max. allowed reference clock phase noise — — 0.03
0.01
0.15
2 Tdck1
1There are two PLL are used in the i.MX35, MPLL and PPLL. Both are based on same DPLL design.
Fmodulation < 50 kHz
50 kHz < Fmodulation 300 Hz
Fmodulation > 300 KHz
Frequency lock time (FOL mode or non-integer MF) — — 80 μs—
Phase lock time — — 100 μs—
Max. allowed PL voltage ripple — — 150
100
150
mV Fmodulation < 50 kHz
50 kHz < Fmodulation 300 Hz
Fmodulation > 300 KHz
Table 29. Clock Input Tolerance
Parameters OSC24M OSC_AUDIO
Normal Frequency 24 MHz 25.576 MHz
Frequency Tolerance 30 ppm 20 ppm (high quality)
ESR <80 Ω<80 Ω
Load Capacitance 8 pF-12 pF 8 pF-12 pF
Shunt capacitance <7 pF <7 pF
Level of drive >150 μW >150 μW
Table 27. CSPI Interface Timing Parameters (continued)
ID Parameter Symbol Min. Max. Units
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor32
4.9.4 Embedded Trace Macrocell (ETM) Electrical Specifications
ETM is an ARM protocol. The timing specifications in this section are given as a guide for a test point
access (TPA) that supports TRACECLK frequencies up to 133 MHz.
Figure 9 depicts the TRACECLK timings of ETM, and Table 30 lists the timing parameters.
Figure 9. ETM TRACECLK Timing Diagram
Figure 10 depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and
Table 31 lists the timing parameters.
Figure 10. Trace Data Timing Diagram
4.9.4.1 Half-Rate Clocking Mode
When half-rate clocking is used, the trace data signals are sampled by the TPA on both the rising and falling
edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in Figure 10. The same
Ts and Th parameters from Table 31 still apply with respect to the falling edge of the TRACECLK signal.
Table 30. ETM TRACECLK Timing Parameters
ID Parameter Min. Max. Unit
Tcyc Clock period Frequency dependent — ns
Twl Low pulse width 2 — ns
Twh High pulse width 2 — ns
TrClock and data rise time — 3 ns
TfClock and data fall time — 3 ns
Table 31. ETM Trace Data Timing Parameters
ID Parameter Min. Max. Unit
TsData setup 2 — ns
ThData hold 1 — ns
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 33
4.9.5 EMI Electrical Specifications
This section provides electrical parametrics and timing for the EMI module.
4.9.5.1 NAND Flash Controller Interface (NFC)
The i.MX35 NFC supports normal timing mode, using two flash clock cycles for one access of RE and
WE. AC timings are provided as multiplications of the clock cycle and fixed delay. Figure 11, Figure 12,
Figure 13, and Figure 14 depict the relative timing requirements among different signals of the NFC at
module level for normal mode. Table 32 lists the timing parameters.
Figure 11. Command Latch Cycle Timing DIagram
Figure 12. Address Latch Cycle Timing DIagram
NFCLE
NFCE
NFWE
NFALE
NFIO[7:0] Command
NF9
NF8
NF1 NF2
NF5
NF3 NF4
NF6 NF7
NFCLE
NFCE
NFWE
NFALE
NFIO[7:0] Address
NF9
NF8
NF1
NF5
NF3 NF4
NF6
NF11
NF10
NF7
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor34
Figure 13. Write Data Latch Cycle Timing DIagram
Figure 14. Read Data Latch Cycle Timing DIagram
Table 32. NFC Timing Parameters1
ID Parameter Symbol
Timing
T = NFC Clock Cycle2
Example Timing for
NFC Clock ≈ 33 MHz
T = 30 ns Unit
Min. Max. Min. Max.
NF1 NFCLE setup time tCLS T – 4.0 ns — 26 — ns
NF2 NFCLE hold time tCLH T – 5.0 ns — 25 — ns
NF3 NFCE setup time tCS T – 2.0 ns — 28 — ns
NF4 NFCE hold time tCH T – 1.0 ns — 29 — ns
NFCLE
NFCE
NFWE
NFALE
NFIO[15:0] Data to NF
NF9
NF8
NF1
NF5
NF3
NF6
NF11
NF10
NF7
NFCLE
NFCE
NFRE
NFRB
NFIO[15:0] Data from NF
NF13
NF15
NF14
NF17
NF12
NF16
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 35
NOTE
High is defined as 80% of signal value and low is defined as 20% of signal
value.
Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is
approximately 33 MHz (30 ns). All timings are listed according to this NFC
clock frequency (multiples of NFC clock phases), except NF16 and NF17,
which are not NFC clock related.
4.9.5.2 Wireless External Interface Module (WEIM)
All WEIM output control signals may be asserted and deasserted by internal clocks related to the BCLK
rising edge or falling edge according to the corresponding assertion or negation control fields. The address
always begins related to BCLK falling edge but may be ended both on rising and falling edge in muxed
mode according to control register configuration. Output data begins related to BCLK rising edge except
in muxed mode where both rising and falling edge may be used according to control register configuration.
NF5 NF_WP pulse width tWP T – 1.0 ns 29 ns
NF6 NFALE setup time tALS T – 4.0 ns — 26 — ns
NF7 NFALE hold time tALH T – 4.5 ns — 25.5 — ns
NF8 Data setup time tDS T – 2.0 ns — 28 — ns
NF9 Data hold time tDH T – 5.0 ns — 25 — ns
NF10 Write cycle time tWC 2T – 3.0 ns 57 ns
NF11 NFWE hold time tWH T – 5.0 ns 25 ns
NF12 Ready to NFRE low tRR 6T — 180 — ns
NF13 NFRE pulse width tRP 1.5T – 1.0 ns — 44 — ns
NF14 READ cycle time tRC 2T – 5.5 ns — 54.5 — ns
NF15 NFRE high hold time tREH 0.5T – 4.0 ns 11 — ns
NF16 Data setup on READ tDSR N/A 9 — ns
NF17 Data hold on READ tDHR N/A 0 — ns
1The flash clock maximum frequency is 50 MHz.
2Subject to DPLL jitter specification listed in Table 28, "DPLL Specifications," on page 31.
Table 32. NFC Timing Parameters1 (continued)
ID Parameter Symbol
Timing
T = NFC Clock Cycle2
Example Timing for
NFC Clock ≈ 33 MHz
T = 30 ns Unit
Min. Max. Min. Max.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor36
Input data, ECB and DTACK all captured according to BCLK rising edge time. Figure 15 depicts the
timing of the WEIM module, and Table 33 lists the timing parameters.
Figure 15. WEIM Bus Timing Diagram
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 37
NOTE
Test conditions: load capacitance, 25 pF. Recommended drive strength for
all controls, address, and BCLK is set to maximum drive.
Table 33. WEIM Bus Timing Parameters1
1“High” is defined as 80% of signal value, and “low” is defined as 20% of signal value.
ID Parameter Min. Max. Unit
WE1 BCLK cycle time2
2BCLK parameters are measured from the 50% point. For example, “high” is defined as 50% of signal value and “low” is defined
as 50% of signal value.
14.5 — ns
WE2 BCLK low-level width27—ns
WE3 BCLK high-level width27—ns
WE4 Address valid to Clock rise/fall 15 21 ns
WE5 Clock rise/fall to address invalid 22 25 ns
WE6 Clock rise/fall to CSx_B valid 15 19 ns
WE7 Clock rise/fall to CSx_B invalid 3.6 5 ns
WE8 Clock rise/fall to RW_B valid 8 12 ns
WE9 Clock rise/fall to RW_B invalid 3 8 ns
WE10 Clock rise/fall to OE_B valid 7 12 ns
WE11 Clock rise/fall to OE_B invalid 3.8 5.5 ns
WE12 Clock rise/fall to EBy_B valid 6 11.5 ns
WE13 Clock rise/fall to EBy_B invalid 6 10 ns
WE14 Clock rise/fall to LBA_B valid 17.5 20 ns
WE15 Clock rise/fall to LBA_B invalid 0 1 ns
WE16 Clock rise/fall to Output Data valid 5 10 ns
WE17 Clock rise to Output Data invalid 0 2.5 ns
WE18 Input Data Valid to Clock rise3
3Parameters W18, W20, W22, and W24 are tested when FCE=1. i.MX35 does not support FCE=0.
1—ns
WE19 Input Data Valid to Clock rise, FCE=0 (in the case there is ECB_B asserted
during access)
(BCLK/2)
+ 3.01
—ns
WE19 Input Data Valid to Clock rise, FCE=0 (in the case there is NO ECB_B
asserted during access)
6.9 — ns
WE20 Clock rise to Input Data invalid31—ns
WE22 ECB_B setup time35—ns
WE24 ECB_B hold time30—ns
WE26 DTACK_B setup time 5.4 — ns
WE27 DTACK_B hold time –3.2 — ns
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor38
Recommended drive strength for all controls, address and BCLK is set to
maximum drive.
Figure 16 through Figure 21 depict some examples of basic WEIM accesses to external memory devices
with the timing parameters mentioned in Table 33 for specific control parameter settings.
Figure 16. Synchronous Memory Timing Diagram for Read Access—WSC = 1
Figure 17. Synchronous Memory Timing Diagram for Write Access—
WSC = 1, EBWA = 1, EBWN = 1, LBN = 1
Last Valid Address V1
V1
BCLK
ADDR
DATA
RW
LBA
OE
EB[y]
CS[x]
Next Address
WE4 WE5
WE6 WE7
WE10 WE11
WE13
WE12
WE14 WE15
WE20, WE21
WE18, WE 19
Last Valid Address V1
V1
BCLK
ADDR
DATA
RW
LBA
OE
EB[y]
CS[x]
Next Address
WE4 WE5
WE6 WE7
WE8 WE9
WE12 WE13
WE14 WE15
WE16
WE17
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 39
Figure 18. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses—
WSC=2, SYNC=1, DOL=0
Figure 19. Synchronous Memory TIming Diagram for Burst Write Access—
BCS = 1, WSC = 4, SYNC = 1, DOL = 0, PSR = 1
Last Valid Addr Address V1 Address V2
V1 V1+2 V2 V2+2
BCLK
ADDR
ECB
DATA Halfword Halfword
CS[x]
RW
LBA
OE
EB[y]
Halfword Halfword
WE4 WE5
WE7
WE10 WE11
WE12 WE13
WE14 WE15
WE18, WE19 WE18, WE19
WE20, WE21
WE20, WE21
WE22, WE23 WE22, WE23
WE24, WE25 WE24, WE25
WE6
Last Valid Addr
BCLK
ADDR
DATA
CS[x]
RW
LBA
OE
EB[y]
ECB
Address V1
V1 V1+4 V1+12V1+8
WE12
WE4 WE5
WE6 WE7
WE8 WE9
WE13
WE14
WE16 WE16
WE17 WE17
WE22, WE23
WE24, WE25
WE15
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor40
Figure 20. Muxed A/D Mode Timing Diagram for Synchronous Write Access—
WSC = 7, LBA = 1, LBN = 1, LAH = 1
Figure 21. Muxed A/D Mode Timing Diagram for Synchronous Read Access—
WSC = 7, LBA = 1, LBN = 1, LAH = 1, OEA = 7
Write
BCLK
ADDR/
RW
LBA
OE
EB[y]
CS[x]
Address V1 Write Data
Last Valid Addr
M_DATA
WE4 WE5
WE6 WE7
WE9
WE8
WE12 WE13
WE14 WE15
WE16
WE17
BCLK
ADDR/
RW
LBA
OE
EB[y]
CS[x]
Address V1 Read Data
Last Valid Addr
M_DATA
WE5
WE6
WE7
WE14
WE15
WE10 WE11
WE12 WE13
WE18, WE19
WE20, WE21
WE4
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 41
Figure 22 through Figure 26, and Table 34 help to determine timing parameters relative chip select (CS)
state for asynchronous and DTACK WEIM accesses with corresponding WEIM bit fields and the timing
parameters mentioned above.
Figure 22. Asynchronous Memory Read Access
Figure 23. Asynchronous A/D muxed Read Access (RWSC = 5)
Last Valid Address Address V1
V1
ADDR
DATA
RW
LBA
OE
EB[y]
CS [x]
Next Address
WE39
WE35
WE37
WE32
WE36
WE38
WE43
WE40
WE31
WE44
Addr. V1 D(V1)
ADDR/
WE
LBA
OE
BE[y]
CS[x]
WE39
WE35A
WE37
WE36
WE38
WE40
WE31
WE44
MAXDI
MAXCO
WE32A
M_DATA
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Freescale Semiconductor42
Figure 24. Asynchronous Memory Write Access
Figure 25. Asynchronous A/D Mux Write Access
Last Valid Address Address V1
D(V1)
ADDR
DATA
RW
LBA
OE
BE[y]
CS[x]
Next Address
WE31
WE39
WE33
WE45
WE32
WE40
WE34
WE46
WE42
WE41
RW
OE
BE[y]
CS[x]
WE33
WE45
WE34
WE46
WE42
Addr. V1 D(V1)
ADDR/
WE31
WE42
WE41
WE32A
M_DATA
LBA WE39 WE40A
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 43
Figure 26. DTACK Read Access
Table 34. WEIM Asynchronous Timing Parameters Relative Chip Select Table
Ref No. Parameter
Determination By
Synchronous Measured
Parameters1
Min
Max
(If 133 MHz is
supported by SoC)
Unit
WE31 CS[x] valid to Address valid WE4 – WE6 – CSA2— 3 – CSA ns
WE32 Address invalid to CS[x] invalid WE7 – WE5 – CSN3—3 – CSNns
WE32A(
muxed
A/D
CS[x] valid to address invalid WE4 – WE7 + (LBN + LBA + 1
– CSA2)
–3 + (LBN + LBA +
1 – CSA)
—ns
WE33 CS[x] valid to WE valid WE8 – WE6 + (WEA – CSA) — 3 + (WEA – CSA) ns
WE34 WE invalid to CS[x] invalid WE7 – WE9 + (WEN – CSN) — 3 – (WEN_CSN) ns
WE35 CS[x] valid to OE valid WE10 – WE6 + (OEA – CSA) — 3 + (OEA – CSA) ns
WE35A
(muxed
A/D)
CS[x] valid to OE valid WE10 – WE6 + (OEA + RLBN
+ RLBA + ADH + 1 – CSA)
–3 + (OEA +
RLBN + RLBA +
ADH + 1 – CSA)
3 + (OEA + RLBN +
RLBA + ADH + 1 –
CSA)
ns
WE36 OE invalid to CS[x] invalid WE7 – WE11 + (OEN – CSN) — 3 – (OEN – CSN) ns
WE37 CS[x] valid to BE[y] valid (read
access)
WE12 – WE6 + (RBEA – CSA) — 3 + (RBEA4 – CSA) ns
WE38 BE[y] invalid to CS[x] invalid
(read access)
WE7 – WE13 + (RBEN – CSN) — 3 – (RBEN5 – CSN) ns
WE39 CS[x] valid to LBA valid WE14 – WE6 + (LBA – CSA) — 3 + (LBA – CSA) ns
WE40 LBA invalid to CS[x] invalid WE7 – WE15 – CSN — 3 – CSN ns
Last Valid Address Address V1
V1
ADDR
DATA
RW
LBA
OE
EB[y]
CS [x]
Next Address
WE39
WE35
WE37
WE32
WE36
WE38
WE43
WE40
WE31
WE44
DATA
WE47
WE48
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor44
WE40A
(muxed
A/D)
CS[x] valid to LBA invalid WE14 – WE6 + (LBN + LBA + 1
– CSA)
–3 + (LBN + LBA +
1 – CSA)
3 + (LBN + LBA + 1 –
CSA)
ns
WE41 CS[x] valid to Output Data valid WE16 – WE6 – WCSA — 3 – WCSA ns
WE41A
(muxed
A/D)
CS[x] valid to Output Data valid WE16 – WE6 + (WLBN +
WLBA + ADH + 1 – WCSA)
— 3 + (WLBN + WLBA +
ADH + 1 – WCSA)
ns
WE42 Output Data invalid to CS[x]
Invalid
WE17 – WE7 – CSN — 3 – CSN ns
WE43 Input Data valid to CS[x] invalid MAXCO – MAXCSO + MAXDI MAXCO6 –
MAXCSO7 +
MAXDI8
—ns
WE44 CS[x] invalid to Input Data
invalid
00—ns
WE45 CS[x] valid to BE[y] valid (write
access)
WE12 – WE6 + (WBEA – CSA) — 3 + (WBEA – CSA) ns
WE46 BE[y] invalid to CS[x] invalid
(write access)
WE7 – WE13 + (WBEN – CSN) — –3 + (WBEN – CSN) ns
WE47 DTACK valid to CS[x] invalid MAXCO – MAXCSO + MAXDTI MAXCO6 –
MAXCSO7 +
MAXDTI9
—ns
WE48 CS[x] Invalid to DTACK invalid 0 0 — ns
1For the value of parameters WE4–WE21, see column BCD = 0 in Ta ble 3 3 .
2CS Assertion. This bit field determines when the CS signal is asserted during read/write cycles.
3CS Negation. This bit field determines when the CS signal is negated during read/write cycles.
4BE Assertion. This bit field determines when the BE signal is asserted during read cycles.
5BE Negation. This bit field determines when the BE signal is negated during read cycles.
6Output maximum delay from internal driving ADDR/control FFs to chip outputs.
7Output maximum delay from CS[x] internal driving FFs to CS[x] out.
8DATA maximum delay from chip input data to its internal FF.
9 DTACK maximum delay from chip dtack input to its internal FF.
Note: All configuration parameters (CSA, CSN, WBEA, WBEN, LBA, LBN, OEN, OEA, RBEA, and RBEN) are in cycle units.
Table 34. WEIM Asynchronous Timing Parameters Relative Chip Select Table (continued)
Ref No. Parameter
Determination By
Synchronous Measured
Parameters1
Min
Max
(If 133 MHz is
supported by SoC)
Unit
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Freescale Semiconductor 45
4.9.5.3 ESDCTL Electrical Specifications
Figure 27 through Figure 35 depict the timings pertaining to the ESDCTL module, which interfaces with
mobile DDR or SDR SDRAM. Table 35 through Table 45 list the timing parameters.
Figure 27. SDRAM Read Cycle Timing Diagram
Table 35. DDR/SDR SDRAM Read Cycle Timing Parameters
ID Parameter Symbol Min. Max. Unit
SD1 SDRAM clock high-level width tCH 3.4 4.1 ns
SD2 SDRAM clock low-level width tCL 3.4 4.1 ns
SD3 SDRAM clock cycle time tCK 7.0 — ns
SD4 CS, RAS, CAS, WE, DQM, CKE setup time tCMS 2.0 — ns
SD5 CS, RAS, CAS, WE, DQM, CKE hold time tCMH 1.8 — ns
SD6 Address setup time tAS 2.0 — ns
SDCLK
WE
ADDR
DQ
DQM
COL/BA
Data
CS
CAS
RAS
Note: CKE is high during the read/write cycle.
SD4
SD1
SD3
SD2
SD4
SD4
SD4
SD4
SD5
SD5
SD5
SD5
SD5
SD6
SD7
SD10
SD8
SD9
SDCLK
ROW/BA
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Freescale Semiconductor46
NOTE
SDR SDRAM CLK parameters are measured from the 50% point—that is,
high is defined as 50% of signal value and low is defined as 50% of signal
value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 35 indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
SD7 Address hold time tAH 1.8 — ns
SD8 SDRAM access time tAC — 6.47 ns
SD9 Data out hold time1tOH 1.2 — ns
SD10 Active to read/write command period tRC 10 — clock
1Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see
Ta b l e 4 4 and Ta b l e 4 5 .
Table 35. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
ID Parameter Symbol Min. Max. Unit
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Freescale Semiconductor 47
Figure 28. SDR SDRAM Write Cycle Timing Diagram
Table 36. SDR SDRAM Write Timing Parameters
ID Parameter Symbol Min. Max. Unit
SD1 SDRAM clock high-level width tCH 0.45 0.55 ns
SD2 SDRAM clock low-level width tCL 0.45 0.55 ns
SD3 SDRAM clock cycle time tCK 7.0 — ns
SD4 CS, RAS, CAS, WE, DQM, CKE setup time tCMS 2.4 — ns
SD5 CS, RAS, CAS, WE, DQM, CKE hold time tCMH 1.4 — ns
SD6 Address setup time tAS 2.4 — ns
SD7 Address hold time tAH 1.4 — ns
SD13 Data setup time tDS 2.4 — ns
SD14 Data hold time tDH 1.4 — ns
CS
CAS
WE
RAS
ADDR
DQ
DQM
BA ROW / BA COL/BA
DATA
SD4
SD4
SD4SD4
SD5
SD5
SD5
SD5
SD7
SD6
SD13 SD14
SDCLK
SD1
SD3
SD2
SDCLK
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Freescale Semiconductor48
NOTE
Test conditions are: pin voltage 1.7 V–1.95 V, capacitance 15 pF for all pins
(both DDR and non-DDR pins), drive strength is high (7.2 mA). “High” is
defined as 80% of signal value and “low” is defined as 20% of signal value.
SDR SDRAM CLK parameters are measured from the 50% point—that is,
“high” is defined as 50% of signal value, and “low” is defined as 50% of
signal value. tCH + tCL will not exceed 7.5 ns for 133 MHz. DDR SDRAM
CLK parameters are measured at the crossing point of SDCLK and SDCLK
(inverted clock).
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 36 indicates SDRAM requirements. All output signals are driven by
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.
Figure 29. SDRAM Refresh Timing Diagram
Table 37. SDRAM Refresh Timing Parameters
ID Parameter Symbol Min. Max. Unit
SD1 SDRAM clock high-level width tCH 3.4 4.1 ns
SD2 SDRAM clock low-level width tCL 3.4 4.1 ns
SD3 SDRAM clock cycle time tCK 7.5 — ns
SD6 Address setup time tAS 1.8 — ns
CS
CAS
WE
RAS
ADDR BA ROW/BA
SD6
SD7
SD11
SD10 SD10
SDCLK
SD1
SD2
SDCLK
SD3
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Freescale Semiconductor 49
NOTE
SDR SDRAM CLK parameters are measured from the 50% point—that is,
“high” is defined as 50% of signal value and “low” is defined as 50% of
signal value.
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 37 indicates SDRAM requirements. All output signals are driven by
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.
Figure 30. SDRAM Self-Refresh Cycle Timing Diagram
SD7 Address hold time tAH 1.8 — ns
SD10 Precharge cycle period1tRP 1 4 clock
SD11 Auto precharge command period1tRC 2 20 clock
1SD10 and SD11 are determined by SDRAM controller register settings.
Table 37. SDRAM Refresh Timing Parameters (continued)
ID Parameter Symbol Min. Max. Unit
SDCLK
CS
CAS
RAS
ADDR BA
WE
CKE
Don’t care
SD16 SD16
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Freescale Semiconductor50
NOTE
The clock will continue to run unless both CKEs are low. Then the clock will
be stopped in low state.
Figure 31. DDR2 SDRAM Basic Timing Parameters
Table 38. SDRAM Self-Refresh Cycle Timing Parameters
ID Parameter Symbol Min. Max. Unit
SD16 CKE output delay time tCKS 1.8 — ns
Table 39. DDR2 SDRAM Timing Parameter Table
ID PARAMETER Symbol
DDR2-400
Unit
Min Max
DDR1 SDRAM clock high-level width tCH 0.45 0.55 tCK
DDR2 SDRAM clock low-level width tCL 0.45 0.55 tCK
DDR3 SDRAM clock cycle time tCK 7.0 8.0 ns
DDR4 CS, RAS, CAS, CKE, WE setup time tIS11.5 — ns
SDCLK
WE
ADDR ROW/BA COL/BA
CS
CAS
RAS
DDR1
DDR3 DDR2
DDR4
DDR4
DDR4
DDR5
DDR5
DDR5
DDR5
DDR6 DDR7
SDCLK
CKE
DDR4
DDR4
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Freescale Semiconductor 51
NOTE
These values are for command/address slew rate of 1 V/ns and SDCLK,
SDCLK_B differential slew rate of 2 V/ns. For different values, use the
derating table.
Table 40. Derating Values for DDR2–400, DDR2–533
DDR5 CS, RAS, CAS, CKE, WE hold time tIH11.25 — ns
DDR6 Address output setup time tIS11.5 — ns
DDR7 Address output hold time tIH11.5 — ns
Table 39. DDR2 SDRAM Timing Parameter Table
ID PARAMETER Symbol
DDR2-400
Unit
Min Max
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Freescale Semiconductor52
Figure 32. DDR2 SDRAM Write Cycle Timing Diagram
NOTE
These values are for DQ/DM slew rate of 1 V/ns and DQS slew rate of
1 V/ns. For different values use the derating table.
Table 41. DDR2 SDRAM Write Cycle Parameters
ID PARAMETER Symbol
DDR2-400
Unit
Min Max
DDR17 DQ and DQM setup time to DQS (single-ended strobe) tDS1(base) 0.5 — ns
DDR18 DQ and DQM hold time to DQS (single-ended strobe) tDH1(base) 0.5 — ns
DDR19 Write cycle DQS falling edge to SDCLK output setup time. tDSS 0.2 — tCK
DDR20 Write cycle DQS falling edge to SDCLK output hold time. tDSH 0.2 — tCK
DDR21 DQS latching rising transitions to associated clock edges tDQSS –0.25 0.25 tCK
DDR22 DQS high level width tDQSH 0.35 — tCK
DDR23 DQS low level width tDQSL 0.35 — tCK
SDCLK
SDCLK_B
DQS (output)
DQ (output)
DQM (output)
Data
Data Data Data Data Data Data Data
DM DM DM DM DM DM DM DM
DDR17
DDR17
DDR17
DDR17
DDR18 DDR18
DDR18 DDR18
DDR19
DDR20
DDR21
DDR23
DDR22
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Freescale Semiconductor 53
Table 42. DDR Single-ended Slew Rate
NOTE
SDR SDRAM CLK parameters are measured from the 50% point—that is,
“high” is defined as 50% of signal value and “low” is defined as 50% of
signal value. DDR SDRAM CLK parameters are measured at the crossing
point of SDCLK and SDCLK (inverted clock).
Test conditions are: Capacitance 15 pF for DDR PADS. Recommended
drive strength is Medium for SDCLK and High for Address and controls.
Figure 33. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram
SDCLK
SDCLK_B
DQS (input)
DQ (input)
DATA
DATA
DATA
DATADATA
DATA
DATADATA
DDR26
DDR24
DDR25
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Freescale Semiconductor54
NOTE
SDRAM CLK and DQS-related parameters are measured from the 50%
point—that is, “high” is defined as 50% of signal value and “low” is defined
as 50% of signal value. DDR SDRAM CLK parameters are measured at the
crossing point of SDCLK and SDCLK (inverted clock).
Test conditions are: Capacitance 15 pF for DDR PADS. Recommended
drive strength is Medium for SDCLK and High for Address and controls.
Figure 34. Mobile DDR SDRAM Write Cycle Timing Diagram
Table 43. DDR2 SDRAM Read Cycle Parameter Table
ID PARAMETER Symbol
DDR2-400
Unit
Min Max
DDR24 DQS – DQ Skew (defines the Data valid window in
read cycles related to DQS).
tDQSQ —0.35ns
DDR25 DQS DQ in HOLD time from DQS1
1The value was calculated for an SDCLK frequency of 133 MHz by the formula tQH = tHP – tQHS = min (tCL,tCH) – tQHS =
0.45 ×tCK – tQHS = 0.45 × 7.5 – 0.45 = 2.925 ns.
tQH 2.925 — ns
DDR26 DQS output access time from SDCLK posedge tDQSCK –0.5 0.5 ns
Table 44. Mobile DDR SDRAM Write Cycle Timing Parameters1
1Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.
ID Parameter Symbol Min. Max. Unit
SD17 DQ and DQM setup time to DQS tDS 0.95 — ns
SD18 DQ and DQM hold time to DQS tDH 0.95 — ns
SD19 Write cycle DQS falling edge to SDCLK output delay time. tDSS 1.8 — ns
SD20 Write cycle DQS falling edge to SDCLK output hold time. tDSH 1.8 — ns
SDCLK
SDCLK
DQS (output)
DQ (output)
DQM (output)
Data Data Data Data Data Data Data Data
DM DM DM DM DM DM DM DM
SD17
SD17
SD17
SD17
SD18
SD18
SD18 SD18
SD19 SD20
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Freescale Semiconductor 55
NOTE
SDRAM CLK and DQS-related parameters are measured from the 50%
point—that is, “high” is defined as 50% of signal value and “low” is defined
as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 44 indicates SDRAM requirements. All output signals are driven by
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.
Figure 35. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram
NOTE
SDRAM CLK and DQS-related parameters are measured from the 50%
point—that is, “high” is defined as 50% of signal value, and “low” is defined
as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 45 indicates SDRAM requirements. All output signals are driven by
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.
Table 45. Mobile DDR SDRAM Read Cycle Timing Parameters
ID Parameter Symbol Min. Max. Unit
SD21 DQS – DQ Skew (defines the Data valid window in read cycles related to DQS). tDQSQ — 0.85 ns
SD22 DQS DQ HOLD time from DQS tQH 2.3 — ns
SD23 DQS output access time from SDCLK posedge tDQSCK — 6.7 ns
SDCLK
SDCLK
DQS (input)
DQ (input) Data
Data
Data
Data
Data
Data
DataData
SD23
SD21
SD22
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Freescale Semiconductor56
4.9.6 Enhanced Serial Audio Interface (ESAI) Timing Specifications
The ESAI consists of independent transmitter and receiver sections, each section with its own clock
generator. Table 46 shows the interface timing values. The number field in the table refers to timing signals
found in Figure 36 and Figure 37.
Table 46. Enhanced Serial Audio Interface Timing
No. Characteristics1,2 Symbol Expression2Min. Max. Condition3Unit
62 Clock cycle4tSSICC 4 × Tc
4 × Tc
30.0
30.0
—
—
i ck
i ck
ns
63 Clock high period
• For internal clock —2
× Tc − 9.0 6 — —
ns
• For external clock — 2 × Tc15 — —
64 Clock low period
• For internal clock —2
× Tc − 9.0 6 — —
ns
• For external clock — 2 × Tc15 — —
65 SCKR rising edge to FSR out (bl) high —
—
—
—
—
—
17.0
7.0
x ck
i ck a
ns
66 SCKR rising edge to FSR out (bl) low —
—
—
—
—
—
17.0
7.0
x ck
i ck a
ns
67 SCKR rising edge to FSR out (wr) high5—
—
—
—
—
—
19.0
9.0
x ck
i ck a
ns
68 SCKR rising edge to FSR out (wr) low5—
—
—
—
—
—
19.0
9.0
x ck
i ck a
ns
69 SCKR rising edge to FSR out (wl) high —
—
—
—
—
—
16.0
6.0
x ck
i ck a
ns
70 SCKR rising edge to FSR out (wl) low —
—
—
—
—
—
17.0
7.0
x ck
i ck a
ns
71 Data in setup time before SCKR (SCK in synchronous
mode) falling edge
—
—
—
—
12.0
19.0
—
—
x ck
i ck
ns
72 Data in hold time after SCKR falling edge —
—
—
—
3.5
9.0
—
—
x ck
i ck
ns
73 FSR input (bl, wr) high before SCKR falling edge5—
—
—
—
2.0
12.0
—
—
x ck
i ck a
ns
74 FSR input (wl) high before SCKR falling edge —
—
—
—
2.0
12.0
—
—
x ck
i ck a
ns
75 FSR input hold time after SCKR falling edge —
—
—
—
2.5
8.5
—
—
x ck
i ck a
ns
78 SCKT rising edge to FST out (bl) high —
—
—
—
—
—
18.0
8.0
x ck
i ck
ns
79 SCKT rising edge to FST out (bl) low —
—
—
—
—
—
20.0
10.0
x ck
i ck
ns
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Freescale Semiconductor 57
80 SCKT rising edge to FST out (wr) high5—
—
—
—
—
—
20.0
10.0
x ck
i ck
ns
81 SCKT rising edge to FST out (wr) low5 —
—
—
—
—
—
22.0
12.0
x ck
i ck
ns
82 SCKT rising edge to FST out (wl) high —
—
—
—
—
—
19.0
9.0
x ck
i ck
ns
83 SCKT rising edge to FST out (wl) low —
—
—
—
—
—
20.0
10.0
x ck
i ck
ns
84 SCKT rising edge to data out enable from high
impedance
—
—
—
—
—
—
22.0
17.0
x ck
i ck
ns
86 SCKT rising edge to data out valid —
—
—
—
—
—
18.0
13.0
x ck
i ck
ns
87 SCKT rising edge to data out high impedance 67 —
—
—
—
—
—
21.0
16.0
x ck
i ck
ns
89 FST input (bl, wr) setup time before SCKT falling edge5—
—
—
—
2.0
18.0
—
—
x ck
i ck
ns
90 FST input (wl) setup time before SCKT falling edge —
—
—
—
2.0
18.0
—
—
x ck
i ck
ns
91 FST input hold time after SCKT falling edge —
—
—
—
4.0
5.0
—
—
x ck
i ck
ns
1i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that SCKT and SCKR are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that SCKT and SCKR are the same clock)
2bl = bit length
wl = word length
wr = word length relative
3SCKT(SCKT pin) = transmit clock
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
4For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
5The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the
second-to-last bit clock of the first word in the frame.
6Periodically sampled and not 100% tested.
Table 46. Enhanced Serial Audio Interface Timing (continued)
No. Characteristics1,2 Symbol Expression2Min. Max. Condition3Unit
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Freescale Semiconductor58
Figure 36. ESAI Transmitter Timing
SCKT
(Input/Output)
FST (Bit)
Out
FST (Word)
Out
Data Out
FST (Bit) In
FST (Word) In
62 64
78 79
82 83
87
8686
84
91
89
90 91
63
Last BitFirst Bit
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Freescale Semiconductor 59
Figure 37. ESAI Receiver Timing
4.9.7 eSDHCv2 AC Electrical Specifications
Figure 38 depicts the timing of eSDHCv2, and Table 47 lists the eSDHCv2 timing characteristics. The
following definitions apply to values and signals described in Table 47:
• LS: low-speed mode. Low-speed card can tolerate a clock up to 400 kHz.
• FS: full-speed mode. For a full-speed MMC card, the card clock can reach 20 MHz; a full-speed
SD/SDIO card can reach 25 MHz.
• HS: high-speed mode. For a high-speed MMC card, the card clock can reach 52 MHz; SD/SDIO
can reach 50 MHz.
SCKR
(Input/Output)
FSR (Bit)
Out
FSR (Word)
Out
Data In
FSR (Bit)
In
FSR (Word)
In
62
64
65
69 70
72
71
75
73
74 75
63
66
First Bit Last Bit
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Freescale Semiconductor60
Figure 38. eSDHCv2 Timing
Table 47. eSDHCv2 Interface Timing S pecification
ID Parameter Symbols Min. Max. Unit
Card Input Clock
SD1 Clock frequency (Low Speed) fPP1
1In low-speed mode, the card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
0400kHz
Clock frequency (SD/SDIO Full Speed/High Speed) fPP2
2In normal-speed mode for the SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
0 25/50 MHz
Clock frequency (MMC Full Speed/High Speed) fPP3
3In normal-speed mode for MMC card, clock frequency can be any value between 0 and 20 MHz. In high-speed mode, clock
frequency can be any value between 0–52 MHz.
0 20/52 MHz
Clock frequency (Identification Mode) fOD 100 400 kHz
SD2 Clock Low time tWL 7—ns
SD3 Clock high time tWH 7—ns
SD4 Clock rise time tTLH —3ns
SD5 Clock fall time tTHL —3ns
eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)
SD6 eSDHC output delay tOD –3 3 ns
eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)
SD7 eSDHC input setup time tISU 5—ns
SD8 eSDHC input hold time tIH4
4To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
2.5 — ns
SD1
SD3
SD5
SD4
SD7
SDHCx_CMD
output from eSDHCv2 to card SDHCx_DAT_1
SDHCx_DAT_7
SDHCx_DAT_0
output from card to eSDHCv2
SDHCx_CLK
SD2
SD8
SD6
SDHCx_CMD
SDHCx_DAT_1
SDHCx_DAT_7
SDHCx_DAT_0
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4.9.8 Fast Ethernet Controller (FEC) AC Electrical Specifications
This section describes the electrical information of the FEC module. The FEC is designed to support both
10- and 100-Mbps Ethernet networks. An external transceiver interface and transceiver function are
required to complete the interface to the media. The FEC supports the 10/100 Mbps Media Independent
Interface (MII) using a total of 18 pins. The 10-Mbps 7-wire interface that is restricted to a 10-Mbps data
rate uses seven of the MII pins for connection to an external Ethernet transceiver.
4.9.8.1 FEC AC Timing
This section describes the AC timing specifications of the FEC. The MII signals are compatible with
transceivers operating at a voltage of 3.3 V.
4.9.8.2 MII Receive Signal Timing
The MII receive timing signals consist of FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and
FEC_RX_CLK. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency
must exceed twice the FEC_RX_CLK frequency. Table 48 lists MII receive channel timings.
1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing when in 10 Mbps 7-wire interface mode.
Figure 39 shows the MII receive signal timings listed in Table 48.
Figure 39. MII Receive Signal Timing Diagram
Table 48. MII Receive Signal Timing
Num. Characteristic1Min. Max. Unit
M1 FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup 5 — ns
M2 FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold 5 — ns
M3 FEC_RX_CLK pulse width high 35% 65% FEC_RX_CLK period
M4 FEC_RX_CLK pulse width low 35% 65% FEC_RX_CLK period
FEC_RX_CLK (input)
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
M3
M4
M1 M2
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4.9.8.3 MII Transmit Signal Timing
The transmitter timing signals consist of FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency
must exceed twice the FEC_TX_CLK frequency. Table 49 lists MII transmit channel timings.
1 FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing when in 10 Mbps 7-wire interface mode.
Figure 40 shows the MII transmit signal timings listed in Table 49.
Figure 40. MII Transmit Signal Timing Diagram
4.9.8.4 MII Asynchronous Inputs Signal Timing
The MII asynchronous timing signals are FEC_CRS and FEC_COL. Table 50 lists MII asynchronous
inputs signal timing.
1 FEC_COL has the same timing in 10 Mbit 7-wire interface mode.
Table 49. MII Transmit Signal Timing
Num Characteristic1Min. Max. Unit
M5 FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER
invalid
5— ns
M6 FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER
valid
—20 ns
M7 FEC_TX_CLK pulse width high 35% 65% FEC_TX_CLK period
M8 FEC_TX_CLK pulse width low 35% 65% FEC_TX_CLK period
Table 50. MII Asynch Inputs Signal Timing
Num Characteristic Min. Max. Unit
M91FEC_CRS to FEC_COL minimum pulse width 1.5 — FEC_TX_CLK period
FEC_TX_CLK (input)
FEC_TXD[3:0] (outputs)
FEC_TX_EN
FEC_TX_ER
M7
M8
M5
M6
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Figure 41 shows MII asynchronous input timings listed in Table 50.
Figure 41. MII Asynch Inputs Timing Diagram
4.9.8.5 MII Serial Management Channel Timing
Serial management channel timing is accomplished using FEC_MDIO and FEC_MDC. The FEC
functions correctly with a maximum MDC frequency of 2.5 MHz. Table 51 lists MII serial management
channel timings.
The MDC frequency should be equal to or less than 2.5 MHz to be compliant with the IEEE 802.3 MII
specification. However the FEC can function correctly with a maximum MDC frequency of 15 MHz.
Table 51. MII Transmit Signal Timing
Num Characteristic Min. Max. Units
M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum
propagation delay)
0— ns
M11 FEC_MDC falling edge to FEC_MDIO output valid (max.
propagation delay)
—5 ns
M12 FEC_MDIO (input) to FEC_MDC rising edge setup 18 — ns
M13 FEC_MDIO (input) to FEC_MDC rising edge hold 0 — ns
M14 FEC_MDC pulse width high 40% 60% FEC_MDC period
M15 FEC_MDC pulse width low 40% 60% FEC_MDC period
FEC_CRS, FEC_COL
M9
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Figure 42 shows MII serial management channel timings listed in Table 51.
Figure 42. MII Serial Management Channel Timing Diagram
4.9.9 FIR Electrical Specifications
FIR implements asynchronous infrared protocols (FIR, MIR) defined by IrDA® (Infrared Data
Association). Refer to the IrDA® website for details on FIR and MIR protocols.
4.9.10 FlexCAN Module AC Electrical Specifications
The electrical characteristics are related to the CAN transceiver outside the chip. The i.MX35 has two
CAN modules available for systems design. Tx and Rx ports for both modules are multiplexed with other
I/O pins. Refer to the IOMUX chapter of the MCIMX35 Multimedia Applications Processor Reference
Manual to see which pins expose Tx and Rx pins; these ports are named TXCAN and RXCAN,
respectively.
FEC_MDC (output)
FEC_MDIO (output)
M14
M15
M10
M11
M12 M13
FEC_MDIO (input)
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4.9.11 I2C AC Electrical Specifications
This section describes the electrical characteristics of the I2C module.
4.9.11.1 I2C Module Timing
Figure 43 depicts the timing of the I2C module. Table 52 lists the I2C module timing parameters.
Figure 43. I2C Bus Timing Diagram
Table 52. I2C Module Timing Parameters
ID Parameter
Standard Mode Fast Mode
Unit
Min. Max. Min. Max.
IC1 I2CLK cycle time 10 — 2.5 — μs
IC2 Hold time (repeated) START condition 4.0 — 0.6 — μs
IC3 Set-up time for STOP condition 4.0 — 0.6 — μs
IC4 Data hold time 01
1A device must internally provide a hold time of at least 300 ns for the I2DAT signal in order to bridge the undefined region of
the falling edge of I2CLK.
3.452
2The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal.
010.92μs
IC5 HIGH Period of I2CLK Clock 4.0 — 0.6 — μs
IC6 LOW Period of the I2CLK Clock 4.7 — 1.3 — μs
IC7 Set-up time for a repeated START condition 4.7 — 0.6 — μs
IC8 Data set-up time 250 — 1003
3A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement of set-up time (ID IC7) of
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
max_rise_time (ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus
specification) before the I2CLK line is released.
—ns
IC9 Bus free time between a STOP and START condition 4.7 — 1.3 — μs
IC10 Rise time of both I2DAT and I2CLK signals — 1000 — 300 ns
IC11 Fall time of both I2DAT and I2CLK signals — 300 — 300 ns
IC12 Capacitive load for each bus line (Cb)—400—400pF
IC10 IC11 IC9
IC2 IC8 IC4 IC7 IC3
IC6
IC10
IC5
IC11 START STOP START
START
I2DAT
I2CLK
IC1
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4.9.12 IPU—Sensor Interfaces
This section contains a list of supported camera sensors, a functional description, and the electrical
characteristics.
4.9.12.1 Supported Camera Sensors
Table 53 lists the known supported camera sensors at the time of publication.
4.9.12.2 Functional Description
There are three timing modes supported by the IPU.
4.9.12.2.1 Pseudo BT.656 Video Mode
Smart camera sensors, which typically include image processing capability, support video mode transfer
operations. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC
signals. The timing syntax is defined by the BT.656 standard.
This operation mode follows the recommendations of the ITU BT.656 specifications. The only control
signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream.
An active line starts with a SAV code and ends with an EAV code. In some cases, digital blanking is
Table 53. Supported Camera Sensors1
1Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only
camera suppliers.
Vendor Model
Conexant CX11646, CX204902, CX204502
2These sensors have not been validated at the time of publication.
Agilant HDCP–2010, ADCS–10212, ADCS–10212
Toshiba TC90A70
ICMedia ICM202A, ICM1022
iMagic IM8801
Transchip TC5600, TC5600J, TC5640, TC5700, TC6000
Fujitsu MB86S02A
Micron MI-SOC–0133
Matsushita MN39980
STMicro W6411, W6500, W65012, W66002, W65522, STV09742
OmniVision OV7620, OV6630, OV2640
Sharp LZ0P3714 (CCD)
Motorola MC30300 (Python)2, SCM200142, SCM201142, SCM221142, SCM200272
National Semiconductor LM96182
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Freescale Semiconductor 67
inserted in between EAV and SAV code. The CSI decodes and filters out the timing coding from the data
stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use.
4.9.12.2.2 Gated Clock Mode
The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See
Figure 44.
Figure 44. Gated Clock Mode Timing Diagram
A frame starts with a rising edge on SENSB_VSYNC (all the timing corresponds to straight polarity of the
corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. The pixel clock
is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.
SENSB_HSYNC goes to low at the end of the line. Pixel clocks then become invalid and the CSI stops
receiving data from the stream. For the next line, the SENSB_HSYNC timing repeats. For the next frame,
the SENSB_VSYNC timing repeats.
4.9.12.2.3 Non-Gated Clock Mode
The timing is the same as the gated-clock mode (described in Section 4.9.12.2.2, “Gated Clock Mode”),
except for the SENSB_HSYNC signal, which is not used. See Figure 45. All incoming pixel clocks are
valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states
low) until valid data is going to be transmitted over the bus.
Figure 45. Non-Gated Clock Mode Timing Diagram
SENSB_VSYNC
SENSB_HSYNC
SENSB_PIX_CLK
SENSB_DATA[9:0] invalid
1st byte
n+1th frame
invalid
1st byte
nth frame
Active Line
Start of Frame
SENSB_VSYNC
SENSB_PIX_CLK
SENSB_DATA[7:0] invalid
1st byte
n+1th frame
invalid
1st byte
nth frame
Start of Frame
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The timing described in Figure 45 is that of a Motorola sensor. Some other sensors may have slightly
different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;
active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
4.9.12.3 Electrical Characteristics
Figure 46 depicts the sensor interface timing, and Table 54 lists the timing parameters.
Figure 46. Sensor Interface Timing Diagram
4.9.13 IPU—Display Interfaces
This section describes the following types of display interfaces:
•Section 4.9.13.1, “Synchronous Interfaces”
•Section 4.9.13.2, “Interface to Sharp HR-TFT Panels”
•Section 4.9.13.3, “Synchronous Interface to Dual-Port Smart Displays”
•Section 4.9.13.4, “Asynchronous Interfaces”
•Section 4.9.13.5, “Serial Interfaces, Functional Description”
Table 54. Sensor Interface Timing Parameters
ID Parameter Symbol Min. Max. Units
IP1 Sensor input clock frequency Fmck 0.01 133 MHz
IP2 Data and control setup time Tsu 5 — ns
IP3 Data and control holdup time Thd 3 — ns
IP4 Sensor output (pixel) clock frequency Fpck 0.01 133 MHz
SENSB_MCLK
IP3
SENSB_DATA,
SENSB_VSYNC,
IP2
1/IP1
1/IP4
SENSB_PIX_CLK
(Sensor Input)
(Sensor Output)
SENSB_HSYNC
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4.9.13.1 Synchronous Interfaces
This section discusses the interfaces to active matrix TFT LCD panels, Sharp HR-TFT, and dual-port smart
displays.
4.9.13.1.4 Interface to Active Matrix TFT LCD Panels, Functional Description
Figure 47 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,
signals are shown with negative polarity. The sequence of events for active matrix interface timing is as
follows:
• DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is
selected). In active mode, DISPB_D3_CLK runs continuously.
• DISPB_D3_HSYNC causes the panel to start a new line.
• DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one
HSYNC pulse.
• DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the
data to be shifted to the display. When disabled, the data is invalid and the trace is off.
Figure 47. Interface Timing Diagram for TFT (Active Matrix) Panels
4.9.13.1.5 Interface to Active Matrix TFT LCD Panels, Electrical Characteristics
Figure 48 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity
DISPB_D3_CLK
123 mm–1
DISPB_D3_HSYNC
DISPB_D3_VSYNC
DISPB_D3_HSYNC
LINE 1 LINE 2 LINE 3 LINE 4 LINE n – 1 LINE n
DISPB_D3_DRDY
DISPB_D3_DATA
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of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC
and DISPB_D3_DRDY signals.
Figure 48. TFT Panels Timing Diagram—Horizontal Sync Pulse
Figure 49 depicts the vertical timing (timing of one frame). All figure parameters shown are
programmable.
Figure 49. TFT Panels Timing Diagram—Vertical Sync Pulse
Table 55 shows timing parameters of signals presented in Figure 48 and Figure 49.
Table 55. Synchronous Display Interface Timing Parameters—Pixel Level
ID Parameter Symbol Value Units
IP5 Display interface clock period Tdicp Tdicp1ns
IP6 Display pixel clock period Tdpcp (DISP3_IF_CLK_CNT_D + 1) ×Tdicp ns
IP7 Screen width Tsw (SCREEN_WIDTH + 1) ×Tdpcp ns
IP8 HSYNC width Thsw (H_SYNC_WIDTH + 1) ×Tdpcp ns
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_DATA
DISPB_D3_CLK
IP7
IP9 IP10
IP8
Start of line IP5
IP6
IP14
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_DRDY
Start of frame End of frame
IP12
IP15
IP13
IP11
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Figure 50 depicts the synchronous display interface timing for access level, and Table 56 lists the timing
parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the
DI_DISP3_TIME_CONF Register.
Figure 50. Synchronous Display Interface Timing Diagram—Access Level
IP9 Horizontal blank interval 1 Thbi1 BGXP ×Tdpcp ns
IP10 Horizontal blank interval 2 Thbi2 (SCREEN_WIDTH – BGXP – FW) ×Tdpcp ns
IP11 HSYNC delay Thsd H_SYNC_DELAY ×Tdpcp ns
IP12 Screen height Tsh (SCREEN_HEIGHT + 1) ×Tsw ns
IP13 VSYNC width Tvsw if V_SYNC_WIDTH_L = 0 than
(V_SYNC_WIDTH + 1) ×Tdpcp
else
(V_SYNC_WIDTH + 1) ×Tsw
ns
IP14 Vertical blank interval 1 Tvbi1 BGYP ×Tsw ns
IP15 Vertical blank interval 2 Tvbi2 (SCREEN_HEIGHT – BGYP – FH) ×Tsw ns
1Display interface clock period immediate value
Display interface clock period average value.
Table 55. Synchronous Display Interface Timing Parameters—Pixel Level (continued)
ID Parameter Symbol Value Units
Tdicp THSP_CLK DISP3_IF_CLK_PER_WR
HSP_CLK_PERIOD
------------------------------------------------------------------
⋅=
IP19
DISPB_D3_CLK
DISPB_DATA
IP18
IP20
DISPB_D3_VSYNC
IP17IP16
DISPB_D3_DRDY
DISPB_D3_HSYNC
other controls
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4.9.13.2 Interface to Sharp HR-TFT Panels
Figure 51 depicts the Sharp HR-TFT panel interface timing, and Table 57 lists the timing parameters. The
CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,
REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and
SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to
Table 56. Synchronous Display Interface Timing Parameters—Access Level
ID Parameter Symbol Min. Typ.1
1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be device specific.
Max. Units
IP16 Display interface clock low time Tckl Tdicd – Tdicu – 1.5 Tdicd2–Tdicu
3
2Display interface clock down time
3Display interface clock up time
where CEIL(X) rounds the elements of X to the nearest integers toward infinity.
Tdicd – Tdicu + 1.5 ns
IP17 Display interface clock high time Tckh Tdicp – Tdicd +
Tdicu–1.5
Tdicp–Tdicd+
Tdicu
Tdicp–Tdicd +
Tdicu + 1.5
ns
IP18 Data setup time Tdsu Tdicd – 3.5 Tdicu — ns
IP19 Data holdup time Tdhd Tdicp – Tdicd – 3.5 Tdicp – Tdicu — ns
IP20 Control signals setup time to
display interface clock
Tcsu Tdicd – 3.5 Tdicu — ns
Tdicd 1
2
---THSP_CLK ceil 2 DISP3_IF_CLK_DOWN_WR⋅HSP_CLK_PERIOD
---------------------------------------------------------------------------------
⋅=
Tdicu 1
2
---THSP_CLK ceil 2 DISP3_IF_CLK_UP_WR⋅HSP_CLK_PERIOD
----------------------------------------------------------------------
⋅=
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Section 4.9.13.1.5, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics.” The timing
images correspond to straight polarity of the Sharp signals.
Figure 51. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level
Table 57. Sharp Synchronous Display Interface Timing Parameters—Pixel Level
ID Parameter Symbol Value Units
IP21 SPL rise time Tsplr (BGXP – 1) × Tdpcp ns
IP22 CLS rise time Tclsr CLS_RISE_DELAY × Tdpcp ns
IP23 CLS fall time Tclsf CLS_FALL_DELAY × Tdpcp ns
IP24 CLS rise and PS fall time Tpsf PS_FALL_DELAY × Tdpcp ns
IP25 PS rise time Tpsr PS_RISE_DELAY × Tdpcp ns
IP26 REV toggle time Trev REV_TOGGLE_DELAY × Tdpcp ns
D1 D2
DISPB_D3_CLK
DISPB_D3_DATA
DISPB_D3_SPL
DISPB_D3_HSYNC
DISPB_D3_CLS
DISPB_D3_PS
DISPB_D3_REV
1 DISPB_D3_CLK period
IP26
D320
Horizontal timing
IP22
IP23
IP25
IP21
IP24
Example is drawn with FW + 1 = 320 pixel/line, FH + 1 = 240 lines.
SPL pulse width is fixed and aligned to the first data of the line.
REV toggles every HSYNC period.
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4.9.13.3 Synchronous Interface to Dual-Port Smart Displays
Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are
identical to parameters of the synchronous interface. See Section 4.9.13.1.5, “Interface to Active Matrix
TFT LCD Panels, Electrical Characteristics.”
4.9.13.3.6 Interface to a TV Encoder—Functional Description
The interface has an 8-bit data bus, transferring a single 8- bit value (Y/U/V) in each cycle. The bits
D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively. Figure 52 depicts the
interface timing.
• The frequency of the clock DISPB_D3_CLK is 27 MHz.
• The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low.
• The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal. It
remains low for a single clock cycle.
• The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC
signal. It remains low for at least one clock cycle.
— At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC
and DISPB_D3_HSYNC coincide.
— At a transition to an even field (of the same frame), they do not coincide.
• The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC
signal being high.
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Figure 52. TV Encoder Interface Timing Diagram
DISPB_D3_CLK
DISPB_D3_HSYNC
DISPB_DATA
DISPB_D3_VSYNC
Cb Y CrCb Y Cr Y
Pixel Data Timing
Line and Field Timing - NTSC
Even Field Odd Field
Odd Field Even Field
624621
311308
Line and Field Timing - PAL
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_VSYNC
Even Field Odd Field
Odd Field Even Field
1523
262261
DISPB_D3_DRDY
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_VSYNC
524 525 2 3 4 10
263 264 265 266 267 268 269 273
622 623 625 1 2 23
309 310 312 313 314 336
56
34
316315
DISPB_D3_DRDY
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4.9.13.3.7 Interface to a TV Encoder, Electrical Characteristics
The timing characteristics of the TV encoder interface are identical to the synchronous display
characteristics. See Section 4.9.13.1.5, “Interface to Active Matrix TFT LCD Panels, Electrical
Characteristics.”
4.9.13.4 Asynchronous Interfaces
This section discusses the asynchronous parallel and serial interfaces.
4.9.13.4.8 Parallel Interfaces, Functional Description
The IPU supports the following asynchronous parallel interfaces:
• System 80 interface
— Type 1 (sampling with the chip select signal) with and without byte enable signals.
— Type 2 (sampling with the read and write signals) with and without byte enable signals.
• System 68k interface
— Type 1 (sampling with the chip select signal) with or without byte enable signals.
— Type 2 (sampling with the read and write signals) with or without byte enable signals.
For each of four system interfaces, there are three burst modes:
1. Burst mode without a separate clock—The burst length is defined by the corresponding parameters
of the IDMAC (when data is transferred from the system memory) or by the HBURST signal (when
the MCU directly accesses the display via the slave AHB bus). For system 80 and system 68k type
1 interfaces, data is sampled by the CS signal and other control signals change only when transfer
direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD signals
(system 80) or by the ENABLE signal (system 68k), and the CS signal stays active during the
whole burst.
2. Burst mode with the separate clock DISPB_BCLK—In this mode, data is sampled with the
DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are
changed simultaneously with data when the bus state (read, write or wait) is altered. The CS
signals and other controls move to non-active state after burst has been completed.
3. Single access mode—In this mode, slave AHB and DMA burst are broken to single accesses. The
data is sampled with CS or other controls according to the interface type as described above. All
controls (including CS) become non-active for one display interface clock after each access. This
mode corresponds to the ATI single access mode.
Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 53,
Figure 54, Figure 55, and Figure 56. These timing images correspond to active-low DISPB_Dn_CS,
DISPB_Dn_WR and DISPB_Dn_RD signals.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 77
Additionally, the IPU allows a programmable pause between two bursts. The pause is defined in the
HSP_CLK cycles. It allows the prevention of timing violation between two sequential bursts or two
accesses to different displays. The range of this pause is from 4 to 19 HSP_CLK cycles.
Figure 53. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Burst access mode with sampling by CS signal
Burst access mode with sampling by separate burst clock (BCLK)
Single access mode (all control signals are not active for one display interface clock after each display access)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor78
Figure 54. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Burst access mode with sampling by WR/RD signals
Burst access mode with sampling by separate burst clock (BCLK)
Single access mode (all control signals are not active for one display interface clock after each display access)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 79
Figure 55. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram
DISPB_D#_CS
DISPB_WR
DISPB_RD
DISPB_DATA
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
DISPB_D#_CS
DISPB_WR
DISPB_RD
DISPB_DATA
(READ/WRITE)
(ENABLE)
DISPB_PAR_RS
DISPB_PAR_RS
(READ/WRITE)
(ENABLE)
(READ/WRITE)
(ENABLE)
Burst access mode with sampling by CS signal
Burst access mode with sampling by separate burst clock (BCLK)
Single access mode (all control signals are not active for one display interface clock after each display access)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor80
Figure 56. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram
Display read operation can be performed with wait states when each read access takes up to 4 display
interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
(READ/WRITE)
(ENABLE)
(READ/WRITE)
(ENABLE)
(READ/WRITE)
(ENABLE)
Burst access mode with sampling by ENABLE signal
Burst access mode with sampling by separate burst clock (BCLK)
Single access mode (all control signals are not active for one display interface clock after each display access)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 81
DI_DISPn_TIME_CONF_3 registers (n = 0,1,2). Figure 57 shows the timing of the parallel interface with
read wait states.
Figure 57. Parallel Interface Timing Diagram—Read Wait States
4.9.13.4.9 Parallel Interfaces, Electrical Characteristics
Figure 58, Figure 60, Figure 59, and Figure 61 depict timing of asynchronous parallel interfaces based on
the system 80 and system 68k interfaces. Table 58 lists the timing parameters at display access level. All
WRITE OPERATION READ OPERATION
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_DATA
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_DATA
DISPB_DATA
DISP0_RD_WAIT_ST=00
DISP0_RD_WAIT_ST=01
DISP0_RD_WAIT_ST=10
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor82
timing images are based on active low control signals (signal polarity is controlled via the
DI_DISP_SIG_POL register).
Figure 58. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram
IP28, IP27
Read Data
IP32, IP30
IP37
IP38
DISPB_PAR_RS
DISPB_DATA
DISPB_DATA
DISPB_WR (WRITE_L)
(Input)
(Output)
IP35, IP33 IP36, IP34
IP31, IP29
IP40
IP39
IP46,IP44
IP47
IP45, IP43
IP42, IP41
DISPB_RD (READ_L)
DISPB_D#_CS
DISPB_DATA[16]
DISPB_DATA[17]
read point
(WRITE_H)
(READ_H)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 83
Figure 59. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram
IP28, IP27
Read Data
IP32, IP30
DISPB_PAR_RS
DISPB_DATA
DISPB_DATA
DISPB_WR (WRITE_L)
(Input)
(Output)
IP36, IP34
IP31, IP29
IP40
IP39
IP47
IP45, IP43
IP42, IP41
DISPB_RD (READ_L)
DISPB_D#_CS
DISPB_DATA[16]
DISPB_DATA[17]
(WRITE_H)
(READ_H)
IP38
IP35, IP33
IP37
read point
IP46,IP44
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor84
Figure 60. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram
IP28, IP27
Read Data
IP32, IP30
IP37 IP38
DISPB_PAR_RS
DISPB_DATA
DISPB_DATA
DISPB_WR
(Input)
(Output)
IP35,IP33 IP36, IP34
IP31, IP29
IP40
IP39
IP47
IP45, IP43
IP42, IP41
DISPB_RD (ENABLE_L)
DISPB_D#_CS
(READ/WRITE)
DISPB_DATA[17]
(ENABLE_H)
read point
IP46,IP44
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 85
Figure 61. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram
Table 58. Asynchronous Parallel Interface Timing Parameters—Access Level
ID Parameter Symbol Min. Typ.1Max. Units
IP27 Read system cycle time Tcycr Tdicpr – 1.5 Tdicpr2Tdicpr + 1.5 ns
IP28 Write system cycle time Tcycw Tdicpw – 1.5 Tdicpw3Tdicpw + 1.5 ns
IP29 Read low pulse width Trl Tdicdr – Tdicur – 1.5 Tdicdr4–Tdicur
5Tdicdr – Tdicur + 1.5 ns
IP30 Read high pulse width Trh Tdicpr – Tdicdr +
Tdicur – 1.5
Tdicpr – Tdicdr +
Tdicur
Tdicpr – Tdicdr + Tdicur
+ 1.5
ns
IP31 Write low pulse width Twl Tdicdw – Tdicuw
–1.5
Tdicdw6–
Tdicuw7
Tdicdw – Tdicuw + 1.5 ns
IP32 Write high pulse width Twh Tdicpw – Tdicdw +
Tdicuw – 1.5
Tdicpw – Tdicdw
+ Tdicuw
Tdicpw – Tdicdw +
Tdicuw + 1.5
ns
IP33 Controls setup time for read Tdcsr Tdicur – 1.5 Tdicur — ns
IP34 Controls hold time for read Tdchr Tdicpr – Tdicdr – 1.5 Tdicpr – Tdicdr — ns
IP28, IP27
Read Data
IP32, IP30
IP37 IP38
DISPB_PAR_RS
DISPB_DATA
DISPB_DATA
DISPB_WR
(Input)
(Output)
IP35,IP33 IP36, IP34
IP31, IP29
IP40
IP39
IP45, IP43
IP42, IP41
DISPB_RD (ENABLE_L)
DISPB_D#_CS
(READ/WRITE)
DISPB_DATA[17]
(ENABLE_H)
read point
IP46,IP44
IP47
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor86
IP35 Controls setup time for write Tdcsw Tdicuw – 1.5 Tdicuw — ns
IP36 Controls hold time for write Tdchw Tdicpw – Tdicdw – 1.5 Tdicpw – Tdicdw — ns
IP37 Slave device data delay8Tracc 0 — Tdrp9–Tlbd
10 –Tdicur–
1.5
ns
IP38 Slave device data hold time8Troh Tdrp–Tlbd–Tdicdr
+1.5
— Tdicpr – Tdicdr – 1.5 ns
IP39 Write data setup time Tds Tdicdw – 1.5 Tdicdw — ns
IP40 Write data hold time Tdh Tdicpw – Tdicdw – 1.5 Tdicpw – Tdicdw — ns
IP41 Read period2Tdicpr Tdicpr – 1.5 Tdicpr Tdicpr + 1.5 ns
IP42 Write period3Tdicpw Tdicpw – 1.5 Tdicpw Tdicpw + 1.5 ns
IP43 Read down time4Tdicdr Tdicdr – 1.5 Tdicdr Tdicdr + 1.5 ns
IP44 Read up time5Tdicur Tdicur – 1.5 Tdicur Tdicur + 1.5 ns
IP45 Write down time6Tdicdw Tdicdw – 1.5 Tdicdw Tdicdw + 1.5 ns
IP46 Write up time7Tdicuw Tdicuw – 1.5 Tdicuw Tdicuw + 1.5 ns
IP47 Read time point9Tdrp Tdrp – 1.5 Tdrp Tdrp + 1.5 ns
1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be device-specific.
2Display interface clock period value for read:
3Display interface clock period value for write:
4Display interface clock down time for read:
5Display interface clock up time for read:
6Display interface clock down time for write:
7Display interface clock up time for write:
8This parameter is a requirement to the display connected to the IPU
Table 58. Asynchronous Parallel Interface Timing Parameters—Access Level (continued)
ID Parameter Symbol Min. Typ.1Max. Units
Tdicpr THSP_CLK ceil⋅DISP#_IF_CLK_PER_RD
HSP_CLK_PERIOD
----------------------------------------------------------------
=
Tdicpw THSP_CLK ceil⋅DISP#_IF_CLK_PER_WR
HSP_CLK_PERIOD
------------------------------------------------------------------
=
Tdicdr 1
2
---THSP_CLK ceil 2 DISP#_IF_CLK_DOWN_RD⋅HSP_CLK_PERIOD
-------------------------------------------------------------------------------
⋅=
Tdicur 1
2
---THSP_CLK ceil 2 DISP#_IF_CLK_UP_RD⋅HSP_CLK_PERIOD
--------------------------------------------------------------------
⋅=
Tdicdw 1
2
---THSP_CLK ceil 2 DISP#_IF_CLK_DOWN_WR⋅HSP_CLK_PERIOD
---------------------------------------------------------------------------------
⋅=
Tdicuw 1
2
---THSP_CLK ceil 2 DISP#_IF_CLK_UP_WR⋅HSP_CLK_PERIOD
----------------------------------------------------------------------
⋅=
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 87
The following parameters are programmed via the DI_DISP#_TIME_CONF_1,
DI_DISP#_TIME_CONF_2, and DI_HSP_CLK_PER registers:
• DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD
• HSP_CLK_PERIOD
• DISP#_IF_CLK_DOWN_WR
• DISP#_IF_CLK_UP_WR
• DISP#_IF_CLK_DOWN_RD
• DISP#_IF_CLK_UP_RD
• DISP#_READ_EN
4.9.13.5 Serial Interfaces, Functional Description
The IPU supports the following types of asynchronous serial interfaces:
• 3-wire (with bidirectional data line)
• 4-wire (with separate data input and output lines)
• 5-wire type 1 (with sampling RS by the serial clock)
• 5-wire type 2 (with sampling RS by the chip select signal)
Figure 62 depicts timing of the 3-wire serial interface. The timing images correspond to active-low
DISPB_D#_CS signal and the straight polarity of the DISPB_SD_D_CLK signal.
For this interface, a bidirectional data line is used outside the device. The IPU still uses separate input and
output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux connects the
internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D signal
provided by the IPU.
Each data transfer can be preceded by an optional preamble with programmable length and contents. The
preamble is followed by read/write (RW) and address (RS) bits. The order of the these bits is
programmable. The RW bit can be disabled. The following data can consist of one word or of a whole
burst. The interface parameters are controlled by the DI_SER_DISPn_CONF registers (n = 1, 2).
9Data read point
10 Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
device – level output delay, board delays, a device – level input delay, an IPU input delay. This value is device specific.
Tdrp THSP_CLK ceil DISP#_READ_EN
HSP_CLK_PERIOD
--------------------------------------------------
⋅=
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor88
Figure 62. 3-Wire Serial Interface Timing Diagram
Figure 63 depicts timing of the 4-wire serial interface. For this interface, there are separate input and output
data lines both inside and outside the device.
Figure 63. 4-Wire Serial Interface Timing Diagram
Preamble
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D RW RS
Input or output data
D7 D6 D5 D4 D3 D2 D1 D0
1 display IF
clock cycle
1 display IF
clock cycle
Preamble
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D RW RS
Output data
D7 D6 D5 D4 D3 D2 D1 D0
DISPB_SD_D
(Output)
(Input)
Preamble
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D RW RS
Input data
DISPB_SD_D D7 D6 D5 D4 D3 D2 D1 D0
(Output)
(Input)
Write
Read
1 display IF
clock cycle
1 display IF
clock cycle
1 display IF
clock cycle
1 display IF
clock cycle
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 89
Figure 64 depicts timing of the 5-wire serial interface (Type 1). For this interface, a separate RS line is
added. When a burst is transmitted within a single active chip select interval, the RS can be changed at
boundaries of words.
Figure 64. 5-Wire Serial Interface (Type 1) Timing Diagram
Preamble
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D RW D7 D6 D5 D4 D3 D2 D1 D0
DISPB_SD_D
(Output)
(Input)
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D RW
DISPB_SD_D D7 D6 D5 D4 D3 D2 D1 D0
(Output)
(Input)
Write
Read
DISPB_SER_RS
DISPB_SER_RS
1 display IF
clock cycle
1 display IF
clock cycle
Output data
1 display IF
clock cycle
1 display IF
clock cycle
Preamble
Input data
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor90
Figure 65 depicts timing of the 5-wire serial interface (Type 2). For this interface, a separate RS line is
added. When a burst is transmitted within a single active chip select interval, the RS can be changed at
boundaries of words.
Figure 65. 5-Wire Serial Interface (Type 2) Timing Diagram
Preamble
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D RW
Output data
D7 D6 D5 D4 D3 D2 D1 D0
DISPB_SD_D
(Output)
(Input)
Preamble
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D RW
Input data
DISPB_SD_D
D7 D6 D5 D4 D3 D2 D1 D0
(Output)
(Input)
Write
Read
DISPB_SER_RS
DISPB_SER_RS
1 display IF
clock cycle
1 display IF
clock cycle
1 display IF
clock cycle
1 display IF
clock cycle
1 display IF
clock cycle
1 display IF
clock cycle
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 91
4.9.13.5.10 Serial Interfaces, Electrical Characteristics
Figure 66 depicts timing of the serial interface. Table 59 lists the timing parameters at display access level.
Figure 66. Asynchronous Serial Interface Timing Diagram
Table 59. Asynchronous Serial Interface Timing Parameters—Access Level
ID Parameter Symbol Min. Typ.1Max. Units
IP48 Read system cycle time Tcycr Tdicpr – 1.5 Tdicpr2Tdicpr + 1.5 ns
IP49 Write system cycle time Tcycw Tdicpw – 1.5 Tdicpw3Tdicpw + 1.5 ns
IP50 Read clock low pulse width Trl Tdicdr – Tdicur – 1.5 Tdicdr4–Tdicur
5Tdicdr – Tdicur + 1.5 ns
IP51 Read clock high pulse width Trh Tdicpr – Tdicdr + Tdicur
–1.5
Tdicpr – Tdicdr +
Tdicur
Tdicpr – Tdicdr + Tdicur
+1.5
ns
IP52 Write clock low pulse width Twl Tdicdw – Tdicuw – 1.5 Tdicdw6–
Tdicuw7
Tdicdw – Tdicuw + 1.5 ns
IP53 Write clock high pulse width Twh Tdicpw – Tdicdw +
Tdicuw – 1.5
Tdicpw – Tdicdw
+Tdicuw
Tdicpw – Tdicdw +
Tdicuw + 1.5
ns
IP54 Controls setup time for read Tdcsr Tdicur – 1.5 Tdicur — ns
IP49, IP48
Read Data
IP51, IP53
IP58 IP59
DISPB_SER_RS
DISPB_DATA
DISPB_DATA
(Input)
(Output)
IP56,IP54 IP57, IP55
IP50, IP52
IP61
IP60
IP67,IP65
IP47
IP64, IP66
IP62, IP63
DISPB_SD_D_CLK
read point
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor92
IP55 Controls hold time for read Tdchr Tdicpr – Tdicdr – 1.5 Tdicpr – Tdicdr — ns
IP56 Controls setup time for write Tdcsw Tdicuw – 1.5 Tdicuw — ns
IP57 Controls hold time for write Tdchw Tdicpw – Tdicdw – 1.5 Tdicpw – Tdicdw — ns
IP58 Slave device data delay8Tr a c c 0 — T d r p 9–Tlbd
10 –Tdicur
–1.5
ns
IP59 Slave device data hold time8Troh Tdrp–Tlbd–Tdicdr
+1.5
— Tdicpr – Tdicdr – 1.5 ns
IP60 Write data setup time Tds Tdicdw – 1.5 Tdicdw — ns
IP61 Write data hold time Tdh Tdicpw – Tdicdw – 1.5 Tdicpw – Tdicdw — ns
IP62 Read period2Tdicpr Tdicpr – 1.5 Tdicpr Tdicpr + 1.5 ns
IP63 Write period3Tdicpw Tdicpw – 1.5 Tdicpw Tdicpw + 1.5 ns
IP64 Read down time4Tdicdr Tdicdr – 1.5 Tdicdr Tdicdr + 1.5 ns
IP65 Read up time5Tdicur Tdicur – 1.5 Tdicur Tdicur + 1.5 ns
IP66 Write down time6Tdicdw Tdicdw – 1.5 Tdicdw Tdicdw + 1.5 ns
IP67 Write up time7Tdicuw Tdicuw – 1.5 Tdicuw Tdicuw + 1.5 ns
IP68 Read time point9Tdrp Tdrp – 1.5 Tdrp Tdrp + 1.5 ns
1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be device specific.
2Display interface clock period value for read:
3Display interface clock period value for write:
4Display interface clock down time for read:
5Display interface clock up time for read:
6Display interface clock down time for write:
7Display interface clock up time for write:
8This parameter is a requirement to the display connected to the IPU.
Table 59. Asynchronous Serial Interface Timing Parameters—Access Level (continued)
ID Parameter Symbol Min. Typ.1Max. Units
Tdicpr THSP_CLK ceil⋅DISP#_IF_CLK_PER_RD
HSP_CLK_PERIOD
----------------------------------------------------------------
=
Tdicpw THSP_CLK ceil⋅DISP#_IF_CLK_PER_WR
HSP_CLK_PERIOD
------------------------------------------------------------------
=
Tdicdr 1
2
---THSP_CLK ceil 2 DISP#_IF_CLK_DOWN_RD⋅HSP_CLK_PERIOD
-------------------------------------------------------------------------------
⋅=
Tdicur 1
2
---THSP_CLK ceil 2 DISP#_IF_CLK_UP_RD⋅HSP_CLK_PERIOD
--------------------------------------------------------------------
⋅=
Tdicdw 1
2
---THSP_CLK ceil 2 DISP#_IF_CLK_DOWN_WR⋅HSP_CLK_PERIOD
---------------------------------------------------------------------------------
⋅=
Tdicuw 1
2
---THSP_CLK ceil 2 DISP#_IF_CLK_UP_WR⋅HSP_CLK_PERIOD
----------------------------------------------------------------------
⋅=
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 93
The following parameters are programmed via the DI_DISP#_TIME_CONF_1,
DI_DISP#_TIME_CONF_2, and DI_HSP_CLK_PER registers:
• DISP#_IF_CLK_PER_WR
• DISP#_IF_CLK_PER_RD
• HSP_CLK_PERIOD
• DISP#_IF_CLK_DOWN_WR
• DISP#_IF_CLK_UP_WR
• DISP#_IF_CLK_DOWN_RD
• DISP#_IF_CLK_UP_RD
• DISP#_READ_EN
4.9.14 Memory Stick Host Controller (MSHC)
Figure 67, Figure 68, and Figure 69 depict the MSHC timings, and Table 60 and Table 61 list the timing
parameters.
Figure 67. MSHC_CLK Timing Diagram
9Data read point:
10 Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
device-level output delay, board delays, a device-level input delay, and an IPU input delay. This value is device specific.
Tdrp THSP_CLK ceil DISP#_READ_EN
HSP_CLK_PERIOD
--------------------------------------------------
⋅=
tSCLKwh tSCLKwl
tSCLKc
tSCLKr tSCLKf
MSHC_SCLK
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor94
Figure 68. Transfer Operation Timing Diagram (Serial)
tSCLKc
MSHC_SCLK
tBSsu tBSh
tDsu tDh
MSHC_BS
MSHC_DATA
(Output)
tDd
MSHC_DATA
(Intput)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 95
Figure 69. Transfer Operation Timing Diagram (Parallel)
NOTE
The memory stick host controller is designed to meet the timing
requirements per Sony's Memory Stick Pro Format Specifications. Tables in
this section detail the specifications’ requirements for parallel and serial
modes, and not the i.MX35 timing.
Table 60. Serial Interface Timing Parameters1
Signal Parameter Symbol
Standards
Unit
Min. Max.
MSHC_SCLK Cycle tSCLKc 50 — ns
H pulse length tSCLKwh 15 — ns
L pulse length tSCLKwl 15 — ns
Rise time tSCLKr — 10 ns
Fall time tSCLKf — 10 ns
MSHC_BS Setup time tBSsu 5 — ns
Hold time tBSh 5 — ns
tSCLKc
MSHC_SCLK
tBSsu tBSh
tDsu tDh
MSHC_BS
MSHC_DATA
(Output)
tDd
MSHC_DATA
(Input)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor96
4.9.15 MediaLB Controller Electrical Specifications
This section describes the electrical information of the MediaLB Controller module.
MSHC_DATA Setup time tDsu 5 — ns
Hold time tDh 5 — ns
Output delay time tDd — 15 ns
1Timing is guaranteed for NVCC from 2.7 V through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See NVCC
restrictions described in Ta b l e 6 1 .
Table 61. Parallel Interface Timing Parameters1
1Timing is guaranteed for NVCC from 2.7 V through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See the NVCC
restrictions described in Table 8.
Signal Parameter Symbol
Standards
Unit
Min. Max.
MSHC_SCLK Cycle tSCLKc 25 — ns
H pulse length tSCLKwh 5 — ns
L pulse length tSCLKwl 5 — ns
Rise time tSCLKr — 10 ns
Fall time tSCLKf — 10 ns
MSHC_BS Setup time tBSsu 8 — ns
Hold time tBSh 1 — ns
MSHC_DATA Setup time tDsu 8 — ns
Hold time tDh 1 — ns
Output delay time tDd — 15 ns
Table 62. MLB 256/512 Fs Timing Parameters
Parameter Symbol Min Typ Max Units Comment
MLBCLK operating frequency1fmck 11.264
12.288
24.576
24.6272
25.600
MHz Min: 256 ×Fs at 44.0 kHz
Typ : 2 5 6 ×Fs at 48.0 kHz
Typ : 5 1 2 ×Fs at 48.0 kHz
Max: 512 ×Fs at 48.1 kHz
Max: 512 ×Fs PLL unlocked
MLBCLK rise time tmckr —— 3 ns V
IL TO VIH
Table 60. Serial Interface Timing Parameters1 (continued)
Signal Parameter Symbol
Standards
Unit
Min. Max.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 97
Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing parameters
specified from the valid voltage threshold as listed below unless otherwise noted.
MLB fall time tmckf —— 3 ns V
IH TO VIL
MLBCLK cycle time tmckc —
—
81
40
—
—
ns 256 ×Fs
512 ×Fs
MLBCLK low time tmckl 31.5
30
37
35.5
—
—
ns 256 ×Fs
256 ×Fs PLL unlocked
14.5
14
17
16.5
—
—
ns 512 ×Fs
512 ×Fs PLL unlocked
MLBCLK high time tmckh 31.5
30
38
36.5
—
—
ns 256 ×Fs
256 ×Fs PLL unlocked
14.5
14
17
16.5
—
—
ns 512 ×Fs
512 ×Fs PLL unlocked
MLBCLK pulse width variation tmpwv —— 2ns pp Note
2
MLBSIG/MLBDAT input valid to
MLBCLK falling
tdsmcf 1— — ns —
MLBSIG/MLBDAT input hold
from MLBCLK low
tdhmcf 0— — ns —
MLBSIG/MLBDAT output high
impedance from MLBCLK low
tmcfdz 0—t
mckl ns —
Bus Hold Time tmdzh 4— — ns Note
3
1The MLB controller can shut off MLBCLK to place MediaLB in a low-power state.
2Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (pp)
3The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
Table 63. MLB Device 1024Fs Timing Parameters
Parameter Symbol Min Typ Max Units Comment
MLBCLK Operating
Frequency1
fmck 45.056
49.152
49.2544
51.200
MHz Min: 1024 ×Fs at 44.0 kHz
Typ: 1024 ×Fs at 48.0 kHz
Max: 1024 ×Fs at 48.1 kHz
Max: 1024 ×Fs PLL unlocked
MLBCLK rise time tmckr —— 1 ns V
IL TO VIH
MLB fall time tmckf —— 1 ns V
IH TO VIL
MLBCLK cycle time tmckc — 20.3 — ns —
MLBCLK low time tmckl 6.5
6.1
7.7
7.3
— ns PLL unlocked
Table 62. MLB 256/512 Fs Timing Parameters (continued)
Parameter Symbol Min Typ Max Units Comment
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4.9.16 1-Wire Timing Specifications
Figure 70 depicts the RPP timing, and Table 64 lists the RPP timing parameters.
Figure 70. Reset and Presence Pulses (RPP) Timing Diagram
MLBCLK high time tmckh 9.7
9.3
10.6
10.2
—
—
ns PLL unlocked
MLBCLK pulse width variation tmpwv ——0.7ns pp Note
2
MLBSIG/MLBDAT input valid
to MLBCLK falling
tdsmcf 1——ns —
MLBSIG/MLBDAT input hold
from MLBCLK low
tdhmcf 0——ns —
MLBSIG/MLBDAT output high
impedance from MLBCLK low
tmcfdz 0—t
mckl ns —
Bus Hold Time tmdzh 2——ns Note
3
1The MLB Controller can shut off MLBCLK to place MediaLB in a low-power state.
2Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge,
measured in ns peak-to-peak (pp)
3The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
Table 64. RPP Sequence Delay Comparisons Timing Parameters
ID Parameters Symbol Min. Typ. Max. Units
OW1 Reset time low tRSTL 480 511 — µs
OW2 Presence detect high tPDH 15 — 60 µs
OW3 Presence detect low tPDL 60 — 240 µs
OW4 Reset time high tRSTH 480 512 — µs
Table 63. MLB Device 1024Fs Timing Parameters (continued)
Parameter Symbol Min Typ Max Units Comment
1-Wire bus
DS2502 Tx
“Presence Pulse”
(BATT_LINE)
1-WIRE Tx
“Reset Pulse”
OW1
OW2
OW3
OW4
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Freescale Semiconductor 99
Figure 71 depicts write 0 sequence timing, and Table 65 lists the timing parameters.
Figure 71. Write 0 Sequence Timing Diagram
Figure 72 shows write 1 sequence timing, and Figure 73 depicts the read sequence timing. Table 66 lists
the timing parameters.
Figure 72. Write 1 Sequence Timing Diagram
Figure 73. Read Sequence Timing Diagram
Table 65. WR0 Sequence Timing Parameters
ID Parameter Symbol Min. Typ. Max. Units
OW5 Write 0 low time tWR0_low 60 100 120 µs
OW6 Transmission time slot tSLOT OW5 117 120 µs
Table 66. WR1/RD Timing Parameters
ID Parameter Symbol Min. Typ. Max. Units
OW7 Write 1/read low time tLOW1 1515 µs
OW8 Transmission time slot tSLOT 60 117 120 µs
OW9 Release time tRELEASE 15 — 45 µs
OW5
OW6
1-Wire bus
(BATT_LINE)
OW7
OW8
1-Wire bus
(BATT_LINE)
OW7
OW8
OW9
1-Wire bus
(BATT_LINE)
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4.9.17 Parallel ATA Module AC Electrical Specifications
The parallel ATA module can work on PIO/multiword DMA/ultra-DMA transfer modes (not available for
the MCIMX351). Each transfer mode has a different data transfer rate, Ultra DMA mode 4 data transfer
rate is up to 100 MBps.
The parallel ATA module interface consists of a total of 29 pins. Some pins have different functions in
different transfer modes. There are various requirements for timing relationships among the function pins,
in compliance with the ATA/ATAPI-6 specification, and these requirements are configurable by the ATA
module registers.
4.9.17.1 General Timing Requirements
Table 67 and Figure 74 define the AC characteristics of the interface signals on all data transfer modes.
Figure 74. ATA Interface Signals Timing Diagram
4.9.17.2 ATA Electrical Specifications (ATA Bus, Bus Buffers)
This section discusses ATA parameters. For a detailed description, refer to the ATA-6 specification.
Level shifters are required for 3.3-V or 5.0-V compatibility on the ATA interface.
The use of bus buffers introduces delays on the bus and introduces skew between signal lines. These factors
make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. Use of bus
buffers is not recommended if fast UDMA mode is required.
The ATA specification imposes a slew rate limit on the ATA bus. According to this limit, any signal driven
on the bus should have a slew rate between 0.4 and 1.2 V/ns with a 40 pF load. Few vendors of bus buffers
specify the slew rate of the outgoing signals.
When bus buffers are used the ata_data bus buffer is bidirectional, and uses the direction control signal
ata_buffer_en. When ata_buffer_en is asserted, the bus should drive from host to device. When
Table 67. AC Characteristics of All Interface Signals
ID Parameter Symbol Min. Max. Unit
SI1 Rising edge slew rate for any signal on the ATA interface1
1SRISE and SFALL meet this requirement when measured at the sender’s connector from 10–90% of full signal amplitude with
all capacitive loads from 15 pF through 40 pF, where all signals have the same capacitive load value.
Srise1—1.25V/ns
SI2 Falling edge slew rate for any signal on the ATA interface1Sfall1—1.25V/ns
SI3 Host interface signal capacitance at the host connector Chost —20pF
ATA Interface Signals
SI1SI2
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Freescale Semiconductor 101
ata_buffer_en is negated, the bus drives from device to host. Steering of the signal is such that contention
on the host and device tri-state buses is always avoided.
4.9.17.3 Timing Parameters
Table 68 shows the parameters used in the timing equations. These parameters depend on the
implementation of the ATA interface on silicon, the bus buffer used, the cable delay, and the cable skew.
Table 68. ATA Timing Parameters
Name Description Value/
Contributing Factor1
1Values provided where applicable.
T Bus clock period (ipg_clk_ata) Peripheral clock
frequency
ti_ds Set-up time ata_data to ata_iordy edge (UDMA-in only)
UDMA0
UDMA1
UDMA2, UDMA3
UDMA4
UDMA5
15 ns
10 ns
7ns
5ns
4ns
ti_dh Hold time ata_iordy edge to ata_data (UDMA-in only)
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA5
5.0 ns
4.6 ns
tco Propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data,
ata_buffer_en
12.0 ns
tsu Set-up time ata_data to bus clock L-to-H 8.5 ns
tsui Set-up time ata_iordy to bus clock H-to-L 8.5 ns
thi Hold time ata_iordy to bus clock H to L 2.5 ns
tskew1 Maximum difference in propagation delay bus clock L-to-H to any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
7ns
tskew2 Maximum difference in buffer propagation delay for any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
Transceiver
tskew3 Maximum difference in buffer propagation delay for any of following signals ata_iordy,
ata_data (read)
Transceiver
tbuf Maximum buffer propagation delay Transceiver
tcable1 Cable propagation delay for ata_data Cable
tcable2 Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack Cable
tskew4 Maximum difference in cable propagation delay between ata_iordy and ata_data (read) Cable
tskew5 Maximum difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack)
and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
Cable
tskew6 Maximum difference in cable propagation delay without accounting for ground bounce Cable
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4.9.17.4 PIO Mode Timing
Figure 75 shows timing for PIO read, and Table 69 lists the timing parameters for PIO read.
Figure 75. PIO Read Timing Diagram
Table 69. PIO Read Timing Parameters
ATA
Parameter
Parameter from
Figure 75 Value Controlling
Variable
t1 t1 t1 (min.) = time_1 × T – (tskew1 + tskew2 + tskew5) time_1
t2 t2r t2 min.) = time_2r × T – (tskew1 + tskew2 + tskew5) time_2r
t9 t9 t9 (min.) = time_9 × T – (tskew1 + tskew2 + tskew6) time_3
t5 t5 t5 (min.) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 If not met, increase
time_2
t6 t6 0 —
tA tA tA (min.) = (1.5 + time_ax) × T – (tco + tsui + tcable2 + tcable2 + 2 ×tbuf) time_ax
trd trd1 trd1 (max.) = (–trd) + (tskew3 + tskew4)
trd1 (min.) = (time_pio_rdx – 0.5) ×T – (tsu + thi)
(time_pio_rdx – 0.5) × T > tsu + thi + tskew3 + tskew4
time_pio_rdx
t0 — t0 (min.) = (time_1 + time_2 + time_9) × T time_1, time_2r, time_9
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Figure 76 shows timing for PIO write, and Table 70 lists the timing parameters for PIO write.
Figure 76. PIO Write Timing Diagram
Table 70. PIO Write Timing Parameters
ATA
Parameter
Parameter
from
Figure 76
Value Controlling
Variable
t1 t1 t1 (min.) = time_1 × T – (tskew1 + tskew2 + tskew5) time_1
t2 t2w t2 (min.) = time_2w × T – (tskew1 + tskew2 + tskew5) time_2w
t9 t9 t9 (min.) = time_9 × T – (tskew1 + tskew2 + tskew6) time_9
t3 — t3 (min.) = (time_2w – time_on) × T – (tskew1 + tskew2 +tskew5) If not met, increase
time_2w
t4 t4 t4 (min.) = time_4 × T – tskew1 time_4
tA tA tA = (1.5 + time_ax) × T – (tco + tsui + tcable2 + tcable2 + 2*tbuf) time_ax
t0 — t0(min.) = (time_1 + time_2 + time_9) × T time_1, time_2r,
time_9
— — Avoid bus contention when switching buffer on by making ton long enough. —
— — Avoid bus contention when switching buffer off by making toff long enough. —
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Figure 77 shows timing for MDMA read, and Figure 78 shows timing for MDMA write. Table 71 lists the
timing parameters for MDMA read and write.
Figure 77. MDMA Read Timing Diagram
Figure 78. MDMA Write Timing Diagram
Table 71. MDMA Read and Write Timing Parameters
ATA
Parameter
Parameter
from
Figure 77,
Figure 78
Value Controlling
Variable
tm, ti tm tm (min.) = ti (min.) = time_m × T – (tskew1 + tskew2 + tskew5) time_m
td td, td1 td1.(min.) = td (min.) = time_d × T – (tskew1 + tskew2 + tskew6) time_d
tk tk tk.(min.) = time_k × T – (tskew1 + tskew2 + tskew6) time_k
t0 — t0 (min.) = (time_d + time_k) × T time_d, time_k
tg(read) tgr tgr (min. – read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2
tgr.(min. – drive) = td – te(drive)
time_d
tf(read) tfr tfr (min. – drive) = 0 —
tg(write) — tg (min. – write) = time_d × T – (tskew1 + tskew2 + tskew5) time_d
tf(write) — tf (min. – write) = time_k × T – (tskew1 + tskew2 + tskew6) time_k
tL — tL (max.) = (time_d + time_k–2) × T – (tsu + tco + 2 × tbuf + 2 ×tcable2) time_d, time_k
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4.9.17.5 UDMA-In Timing
Figure 79 shows timing when the UDMA-in transfer starts, Figure 80 shows timing when the UDMA-in
host terminates transfer, Figure 81 shows timing when the UDMA-in device terminates transfer, and
Table 72 lists the timing parameters for the UDMA-in burst.
Figure 79. UDMA-In Transfer Starts Timing Diagram
Figure 80. UDMA-In Host Terminates Transfer Timing Diagram
tn, tj tkjn tn = tj = tkjn = (max.(time_k,. time_jn) × T – (tskew1 + tskew2 + tskew6) time_jn
—ton
toff
ton = time_on × T – tskew1
toff = time_off × T – tskew1
—
Table 71. MDMA Read and Write Timing Parameters (continued)
ATA
Parameter
Parameter
from
Figure 77,
Figure 78
Value Controlling
Variable
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Figure 81. UDMA-In Device Terminates Transfer Timing Diagram
Table 72. UDMA-In Burst Timing Parameters
ATA
Parameter
Parameters
from
Figure 79,
Figure 80,
Figure 81
Description Controlling Variable
tack tack tack (min.) = (time_ack × T) – (tskew1 + tskew2) time_ack
tenv tenv tenv (min.) = (time_env × T) – (tskew1 + tskew2)
tenv (max.) = (time_env × T) + (tskew1 + tskew2)
time_env
tds tds1 tds – (tskew3) – ti_ds > 0 tskew3, ti_ds, ti_dh
should be low enough
tdh tdh1 tdh – (tskew3) – ti_dh > 0
tcyc tc1 (tcyc – tskew > T T big enough
trp trp trp (min.) = time_rp × T – (tskew1 + tskew2 + tskew6) time_rp
—tx1
1
1There is a special timing requirement in the ATA host that requires the internal DIOW to go high three clocks after the last active
edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
2. Make ton and toff large enough to avoid bus contention.
(time_rp × T) – (tco + tsu + 3T + 2 × tbuf + 2 × tcable2) > trfs (drive) time_rp
tmli tmli1 tmli1 (min.) = (time_mlix + 0.4) × T time_mlix
tzah tzah tzah (min.) = (time_zah + 0.4) × T time_zah
tdzfs tdzfs tdzfs = (time_dzfs × T) – (tskew1 + tskew2) time_dzfs
tcvh tcvh tcvh = (time_cvh × T) – (tskew1 + tskew2) time_cvh
—ton
toff
ton = time_on × T – tskew1
toff = time_off × T – tskew1
—
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4.9.17.6 UDMA-Out Timing
Figure 82 shows timing when the UDMA-out transfer starts, Figure 83 shows timing when the UDMA-out
host terminates transfer, Figure 84 shows timing when the UDMA-out device terminates transfer, and
Table 73 lists the timing parameters for the UDMA-out burst.
Figure 82. UDMA-Out Transfer Starts Timing Diagram
Figure 83. UDMA-Out Host Terminates Transfer Timing Diagram
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Freescale Semiconductor108
Figure 84. UDMA-Out Device Terminates Transfer Timing Diagram
Table 73. UDMA-Out Burst Timing Parameters
ATA
Parameter
Parameter
from
Figure 82,
Figure 83,
Figure 84
Value Controlling
Variable
tack tack tack (min.) = (time_ack × T) – (tskew1 + tskew2) time_ack
tenv tenv tenv (min.) = (time_env × T) – (tskew1 + tskew2)
tenv (max.) = (time_env × T) + (tskew1 + tskew2)
time_env
tdvs tdvs tdvs = (time_dvs ×T) – (tskew1 + tskew2) time_dvs
tdvh tdvh tdvs = (time_dvh × T) – (tskew1 + tskew2) time_dvh
tcyc tcyc tcyc = time_cyc × T – (tskew1 + tskew2) time_cyc
t2cyc — t2cyc = time_cyc × 2 × T time_cyc
trfs1 trfs trfs = 1.6 × T + tsui + tco + tbuf + tbuf —
— tdzfs tdzfs = time_dzfs × T – (tskew1) time_dzfs
tss tss tss = time_ss × T – (tskew1 + tskew2) time_ss
tmli tdzfs_mli tdzfs_mli = max. (time_dzfs, time_mli) × T – (tskew1 + tskew2) —
tli tli1 tli1 > 0 —
tli tli2 tli2 > 0 —
tli tli3 tli3 > 0 —
tcvh tcvh tcvh = (time_cvh ×T) – (tskew1 + tskew2) time_cvh
—ton
toff
ton = time_on × T – tskew1
toff = time_off × T – tskew1
—
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4.9.18 Parallel Interface (ULPI) Timing
Electrical and timing specifications of the parallel interface are presented in the subsequent sections.
Figure 85. USB Transmit/Receive Waveform in Parallel Mode
4.9.19 PWM Electrical Specifications
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
Table 74. Signal Definitions—Parallel Interface
Name Direction Signal Description
USB_Clk In Interface clock. All interface signals are synchronous to the clock.
USB_Data[7:0] I/O Bidirectional data bus, driven low by the link during idle. Bus ownership is determined by Dir.
USB_Dir In Direction. Control the direction of the data bus.
USB_Stp Out Stop. The link asserts this signal for 1 clock cycle to stop the data stream currently on the bus.
USB_Nxt In Next. The PHY asserts this signal to throttle the data.
Table 75. USB Timing Specification in VP_VM Unidirectional Mode
ID Parameter Min. Max. Unit Conditions /
Reference Signal
US15 USB_TXOE_B — 6.0 ns 10 pF
US16 USB_DAT_VP — 0.0 ns 10 pF
US17 USB_SE0_VM — 9.0 ns 10 pF
USB_Dir/Nxt
USB_Stp
US17
US16
USB_Data
US15
US16
US15
US17
USB_Clk
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Freescale Semiconductor110
pin. The modulated signal of the module is observed at this pin. It can be viewed as a clock signal whose
period and duty cycle can be varied with different settings of the PWM. The smallest period is two ipg_clk
periods with duty cycle of 50 percent.
4.9.20 SJC Electrical Specifications
This section details the electrical characteristics for the SJC module. Figure 86 depicts the SJC test clock
input timing. Figure 87 depicts the SJC boundary scan timing, Figure 88 depicts the SJC test access port,
Figure 89 depicts the SJC TRST timing, and Table 76 lists the SJC timing parameters.
Figure 86. Test Clock Input Timing Diagram
Figure 87. Boundary Scan (JTAG) Timing Diagram
TCK
(Input) VM VM
VIH VIL
SJ1
SJ2 SJ2
SJ3
SJ3
TCK
(Input)
Data
Inputs
Data
Outputs
Data
Outputs
Data
Outputs
VIH
VIL
Input Data Valid
Output Data Valid
Output Data Valid
SJ4 SJ5
SJ6
SJ7
SJ6
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Figure 88. Test Access Port Timing Diagram
Figure 89. TRST Timing Diagram
Table 76. SJC Timing Parameters
ID Parameter
All Frequencies
Unit
Min. Max.
SJ1 TCK cycle time 1001—ns
SJ2 TCK clock pulse width measured at VM240 — ns
SJ3 TCK rise and fall times — 3 ns
SJ4 Boundary scan input data set-up time 10 — ns
SJ5 Boundary scan input data hold time 50 — ns
SJ6 TCK low to output data valid — 50 ns
SJ7 TCK low to output high impedance — 50 ns
SJ8 TMS, TDI data set-up time 10 — ns
SJ9 TMS, TDI data hold time 50 — ns
SJ10 TCK low to TDO data valid — 44 ns
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output)
TDO
(Output)
VIH
VIL
Input Data Valid
Output Data Valid
Output Data Valid
TMS
SJ8 SJ9
SJ10
SJ11
SJ10
TCK
(Input)
TRST
(Input)
SJ13
SJ12
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4.9.21 SPDIF Timing
SPDIF data is sent using bi-phase marking code. When encoding, the SPDIF data signal is modulated by
a clock that is twice the bit rate of the data signal.
Figure 90 shows SPDIF timing parameters, including the timing of the modulating Rx clock (SRCK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (STCLK). for SPDIF in Tx mode.
SJ11 TCK low to TDO high impedance — 44 ns
SJ12 TRST assert time 100 — ns
SJ13 TRST set-up time to TCK low 40 — ns
1On cases where SDMA TAP is put in the chain, the max. TCK frequency is limited by max. ratio of 1:8 of SDMA core frequency
to TCK limitation. This implies max. frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock.
2VM = mid point voltage
Table 77. SPDIF Timing Parameters
Parameters Symbol
Timing Parameter Range
Units
Min. Max.
SPDIFIN Skew: asynchronous inputs, no specs apply — — 0.7 ns
SPDIFOUT output (Load = 50 pf)
•Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
24.2
31.3
ns
SPDIFOUT1 output (Load = 30 pf)
•Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
13.6
18.0
ns
Modulating Rx clock (SRCK) period srckp 40.0 — ns
SRCK high period srckph 16.0 — ns
SRCK low period srckpl 16.0 — ns
Modulating Tx clock (STCLK) period stclkp 40.0 — ns
STCLK high period stclkph 16.0 — ns
STCLK low period stclkpl 16.0 — ns
Table 76. SJC Timing Parameters (continued)
ID Parameter
All Frequencies
Unit
Min. Max.
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Figure 90. SRCK Timing
Figure 91. STCLK Timing
4.9.22 SSI Electrical Specifications
This section describes electrical characteristics of the SSI.
NOTE
• All of the timing for the SSI is given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
• All timing is on AUDMUX signals when SSI is being used for data
transfer.
• “Tx” and “Rx” refer to the transmit and receive sections of the SSI,
respectively.
• For internal frame sync operations using the external clock, the FS
timing will be the same as that of Tx Data (for example, during AC97
mode of operation).
SRCK
(Output)
VMVM
srckp
srckph
srckpl
STCLK
(Input)
VMVM
stclkp
stclkph
stclkpl
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4.9.22.1 SSI Transmitter Timing with Internal Clock
Figure 92 depicts the SSI transmitter timing with internal clock, and Table 78 lists the timing parameters.
Figure 92. SSI Transmitter with Internal Clock Timing Diagram
SS19
AD1_TXC
AD1_TXFS (bl)
AD1_TXFS (wl)
SS1
AD1_TXD
AD1_RXD
SS2 SS4
SS3
SS5
SS6 SS8
SS10 SS12
SS14
SS18
SS15
SS17
SS16
SS43
SS42
Note: SRXD Input in Synchronous mode only
(Output)
(Output)
(Output)
(Output)
(Input)
SS19
DAM1_T_CLK
DAM1_T_FS (bl)
DAM1_T_FS (wl)
SS1
DAM1_TXD
DAM1_RXD
SS2 SS4
SS3
SS5
SS6 SS8
SS10 SS12
SS14
SS18
SS15
SS17SS16
SS42
Note: SRXD Input in Synchronous mode only
(Output)
(Output)
(Output)
(Output)
(Input)
SS43
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Table 78. SSI Transmitter with Internal Clock Timing Parameters
ID Parameter Min. Max. Unit
Internal Clock Operation
SS1 (Tx/Rx) CK clock period 81.4 — ns
SS2 (Tx/Rx) CK clock high period 36.0 — ns
SS3 (Tx/Rx) CK clock rise time — 6 ns
SS4 (Tx/Rx) CK clock low period 36.0 — ns
SS5 (Tx/Rx) CK clock fall time — 6 ns
SS6 (Tx) CK high to FS (bl) high — 15.0 ns
SS8 (Tx) CK high to FS (bl) low — 15.0 ns
SS10 (Tx) CK high to FS (wl) high — 15.0 ns
SS12 (Tx) CK high to FS (wl) low — 15.0 ns
SS14 (Tx/Rx) Internal FS rise time — 6 ns
SS15 (Tx/Rx) Internal FS fall time — 6 ns
SS16 (Tx) CK high to STXD valid from high impedance — 15.0 ns
SS17 (Tx) CK high to STXD high/low — 15.0 ns
SS18 (Tx) CK high to STXD high impedance — 15.0 ns
SS19 STXD rise/fall time — 6 ns
Synchronous Internal Clock Operation
SS42 SRXD setup before (Tx) CK falling 10.0 — ns
SS43 SRXD hold after (Tx) CK falling 0 — ns
SS52 Loading —25pF
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4.9.22.2 SSI Receiver Timing with Internal Clock
Figure 93 depicts the SSI receiver timing with internal clock. Table 79 lists the timing parameters shown
in Figure 93.
Figure 93. SSI Receiver with Internal Clock Timing Diagram
SS50
SS48
AD1_TXC
AD1_TXFS (bl)
AD1_TXFS (wl)
AD1_RXD
AD1_RXC
SS1
SS4SS2
SS51
SS20
SS21
SS49
SS7 SS9
SS11 SS13
SS47
(Output)
(Output)
(Output)
(Input)
(Output)
SS3
SS5
SS50
SS48
DAM1_T_CLK
DAM1_T_FS (bl)
DAM1_T_FS (wl)
DAM1_RXD
DAM1_R_CLK
SS3
SS1
SS4
SS2
SS5
SS51
SS20
SS21
SS49
SS7 SS9
SS11 SS13
SS47
(Output)
(Output)
(Output)
(Input)
(Output)
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Table 79. SSI Receiver with Internal Clock Timing Parameters
ID Parameter Min. Max. Unit
Internal Clock Operation
SS1 (Tx/Rx) CK clock period 81.4 — ns
SS2 (Tx/Rx) CK clock high period 36.0 — ns
SS3 (Tx/Rx) CK clock rise time — 6 ns
SS4 (Tx/Rx) CK clock low period 36.0 — ns
SS5 (Tx/Rx) CK clock fall time — 6 ns
SS7 (Rx) CK high to FS (bl) high — 15.0 ns
SS9 (Rx) CK high to FS (bl) low — 15.0 ns
SS11 (Rx) CK high to FS (wl) high — 15.0 ns
SS13 (Rx) CK high to FS (wl) low — 15.0 ns
SS20 SRXD setup time before (Rx) CK low 10.0 — ns
SS21 SRXD hold time after (Rx) CK low 0 — ns
Oversampling Clock Operation
SS47 Oversampling clock period 15.04 — ns
SS48 Oversampling clock high period 6 — ns
SS49 Oversampling clock rise time — 3 ns
SS50 Oversampling clock low period 6 — ns
SS51 Oversampling clock fall time — 3 ns
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4.9.22.3 SSI Transmitter Timing with External Clock
Figure 94 depicts the SSI transmitter timing with external clock, and Table 80 lists the timing parameters.
Figure 94. SSI Transmitter with External Clock Timing Diagram
SS45
SS33
SS24
SS26
SS25
SS23
AD1_TXC
AD1_TXFS (bl)
AD1_TXFS (wl)
AD1_TXD
AD1_RXD
Note: SRXD Input in Synchronous mode only
SS31
SS29
SS27
SS22
SS44
SS39
SS38
SS37
SS46
(Input)
(Input)
(Input)
(Output)
(Input)
SS45
SS33
SS24
SS26
SS25
SS23
DAM1_T_CLK
DAM1_T_FS (bl)
DAM1_T_FS (wl)
DAM1_TXD
DAM1_RXD
Note: SRXD Input in Synchronous mode only
SS31
SS29
SS27
SS22
SS44
SS39
SS38
SS37
SS46
(Input)
(Input)
(Input)
(Output)
(Input)
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Table 80. SSI Transmitter with External Clock Timing Parameters
ID Parameter Min. Max. Unit
External Clock Operation
SS22 (Tx/Rx) CK clock period 81.4 — ns
SS23 (Tx/Rx) CK clock high period 36.0 — ns
SS24 (Tx/Rx) CK clock rise time — 6.0 ns
SS25 (Tx/Rx) CK clock low period 36.0 — ns
SS26 (Tx/Rx) CK clock fall time — 6.0 ns
SS27 (Tx) CK high to FS (bl) high –10.0 15.0 ns
SS29 (Tx) CK high to FS (bl) low 10.0 — ns
SS31 (Tx) CK high to FS (wl) high –10.0 15.0 ns
SS33 (Tx) CK high to FS (wl) low 10.0 — ns
SS37 (Tx) CK high to STXD valid from high impedance — 15.0 ns
SS38 (Tx) CK high to STXD high/low — 15.0 ns
SS39 (Tx) CK high to STXD high impedance — 15.0 ns
Synchronous External Clock Operation
SS44 SRXD setup before (Tx) CK falling 10.0 — ns
SS45 SRXD hold after (Tx) CK falling 2.0 — ns
SS46 SRXD rise/fall time — 6.0 ns
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4.9.22.4 SSI Receiver Timing with External Clock
Figure 95 depicts the SSI receiver timing with external clock, and Table 81 lists the timing parameters.
Figure 95. SSI Receiver with External Clock Timing Diagram
Table 81. SSI Receiver with External Clock Timing Parameters
ID Parameter Min. Max. Unit
External Clock Operation
SS22 (Tx/Rx) CK clock period 81.4 — ns
SS23 (Tx/Rx) CK clock high period 36.0 — ns
SS24 (Tx/Rx) CK clock rise time — 6.0 ns
SS24
SS34
SS35
SS30
SS28
SS26
SS25
SS23
AD1_TXC
AD1_TXFS (bl)
AD1_TXFS (wl)
AD1_RXD
SS40
SS22
SS32
SS36
SS41
(Input)
(Input)
(Input)
(Input)
SS24
SS34
SS35
SS30
SS28
SS26
SS25
SS23
DAM1_T_CLK
DAM1_T_FS (bl)
DAM1_T_FS (wl)
DAM1_RXD
SS40
SS22
SS32
SS36
SS41
(Input)
(Input)
(Input)
(Input)
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4.9.23 UART Electrical
This section describes the electrical information of the UART module.
4.9.23.1 UART RS-232 Serial Mode Timing
The following subsections give the UART transmit and receive timings in RS-232 serial mode.
4.9.23.1.11 UART Transmitter
Figure 96 depicts the transmit timing of UART in RS-232 serial mode, with 8 data bit/1 stop bit format.
Table 82 lists the UART RS-232 serial mode transmit timing characteristics.
Figure 96. UART RS-232 Serial Mode Transmit Timing Diagram
SS25 (Tx/Rx) CK clock low period 36.0 — ns
SS26 (Tx/Rx) CK clock fall time — 6.0 ns
SS28 (Rx) CK high to FS (bl) high –10.0 15.0 ns
SS30 (Rx) CK high to FS (bl) low 10.0 — ns
SS32 (Rx) CK high to FS (wl) high –10.0 15.0 ns
SS34 (Rx) CK high to FS (wl) low 10.0 — ns
SS35 (Tx/Rx) External FS rise time — 6.0 ns
SS36 (Tx/Rx) External FS fall time — 6.0 ns
SS40 SRXD setup time before (Rx) CK low 10.0 — ns
SS41 SRXD hold time after (Rx) CK low 2.0 — ns
Table 81. SSI Receiver with External Clock Timing Parameters (continued)
ID Parameter Min. Max. Unit
Bit 1 Bit 2Bit 0 Bit 4 Bit 5 Bit 6 Bit 7
TXD
(output) Bit 3
Start
Bit STOP
BIT
Next
Start
Bit
Possible
Parity
Bit
Par Bit
UA1
UA1 UA1
UA1
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4.9.23.1.12 UART Receiver
Figure 97 depicts the RS-232 serial mode receive timing, with 8 data bit/1 stop bit format. Table 83 lists
serial mode receive timing characteristics.
Figure 97. UART RS-232 Serial Mode Receive Timing Diagram
4.9.23.2 UART IrDA Mode Timing
The following subsections give the UART transmit and receive timings in IrDA mode.
4.9.23.2.13 UART IrDA Mode Transmitter
Figure 98 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 84 lists
the transmit timing characteristics.
Figure 98. UART IrDA Mode Transmit Timing Diagram
Table 82. RS-232 Serial Mode Transmit Timing Parameters
ID Parameter Symbol Min. Max. Units
UA1 Transmit Bit Time tTbit 1/Fbaud_rate1 –
Tref_clk2
1Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
2Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
1/Fbaud_rate +
Tref_clk
—
Table 83. RS-232 Serial Mode Receive Timing Parameters
ID Parameter Symbol Min. Max. Units
UA2 Receive Bit Time1
1The UART receiver can tolerate 1/(16 ×Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 ×Fbaud_rate).
tRbit 1/Fbaud_rate2 –
1/(16 ×Fbaud_rate)
2Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency) ÷16.
1/Fbaud_rate +
1/(16 ×Fbaud_rate)
—
Bit 1 Bit 2Bit 0 Bit 4 Bit 5 Bit 6 Bit 7
RXD
(input) Bit 3
Start
Bit STOP
BIT
Next
Start
Bit
Possible
Parity
Bit
Par Bit
UA2 UA2
UA2 UA2
Bit 1 Bit 2
Bit 0 Bit 4 Bit 5 Bit 6 Bit 7
TXD
(output)
Bit 3
Start
Bit
STOP
BIT
Possible
Parity
Bit
UA3 UA3 UA3 UA3
UA4
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4.9.23.2.14 UART IrDA Mode Receiver
Figure 99 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 85 lists the
receive timing characteristics.
Figure 99. UART IrDA Mode Receive Timing Diagram
4.9.24 USB Electrical Specifications
In order to support four different serial interfaces, the USB serial transceiver can be configured to operate
in one of four modes:
• DAT_SE0 bidirectional, 3-wire mode
• DAT_SE0 unidirectional, 6-wire mode
• VP_VM bidirectional, 4-wire mode
• VP_VM unidirectional, 6-wire mode
Table 84. IrDA Mode Transmit Timing Parameters
ID Parameter Symbol Min. Max. Units
UA3 Transmit bit time in IrDA mode tTIRbit 1/Fbaud_rate1 –
Tref_clk2
1Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
2Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
1/Fbaud_rate + Tref_clk —
UA4 Transmit IR pulse duration tTIRpulse (3/16) ×(1/Fbaud_rate)
– Tref_clk
(3/16) ×(1/Fbaud_rate)
+ Tref_clk
—
Table 85. IrDA Mode Receive Timing Parameters
ID Parameter Symbol Min. Max. Units
UA5 Receive bit time1 in IrDA mode
1 The UART receiver can tolerate 1/(16 ×Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 ×Fbaud_rate).
tRIRbit 1/Fbaud_rate2 –
1/(16 ×Fbaud_rate)
2Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency) ÷16.
1/Fbaud_rate +
1/(16 ×Fbaud_rate)
—
UA6 Receive IR pulse duration tRIRpulse 1.41 us (5/16) ×(1/Fbaud_rate)—
Bit 1 Bit 2
Bit 0 Bit 4 Bit 5 Bit 6 Bit 7
RXD
(input)
Bit 3
Start
Bit
STOP
BIT
Possible
Parity
Bit
UA5 UA5 UA5 UA5
UA6
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4.9.24.1 DAT_SE0 Bidirectional Mode
Table 86 defines the signals for DAT_SE0 bidirectional mode. Figure 100 and Figure 101 show the
transmit and receive waveforms respectively.
Figure 100. USB Transmit Waveform in DAT_SE0 Bidirectional Mode
Figure 101. USB Receive Waveform in DAT_SE0 Bidirectional Mode
Table 86. Signal Definitions—DAT_SE0 Bidirectional Mode
Name Direction Signal Description
USB_TXOE_B Out Transmit enable, active low
USB_DAT_VP Out
In
Tx data when USB_TXOE_B is low
Differential Rx data when USB_TXOE_B is high
USB_SE0_VM Out
In
SE0 drive when USB_TXOE_B is low
SE0 Rx indicator when USB_TXOE_B is high
USB_DAT_VP
USB_SE0_VM US1
US2
Transmit
US4
USB_TXOE_B
US3
US8US7
USB_DAT_VP
USB_TXOE_B
Receive
USB_SE0_VM
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Table 87 describes the port timing specification in DAT_SE0 bidirectional mode.
4.9.24.2 DAT_SE0 Unidirectional Mode
Table 88 defines the signals for DAT_SE0 unidirectional mode. Figure 102 and Figure 103 show the
transmit and receive waveforms respectively.
Figure 102. USB Transmit Waveform in DAT_SE0 Unidirectional Mode
Table 87. Port Timing Specification in DAT_SE0 Bidirectional Mode
No. Parameter Signal Name Direction Min. Max. Unit Conditions/Reference Signal
US1 Tx rise/fall time USB_DAT_VP Out — 5.0 ns 50 pF
US2 Tx rise/fall time USB_SE0_VM Out — 5.0 ns 50 pF
US3 Tx rise/fall time USB_TXOE_B Out — 5.0 ns 50 pF
US4 Tx duty cycle USB_DAT_VP Out 49.0 51.0 % —
US7 Rx rise/fall time USB_DAT_VP In — 3.0 ns 35 pF
US8 Rx rise/fall time USB_SE0_VM In — 3.0 ns 35 pF
Table 88. Signal Definitions—DAT_SE0 Unidirectional Mode
Name Direction Signal Description
USB_TXOE_B Out Transmit enable, active low
USB_DAT_VP Out Tx data when USB_TXOE_B is low
USB_SE0_VM Out SE0 drive when USB_TXOE_B is low
USB_VP1 In Buffered data on DP when USB_TXOE_B is high
USB_VM1 In Buffered data on DM when USB_TXOE_B is high
USB_RCV In Differential Rx data when USB_TXOE_B is high
USB_DAT_VP
USB_SE0_VM US9
US10
Transmit
US12
USB_TXOE_B
US11
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Figure 103. USB Receive Waveform in DAT_SE0 Unidirectional Mode
Table 89 describes the port timing specification in DAT_SE0 unidirectional mode.
4.9.24.3 VP_VM Bidirectional Mode
Table 90 defines the signals for VP_VM bidirectional mode. Figure 104 and Figure 105 show the transmit
and receive waveforms respectively.
Table 89. USB Port Timing Specification in DAT_SE0 Unidirectional Mode
No. Parameter Signal Name Signal
Source Min. Max. Unit Condition/
Reference Signal
US9 Tx rise/fall time USB_DAT_VP Out — 5.0 ns 50 pF
US10 Tx rise/fall time USB_SE0_VM Out — 5.0 ns 50 pF
US11 Tx rise/fall time USB_TXOE_B Out — 5.0 ns 50 pF
US12 Tx duty cycle USB_DAT_VP Out 49.0 51.0 % —
US15 Rx rise/fall time USB_VP1 In — 3.0 ns 35 pF
US16 Rx rise/fall time USB_VM1 In — 3.0 ns 35 pF
US17 Rx rise/fall time USB_RCV In — 3.0 ns 35 pF
Table 90. Signal Definitions—VP_VM Bidirectional Mode
Name Direction Signal Description
USB_TXOE_B Out Transmit enable, active low
USB_DAT_VP Out (Tx)
In (Rx)
Tx VP data when USB_TXOE_B is low
Rx VP data when USB_TXOE_B is high
USB_SE0_VM Out (Tx)
In (Rx)
Tx VM data when USB_TXOE_B low
Rx VM data when USB_TXOE_B high
USB_RCV In Differential Rx data
US16US15/US17
USB_VP1
USB_TXOE_B
Receive
USB_VM1
USB_RCV
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Figure 104. USB Transmit Waveform in VP_VM Bidirectional Mode
Figure 105. USB Receive Waveform in VP_VM Bidirectional Mode
Table 91 describes the port timing specification in VP_VM bidirectional mode.
Table 91. USB Port Timing Specification in VP_VM Bidirectional Mode
No. Parameter Signal Name Direction Min. Max. Unit Condition/
Reference Signal
US18 Tx rise/fall time USB_DAT_VP Out — 5.0 ns 50 pF
US19 Tx rise/fall time USB_SE0_VM Out — 5.0 ns 50 pF
US20 Tx rise/fall time USB_TXOE_B Out — 5.0 ns 50 pF
US21 Tx duty cycle USB_DAT_VP Out 49.0 51.0 % —
US22 Tx overlap USB_SE0_VM Out –3.0 +3.0 ns USB_DAT_VP
US26 Rx rise/fall time USB_DAT_VP In — 3.0 ns 35 pF
US27 Rx rise/fall time USB_SE0_VM In — 3.0 ns 35 pF
USB_DAT_VP
USB_SE0_VM
US18
US19
Transmit
USB_TXOE_B
US20
US22
US21
US22
USB_DAT_VP
USB_SE0_VM
Receive US26
US28 US27
US29
USB_RCV
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4.9.24.4 VP_VM Unidirectional Mode
Table 92 defines the signals for VP_VM unidirectional mode. Figure 106 and Figure 107 show the
transmit and receive waveforms respectively.
Figure 106. USB Transmit Waveform in VP_VM Unidirectional Mode
US28 Rx skew USB_DAT_VP In –4.0 +4.0 ns USB_SE0_VM
US29 Rx skew USB_RCV In –6.0 +2.0 ns USB_DAT_VP
Table 92. Signal Definitions—VP_VM Unidirectional Mode
Name Direction Signal Description
USB_TXOE_B Out Transmit enable, active low
USB_DAT_VP Out Tx VP data when USB_TXOE_B is low
USB_SE0_VM Out Tx VM data when USB_TXOE_B is low
USB_VP1 In Rx VP data when USB_TXOE_B is high
USB_VM1 In Rx VM data when USB_TXOE_B is high
USB_RCV In Differential Rx data
Table 91. USB Port Timing Specification in VP_VM Bidirectional Mode (continued)
No. Parameter Signal Name Direction Min. Max. Unit Condition/
Reference Signal
USB_DAT_VP
USB_SE0_VM
US30
US31
Transmit
USB_TXOE_B
US32
US34
US33
US34
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Figure 107. USB Receive Waveform in VP_VM Unidirectional Mode
Table 93 describes the port timing specification in VP_VM unidirectional mode.
Table 93. USB Timing Specification in VP_VM Unidirectional Mode
No. Parameter Signal Direction Min. Max. Unit Conditions/Reference Signal
US30 Tx rise/fall time USB_DAT_VP Out — 5.0 ns 50 pF
US31 Tx rise/fall time USB_SE0_VM Out — 5.0 ns 50 pF
US32 Tx rise/fall time USB_TXOE_B Out — 5.0 ns 50 pF
US33 Tx duty cycle USB_DAT_VP Out 49.0 51.0 % —
US34 Tx overlap USB_SE0_VM Out –3.0 +3.0 ns USB_DAT_VP
US38 Rx rise/fall time USB_VP1 In — 3.0 ns 35 pF
US39 Rx rise/fall time USB_VM1 In — 3.0 ns 35 pF
US40 Rx skew USB_VP1 In –4.0 +4.0 ns USB_VM1
US41 Rx skew USB_RCV In –6.0 +2.0 ns USB_VP1
US38
USB_VM1
Receive
USB_RCV
USB_TXOE_B
US41
US40
US39
USB_VP1
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5 Package Information and Pinout
This section includes the following:
• Mechanical package drawing
• Pin/contact assignment information
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5.1 MAPBGA Production Package 1568-01, 17 ×17 mm, 0.8 Pitch
See Figure 108 for the package drawing and dimensions of the production package.
Figure 108. Production Package: Mechanical Drawing
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5.2 MAPBGA Signal Assignments
Table 94 and Table 95 list MAPBGA signals, alphabetized by signal name, for silicon revisions 2.0 and
2.1, respectively. Table 96 and Table 97 show the signal assignment on the i.MX35 ball map for silicon
revisions 2.0 and 2.1, respectively. The ball map for silicon revision 2.1 is different than the ballmap for
silicon revision 2.0. The layout for each revision is not compatible, so it is important that the correct
ballmap be used to implement the layout.
Table 94. Silicon Revision 2.0 Signal Ball Map Locations
Signal ID Ball Location Signal ID Ball Location
A0 A5 ATA_DATA71Y3
A1 D7 ATA_DATA81U4
A10 F15 ATA_DATA91W3
A11 D5 ATA_DIOR1Y6
A12 F6 ATA_DIOW1W6
A13 B3 ATA_DMACK1V6
A14 D14 ATA_DMARQ1T3
A15 D15 ATA_INTRQ1V2
A16 D13 ATA_IORDY1U6
A17 D12 ATA_RESET_B1T6
A18 E11 BCLK E14
A19 D11 BOOT_MODE0 W10
A2 E7 BOOT_MODE1 U9
A20 D10 CAPTURE V12
A21 E10 CAS E16
A22 D9 CLK_MODE0 Y10
A23 E9 CLK_MODE1 T10
A24 D8 CLKO V10
A25 E8 COMPARE T12
A3 C6 CONTRAST1L16
A4 D6 CS0 F17
A5 B5 CS1 E19
A6 C5 CS2 B20
A7 A4 CS3 C19
A8 B4 CS4 E18
A9 A3 CS5 F19
ATA _ B U F F _ E N 1T5 CSI_D101V16
ATA _ C S 0 1V7 CSI_D111T15
ATA _ C S 1 1T7 CSI_D121W16
ATA _ DA 0 1R4 CSI_D131V15
ATA _ DA 1 1V1 CSI_D141U14
ATA _ DA 2 1R5 CSI_D151Y16
ATA _ DATA 0 1Y5 CSI_D81U15
ATA _ DATA 1 1W5 CSI_D91W17
ATA _ DATA 1 0 1V3 CSI_HSYNC1V14
ATA _ DATA 1 1 1Y2 CSI_MCLK1W15
ATA _ DATA 1 2 1U3 CSI_PIXCLK1Y15
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ATA _ DATA 1 3 1W2 CSI_VSYNC1T14
ATA _ DATA 1 4 1W1 CSPI1_MISO V9
ATA _ DATA 1 5 1T4 CSPI1_MOSI W9
ATA _ DATA 2 1V5 CSPI1_SCLK W8
ATA_DATA3 U5 CSPI1_SPI_RDY T8
ATA_DATA4 Y4 CSPI1_SS0 Y8
ATA_DATA5 W4 CSPI1_SS1 U8
ATA _ DATA 6 V 4 C T S 1 R 3
CTS2 G5 FEC_TDATA0 P5
D0 A2 FEC_TDATA1 M4
D1 D4 FEC_TDATA2 M5
D10 D2 FEC_TDATA3 L6
D11 E6 FEC_TX_CLK P4
D12 E3 FEC_TX_EN T1
D13 F5 FEC_TX_ERR N4
D14 D1 FSR K5
D15 E2 FST J1
D2 B2 FUSE_VDD P13
D3 E5 FUSE_VSS M11
D3_CLS1L17 GPIO1_0 T11
D3_DRDY1L20 GPIO1_1 Y11
D3_FPSHIFT1L15 GPIO2_0 U11
D3_HSYNC1L18 GPIO3_0 V11
D3_REV1M17 HCKR K2
D3_SPL1M18 HCKT J5
D3_VSYNC1M19 I2C1_CLK M20
D4 C3 I2C1_DAT N17
D5 B1 I2C2_CLK L3
D6 D3 I2C2_DAT M1
D7 C2 LBA D20
D8 C1 LD01F20
D9 E4 LD11G18
DE_B W19 LD101H20
DQM0 B19 LD111J18
DQM1 D17 LD121J16
DQM2 D16 LD131J19
DQM3 C18 LD141J17
EB0 F18 LD151J20
EB1 F16 LD161K14
ECB D19 LD171K19
EXT_ARMCLK V8 LD181K18
EXTAL_AUDIO W20 LD191K20
EXTAL24M T20 LD21G17
FEC_COL P3 LD201K16
FEC_CRS N5 LD211K17
FEC_MDC R1 LD221K15
Table 94. Silicon Revision 2.0 Signal Ball Map Locations (continued)
Signal ID Ball Location Signal ID Ball Location
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FEC_MDIO P1 LD231L19
FEC_RDATA0 P2 LD31G16
FEC_RDATA1 N2 LD41G19
FEC_RDATA2 M3 LD51H16
FEC_RDATA3 N1 LD61H18
FEC_RX_CLK R2 LD71G20
FEC_RX_DV T2 LD81H17
FEC_RX_ERR N3 LD91H19
MA10 C4 NVCC_EMI2 G12
MGND N11 NVCC_EMI2 F13
MLB_CLK W13 NVCC_EMI2 F14
MLB_DAT Y13 NVCC_EMI3 G14
MLB_SIG W12 NVCC_JTAG P16
MVDD P11 NVCC_LCDC H14
NF_CE0 G3 NVCC_LCDC J14
NFALE F2 NVCC_LCDC L14
NFCLE E1 NVCC_LCDC M14
NFRB F3 NVCC_MISC K6
NFRE_B F1 NVCC_MISC K7
NFWE_B G2 NVCC_MISC L8
NFWP_B F4 NVCC_MLB R10
NGND_ATA M9 NVCC_NFC G6
NGND_ATA P9 NVCC_NFC H6
NGND_ATA L10 NVCC_NFC H7
NGND_CRM L11 NVCC_SDIO P14
NGND_CSI N10 OE E20
NGND_EMI1 H8 OSC_AUDIO_VDD V20
NGND_EMI1 H10 OSC_AUDIO_VSS U19
NGND_EMI1 J10 OSC24M_VDD T19
NGND_EMI2 J11 OSC24M_VSS T18
NGND_EMI3 J12 PGND M12
NGND_EMI3 K12 PHY1_VDDA M15
NGND_JTAG M13 PHY1_VDDA N20
NGND_LCDC K11 PHY1_VSSA N16
NGND_LCDC L12 PHY1_VSSA P20
NGND_MISC M7 PHY2_VDD R13
NGND_MISC K8 PHY2_VSS P12
NGND_MLB M10 POR_B W11
NGND_NFC K9 POWER_FAIL Y9
NGND_SDIO N12 PVDD N13
NVCC_ATA N6 RAS E15
NVCC_ATA P6 RESET_IN_B U10
NVCC_ATA P7 RTCK U18
NVCC_ATA P8 RTS1 U1
NVCC_CRM R9 RTS2 G1
NVCC_CSI R11 RW C20
Table 94. Silicon Revision 2.0 Signal Ball Map Locations (continued)
Signal ID Ball Location Signal ID Ball Location
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 135
NVCC_EMI1 G7 RXD1 U2
NVCC_EMI1 G8 RXD2 H3
NVCC_EMI1 G9 SCK4 L4
NVCC_EMI1 H9 SCK5 L5
NVCC_EMI1 F10 SCKR K3
NVCC_EMI1 G10 SCKT J4
NVCC_EMI1 F11 SD0 C17
NVCC_EMI1 G11 SD1 A19
SD1_CLK V18 SDCLK E12
SD1_CMD Y19 SDCLK_B E13
SD1_DATA0 R14 SDQS0 B17
SD1_DATA1 U16 SDQS1 A13
SD1_DATA2 W18 SDQS2 A10
SD1_DATA3 V17 SDQS3 C7
SD10 A15 SDWE G15
SD11 B15 SJC_MOD U17
SD12 C13 SRXD4 L1
SD13 B14 SRXD5 K4
SD14 A14 STXD4 M2
SD15 B13 STXD5 K1
SD16 C12 STXFS4 L2
SD17 C11 STXFS5 J6
SD18 A12 TCK R17
SD19 B12 TDI P15
SD2 B18 TDO R15
SD2_CLK W14 TEST_MODE Y7
SD2_CMD U13 TMS R16
SD2_DATA0 V13 TRSTB T16
SD2_DATA1 T13 TTM_PIN M16
SD2_DATA2 Y14 TX0 G4
SD2_DATA3 U12 TX1 H1
SD20 B11 TX2_RX3 H5
SD21 A11 TX3_RX2 J2
SD22 C10 TX4_RX1 H4
SD23 B10 TX5_RX0 J3
SD24 A9 TXD1 R6
SD25 C9 TXD2 H2
SD26 B9 USBOTG_OC U7
SD27 A8 USBOTG_PWR W7
SD28 B8 USBPHY1_DM N19
SD29 C8 USBPHY1_DP P19
SD3 C16 USBPHY1_RREF R19
SD30 A7 USBPHY1_UID N18
SD31 B7 USBPHY1_UPLLGND N14
SD4 A18 USBPHY1_UPLLVDD N15
SD5 C15 USBPHY1_UPLLVDD P17
Table 94. Silicon Revision 2.0 Signal Ball Map Locations (continued)
Signal ID Ball Location Signal ID Ball Location
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor136
SD6 A17 USBPHY1_VBUS P18
SD7 B16 USBPHY1_VDDA_BIAS R20
SD8 C14 USBPHY1_VSSA_BIAS R18
SD9 A16 USBPHY2_DM Y17
SDBA0 A6 USBPHY2_DP Y18
SDBA1 B6 VDD M6
SDCKE0 D18 VDD F7
SDCKE1 E17 VDD J7
VDD L7 VSS L9
VDD N7 VSS N9
VDD R7 VSS K10
VDD F8 VSS P10
VDD R8 VSS H11
VDD F9 VSS H12
VDD F12 VSS H13
VDD R12 VSS J13
VDD G13 VSS K13
VDD H15 VSS L13
VDD J15 VSS T17
VSS A1 VSS A20
VSS Y1 VSS Y20
VSS J8 VSTBY T9
VSS M8 WDOG_RST Y12
VSS N8 XTAL_AUDIO V19
VSS J9 XTAL24M U20
1Not available for the MCIMX351.
Table 94. Silicon Revision 2.0 Signal Ball Map Locations (continued)
Signal ID Ball Location Signal ID Ball Location
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 137
Table 95. Silicon Revision 2.1 Signal Ball Map Locations
Signal ID Ball Location Signal ID Ball Location
A0 A5 ATA_DATA7 Y3
A1 D7 ATA_DATA8 U4
A10 F15 ATA_DATA9 W3
A11 D5 ATA_DIOR Y6
A12 F6 ATA_DIOW W6
A13 B3 ATA_DMACK V6
A14 D14 ATA_DMARQ T3
A15 D15 ATA_INTRQ V2
A16 D13 ATA_IORDY U6
A18 D12 ATA_RESET_B T6
SDQS1 E11 SDQS0 E14
A19 D11 BOOT_MODE0 W10
A2 E7 BOOT_MODE1 U9
A21 D10 CAPTURE V12
SDQS2 E10 RAS E16
A22 D9 CLK_MODE0 Y10
SDQS3 E9 CLK_MODE1 T10
A24 D8 CLKO V10
A25 E8 COMPARE T12
A3 C6 CONTRAST L16
A4 D6 CS0 F17
A5 B5 CS1 E19
A6 C5 CS2 B20
A7 A4 CS3 C19
A8 B4 CS4 E18
A9 A3 CS5 F19
ATA _ B U F F _ E N 1T5 CSI_D10 V16
ATA_CS0 V7 CSI_D11 T15
ATA_CS1 T7 CSI_D12 W16
ATA_DA0 R4 CSI_D13 V15
ATA_DA1 V1 CSI_D14 U14
ATA_DA2 R5 CSI_D15 Y16
ATA _ DATA 0 Y 5 C S I _ D 8 U 1 5
ATA_DATA1 W5 CSI_D9 W17
ATA_DATA10 V3 CSI_HSYNC V14
ATA_DATA11 Y2 CSI_MCLK W15
ATA_DATA12 U3 CSI_PIXCLK Y15
ATA_DATA13 W2 CSI_VSYNC T14
ATA_DATA14 W1 CSPI1_MISO V9
ATA_DATA15 T4 CSPI1_MOSI W9
ATA_DATA2 V5 CSPI1_SCLK W8
ATA_DATA3 U5 CSPI1_SPI_RDY T8
ATA_DATA4 Y4 CSPI1_SS0 Y8
ATA_DATA5 W4 CSPI1_SS1 U8
ATA _ DATA 6 V 4 C T S 1 R 3
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor138
CTS2 G5 FEC_TDATA0 P5
D0 A2 FEC_TDATA1 M4
D1 D4 FEC_TDATA2 M5
D10 D2 FEC_TDATA3 L6
D11 E6 FEC_TX_CLK P4
D12 E3 FEC_TX_EN T1
D13 F5 FEC_TX_ERR N4
D14 D1 FSR K5
D15 E2 FST J1
D2 B2 FUSE_VDD P13
D3 E5 FUSE_VSS M11
D3_CLS L17 GPIO1_0 T11
D3_DRDY L20 GPIO1_1 Y11
D3_FPSHIFT L15 GPIO2_0 U11
D3_HSYNC L18 GPIO3_0 V11
D3_REV M17 HCKR K2
D3_SPL M18 HCKT J5
D3_VSYNC M19 I2C1_CLK M20
D4 C3 I2C1_DAT N17
D5 B1 I2C2_CLK L3
D6 D3 I2C2_DAT M1
D7 C2 LBA D20
D8 C1 LD0 F20
D9 E4 LD1 G18
DE_B W19 LD10 H20
DQM0 B19 LD11 J18
SDCKE1 D17 LD12 J16
DQM2 D16 LD13 J19
DQM3 C18 LD14 J17
EB0 F18 LD15 J20
EB1 F16 LD16 K14
ECB D19 LD17 K19
EXT_ARMCLK V8 LD18 K18
EXTAL_AUDIO W20 LD19 K20
EXTAL24M T20 LD2 G17
FEC_COL P3 LD20 K16
FEC_CRS N5 LD21 K17
FEC_MDC R1 LD22 K15
FEC_MDIO P1 LD23 L19
FEC_RDATA0 P2 LD3 G16
FEC_RDATA1 N2 LD4 G19
FEC_RDATA2 M3 LD5 H16
FEC_RDATA3 N1 LD6 H18
FEC_RX_CLK R2 LD7 G20
FEC_RX_DV T2 LD8 H17
FEC_RX_ERR N3 LD9 H19
Table 95. Silicon Revision 2.1 Signal Ball Map Locations (continued)
Signal ID Ball Location Signal ID Ball Location
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 139
MA10 C4 NVCC_EMI2 G12
MGND N11 NVCC_EMI2 F13
MLB_CLK W13 VSS F14
MLB_DAT Y13 NVCC_EMI3 G14
MLB_SIG W12 NVCC_JTAG P16
MVDD P11 NVCC_LCDC H14
NF_CE0 G3 NVCC_LCDC J14
NFALE F2 NVCC_LCDC L14
NFCLE E1 NVCC_LCDC M14
NFRB F3 NVCC_MISC K6
NFRE_B F1 NVCC_MISC K7
NFWE_B G2 NVCC_MISC L8
NFWP_B F4 NVCC_MLB R10
NGND_ATA M9 NVCC_NFC G6
NGND_ATA P9 NVCC_NFC H6
NGND_ATA L10 NVCC_NFC H7
NGND_CRM L11 NVCC_SDIO P14
NGND_CSI N10 OE E20
NGND_EMI1 H8 OSC_AUDIO_VDD V20
NVCC_EMI1 H10 OSC_AUDIO_VSS U19
NGND_EMI1 J10 OSC24M_VDD T19
NGND_EMI2 J11 OSC24M_VSS T18
NGND_EMI3 J12 PGND M12
NGND_EMI3 K12 PHY1_VDDA M15
NGND_JTAG M13 PHY1_VDDA N20
NGND_LCDC K11 PHY1_VSSA N16
NGND_LCDC L12 PHY1_VSSA P20
NGND_MISC M7 PHY2_VDD R13
NGND_MISC K8 PHY2_VSS P12
NGND_MLB M10 POR_B W11
NGND_NFC K9 POWER_FAIL Y9
NGND_SDIO N12 PVDD N13
NVCC_ATA N6 BCLK E15
NVCC_ATA P6 RESET_IN_B U10
NVCC_ATA P7 RTCK U18
NVCC_ATA P8 RTS1 U1
NVCC_CRM R9 RTS2 G1
NVCC_CSI R11 RW C20
NVCC_EMI1 G7 RXD1 U2
NVCC_EMI1 G8 RXD2 H3
NVCC_EMI1 G9 SCK4 L4
NVCC_EMI1 H9 SCK5 L5
NGND_EMI1 F10 SCKR K3
NVCC_EMI1 G10 SCKT J4
NVCC_EMI1 F11 DQM1 C17
NVCC_EMI1 G11 SD1 A19
Table 95. Silicon Revision 2.1 Signal Ball Map Locations (continued)
Signal ID Ball Location Signal ID Ball Location
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor140
SD1_CLK V18 SDCLK E12
SD1_CMD Y19 SDCLK_B E13
SD1_DATA0 R14 SD0 B17
SD1_DATA1 U16 SD15 A13
SD1_DATA2 W18 SD23 A10
SD1_DATA3 V17 A23 C7
SD10 A15 SDWE G15
SD11 B15 SJC_MOD U17
A17 C13 SRXD4 L1
SD13 B14 SRXD5 K4
SD14 A14 STXD4 M2
SD12 B13 STXD5 K1
SD16 C12 STXFS4 L2
SD17 C11 STXFS5 J6
SD18 A12 TCK R17
SD19 B12 TDI P15
SD2 B18 TDO R15
SD2_CLK W14 TEST_MODE Y7
SD2_CMD U13 TMS R16
SD2_DATA0 V13 TRSTB T16
SD2_DATA1 T13 TTM_PIN M16
SD2_DATA2 Y14 TX0 G4
SD2_DATA3 U12 TX1 H1
SD20 B11 TX2_RX3 H5
SD21 A11 TX3_RX2 J2
A20 C10 TX4_RX1 H4
SD22 B10 TX5_RX0 J3
SD24 A9 TXD1 R6
SD25 C9 TXD2 H2
SD26 B9 USBOTG_OC U7
SD27 A8 USBOTG_PWR W7
SD28 B8 USBPHY1_DM N19
SD29 C8 USBPHY1_DP P19
SD3 C16 USBPHY1_RREF R19
SD30 A7 USBPHY1_UID N18
SD31 B7 USBPHY1_UPLLGND N14
SD4 A18 USBPHY1_UPLLVDD N15
SD5 C15 USBPHY1_UPLLVDD P17
SD6 A17 USBPHY1_VBUS P18
SD7 B16 USBPHY1_VDDA_BIAS R20
SD8 C14 USBPHY1_VSSA_BIAS R18
SD9 A16 USBPHY2_DM Y17
SDBA0 A6 USBPHY2_DP Y18
SDBA1 B6 VDD M6
SDCKE0 D18 VDD F7
CAS E17 VDD J7
Table 95. Silicon Revision 2.1 Signal Ball Map Locations (continued)
Signal ID Ball Location Signal ID Ball Location
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 141
VDD L7 VSS L9
VDD N7 VSS N9
VDD R7 VSS K10
VDD F8 VSS P10
VDD R8 VSS H11
VDD F9 VSS H12
VDD F12 NVCC_EMI2 H13
VDD R12 VSS J13
VDD G13 VSS K13
VDD H15 VSS L13
VDD J15 VSS T17
VSS A1 VSS A20
VSS Y1 VSS Y20
VSS J8 VSTBY T9
VSS M8 WDOG_RST Y12
VSS N8 XTAL_AUDIO V19
VSS J9 XTAL24M U20
1Not available for the MCIMX351.
Table 95. Silicon Revision 2.1 Signal Ball Map Locations (continued)
Signal ID Ball Location Signal ID Ball Location
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor142
Table 96. Silicon Revision 2.0 Ball Map—17 x 17, 0.8 mm Pitch1
1234567891011121314151617181920
A VSS D0 A9 A7 A0 SDB
A0
SD3
0
SD2
7
SD2
4
SDQ
S2
SD2
1
SD1
8
SDQ
S1
SD1
4
SD1
0
SD9SD6SD4SD1VSSA
B D5 D2 A13 A8 A5 SDB
A1
SD3
1
SD2
8
SD2
6
SD2
3
SD2
0
SD1
9
SD1
5
SD1
3
SD1
1
SD7 SDQ
S0
SD2 DQM
0
CS2 B
CD8D7D4MA1
0
A6 A3 SDQ
S3
SD2
9
SD2
5
SD2
2
SD1
7
SD1
6
SD1
2
SD8 SD5 SD3 SD0 DQM
3
CS3 RW C
D D14 D10 D6 D1 A11 A4 A1 A24 A22 A20 A19 A17 A16 A14 A15 DQM
2
DQM
1
SDC
KE0
ECB LBA D
ENFC
LE
D15 D12 D9 D3 D11 A2 A25 A23 A21 A18 SDC
LK
SDC
LK_
B
BCL
K
RAS CAS SDC
KE1
CS4 CS1 OE E
FNFR
E_B
NFA
LE
NFR
B
NFW
P_B
D13 A12 VDD VDD VDD NVC
C_E
MI1
NVC
C_E
MI1
VDD NVC
C_E
MI2
NVC
C_E
MI2
A10 EB1 CS0 EB0 CS5 LD0 F
GRTS
2
NFW
E_B
NF_
CE0
TX0 CTS
2
NVC
C_N
FC
NVC
C_E
MI1
NVC
C_E
MI1
NVC
C_E
MI1
NVC
C_E
MI1
NVC
C_E
MI1
NVC
C_E
MI2
VDD NVC
C_E
MI3
SDW
E
LD3 LD2 LD1 LD4 LD7 G
HTX1TXD
2
RXD
2
TX4_
RX1
TX2_
RX3
NVC
C_N
FC
NVC
C_N
FC
NGN
D_E
MI1
NVC
C_E
MI1
NGN
D_E
MI1
VSS VSS VSS NVC
C_L
CDC
VDD LD5 LD8 LD6 LD9 LD10 H
JFSTTX3_
RX2
TX5_
RX0
SCK
T
HCK
T
STX
FS5
VDD VSS VSS NGN
D_E
MI1
NGN
D_E
MI2
NGN
D_E
MI3
VSS NVC
C_L
CDC
VDD LD12 LD14 LD11 LD13 LD15 J
KSTX
D5
HCK
R
SCK
R
SRX
D5
FSR NVC
C_MI
SC
NVC
C_MI
SC
NGN
D_MI
SC
NGN
D_N
FC
VSS NGN
D_L
CDC
NGN
D_E
MI3
VSS LD16 LD22 LD20 LD21 LD18 LD17 LD19 K
LSRX
D4
STX
FS4
I2C2
_CL
K
SCK
4
SCK
5
FEC
_TD
ATA 3
VDD NVC
C_MI
SC
VSS NGN
D_A
TA
NGN
D_C
RM
NGN
D_L
CDC
VSS NVC
C_L
CDC
D3_
FPS
HIFT
CON
TRA
ST
D3_
CLS
D3_
HSY
NC
LD23 D3_
DRD
Y
L
MI2C2
_DAT
STX
D4
FEC
_RD
ATA 2
FEC
_TD
ATA 1
FEC
_TD
ATA 2
VDD NGN
D_MI
SC
VSS NGN
D_A
TA
NGN
D_M
LB
FUS
E_V
SS
PGN
D
NGN
D_JT
AG
NVC
C_L
CDC
PHY
1_V
DDA
TTM
_PIN
D3_
REV
D3_
SPL
D3_
VSY
NC
I2C1
_CL
K
M
NFEC
_RD
ATA3
FEC
_RD
ATA 1
FEC
_RX
_ER
R
FEC
_TX_
ERR
FEC
_CR
S
NVC
C_A
TA
VDD VSS VSS NGN
D_C
SI
MGN
D
NGN
D_S
DIO
PVD
D
USB
PHY
1_U
PLL
GND
USB
PHY
1_U
PLLV
DD
PHY
1_V
SSA
I2C1
_DAT
USB
PHY
1_UI
D
USB
PHY
1_D
M
PHY
1_V
DDA
N
PFEC
_MDI
O
FEC
_RD
ATA 0
FEC
_CO
L
FEC
_TX_
CLK
FEC
_TD
ATA 0
NVC
C_A
TA
NVC
C_A
TA
NVC
C_A
TA
NGN
D_A
TA
VSS MVD
D
PHY
2_V
SS
FUS
E_V
DD
NVC
C_S
DIO
TDI NVC
C_JT
AG
USB
PHY
1_U
PLLV
DD
USB
PHY
1_V
BUS
USB
PHY
1_D
P
PHY
1_V
SSA
P
RFEC
_MD
C
FEC
_RX
_CL
K
CTS
1
ATA _
DA0
ATA _
DA2
TXD
1
VDD VDD NVC
C_C
RM
NVC
C_M
LB
NVC
C_C
SI
VDD PHY
2_V
DD
SD1
_DAT
A0
TDO TMS TCK USB
PHY
1_V
SSA
_BIA
S
USB
PHY
1_R
REF
USB
PHY
1_V
DDA
_BIA
S
R
TFEC
_TX_
EN
FEC
_RX
_DV
ATA _
DMA
RQ
ATA _
DATA
15
ATA _
BUF
F_E
N
ATA _
RES
ET_
B
ATA_
CS1
CSPI
1_S
PI_R
DY
VST
BY
CLK
_MO
DE1
GPI
O1_
0
COM
PAR
E
SD2
_DAT
A1
CSI_
VSY
NC
CSI_
D11
TRS
TB
VSS OSC
24M
_VS
S
OSC
24M
_VD
D
EXT
AL24
M
T
URTS
1
RXD
1
ATA _
DATA
12
ATA _
DATA
8
ATA _
DATA
3
ATA _
IOR
DY
USB
OTG
_OC
CSPI
1_S
S1
BOO
T_M
ODE
1
RES
ET_I
N_B
GPI
O2_
0
SD2
_DAT
A3
SD2
_CM
D
CSI_
D14
CSI_
D8
SD1
_DAT
A1
SJC
_MO
D
RTC
K
OSC
_AU
DIO_
VSS
XTAL
24M
U
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 143
VATA_
DA1
ATA _
INTR
Q
ATA _
DATA
10
ATA _
DATA
6
ATA _
DATA
2
ATA _
DMA
CK
ATA_
CS0
EXT
_AR
MCL
K
CSPI
1_MI
SO
CLK
O
GPI
O3_
0
CAP
TUR
E
SD2
_DAT
A0
CSI_
HSY
NC
CSI_
D13
CSI_
D10
SD1
_DAT
A3
SD1
_CL
K
XTAL
_AU
DIO
OSC
_AU
DIO_
VDD
V
WATA_
DATA
14
ATA _
DATA
13
ATA _
DATA
9
ATA _
DATA
5
ATA _
DATA
1
ATA _
DIO
W
USB
OTG
_PW
R
CSPI
1_S
CLK
CSPI
1_M
OSI
BOO
T_M
ODE
0
POR
_B
MLB
_SIG
MLB
_CL
K
SD2
_CL
K
CSI_
MCL
K
CSI_
D12
CSI_
D9
SD1
_DAT
A2
DE_
B
EXT
AL_
AUDI
O
W
Y VSS ATA_
DATA
11
ATA _
DATA
7
ATA _
DATA
4
ATA _
DATA
0
ATA _
DIO
R
TES
T_M
ODE
CSPI
1_S
S0
POW
ER_
FAIL
CLK
_MO
DE0
GPI
O1_
1
WD
OG_
RST
MLB
_DAT
SD2
_DAT
A2
CSI_
PIXC
LK
CSI_
D15
USB
PHY
2_D
M
USB
PHY
2_D
P
SD1
_CM
D
VSS Y
1See Ta bl e 9 5 for pins unavailable in the MCIMX351 SoC.
Table 97. Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch
1 2 3 4 5 6 7 8 9 1011121314151617181920
A GND D0 A9 A7 A0 SDB
A0
SD30 SD27 SD24 SD23 SD21 SD18 SD15 SD14 SD10 SD9 SD6 SD4 SD1 GND A
B D5 D2 A13 A8 A5 SDB
A1
SD31 SD28 SD26 SD22 SD20 SD19 SD12 SD13 SD11 SD7 SD0 SD2 DQM
0
CS2 B
CD8D7D4MA1
0
A6 A3 A23 SD29 SD25 A20 SD17 SD16 A17 SD8 SD5 SD3 DQM
1
DQM
3
CS3 RW C
D D14 D10 D6 D1 A11 A4 A1 A24 A22 A21 A19 A18 A16 A14 A15 DQM
2
SDC
KE1
SDC
KE0
ECB LBA D
ENFC
LE
D15 D12 D9 D3 D11 A2 A25 SDQ
S3
SDQ
S2
SDQ
S1
SDC
LK
SDC
LK_B
SDQ
S0
BCL
K
RAS CAS CS4 CS1 OE E
FNFR
E_B
NFAL
E
NFR
B
NFW
P_B
D13 A12 VDD
7
VDD
7
VDD
7
GND NVC
C_E
MI1
VDD
7
NVC
C_E
MI2
GND A10 EB1 CS0 EB0 CS5 LD0 F
GRTS
2
NFW
E_B
NF_
CE0
TX0 CTS
2
NVC
C_N
FC
NVC
C_E
MI1
NVC
C_E
MI1
NVC
C_E
MI1
NVC
C_E
MI1
NVC
C_E
MI1
NVC
C_E
MI2
VDD
6
NVC
C_E
MI3
SDW
E
LD3 LD2 LD1 LD4 LD7 G
HTX1TXD
2
RXD
2
TX4_
RX1
TX2_
RX3
NVC
C_N
FC
NVC
C_N
FC
GND NVC
C_E
MI1
NVC
C_E
MI1
GND GND NVC
C_E
MI2
NVC
C_L
CDC
VDD
5
LD5 LD8 LD6 LD9 LD10 H
JFSTTX3_
RX2
TX5_
RX0
SCK
T
HCK
T
STX
FS5
VDD
1
GND GND GND GND GND GND NVC
C_L
CDC
VDD
5
LD12 LD14 LD11 LD13 LD15 J
KSTX
D5
HCK
R
SCK
R
SRX
D5
FSR NVC
C_MI
SC
NVC
C_MI
SC
GND GND GND GND GND GND LD16 LD22 LD20 LD21 LD18 LD17 LD19 K
LSRX
D4
STX
FS4
I2C2
_CLK
SCK
4
SCK
5
FEC
_TDA
TA 3
VDD
2
NVC
C_MI
SC
GND GND GND GND GND NVC
C_L
CDC
D3_F
PSHI
FT
CON
TRA
ST
D3_
CLS
D3_
HSY
NC
LD23 D3_
DRD
Y
L
MI2C2
_DAT
STX
D4
FEC
_RD
ATA 2
FEC
_TDA
TA 1
FEC
_TDA
TA2
VDD
2
GND GND GND GND FUS
E_V
SS
PGN
D
GND NVC
C_L
CDC
PHY
1_VD
DA
TTM
_PAD
D3_
REV
D3_S
PL
D3_V
SYN
C
I2C1
_CLK
M
NFEC
_RD
ATA 3
FEC
_RD
ATA 1
FEC
_RX_
ERR
FEC
_TX_
ERR
FEC
_CR
S
NVC
C_AT
A
VDD
3
GND GND GND MGN
D
GND PVD
D
USB
PHY
1_UP
LLG
ND
USB
PHY
1_UP
LLVD
D
PHY
1_VS
SA
I2C1
_DAT
USB
PHY
1_UI
D
USB
PHY
1_D
M
PHY
1_VD
DA
N
Table 96. Silicon Revision 2.0 Ball Map—17 x 17, 0.8 mm Pitch1 (continued)
1234567891011121314151617181920
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor144
6 Product Documentation
All related product documentation for the i.MX35 processor is located at http://www.freescale.com/imx.
PFEC
_MDI
O
FEC
_RD
ATA 0
FEC
_CO
L
FEC
_TX_
CLK
FEC
_TDA
TA0
NVC
C_AT
A
NVC
C_AT
A
NVC
C_AT
A
GND GND MVD
D
PHY
2_VS
S
FUS
E_V
DD
NVC
C_S
DIO
TDI NVC
C_JT
AG
USB
PHY
1_UP
LLVD
D
USB
PHY
1_VB
US
USB
PHY
1_DP
PHY
1_VS
SA
P
RFEC
_MD
C
FEC
_RX_
CLK
CTS
1
ATA _
DA0
ATA _
DA2
TXD
1
VDD
3
VDD
3
NVC
C_C
RM
NVC
C_M
LB
NVC
C_C
SI
VDD
4
PHY
2_VD
D
SD1_
DATA
0
TDO TMS TCK USB
PHY
1_VS
SA_
BIAS
USB
PHY
1_R
REF
USB
PHY
1_VD
DA_
BIAS
R
TFEC
_TX_
EN
FEC
_RX_
DV
ATA _
DMA
RQ
ATA _
DATA
15
ATA _
BUF
F_E
N
ATA _
RES
ET_B
ATA _
CS1
CSPI
1_SP
I_RD
Y
VST
BY
CLK_
MOD
E1
GPIO
1_0
COM
PA R
E
SD2_
DATA
1
CSI_
VSY
NC
CSI_
D11
TRS
TB
GND OSC
24M_
VSS
OSC
24M_
VDD
EXTA
L24M
T
URTS
1
RXD
1
ATA _
DATA
12
ATA _
DATA
8
ATA _
DATA
3
ATA _
IORD
Y
USB
OTG
_OC
CSPI
1_SS
1
BOO
T_M
ODE
1
RES
ET_I
N_B
GPIO
2_0
SD2_
DATA
3
SD2_
CMD
CSI_
D14
CSI_
D8
SD1_
DATA
1
SJC_
MOD
RTC
K
OSC
_AU
DIO_
VSS
XTAL
24M
U
VATA_
DA1
ATA _
INTR
Q
ATA _
DATA
10
ATA _
DATA
6
ATA _
DATA
2
ATA _
DMA
CK
ATA _
CS0
EXT_
ARM
CLK
CSPI
1_MI
SO
CLK
O
GPIO
3_0
CAP
TUR
E
SD2_
DATA
0
CSI_
HSY
NC
CSI_
D13
CSI_
D10
SD1_
DATA
3
SD1_
CLK
XTAL
_AU
DIO
OSC
_AU
DIO_
VDD
V
WATA_
DATA
14
ATA _
DATA
13
ATA _
DATA
9
ATA _
DATA
5
ATA _
DATA
1
ATA _
DIO
W
USB
OTG
_PW
R
CSPI
1_SC
LK
CSPI
1_M
OSI
BOO
T_M
ODE
0
POR
_B
MLB
_SIG
MLB
_CLK
SD2_
CLK
CSI_
MCL
K
CSI_
D12
CSI_
D9
SD1_
DATA
2
DE_
B
EXTA
L_AU
DIO
W
YGNDATA_
DATA
11
ATA _
DATA
7
ATA _
DATA
4
ATA _
DATA
0
ATA _
DIOR
TES
T_M
ODE
CSPI
1_SS
0
POW
ER_
FAIL
CLK_
MOD
E0
GPIO
1_1
WDO
G_R
ST
MLB
_DAT
SD2_
DATA
2
CSI_
PIXC
LK
CSI_
D15
USB
PHY
2_D
M
USB
PHY
2_DP
SD1_
CMD
GND Y
1 2 3 4 5 6 7 8 9 1011121314151617181920
Table 97. Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch (continued)
1 2 3 4 5 6 7 8 9 1011121314151617181920
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor 145
7 Revision History
Table 98 shows the revision history of this document. Note: There were no revisions of this document
between revision 1 and revision 4 or between revision 6 and revision 7.
Table 98. i.MX35 Data Sheet Revision History
Revision
Number Date Substantive Change(s)
10 06/2012 • In Table 2, "Functional Differences in the i.MX35 Parts," on page 3, added two columns for part
numbers MCIMX353 and MCIMX357.
• Added Table 29, "Clock Input Tolerance," on page 31 in Section 4.9.3, “DPLL Electrical
Specifications.”
• Updated Table 39, "DDR2 SDRAM Timing Parameter Table," on page 50 for DDR2-400 values.
• Updated Table 41, "DDR2 SDRAM Write Cycle Parameters," on page 52 for DDR2-400 values.
• Added Table 15, "AC Requirements of I/O Pins," on page 24.
• Updated WE4 parameter in Table 33, "WEIM Bus Timing Parameters," on page 37.
9 08/2010 • Updated Table 32, “NFC Timing Parameters.”
• Updated Table 33, “WEIM Bus Timing Parameters.”
8 04/2010 • Updated Ta b l e 1 4 , “I/O Pin DC Electrical Characteristics.”
7 12/18/2009 • Updated Ta b l e 1 , “Ordering Information.”
6 10/21/2009 • Added information for silicon rev. 2.1
• Updated Ta b l e 1 , “Ordering Information.”
• Added Ta bl e 9 5 , “Silicon Revision 2.1 Signal Ball Map Locations.”
• Added Ta bl e 9 7 , “Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch.”
5 08/06/2009 • Added a line for TA = –40 to 85 oC in Ta b l e 1 4 , “I/O Pin DC Electrical Characteristics”
• Filled in TBDs in Ta bl e 1 4 .
•Revised Figure 15 and Ta bl e 3 3 by removing FCE = 0 and FCE = 1. Added footnote 3 to the table.
• Added Ta bl e 2 6 , “AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive
(1.8 V).”
4 04/30/2009 Note: There were no revisions of this document between revision 1 and revision 4.
•In Section 4.3.1, “Powering Up,” reverse positions of steps 5 and 6.
• Updated values in Table 10, “i.MX35 Power Modes.”
• Added Section 4.4, “Reset Timing.”
•In Section 4.8.2, “AC Electrical Characteristics for DDR Pins (DDR2, Mobile DDR, and SDRAM
Modes),” removed Slow Slew rate tables, relabeled Table 24, “AC Electrical Characteristics of DDR
Type IO Pins in mDDR Mode,” and Table 25, “AC Electrical Characteristics of DDR Type IO Pins in
SDRAM Mode,” to exclude mention of slew rate.
•In Section 4.9.5.2, “Wireless External Interface Module (WEIM),” modified Figure 16, “Synchronous
Memory Timing Diagram for Read Access—WSC = 1,” through Figure 21, “Muxed A/D Mode Timing
Diagram for Synchronous Read Access— WSC = 7, LBA = 1, LBN = 1, LAH = 1, OEA = 7.”
•In Section 4.9.6, “Enhanced Serial Audio Interface (ESAI) Timing Specifications,” modified
Figure 36, “ESAI Transmitter Timing,” and Figure 37, “ESAI Receiver Timing,” to remove extraneous
signals. Removed a note from Figure 36, “ESAI Transmitter Timing.”
3 03/2009 • In Section 4.3.1, “Powering Up,” reverse positions of steps 5 and 6.
2 02/2009 • Added the following parts to Ta bl e 1 , “Ordering Information”: PCIMX357CVM5B,
MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Throughout
consumer data sheet: Removed or updated information related to Media Local Bus
interface.Updated Section 4.3.1, “Powering Up.”
• Updated values in Table 10, “i.MX35 Power Modes.”
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor146
1 12/2008 • Updated Section 4.3.1, “Powering Up.”
• Section 4.7, “Module-Level AC Electrical Specifications”: Updated NFC, SDRAM and mDDR
SDRAM timing. Inserted DDR2 SDRAM timing.
0 10/2008 Initial public release
Table 98. i.MX35 Data Sheet Revision History (continued)
Revision
Number Date Substantive Change(s)
Document Number: MCIMX35SR2CEC
Rev. 10
06/2012
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