BUK135-50L/T3 - NXP Semiconductors / Philips Semiconductors

Philips Semiconductors Product Specification

Logic level TOPFET BUK135-50L

SMD version of BUK124-50L

DESCRIPTION QUICK REFERENCE DATA

Monolithic logic level protected SYMBOL PARAMETER MAX. UNIT

power MOSFET using TOPFET2

technology assembled in a 5 pin VDS Continuous drain source voltage 50 V

surface mounting plastic package. IDContinuous drain current 30 A

Ptot Total power dissipation 90 W

APPLICATIONS TjContinuous junction temperature 150 ˚C

RDS(ON) Drain-source on-state resistance 28 mΩ

General purpose switch for

automotive systems and other SYMBOL PARAMETER NOM. UNIT

applications. VPS Protection supply voltage 5 V

FEATURES FUNCTIONAL BLOCK DIAGRAM

TrenchMOS output stage with

low on-state resistance

Separate input pin for higher

frequency drive

5 V logic compatible input

Separate supply pin for logic

and protection circuits with low

operating current

Overtemperature protection

Drain current limiting

Short circuit load protection

Latched overload trip state reset

by the protection pin

Diagnostic flag pin indicates

protection supply connected,

overtemperature condition,overload

tripped state, or open circuit load

(detected in the off-state)

ESD protection on all pins

Overvoltage clamping

Fig.1. Elements of the TOPFET.

PINNING - SOT426 PIN CONFIGURATION SYMBOL

PIN DESCRIPTION

1 input

2 flag

3 (connected to mb)

4 protection supply

5 source Fig. 2. Fig. 3.

mb drain

POWER

MOSFET

DRAIN

SOURCE

INPUT

O/V

CLAMP

PROTECTION SUPPLY

FLAG OC LOAD

DETECT

LOGIC AND

PROTECTION

RIG

12 45

TOPFET

July 2002 1 Rev 1.100

Philips Semiconductors Product Specification

Logic level TOPFET BUK135-50L

SMD version of BUK124-50L

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Continuous voltage

VDS Drain source voltage1VIS = 0 V - 50 V

Continuous currents

IDDrain current VPS = 5 V; Tmb = 25˚C - self - A

limited

VPS = 0 V; Tmb = 85˚C - 30 A

IIInput current -5 5 mA

IFFlag current -5 5 mA

IPProtection supply current -5 5 mA

Thermal

Ptot Total power dissipation Tmb = 25˚C - 90 W

Tstg Storage temperature -55 175 ˚C

TjJunction temperature2continuous - 150 ˚C

Tsold Mounting base temperature during soldering - 260 ˚C

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VCElectrostatic discharge capacitor Human body model; - 2 kV

voltage C = 250 pF; R = 1.5 kΩ

OVERLOAD PROTECTION LIMITING VALUE

With an adequate protection supply For overload conditions an n-MOS The drain current is limited to

connected, TOPFET can protect transistor turns on between the reduce dissipation in case of short

itself from two types of overload - input and source to quickly circuit load. Refer to OVERLOAD

overtemperature and short circuit discharge the power MOSFET CHARACTERISTICS.

load. gate capacitance.

SYMBOL PARAMETER REQUIRED CONDITION MIN. MAX. UNIT

Overload protection3protection supply

VDS Drain source voltage VPS ≥ 4 V 0 35 V

OVERVOLTAGE CLAMPING LIMITING VALUES

At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Inductive load turn off IDM = 20 A; VDD ≤ 20 V

EDSM Non-repetitive clamping energy Tmb = 25˚C - 350 mJ

EDRM Repetitive clamping energy Tmb ≤ 95˚C; f = 250 Hz - 45 mJ

1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.

2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch.

3 All control logic and protection functions are disabled during conduction of the source drain diode. If the protection circuit was previously

latched, it would be reset by this condition.

July 2002 2 Rev 1.100

Philips Semiconductors Product Specification

Logic level TOPFET BUK135-50L

SMD version of BUK124-50L

THERMAL CHARACTERISTIC

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Thermal resistance

Rth j-mb Junction to mounting base - - 1.2 1.39 K/W

OUTPUT CHARACTERISTICS

Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Off-state VIS = 0 V

V(CL)DSS Drain-source clamping voltage ID = 10 mA 50 - 70 V

IDM = 4 A; tp ≤ 300 µs; δ ≤ 0.01 50 60 70 V

IDSS Drain source leakage current1VPS = 0 V; VDS = 40 V - - 100 µA

Tmb = 25˚C - 0.1 10 µA

On-state tp ≤ 300 µs; δ ≤ 0.01; VPS ≥ 4 V

RDS(ON) Drain-source resistance IDM = 10 A; VIS ≥ 4.4 V - - 50 mΩ

Tmb = 25˚C - 21 28 mΩ

INPUT CHARACTERISTICS

Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Normal operation

VIS(TO) Input threshold voltage2ID = 1 mA 0.6 - 2.6 V

Tmb = 25˚C 1.1 1.6 2.1 V

IIS Input current VIS = 5 V - 16 100 µA

V(CL)IS Input clamping voltage II = 1 mA 5.5 6.4 8.5 V

RIG Internal series resistance3to gate of power MOSFET - 1.7 - kΩ

Overload protection latched VPS ≥ 4 V

IISL Input current VIS = 5 V 1 2.7 4 mA

1 The drain current required for open circuit load detection is switched off when there is no protection supply, in order to ensure a low off-state

quiescent current. Refer to OPEN CIRCUIT LOAD DETECTION CHARACTERISTICS.

2 The measurement method is simplified if VPS = 0 V, in order to distinguish ID from IDSP. Refer to OPEN CIRCUIT LOAD DETECTION

CHARACTERISTICS.

3 This is not a directly measurable parameter.

July 2002 3 Rev 1.100

Philips Semiconductors Product Specification

Logic level TOPFET BUK135-50L

SMD version of BUK124-50L

PROTECTION SUPPLY CHARACTERISTICS

Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Protection & detection

VPSF Threshold voltage1IF = 100 µA; VDS = 5 V 2.5 3.45 4 V

Normal operation or

protection latched

IPS, IPSL Supply current VPS = 4.5 V - 210 450 µA

V(CL)PS Clamping voltage IP = 1.5 mA 5.5 6.5 8.5 V

Overload protection latched

VPSR Reset voltage 1 1.8 3 V

tpr Reset time VPS ≤ 1 V 10 45 120 µs

OPEN CIRCUIT LOAD DETECTION CHARACTERISTICS

An open circuit load condition can be detected while the TOPFET is in the off-state. Refer to TRUTH TABLE.

VPS = 5 V. Limits are for -40˚C ≤ Tmb ≤ 150˚C and typicals are for Tmb = 25˚C.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

IDSP Off-state drain current2VIS = 0 V; 2 V ≤ VDS ≤ 40 V 0.9 1.8 2.7 mA

VDSF Drain threshold voltage3VIS = 0 V 0.2 1 2 V

VISF Input threshold voltage4ID = 100 µA 0.3 0.8 1.1 V

OVERLOAD CHARACTERISTICS

Tmb = 25˚C unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Short circuit load VPS > 4 V

IDDrain current limiting VIS = 5 V; -40˚C ≤ Tmb ≤ 150˚C 28.5 44 60 A

Overload protection VPS > 4 V

PD(TO) Overload power threshold device trips if PD > PD(TO) 75 185 250 W

TDSC Characteristic time which determines trip time5250 380 600 µs

Overtemperature protection VPS = 5 V

Tj(TO) Threshold temperature from ID ≥ 4 A or VDS > 0.2 V 150 170 - ˚C

1 When VPS is less than VPSF the flag pin indicates low protection supply voltage. Refer to TRUTH TABLE.

2 The drain source current which flows in a normal load when the protection supply is high and the input is low.

3 If VDS < VDSF then the flag indicates open circuit load.

4 For open circuit load detection, VIS must be less than VISF.

5 Trip time td sc varies with overload dissipation PD according to the formula td sc ≈ TDSC / ln[ PD / PD(TO)].

July 2002 4 Rev 1.100

Philips Semiconductors Product Specification

Logic level TOPFET BUK135-50L

SMD version of BUK124-50L

TRUTH TABLE

For normal, open-circuit load and overload conditions or inadequate protection supply voltage.

Assumes proper external pull-up for flag pin. Refer to FLAG CHARACTERISTICS.

CONDITION PROTECTION INPUT FLAG OUTPUT

Normal on-state 1 1 0 ON

Normal off-state 1 0 0 OFF

Open circuit load 1 1 0 ON

Open circuit load 1 0 1 OFF

Short circuit load11 1 1 OFF

Over temperature 1 X 1 OFF

Low protection supply voltage 0 1 1 ON

Low protection supply voltage 0 0 1 OFF

KEY ‘0’ equals low

‘1’ equals high

‘X’ equals don’t care.

FLAG CHARACTERISTICS

The flag is an open drain transistor which requires an external pull-up circuit.

Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Flag ‘low’ normal operation; VPS = 5 V

VFSF Flag voltage IF = 100 µA - 0.8 1 V

IFSF Flag saturation current VFS = 5 V - 10 - mA

Flag ‘high’ overload or fault

IFSO Flag leakage current VFS = 5 V - 0.1 10 µA

V(CL)FS Flag clamping voltage IF = 100 µA 5.5 6.2 8.5 V

Application information

RFSuitable external pull-up VFF = 5 V - 47 - kΩ

resistance

SWITCHING CHARACTERISTICS

Tmb = 25˚C; RI = 50 Ω; RIS = 50 Ω; VDD = 15 V; resistive load RL = 10 Ω.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

td on Turn-on delay time VIS: 0 V ⇒ 5 V - 1.8 5 µs

trRise time - 3.5 8 µs

td off Turn-off delay time VIS: 5 V ⇒ 0 V - 11 30 µs

tfFall time - 5 12 µs

1 In this condition the protection circuit is latched. To reset the latch the protection pin must be taken low. Refer to PROTECTION SUPPLY

CHARACTERISTICS.

July 2002 5 Rev 1.100

Philips Semiconductors Product Specification

Logic level TOPFET BUK135-50L

SMD version of BUK124-50L

CAPACITANCES

Tmb = 25 ˚C; f = 1 MHz

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Ciss Input capacitance VDS = 25 V; VIS = 0 V - 710 1050 pF

Coss Output capacitance VDS = 25 V; VIS = 0 V - 370 550 pF

Crss Reverse transfer capacitance VDS = 25 V; VIS = 0 V - 26 40 pF

Cpso Protection supply pin VPS = 5 V - 22 - pF

capacitance

Cfso Flag pin capacitance VFS = 5 V; VPS = 0 V - 12 - pF

Fig.4. Normalised limiting power dissipation.

PD% = 100⋅PD/PD(25˚C) = f(Tmb)

Fig.5. Continuous drain current.

ID = f(Tamb); condition: VIS = 5 V

Fig.6. Typical output characteristics, Tj = 25˚C.

ID = f(VDS); parameter VIS; tp = 300 µs & tp < td sc

Fig.7. Typical on-state characteristics, Tj = 25˚C.

ID = f(VDS); parameter VIS; tp = 300 µs

100

120

0 20 40 60 80 100 120 140

%Normalise Power Derating

0246810121416

VDS / V

ID / A

BUK135-50L

VIS / V =

0 20 40 60 80 100 120 140

ID / A BUK135-50L

Tmb / OC

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2

/ V

/ A BUK135-50L

/ V =

July 2002 6 Rev 1.100

Philips Semiconductors Product Specification

Logic level TOPFET BUK135-50L

SMD version of BUK124-50L

Fig.8. Normalised drain-source on-state resistance.

a = RDS(ON)/RDS(ON)25˚C = f(Tj); ID = 10 A; VIS = 4.4 V

Fig.9. Typical on-state resistance, Tj = 25˚C. RDS(ON)

= f(VIS); conditions: ID = 10 A; VPS = 4 V; tp = 300 µs

Fig.10. Typical transfer characteristics, Tj = 25˚C.

ID = f(VIS); conditions: VPS ≥ 4 V tp = 300 µs

Fig.11. Typical overtemperature protection threshold.

Tj(TO) = f(VPS); conditions: VIS = 5 V

Fig.12. Typical drain source leakage current.

IDSS = f(Tj); conditions: VDS = 40 V; VPS = VIS = 0 V

Fig.13. Typical DC input characteristics, Tj = 25˚C.

IIS & IISL = f(VIS); normal operation & protection latched

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-50 0 50 100 150

Normalised R

DS(ON)

= f(T

)

j (TO)

150

160

170

180

190

200

345678

BUK135-50L

/ V

Data below 4V is for

information only. All

spec. values are for

normal operation at

4V and above.

012345678

/ V

DS(ON)

/ mOhm BUK135-50L

typ.

max.

1E-9

10E-9

100E-9

1E-6

10E-6

100E-6

-50 0 50 100 150

max.

typ.

DSS

/ A BUK135-50L

012345678

/ V

/ A BUK135-50L

= 13V

0.5

1.0

1.5

2.0

2.5

3.0

3.5

01234567

Latched

Unlatched

IIS / mA BUK135-50L

VIS / V

July 2002 7 Rev 1.100

Philips Semiconductors Product Specification

Logic level TOPFET BUK135-50L

SMD version of BUK124-50L

Fig.14. Typical DC input currents. IIS & IISL = f(Tj);

normal & latched; conditions: VIS = 5 V; VPS = 5 V

Fig.15. Input threshold voltage.

VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V

Fig.16. Typical input clamping characteristic.

II = f(VIS); normal operation, Tj = 25˚C

Fig.17. Off state drain current characteristic.

IDSP = f(VDS); conditions: Tj = 25˚C; VPS = 5 V; VIS = 0 V

Fig.18. Off state drain current vs protection supply.

IDSP = f(VPS); Tj = 25˚C; VDS = 13 V; VIS = 0 V

Fig.19. Typical off state drain current IDSP = f(Tj);

conditions: VDS = 13 V; VPS = 5 V; VIS = 0 V

10E-6

00E-6

1E-3

10E-3

-50 0 50 100 150

ISL

BUK135-50L

& I

ISL

0.5

1.0

1.5

2.0

2.5

012345

BUK135-50L

DSP

/ mA

/ V

DSP

is constant from Vds = 2V to 40V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

-50 0 50 100 150

max.

typ.

min.

Tj / OC

VIS(TO) / V BUK135-50L

0.5

1.0

1.5

2.0

2.5

012345678

VPS / V

IDSP / mA BUK135-50L

02468

BUK135-50L

IIS / mA

VIS / V

1.5

2.0

2.5

-50 0 50 100 150

BUK135-50L

DSP

/ mA

July 2002 8 Rev 1.100

Philips Semiconductors Product Specification

Logic level TOPFET BUK135-50L

SMD version of BUK124-50L

Fig.20. Open circuit detection threshold voltage.

VDSF = f(Tj); VPS ≥ 4 V ; VIS = 0 V

Fig.21. Open circuit input threshold voltage.

VISF = f(Tj); VPS ≥ 4 V ; ID = 100 µA

Fig.22. Typical DC protection supply characteristics.

IPS = f(VPS); normal or overload operation; Tj = 25 ˚C

Fig.23. Typical protection reset voltage.

VPSR = f(Tj); tlr = 100 µs

Fig.24. Typical flag characteristics. IFS = f(Tj);

fault & overload operation; VIS = 5 V; VFS = 5 V

Fig.25. Typical protection threshold voltage.

VPSF = f(Tj); VDS = 5 V ; IF = 100 µA

DSF

/ V

-50 0 50 100 150

BUK135-50L

typ.

Normal load

Open circuit load

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

-50 0 50 100 150

BUK135-50L

PSR

/ V

ISF

/ V

0.5

1.0

-50 0 50 100 150

BUK135-50L

Open circuit detection

Normal operation

typ.

10E-9

00E-9

1E-6

10E-6

-50 0 50 100 150

BUK135-50L

/ A

= 0 or 5V

typ.

max.

012345678

BUK135-50L

IPS / mA

VPS / V

3.0

3.2

3.4

3.6

3.8

4.0

-50 0 50 100 150

BUK135-50L

PSF

/ V

July 2002 9 Rev 1.100

Philips Semiconductors Product Specification

Logic level TOPFET BUK135-50L

SMD version of BUK124-50L

Fig.26. Clamping energy test circuit, RIS = 100 Ω.

Fig.27. Typical non-repetitive clamping energy.

EDSM = f(L); conditions: VIS = 0 V

Fig.28. Typical clamping characteristic, 25˚C.

ID = f(VDS); conditions: VIS = 0 V; tp ≤ 300 µs

Fig.29. Test circuit for resistive load switching times.

VIS = 5 V

Fig.30. Typical switching waveforms, resistive load.

RL = 10 Ω; adjust VDD to obtain ID = 1.5 A; Tj = 25˚C

Fig.31. Overvoltage clamping characteristic.

VDS = f(Tj); conditions: VIS = 0 V; tp ≤ 300 µs

D.U.T.

VDD

RI = RIS R 01

VDS

-ID/100

shunt

VIS

VDS

0VDD

V(CL)DSR

TOPFET

VPS

TOPFET

VII

RIS

VIS

EDSM =0.5 ⋅LID

2⋅V(CL)DSR/(V(CL)DSR −VDD)

BUK135-50L

0.2

0.4

0.6

0.8

1.0

1.2

0.1 1 10 100

EDSM / J

25OC

150OC

L / mH

0 5 10 15 20 25 30 35 40 45 50

& V

/ V BUK135-50L

Time / µs

50 60 70

BUK135-50L

/ A

/ V

DSS

/ V

-50 0 50 100 150

BUK135-50L

10mA

July 2002 10 Rev 1.100

Philips Semiconductors Product Specification

Logic level TOPFET BUK135-50L

SMD version of BUK124-50L

Fig.32. Typical overload current, VDS = 5 V.

ID = f(Tj); conditions: VIS = 5 V; VPS = 4 V; tp = 300 µs

Fig.33. Typical reverse diode current, Tj = 25 ˚C.

IS = f(VSDS); conditions: VIS = 0 V; tp = 300 µs

Fig.34. Typical capacitances, Ciss, Coss, Crss.

C = f(VDS); conditions: VIS = 0 V; f = 1 MHz

Fig.35. Transient thermal impedance.

Zth j-mb = f(t); parameter D = tp/T

-50 0 50 100 150

BUK135-50L

/ A

max.

typ.

min.

100

1000

10000

0 1020304050

VDS / V

Capacitance / pF BUK135-50L

Ciss

oss

Crss

0 0.5 1

BUK135-50L

VSD / V

/ A

1E-03

1E-02

1E-01

1E+00

1E+01

1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01

t / s

0.02

0.05

0.1

0.2

0.5

BUK135-50L

D = t

/ ( K / W )

July 2002 11 Rev 1.100

Philips Semiconductors Product Specification

Logic level TOPFET BUK135-50L

SMD version of BUK124-50L

MECHANICAL DATA

Fig.36. SOT426 surface mounting package1, centre pin connected to mounting base.

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

SOT426

0 2.5 5 mm

scale

Plastic single-ended surface mounted package (Philips version of D2-PAK); 5 leads

(one lead cropped) SOT426

e e ee

A1Lp

bcD

max. e

UNIT

DIMENSIONS (mm are the original dimensions)

mm 4.50

4.10 1.40

1.27 0.85

0.60 0.64

0.46 2.90

2.10

15.80

14.80

2.60

2.20

10.30

9.70

1.60

1.20 1.70

98-12-14

99-06-25

24 5

mounting

base

1 Epoxy meets UL94 V0 at 1/8". Net mass: 1.5 g.

For soldering guidelines and SMD footprint design, please refer to Data Handbook SC18.

July 2002 12 Rev 1.100

Philips Semiconductors Product Specification

Logic level TOPFET BUK135-50L

SMD version of BUK124-50L

DEFINITIONS

DATA SHEET STATUS

DATA SHEET PRODUCT DEFINITIONS

STATUS1STATUS2

Objective data Development This data sheet contains data from the objective specification for

product development. Philips Semiconductors reserves the right to

change the specification in any manner without notice

Preliminary data Qualification This data sheet contains data from the preliminary specification.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the specification without

notice, in order to improve the design and supply the best possible

product

Product data Production This data sheet contains data from the product specification. Philips

Semiconductors reserves the right to make changes at any time in

order to improve the design, manufacturing and supply. Changes will

be communicated according to the Customer Product/Process

Change Notification (CPCN) procedure SNW-SQ-650A

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 2002

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury. Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

1 Please consult the most recently issued datasheet before initiating or completing a design.

2 The product status of the device(s) described in this datasheet may have changed since this datasheet was published. The latest information is

available on the Internet at URL http://www.semiconductors.philips.com.

July 2002 13 Rev 1.100