24LC32AT-I/PG - Microchip Technology, Inc.

24AA32A/24LC32A

Device Selection Table

Features:

• Single-supply with operation down to 1.8V

• Low-power CMOS technology:

- 1 mA active current, ty pical

-1μA standby current (max.) (I-temp)

• Organized as a single block of 4K bytes (32 Kbit)

• 2-wire serial interface bus, I2C™ compatible

• Cascadable for up to eight devices

• Schmitt Trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz (<2.5V) and 400 kHz (≥2.5V)

compatibility

• Self-timed write cycle (including auto-erase)

• Page write buffer for up to 32 bytes

• Hardware write-protect for entire memory

• Can be operated as a serial ROM

• Factory programming (QTP) available

• ESD protection > 4,000V

• 1,000,000 erase/write cycles

• Data retention > 200 years

• 8-lead PDIP, SOIC, TSSOP, DFN and MSOP

packages

• Pb-free finish available

• Available temperature ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

Description:

The Microchip Technology Inc. 24AA32A/24LC32A

(24XX32A*) is a 32 Kbit Electrically Erasable PROM.

The device is organized as a single block of 4K x 8-bit

memory with a 2-wire serial interface. Low-voltage

design permits operation down to 1.8V, with standby

and active currents of only 1 μA and 1 mA,

respect ive ly. It has been develop ed for adv an ced , low-

power applications such as personal communications

or data acquisition. The 24XX32A also has a p age write

capa bility for up to 32 bytes of dat a. Function al address

lines allow up to eight devices on the same bus, for up

to 256 Kbits address space. The 24XX32A is available

in the standard 8-pin PDIP, surface mount SOIC,

TSSO P, 2x3 DFN and MSOP packages.

Package Types

Block Diagram

Part

Number VCC

Range Max. Clock

Frequency Temp.

Ranges

24AA32A 1.8-5.5 400 kHz(1) I

24LC32A 2.5-5.5 400 kHz I, E

Note 1: 100 kHz for VCC <2.5V

Vcc

SCL

SDA

Vss

VSS

VCC

SCL

SDA

PDIP, MSOP SOIC, TSSOP

VSS

VCC

SCL

SDA

DFN

VSS

SCL

SDA

VCC

ROTATED TSSOP

HV Genera to r

EEPROM

Array

Page Latches

YDEC

XDEC

Sense Amp.

R/W Control

I/O

Control

Logic

I/O

Memory

Control

Logic

SCL

SDA

Vcc

32K I2C™ Serial EEPROM

*24XX32A is used in this document as a generic part

number for the 24AA32A/2 4LC3 2A dev ices.

24AA32A/24LC32A

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins......................................................................................................................................................≥ 4kV

TABLE 1-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at those or any other conditions

above th ose indi cated in the opera tional li stings of this sp ecificati on is no t implie d. Exposu re to maxim um rating

conditions for extended periods may affect device reliability.

DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to +5.5V

Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V

Param.

No. Symbol Characteristic Min. Typ. Max. Units Conditions

D1 — A0, A1, A2, WP, SCL

and SDA pins —————

D2 VIH High-level input voltage 0.7 VCC ——V—

D3 VIL Low-level input voltage — — 0.3 VCC

0.2 VCC V

VVCC ≥ 2.5V

VCC < 2.5V

D4 VHYS Hysteresis of Schmitt

Trigger inputs (SDA,

SCL p ins)

0.05 VCC ——VVCC ≥ 2.5V (Note 1)

D5 VOL Low-level output voltage — — 0.40 V IOL = 3.0 mA, VCC = 4.5V

IOL = 2.1 mA, Vcc = 2.5V

D6 ILI Input leakage current ——±1μAVIN = VSS or VCC, WP = VSS

VIN = VSS or VCC, WP = VCC

D7 ILO Output leakage current ——±1μAVOUT = VSS or VCC

D8 CIN,

COUT Pin capacitance

(all inputs/ou tpu t s) ——10pFVCC = 5.0V (Note 1)

TA = 25°C, FCLK = 1 MHz

D9 ICC write Operating current —0.13mAVCC = 5.5V, SCL = 400 kHz

D10 ICC read — 0.05 400 μA

D11 ICCS Standby current —

—0.01

—1

5μA

μAIndustrial

Automotive

SDA = SCL = VCC = 5.5V

A0, A1, A2, WP = VSS

Note 1: This parameter is periodically sampled and not 100% tested.

2: Typical measurements taken at room temperature.

24AA32A/24LC32A

TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS Industrial (I ): TA = -40°C to +8 5°C, VCC = +1.8V to +5.5V

Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V

Param.

No. Symbol Characteristic Min. Max. Units Conditions

CLK Clock Frequency —

—400

100 kHz 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA32A)

2THIGH Clock High Time 600

4000 —

—ns 2.5V ≤ VCC ≤ 5.5 V

1.8V ≤ VCC < 2.5V (24AA32A)

LOW Clock Low Time 1300

4700 —

—ns 2.5V ≤ VCC ≤ 5.5 V

1.8V ≤ VCC < 2.5V (24AA32A)

4TRSDA and SCL Rise Time

(Note 1) —

—300

1000 ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA32A)

5TFSDA and SCL Fall Time — 300 ns (Note 1)

6THD:STA Start Condition Hold Time 600

4000 —

—ns 2.5V ≤ VCC ≤ 5.5 V

1.8V ≤ VCC < 2.5V (24AA32A)

7TSU:STA Start Condition Setup Time 600

4700 —

—ns 2.5V ≤ VCC ≤ 5.5 V

1.8V ≤ VCC < 2.5V (24AA32A)

HD:DAT Data Input Hold Time 0 — ns (Note 2)

9TSU:DAT Data Input Setup Time 100

250 —

—ns 2.5V ≤ VCC ≤ 5.5 V

1.8V ≤ VCC < 2.5V (24AA32A)

10 TSU:STO Stop Condition Setup Time 600

4000 —

—ns 2.5V ≤ VCC ≤ 5.5 V

1.8V ≤ VCC < 2.5V (24AA32A)

11 TSU:WP WP Setup Time 600

4000 —

—ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA32A)

12 THD:WP WP Hold Time 1300

4700 —

—ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA32A)

13 TAA Output Valid from Clock

(Note 2) —

—900

3500 ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA32A)

14 TBUF Bus free time: Time the bus

must be free before a new

transmission can start

1300

4700 —

—ns 2.5V ≤ VCC ≤ 5.5 V

1.8V ≤ VCC < 2.5V (24AA32A)

15 TOF Output Fall Time from V IH

Minimum to VIL Max imum 20+0.1CB

—250

250 ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA32A)

16 TSP Input Filter Sp ik e Su ppre ssio n

(SDA and SCL pins) —50ns(Notes 1 and 3)

17 TWC Write Cycle Time (byte or

page) —5ms—

18 — Endurance 1M — cycles 25°C, (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The com bined TSP and VHYS specifi cation s are due to n ew Schm itt Trigger input s w hich provide i mprov ed

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but ensur ed by c haracterization. For endurance estimates in a specific

applic ation, ple ase cons ult the Tot al Enduranc e™ Model which can b e obt ained on Microchip’ s w eb site at

www.microchip.com.

24AA32A/24LC32A

FIGURE 1-1: BUS T IMING DATA

(unprotected)

(protected)

SCL

SDA

OUT

D4 4

11 12

24AA32A/24LC32A

2.0 FUNCTIONAL DESCRIPTION

The 24XX32A supports a bidirectional, 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, while a device

receiving data is defined as a receiver. The bus has to

be controlled by a master device which generates the

Serial Clock (SCL), controls the bus access and gener-

ates the Start and Stop conditions, while the 24XX32A

works as slave. Both master and slave can operate as

transmitter or receiver, but the master device

determines which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stab le when ever th e clock lin e is high . Change s in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

3.1 Bus Not Busy (A)

Both data and clock lines remain high.

3.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

3.3 S top Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each dat a transf er is initiated w ith a S tart condition an d

terminated with a Stop condition. The number of data

bytes transferred between Start and Stop conditions is

determined by the master device and is, theoretically,

unlimited (although only the last thirty two bytes will be

stored when doing a write operation). When an over-

write doe s occu r, it wi ll re pla ce da t a in a fi rst- in first-o ut

(FIFO) fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The mast er device mus t ge nera te a n ext ra c lock

pulse which is associated with this Acknowledge bit.

The device that acknowledges, has to pull down the

SDA line du ring the Acknow ledge cl ock pulse in s uch a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end of

data to t he sla ve by no t gene rating a n Ack nowledg e bit

on the las t by te that has be en c loc ke d ou t of th e sl av e.

In this case, the slave (24XX32A) will leave the data

line high to enable the master to generate the Stop

condition.

FIGURE 3-1: DAT A TRANSFER SEQUENCE ON THE SERIAL BUS

Note: The 24XX32A does not generate any

Acknowledge bits if an internal

programming cycle is in progress.

SCL

SDA

(A) (B) (D) (D) (A)(C)

Start

Condition Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

24AA32A/24LC32A

3.6 Device Addressing

A control byte is the first byte received following the

Start condition from the master device (Figure 3-2).

The con trol by te co nsi sts of a fou r-bi t c ontro l c od e. For

the 24XX32A, this is set as ‘1010’ binary for read and

write op erat ion s. Th e ne xt three bit s of th e co ntro l by te

are t he C hip Sele ct b its (A 2, A1 , A0) . Th e C hip S ele ct

bits allow the use of up to eight 24XX32A devices on

the same bus and are used to select which device is

accessed. The Chip Select bits in the control byte must

corresp ond to the logic lev els on the corresp onding A2,

A1 and A0 pins for the device to respond. These bits

are in effect the three Most Significant bits of the word

address.

The last bit of the control byte defines the operation to

be performed. When set to a ‘1’, a read operation is

selected. When set to a zero, a write operation is

selected. The next two bytes received define the

address of the first data byte (Figure 3-3). Because

only A11 to A0 are used, the upper fo ur address bits are

“don’t c are” bits. Th e upper addre ss bits ar e transferred

first, followed by the Less Significant bits.

Following the Start condition, the 24XX32A monitors

the SDA bus checking the device type identifier being

transmitted and, upon receiving a ‘1010’ code and

appropri ate dev ice s elect b its , the s lave d evice output s

an Ackn owle dge si gnal on the SDA li ne. Dependi ng on

the state of the R/W bit, the 24XX3 2A will select a rea d

or write operation.

FIGURE 3-2: CONTROL BYTE FORMAT

3.7 Contiguous Addressing Across

Multiple Devices

The Chip Select bits A2, A1 and A0 can be used to

expand the contiguous address space for up to 256K

bits by adding up to eight 24XX32A devices on the

same bu s. In this case , software can use A0 of the co n-

trol byte as address b it A12; A1 a s address bit A13; an d

A2 as ad dres s bi t A14 . It is no t p oss ib le to seq ue ntia ll y

read across device boundaries.

FIGURE 3-3: ADDRES S SEQUENCE BIT ASSIGN MENTS

1010A2 A1 A0SACK

R/W

Control Code Chip Select

Bits

Slave Address

Acknowledge Bit

Start Bit

Read/Write Bit

1 010A

0R/W x xxxA

11 A

10 A

8••••••

Control Byte Address High Byte Address Low Byte

Control

Code Chip

Select

Bits x = “don’t care” bit

24AA32A/24LC32A

4.0 WRITE OPERATIONS

4.1 Byte Write

Following the Start condition from the master, the

control code (4 bits), the Chip Select (3 bits), and the

R/W bi t (wh ich is a lo gic low) ar e clo cked onto t he b us

by the master transmitter. This indicates to the

addressed slave receiver that the address high byte

will follow once it has generated an Acknowledge bit

during the ni nth cloc k cycle. Theref ore, the next by te

transmitted by the master is the high-order byte of the

word address and will be written into the Address

Pointer of the 24XX32A. The next byte is the Least

Significant Address Byte. After receiving another

Acknowledge signal from the 24XX32A, the master

device will transmit the data word to be written into the

addressed memory location. The 24XX32A acknowl-

edges again and the master generates a Stop

condition. This initiates the internal write cycle and,

during this time, the 24XX32A will not generate

Acknowledge signals (Figure 4-1). If an attempt is

made to write to the array with the WP pin held high,

the device will acknowledge the command, but no

write cycle will occur. No data will be written and the

device will immediately accept a new command. After

a byte Write command, the internal address counter

will point to the address location following the one that

was just written.

4.2 Page Write

The write control byte, word address and the first data

byte are transmitted to the 24XX32A in the same way

as in a byte write. However, instead of generating a

S top conditio n, the master tra nsmit s up to 31 additional

bytes which are temporarily stored in the on-c hip page

buffer and will be written into memory once the master

has transmitted a Stop condition. Upon receipt of each

word, the five lower Address Pointer bits are internally

inc rem en t ed b y ‘ 1’. If the master should transmit more

than 32 byt es prior to generating the S top conditi on, the

address counter will roll over and the previously

receive d dat a will be overwri tten. As w ith the byte w rite

operation, once the Stop condition is received, an

internal write c ycle wil l begin (Figure 4-2). If an att empt

is made to wr i te t o the array w i th t he W P pin he ld h ig h,

the devic e will acknowled ge the command , but no wri te

cycle will occur, no data will be written, and the device

will immediately accept a new command.

4.3 Write Protection

The W P pin a llows th e user t o writ e-prote ct the entire

array (000-FFF) when the pin is tied to VCC. If tied to

VSS the write protection is disabled. The WP pin is

sampled at the Stop bit for every Write command

(Figure 3-1). Toggling the WP pin after the Stop bit will

have no effect on the execution of the write cycle.

Note: Page write opera tions are l imited to wri ting

bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples o f the page buf fer size (or

‘pag e size’) an d, end at addresses tha t are

integer multiples of [page size – 1]. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being w ritte n to th e nex t page as mi ght be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

24AA32A/24LC32A

FIGURE 4-1: BYTE W RITE

FIGURE 4-2: PAGE W RITE

xxx

Bus Acti vi ty

Master

SDA Line

Bus Acti vi ty

Control

Byte Address

High Byte Address

Low Byte Data S

x = “don’t care” bit

S1010 0

xxx

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte Address

High Byte Address

Low Byte Data Byte 0 S

Data Byte 31

x = “don’t care” bit

S101 0 0

24AA32A/24LC32A

5.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

comma nd has been is sued from the master , the device

initiates the internally-timed write cycle. ACK polling

can then be initiated immediately. This involves the

master sending a S tart c ondition fo llowed by t he contro l

byte for a Write command (R/W = 0). If the device is stil l

busy with the write cycle, then no ACK will be returned.

If no ACK is returned, the S tart b it and control byte must

be re-sent. If the cycle is complete, the device will

return the ACK and the master can then proceed with

the next Read or Write command. See Figure 5-1 for

flow diagram of this operation.

FIGURE 5-1: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

Yes

24AA32A/24LC32A

6.0 READ OPERATION

Read operations are initiated in the same way as write

operations, with the exception that the R/W bit of the

control by te is se t to ‘1’. There are three basic types of

read operations: current address read, random read

and sequential read.

6.1 Current Address Read

The 24XX32A contains an address counter that main-

tains the address of the last word accessed, internally

incremented by ‘1’. Therefore, if the previous read

access was to address ‘n’ (n is any legal address), the

next curren t address read operati on would access dat a

from addre ss n + 1.

Upon receipt of the control byte with R/W bit set to ‘1’,

the 24XX3 2A issues an acknowl edge and t ransmits th e

8-bit data word. The master will not acknowledge the

transfer, but does generate a Stop condition and the

24XX32A discontinues transmission (Figure 6-1).

6.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, the word address must

first be set. This is accomplished by sending the word

address to the 24XX32A as part of a write operation

(R/W bit set to ‘0’). On ce the word addr ess i s sent, the

master generates a Start condition following the

acknowledge. This terminates the write operation, but

not before the internal Address Pointer is set. The

master issues the control byte again, but with the R/W

bit set to a ‘1’. The 24XX32A will then issue an

acknowledge and transmit the 8-bit data word. The

master will not acknowledge the transfer, but does

generate a Stop condition which causes the 24XX32A

to discontinue transmission (Figure 6-2). After a

random Read command, the internal address counter

will point to the address location following the one that

was just read .

6.3 Sequentia l Read

Sequential reads are initiated in the same way as a

random read , exc ep t that onc e the 24 XX32A tran sm its

the first data byte, the master issues an acknowledge

as opposed to the Stop condition used in a random

read. This acknowledge directs the 24XX32A to

transmit the next sequentially addressed 8-bit word

(Figure 6-3). Following the final byte transmitted to the

master, the m aster will NOT generate an ackn owledg e,

but will generate a Stop condition. To provide sequen-

tial reads, the 24XX32A contains an internal Address

Pointer w h ich i s inc rem en ted by ‘1’ upon c om pl etio n of

each operation. This Address Pointer allows the entire

memory contents to be serially read during one

operation. The internal Address Pointer will automati-

cally roll over from address FFF to address 000 if the

master ac kn owle dges the byte recei ved from the arra y

address FFF.

FIGURE 6-1: CURRENT ADDRESS READ

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte Data (n)

24AA32A/24LC32A

FIGURE 6-2: RANDOM READ

FIGU RE 6-3 : S EQ U ENT I AL REA D

xxx

Bus Activity

Master

SDA Line

Bus Activity A

TControl

Byte Address

High Byte Address

Low Byte Control

Byte Data

Byte

x = “don’t care” bit

S1010AAA0

210 S1010AAA1

210 P

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte Data n Data n + 1 Data n + 2 Data n + x

24AA32A/24LC32A

7.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 7-1.

TABLE 7-1: PIN FUNCTION TABLE

7.1 A0, A1, A2 Chip Address Inputs

The A0, A 1 and A2 i nputs are used by the 24XX3 2A for

multiple device operation. The levels on these inputs

are compared with the corresponding bits in the slave

address. The chip is selected if the comparison is true.

Up to eigh t devi ces ma y be conn ected to th e sam e bu s

by using different Chip Select bit combinations. These

inputs must be connected to either VCC or VSS.

In most applications, the chip address inputs A0, A1

and A2 are hard-wired to logic ‘0’ or logic ‘1’. For

applications in which these pins are controlled by a

microc ontroller or oth er programmabl e device, th e chip

address pins must be driven to logic ‘0’ or logic ‘1’

before normal device operation can proceed.

7.2 Serial Data (SDA)

SDA is a bidirectional pin used to transfer addresses

and data into and out of the device. It is an open-drain

terminal, therefore, the SDA bus requires a pull-up

resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for

400 kHz)

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating Start and Stop conditions.

7.3 Serial Clock (SCL)

The SCL in put is u sed to s ynchro niz e th e da ta transf er

to and from the device.

7.4 Wr it e-Protect (WP)

This pin m ust be conne cted to e ither VSS or VCC. If tied

to VSS, write operations are enabled. If tied to VCC,

write operations are inhibited but read operations are

not affected.

Name PDIP SOIC TSSOP DFN MSOP ROTATED

TSSOP Description

A0 1 1 1 1 1 3 Chip Address Input

A1 2 2 2 2 2 4 Chip Address Input

A2 3 3 3 3 3 5 Chip Address Input

VSS 4 4 4 4 4 6 Ground

SDA 5 5 5 5 5 7 Serial Address/Data I/O

SCL 6 6 6 6 6 8 Ser ial Clock

WP 7 7 7 7 7 1 Write-Protect Input

VCC 8 8 8 8 8 2 +1.8V to 5.5V Power Supply

24AA32A/24LC32A

8.0 PACKAGING INFORMATION

8.1 Package Marking Information

XXXXXXXX

T/XXXNNN

YYWW

8-Lead PDIP (300 mil) Example:

8-Lead SOIC (150 mil) Example:

XXXXXXXT

XXXXYYWW

NNN

8-Lead TSSOP Example:

24LC32A

I/P 13F

0527

24LC32AI

SN 0527

13F

4LA

I527

13F

8-Lead MSOP Example:

XXXXXT

YWWNNN 4L32AI

52713F

8-Lead SOIC (208 mil) Example:

XXXXXXXX

T/XXXXXX

YYWWNNN

24LC32A

I/SM

052713F

XXXX

TYWW

NNN

8-Lead 2x3 DFN Example:

264

527

XXX

YWW

24AA32A/24LC32A

Part Number

1st Line Marking Codes

TSSOP MSOP DFN

Standard Rotated I Temp. E Temp.

24AA32A 4AA 4AAX 4A32AT 261 262

24LC32A 4LA 4LAX 4L32AT 264 265

Note: T = Temperature grade (I, E)

Legend: XX...X Part number or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week o f January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event th e full Mi croch ip pa rt numbe r canno t be ma rked on one line , it wil

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.

*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.

24AA32A/24LC32A

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Units INCHES* MILLIMETERS

Dime nsion Limits MIN NOM MAX MIN NOM MAX

Number of Pins n88

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to Shoulder W idt h E .300 .313 .325 7.62 7.94 8.26

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overall Length D .360 .373 .385 9.14 9.46 9.78

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thickness c.008 .012 .015 0.20 0.29 0.38

Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78

Lower Lead Width B .014 .018 .022 0.36 0.46 0.56

Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92

Mold Draft Angle Top α51015 51015

Mold Draft Angle Bottom β51015 51015

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

JEDEC Equivalent: MS-001

Drawing No. C04-018

.010” (0.254mm) per side.

§ Significant Characteristic

24AA32A/24LC32A

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

Foot A ngle φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008

Lead Thickness

0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Pa ckag e Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004

Standoff § 1.551.421.32.061.056.052A2Molded Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050

Pitch 88

Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

§ Significant Characteristic

24AA32A/24LC32A

8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC)

Foot A ngle φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.430.36.020.017.014BLead Width 0.250.230.20.010.009.008

Lead Thickness

0.760.640.51.030.025.020LFoot Lengt h 5.335.215.13.210.205.202DOverall Length 5.385.285.11.212.208.201E1Molded Packag e Width 8.267.957.62.325.313.300EOverall Width 0.250.130.05.010.005.002A1Standoff § 1.98.078A2M old ed Pa ckag e Thick ness 2.03.080AOverall Height 1.27.050

Pitch 88

Number of Pins MAXNOMMINMAXNOMMINDimensi on Li mits MILLIMETERSINCHES*Units

.070 .075

.069 .074 1.78

1.75 1.97

1.88

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

Drawing No. C04-056

§ Significant Characteristic

24AA32A/24LC32A

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

10501050

Mold Draft Angle Bottom 10501050

Mold Draft Angle Top 0.300.250.19.012.010.007BLead Width 0.200.150.09.008.006.004

Lead Thickness

0.700.600.50.028.024.020LFoot Lengt h 3.103.002.90.122.118.114DMolded Package Length 4.504.404.30.177.173.169E1Mold ed Pa ckag e Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002

Standoff § 0.950.900.85.037.035.033A2Molded Pa ckag e Thick ness 1.10.043AOverall Height 0.65.026

Pitch 88

Number of Pins MAXNOMMINMAXNOMMINDimensi on Li mits MILLIMETERS*INCHES

Units

Foot A ngle φ048048

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-086

§ Significant Characteristic

24AA32A/24LC32A

8-Lead Plastic Dual Flat No Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated

Exposed Pad Width

Exposed Pad Length

Contact Length

*Controlling Parameter

Contact Width

Drawing No. C04-123

Notes:

Exposed pad dimensions vary with paddle size.

Overall Width

.016

.012

.008

.047

.055

.010

.118 BSC

Number of Pins

Standoff

Contact Thickness

Overall Length

Overall Height

Pitch p

Units

Dimension Limits

.000 .001

.008 REF.

.079 BSC

.031

.020 BSC

MIN

INCHES

NOM

0.40

0.25

3.00 BSC

0.30

.020

.071

.012

.064

0.20

1.20

1.39

0.50

0.30

1.80

1.62

0.02

0.80

2.00 BSC

0.20 REF.

0.50 BSC

MILLIMETERS*

.002

.039

0.00

MINMAX NOM

0.05

1.00

MAX

Package may have one or more exposed tie bars at ends.1.

Pin 1 visual index feature may vary, but must be located within the hatched area.2.

0.90.035

(Note 3)

4. JEDEC equivalent: MO-229

A3 A1

TOP VIEW

EXPOSED

PAD

METAL

BOTTOM VIEW

(NOTE 1)

EXPOSED

TIE BAR

PIN 1

(NOTE 2)

ID INDEX

AREA

Revised 05/24/04

-- --

24AA32A/24LC32A

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

(F)

n 1

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

.037 REFFFootprint (Reference)

exceed .010" (0.254mm) per side.

Notes:

Drawing No. C04-111

*Controlling Parameter

Mold Draft Angle Top

Mold Draft Angle Bottom

Foot Angle

Lead Width

Lead Thickness

.003

.009

.006

.012

Dimension Limits

Overall Height

Molded Package Thickness

Molded Package Width

Overall Length

Foot Length

Standoff

Overall Width

Number of Pins

Pitch

.016 .024

.118 BSC

.000

.030

.193 TYP.

.033

MIN

Units

.026 BSC

NOM

INCHES

0.95 REF

.009

.016

0.08

0.22

0°

0.23

0.40

8°

MILLIMETERS*

0.65 BSC

0.85

3.00 BSC

0.60

4.90 BSC

.043

.031

.037

.006

0.40

0.00

0.75

MIN

MAX NOM

1.10

0.80

0.15

0.95

MAX

15°5° -

JEDEC Equivalent: MO-187

0° - 8°

5°

5° -

15°

24AA32A/24LC32A

APPENDIX A: REVISION HISTORY

Revision D

Corrections to Section 1.0, Electrical Characteristics.

Revision E

Added DFN package.

Revision F

Revised Sections 4.3, 7.2 and 7.4.

24AA32A/24LC32A

NOTES:

24AA32A/24LC32A

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

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Questions (FAQ), technical support requests,

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Technical s upport is a vailable through the web site

at: http://support.microchip.com

24AA32A/24LC32A

READER RESPONSE

It is ou r intentio n to provide you with the b es t do cument a t ion po ss ib le to e ns ure suc c es sfu l u se of y ou r M icr oc hip pro d-

uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subj ect matte r , and ways i n which o ur docum entatio n

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

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Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS21713F24AA32A/24LC32A

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

24AA32A/24LC32A

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Note 1: Most products manufactured after January 2005 will have a Matte Tin (Pb-free) finish. Most products manufactured

before January 2005 will have a finish of approximately 63% Sn and 37% Pb (Sn/Pb).

Please visit www.microchip.com for the latest information on Pb-free conversion, including conversion date codes.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Dat a Sheet (include Literature #) you are using.

New Customer Notification System

PART NO. X/XX

PackageTemperature

Range

Device

Device: 24AA32A: 1.8V, 32 Kbit I2C Serial EEPRO M

24AA32AT: 1.8V, 32 Kbit I2C Serial EEPRO M

(Tape and Reel)

24AA32AX 1.8V, 32 Kbit I2C Ser ia l EE PRO M in

alternate pinout (ST only)

24AA32AXT 1.8V, 32 Kbit I2C Seria l EEPR O M in

alternate pinout (ST only)

24LC32A: 2.5V, 32 Kbit I2C Serial EEPRO M

24LC32AT: 2.5V, 32 Kbit I2C Serial EE PRO M

(Tape and Reel)

24LC32AX 2.5V, 32 Kbit I2C Ser ia l EEPR O M in

alternate pinout (ST only)

24LC32AXT 2.5V, 32 Kbit I2C Ser ia l EE PRO M in

alternate pinout (ST only)

Temperature

Range: I = -40°C to +85°C

E = -40°C to +125°C

Package: P = Plastic DIP (300 mil body), 8-lead

SN = Plastic SOIC (150 mil body), 8-lead

SM = Plastic SOIC (208 mil body), 8-lead

ST = Plastic TSSOP (4.4 mm), 8-lead

MS = Plastic Micro Small Outline (MSOP), 8-lead

MC = 2x3 DFN, 8-lead

Lead Finish: Blank = Pb-free – Matte Tin (see Note 1)

G = Pb-free – Matte Tin only

Examples:

a) 24AA32A-I/P: Industrial Temperature,1.8V,

PDIP package

b) 24AA32A-I/SN: Industrial Temperature,1.8V,

SOIC pack ag e

c) 24AA32A-I/SM : Industrial Temperature.,1.8V,

SOIC (208 mil) package

d) 24AA32AX -I/ST: Industrial Tem p.,1.8V,

Rotated TSSOP package

e) 24AA32A-I/ST: Industrial Temperature.,1.8V,

TSSO P package

f) 24LC32A-I/P: Industrial Temperature, 2.5V,

PDIP package

g) 24LC32A-E/SN: Automotive Temperature

2.5V SOIC package

h) 24LC32A-E/SM : Automotive Temperature,

2.5V SOIC (208 mil) package

i) 24LC32AX-E/ST: Automotive Temperature,

2.5V, Rotated TSSOP package

j) 24LC32AT - I/ST: Industrial Temperature, 2.5V,

TSSOP package, Tape and Reel

Lead Finish

24AA32A/24LC32A

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

RANTIES OF ANY KIN D WHETHER EXPRESS OR IMPLIED ,

WRITTEN OR ORAL, STATUTORY OR OTHERWISE,

RELATED TO THE INFORMATION, INCLUDING BUT NOT

LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and

its use. U se of Microc hip’s products as critical com ponents in

life support systems is not authorized except with express

written approval by Microchip. No licenses are conveyed,

implicitly or otherwise, under any Microchip intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXD EV, MXLAB,

PICMASTER, SEEVAL, SmartSensor and The Embedded

Control Solutions Company are registered trademarks of

Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Programming, ICSP, ICEPIC, Linear Active Thermistor,

MPASM , MPLIB, MPL I N K, MPSIM, PI Ckit , PICDEM,

PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,

PowerMate, Powe rTool, rfLAB, rfPICDEM , Select Mode,

Smart Serial, SmartTel, Total Endurance and WiperLock are

trademarks of Microchip Technology Incorporated in the

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SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of the most secure families of it s kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microchip are committed to continuously improving the c ode prot ection f eatures of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping

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08/24/05