TLE9871QXA20 Microcontroller with PWM Interface and BLDC MOSFET Driver for Automotive Applications BF-Step Data Sheet Rev. 1.0, 2017-03-03 Automotive Power TLE9871QXA20 Table of Contents Table of Contents 1 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 3.1 3.2 Device Pinout and Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 5.1 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.2 5.3.3 Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PMU Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Generation Unit (PGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Regulator 5.0V (VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Regulator 1.5V (VDDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Voltage Regulator 5.0V (VDDEXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 18 19 21 22 22 23 24 6 6.1 6.2 6.2.1 6.3 6.3.1 6.3.2 6.3.2.1 6.3.2.2 System Control Unit - Digital Modules (SCU-DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Precision Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Precision Oscillator Circuit (OSC_HP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Input Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Crystal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 25 26 27 28 28 28 28 7 7.1 7.2 7.2.1 System Control Unit - Power Modules (SCU-PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 30 30 8 8.1 8.2 8.2.1 ARM Cortex-M3 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 32 33 33 9 9.1 9.2 9.2.1 9.3 9.3.1 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Mode Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 34 35 35 36 36 10 Address Space Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11 11.1 11.2 11.2.1 11.3 Memory Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVM Module (Flash Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 2 38 38 38 38 40 Rev. 1.0, 2017-03-03 TLE9871QXA20 Table of Contents 12 12.1 12.2 12.2.1 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13.1 13.2 Watchdog Timer (WDT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14 14.1 14.2 14.2.1 14.2.2 14.3 14.3.1 14.3.1.1 14.3.2 14.3.2.1 14.3.3 14.3.3.1 GPIO Ports and Peripheral I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 and Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLE9871QXA20 Port Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 45 45 45 47 48 48 48 50 50 52 52 15 15.1 15.1.1 15.1.2 15.2 15.2.1 15.2.2 General Purpose Timer Units (GPT12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 53 53 53 53 54 55 16 16.1 16.2 16.2.1 Timer2 and Timer21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer2 and Timer21 Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 56 56 56 17 17.1 17.2 17.3 17.3.1 Timer3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer3 Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 57 57 57 57 18 18.1 18.2 18.2.1 Capture/Compare Unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Feature Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 59 59 60 19 19.1 19.2 19.2.1 19.3 UART1/UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 61 61 61 62 20 20.1 20.2 20.2.1 High Voltage PWM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 63 63 64 Data Sheet 3 41 41 41 41 Rev. 1.0, 2017-03-03 TLE9871QXA20 Table of Contents 21 21.1 21.2 21.2.1 High-Speed Synchronous Serial Interface (SSC1/SSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 65 66 66 22 Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2.1.1 Block Diagram BEMF Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 67 67 68 69 23 23.1 23.2 23.2.1 23.2.2 Measurement Core Module (incl. ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measurement Core Module Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 70 70 70 71 24 24.1 24.2 24.2.1 10-Bit Analog Digital Converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 72 72 73 25 25.1 25.2 25.2.1 High-Voltage Monitor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 74 74 74 26 26.1 26.2 26.2.1 26.2.2 Bridge Driver (incl. Charge Pump) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 75 75 76 76 27 27.1 27.2 27.2.1 Current Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 77 77 77 28 28.1 28.2 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 BLDC Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 ESD Immunity According to IEC61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 29 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.1.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.1.3 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.1.4 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.1.5 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.2 Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.2.1 PMU I/O Supply (VDDP) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.2.2 PMU Core Supply (VDDC) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.2.3 VDDEXT Voltage Regulator (5.0V) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.2.4 VPRE Voltage Regulator (PMU Subblock) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.2.4.1 Load Sharing Scenarios of VPRE Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.2.5 Power Down Voltage Regulator (PMU Subblock) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 4 81 81 81 84 85 87 87 88 88 90 91 93 93 94 Rev. 1.0, 2017-03-03 TLE9871QXA20 Table of Contents 29.3 29.3.1 29.3.2 29.4 29.4.1 29.5 29.5.1 29.5.2 29.5.3 29.6 29.6.1 29.7 29.7.1 29.8 29.8.1 29.8.2 29.8.3 29.8.3.1 29.8.3.2 29.9 29.9.1 29.9.2 29.10 29.11 29.11.1 29.12 29.12.1 29.13 29.13.1 System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Oscillators and PLL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 External Clock Parameters XTAL1, XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Flash Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Parallel Ports (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Description of Keep and Force Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 DC Parameters of Port 0, Port 1, TMS and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 DC Parameters of Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 PWM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 SSC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 System Voltage Measurement Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Central Temperature Sensor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ADC2-VBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 ADC2 Reference Voltage VBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 ADC2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 ADC1 Reference Voltage - VAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Electrical Characteristics VAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Electrical Characteristics ADC1 (10-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 High-Voltage Monitoring Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 30 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 31 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Data Sheet 5 Rev. 1.0, 2017-03-03 Microcontroller with PWM Interface and BLDC MOSFET Driver for Automotive Applications 1 TLE9871QXA20 Overview Summary of Features * * * * * * * * * * * * * * * * * * * * * * 32 bit ARM Cortex M3 Core - up to 24 MHz clock frequency - one clock per machine cycle architecture On-chip memory - 36 kByte Flash including - 4 kByte EEPROM (emulated in Flash) - 1024 Byte 100 Time Programmable Memory (100TP) - 3 kByte RAM - Boot ROM for startup firmware and Flash routines On-chip OSC and PLL for clock generation - PLL loss-of-lock detection MOSFET driver including charge pump 10 general-purpose I/O Ports (GPIO) 5 analog inputs, 10-bit A/D Converter (ADC1) 16-bit timers - GPT12, Timer 2, Timer 21 and Timer 3 Capture/compare unit for PWM signal generation (CCU6) 2 full duplex serial interfaces (UART) 2 synchronous serial channels (SSC) On-chip debug support via 2-wire SWD Bidirectional PWM interface 1 high voltage monitoring input Single power supply from 5.5 V to 27 V Extended power supply voltage range from 3 V to 28 V Low-dropout voltage regulators (LDO) High speed operational amplifier for motor current sensing via shunt 5 V voltage supply for external loads (e.g. Hall sensor) Core logic supply at 1.5 V Programmable window watchdog (WDT1) with independent on-chip clock source Power saving modes - MCU slow-down Mode - Sleep Mode - Stop Mode - Cyclic wake-up Sleep Mode Power-on and undervoltage/brownout reset generator Type Package TLE9871QXA20 VQFN-48-31 Data Sheet VQFN-48-31 Marking 6 Rev. 1.0, 2017-03-03 TLE9871QXA20 Overview * * * * * * * Overtemperature protection Short circuit protection Loss of clock detection with fail safe mode entry for low system power consumption Temperature Range Tj = -40 C to +150 C Package VQFN-48 with LTI feature Green package (RoHS compliant) AEC qualified Data Sheet 7 Rev. 1.0, 2017-03-03 TLE9871QXA20 Overview 1.1 Abbreviations The following acronyms and terms are used within this document. List see in Table 1. Table 1 Acronyms Acronyms Name AHB Advanced High-Performance Bus APB Advanced Peripheral Bus CCU6 Capture Compare Unit 6 CGU Clock Generation Unit CMU Cyclic Management Unit CP Charge Pump for MOSFET driver CSA Current Sense Amplifier DPP Data Post Processing ECC Error Correction Code EEPROM Electrically Erasable Programmable Read Only Memory EIM Exceptional Interrupt Measurement FSM Finite State Machine GPIO General Purpose Input Output H-Bridge Half Bridge ICU Interrupt Control Unit IEN Interrupt Enable IIR Infinite Impulse Response LDM Load Instruction LDO Low DropOut voltage regulator LSB Least Significant Bit LTI Lead Tip Inspection MCU Memory Control Unit MF Measurement Functions MSB Most Significant Bit MPU Memory Protection Unit MRST Master Receive Slave Transmit MTSR Master Transmit Slave Receive MU Measurement Unit NMI Non Maskable Interrupt NVIC Nested Vector Interrupt Controller NVM Non-Volatile Memory OTP One Time Programmable OSC Oscillator PBA Peripheral Bridge PCU Power Control Unit Data Sheet 8 Rev. 1.0, 2017-03-03 TLE9871QXA20 Overview Table 1 Acronyms Acronyms Name PD Pull Down PGU Power supply Generation Unit PLL Phase Locked Loop PPB Private Peripheral Bus PU Pull Up PWM Pulse Width Modulation RAM Random Access Memory RCU Reset Control Unit RMU Reset Management Unit ROM Read Only Memory SCU-DM System Control Unit - Digital Modules SCU-PM System Control Unit - Power Modules SFR Special Function Register SOW Short Open Window (for WDT) SPI Serial Peripheral Interface SSC Synchronous Serial Channel STM Store Instruction SWD ARM Serial Wire Debug TCCR Temperature Compensation Control Register TMS Test Mode Select TSD Thermal Shut Down UART Universal Asynchronous Receiver Transmitter VBG Voltage reference Band Gap VCO Voltage Controlled Oscillator VPRE Pre Regulator WDT Watchdog Timer in SCU-DM WDT1 Watchdog Timer in SCU-PM WMU Wake-up Management Unit 100TP 100 Time Programmable Data Sheet 9 Rev. 1.0, 2017-03-03 TLE9871QXA20 Block Diagram 2 Block Diagram TMS P0.0 TEST / DEBUG INTERFACE ARM CORTEX-M3 DMA CONTROLLER systembus FLASH slave SRAM slave ROM slave slave Multilayer AHB Matrix slave VAREF GND_REF P2.0, P2.2, P2.3, P2.4, P2.5 (AN0, AN2, AN3, AN4, AN5) Figure 1 Data Sheet PBA1 SCU_DM ADC 1 DPP1 GPT12 UART1 UART2 SSC1 SSC2 MOSFET Driver CCU6 T2 T21 SCU_DM WDT SCU_PM WDT1/ CLKWDT CP DMA Controller T3 OP AMP VCP VSD CP2H CP2L CP1H CP1L PBA0 OP AMP VDH GH3 SH3 GL3 GH2 SH2 GL2 GH1 SH1 GL1 SL MU-VAREF slave PLL XTAL1 XTAL2 GPIO P0.1 - P0.4 P1.0 - P1.4 PWM PWM_IO GND_PWM MU MF / ADC2 DPP2 OP AMP OP1 OP2 PMU - Power Control System Functions VS RESET VDDEXT VDDP VDDC MON MON Block Diagram TLE9871QXA20 10 Rev. 1.0, 2017-03-03 TLE9871QXA20 25 P0.2 27 P1.4 28 GND 29 P2.0/XTAL1 30 P2.2/XTAL2 31 P2.5 32 P2.4 33 GND_REF Device Pinout 34 VAREF 3.1 35 P2.3 Device Pinout and Pin Configuration 36 OP2 3 26 P1.3 Device Pinout and Pin Configuration OP1 37 24 P0.3 EP VDDC 38 23 P0.1 EP GND 39 22 RESET VDDP 40 21 P0.0 VDDEXT 41 20 TMS GND_PWM 42 19 GND TLE 9871 PWM_IO 43 18 P0.4 VDH 44 17 P1.2 VS 45 16 P1.1 SH3 46 15 P1.0 VSD 47 14 MON 13 GL1 Note: Figure 2 Data Sheet GL2 12 GL3 11 SL 10 GH1 9 SH1 8 GH2 7 SH2 6 GH3 5 CP2L 4 VCP 2 CP2H 3 CP1L 1 CP1H 48 = Low voltage pins Device Pinout, TLE9871QXA20 11 Rev. 1.0, 2017-03-03 TLE9871QXA20 Device Pinout and Pin Configuration 3.2 Pin Configuration After reset, all pins are configured as input (except supply pin) with one of the following settings: * * * * Pull-up device enabled only (PU) Pull-down device enabled only (PD) Input with both pull-up and pull-down devices disabled (I) Output with output stage deactivated = high impedance state (Hi-Z) The functions and default states of the TLE9871QXA20 external pins are provided in the following table. Type: indicates the pin type. * * * * I/O: Input or output I: Input only O: Output only P: Power supply Not all alternate functions listed. Table 2 Symbol Pin Definitions and Functions Pin Number Type Reset State1) P0 Function Port 0 Port 0 is a 5-bit bidirectional general purpose I/O port. Alternate functions can be assigned and are listed in the port description. Main function is listed below. P0.0 21 I/O I/PU SWD Serial Wire Debug Clock P0.1 23 I/O I/PU GPIO General Purpose IO Alternate function mapping see Table 8 P0.2 25 I/O I/PD GPIO General Purpose IO Alternate function mapping see Table 8 Note: For a functional SWD connection this GPIO must be tied to zero! P0.3 24 I/O I/PU GPIO General Purpose IO Alternate function mapping see Table 8 P0.4 18 I/O I/PD GPIO General Purpose IO Alternate function mapping see Table 8 P1 Port 1 Port 1 is a 5-bit bidirectional general purpose I/O port. Alternate functions can be assigned and are listed in the Port description. The principal functions are listed below. P1.0 15 I/O I GPIO General Purpose IO Alternate function mapping see Table 9 P1.1 16 I/O I GPIO General Purpose IO Alternate function mapping see Table 9 P1.2 17 I/O I GPIO General Purpose IO Alternate function mapping see Table 9 P1.3 26 I/O I GPIO General Purpose IO, used for Inrush Transistor Alternate function mapping see Table 9 P1.4 27 I/O I GPIO General Purpose IO Alternate function mapping see Table 9 Data Sheet 12 Rev. 1.0, 2017-03-03 TLE9871QXA20 Device Pinout and Pin Configuration Table 2 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset State1) P2 Function Port 2 Port 2 is a 5-bit general purpose input-only port. Alternate functions can be assigned and are listed in the Port description. Main function is listed below. P2.0/XTAL1 29 I/I I AN0 ADC analog input 0 Alternate function mapping see Table 10 P2.2/XTAL2 30 I/O I AN2 ADC analog input 2 Alternate function mapping see Table 10 P2.3 35 I I AN3 ADC analog input 3 Alternate function mapping see Table 10 P2.4 32 I I AN4 ADC analog input 4 Alternate function mapping see Table 10 P2.5 31 I I AN5 ADC analog input 5 Alternate function mapping see Table 10 VS 45 P - Battery supply input VDDP 40 P - 2) Power Supply I/O port supply (5.0 V). Connect external buffer capacitor. VDDC 38 P - 3) VDDEXT 41 P - External voltage supply output (5.0 V, 20 mA) GND 19 P - GND digital GND 28 P - GND digital GND 39 P - GND analog 14 I - High Voltage Monitor Input PWM_IO 43 I/O - PWM interface input/output GND_PWM 42 P - PWM ground CP1H 48 P - Charge Pump Capacity 1 High, connect external C CP1L 1 P - Charge Pump Capacity 1 Low, connect external C CP2H 3 P - Charge Pump Capacity 2 High, connect external C CP2L 4 P - Charge Pump Capacity 2 Low, connect external C VCP 2 P - Charge Pump Capacity VSD 47 P - Battery supply input for Charge Pump VDH 44 P - Voltage Drain High Side MOSFET Driver SH3 46 P - Source High Side FET 3 SH2 6 P - Source High Side FET 2 Core supply (1.5 V during Active Mode). Do not connect external loads, connect external buffer capacitor. Monitor Input MON PWM Interface Charge Pump MOSFET Driver Data Sheet 13 Rev. 1.0, 2017-03-03 TLE9871QXA20 Device Pinout and Pin Configuration Table 2 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset State1) Function GH2 7 P - Gate High Side FET 2 SH1 8 P - Source High Side FET 1 GH1 9 P - Gate High Side FET 1 SL 10 P - Source Low Side FET GL2 12 P - Gate Low Side FET 2 GL1 13 P - Gate Low Side FET 1 GH3 5 P - Gate High Side FET 3 GL3 11 P - Gate Low Side FET 3 GND_REF 33 P - GND for VAREF VAREF 34 I/O - 5V ADC1 reference voltage, optional buffer or input OP1 37 I - Negative operational amplifier input OP2 36 I - Positive operational amplifier input TMS 20 I I/O I/PD TMS SWD RESET 22 I/O - Reset input, not available during Sleep Mode EP - - - Exposed Pad, connect to GND Others Test Mode Select input Serial Wire Debug input/output 1) Only valid for digital IOs 2) Also named VDD5V. 3) Also named VDD1V5. Data Sheet 14 Rev. 1.0, 2017-03-03 TLE9871QXA20 Modes of Operation 4 Modes of Operation This highly integrated circuit contains analog and digital functional blocks. An embedded 32-bit microcontroller is available for system and interface control. On-chip, low-dropout regulators are provided for internal and external power supply. An internal oscillator provides a cost effective clock that is particularly well suited for PWM communications. A PWM interface is available as a communication interface. Driver stages for a Motor Bridge or BLDC Motor Bridge with external MOSFET are integrated, featuring PWM capability, protection features and a charge pump for operation at low supply voltage. A 10-bit SAR ADC is implemented for high precision sensor measurement. An 8-bit ADC is used for diagnostic measurements. The Micro Controller Unit supervision and system protection (including a reset feature) is complemented by a programmable window watchdog. A cyclic wake-up circuit, supply voltage supervision and integrated temperature sensors are available on-chip. All relevant modules offer power saving modes in order to support automotive applications connected to terminal 30. A wake-up from power-save mode is possible via a PWM interface, via the monitoring input or using a programmable time period (cyclic wake-up). Featuring LTI, the integrated circuit is available in a VQFN-48-31 package with 0.5 mm pitch, and is designed to withstand the severe conditions of automotive applications. The TLE9871QXA20 has several operation modes mainly to support low power consumption requirements. Reset Mode The Reset Mode is a transition mode used e.g. during power-up of the device after a power-on reset, or after wakeup from Sleep Mode. In this mode, the on-chip power supplies are enabled and all other modules are initialized. Once the core supply VDDC is stable, the device enters Active Mode. If the watchdog timer WDT1 fails more than four times, the device performs a fail-safe transition to Sleep Mode. Active Mode In Active Mode, all modules are activated and the TLE9871QXA20 is fully operational. Stop Mode Stop Mode is one of two major low power modes. The transition to the low power modes is performed by setting the corresponding bits in the mode control register. In Stop Mode the embedded microcontroller is still powered, allowing faster wake-up response times. Wake-up from this mode is possible through LIN bus activity, by using the high-voltage monitoring pin or the corresponding 5V GPIOs. Stop Mode with Cyclic Wake-Up The Cyclic Wake-Up Mode is a special operating mode of the Stop Mode. The transition to the Cyclic Wake-Up Mode is done by first setting the corresponding bits in the mode control register followed by the Stop Mode command. In addition to the cyclic wake-up behavior (wake-up after a programmable time period), asynchronous wake events via the activated sources (LIN and/or MON) are available, as in normal Stop Mode. Sleep Mode The Sleep Mode is a low-power mode. The transition to the low-power mode is done by setting the corresponding bits in the MCU mode control register or in case of failure, see below. In Sleep Mode the embedded microcontroller power supply is deactivated allowing the lowest system power consumption. A wake-up from this mode is possible by PWM Interface activity, the High Voltage Monitor Input pin or Cyclic Wake-up. Sleep Mode in Case of Failure Data Sheet 15 Rev. 1.0, 2017-03-03 TLE9871QXA20 Modes of Operation Sleep Mode is activated after 5 consecutive watchdog failures or in case of supply failure (5 times). In this case, MON is enabled as the wake source and Cyclic Wake-Up is activated with 1s of wake time. Sleep Mode with Cyclic Wake-Up The Cyclic Wake-Up Mode is a special operating mode of the Sleep Mode. The transition to Cyclic Wake-Up Mode is performed by first setting the corresponding bits in the mode control register followed by the Sleep and Stop Mode command. In addition to the cyclic wake-up behavior (wake-up after a programmable time period), asynchronous wake events via the activated sources (PWM interface and/or MON) are available, as in normal Sleep Mode. When using Sleep Mode with cyclic wake-up the voltage regulator is switched off and started again with the wake. A limited number of registers is buffered during sleep, and can be used by SW e.g. for counting sleep/wake cycles. MCU Slow Down Mode In MCU Slow Down Mode the MCU frequency is reduced for saving power during operation. PWM communication is still possible. LS MOSFET can be activated. Wake-Up Source Prioritization All wake-up sources have the same priority. In order to handle the asynchronous nature of the wake-up sources, the first wake-up signal will initiate the wake-up sequence. Nevertheless all wake-up sources are latched in order to provide all wake-up events to the application software. The software can clear the wake-up source flags. This is to ensure that no wake-up event is lost. As default wake-up source, the MON input is activated after power-on reset only. Additionally, the device is in Cyclic Wake-Up Mode with the max. configurable dead time setting. The following table shows the possible power mode configurations including the Stop Mode. Table 3 Power Mode Configurations Module/Function Active Mode Stop Mode Sleep Mode Comment VDDEXT ON/OFF ON (no dynamic load)/OFF OFF - Bridge Driver ON/OFF OFF OFF PWM TRx ON/OFF wake-up only/ OFF wake-up only/ OFF - VS sense ON/OFF brownout detection brownout detection POR on VS brownout det. done in PCU GPIO 5V (wake-up) n.a. disabled/static OFF - GPIO 5V (active) ON ON OFF - WDT1 ON OFF OFF - CYCLIC WAKE n.a. cyclic wake-up/ cyclic sense/OFF cyclic wake-up/ OFF - Measurement ON1) OFF OFF - 2) MCU ON/slowdown/STOP STOP OFF - CLOCK GEN (MC) ON OFF OFF - Data Sheet 16 Rev. 1.0, 2017-03-03 TLE9871QXA20 Modes of Operation Table 3 Power Mode Configurations (cont'd) Module/Function Active Mode Stop Mode Sleep Mode Comment LP_CLK (18 MHz) ON OFF OFF WDT1 LP_CLK2 (100 kHz) ON/OFF ON/OFF ON/OFF for cyclic wake-up 1) May not be switched off due to safety reasons 2) MC PLL clock disabled, MC supply reduced to 1.1 V Wake-Up Levels and Transitions The wake-up can be triggered by rising, falling or both signal edges for the monitor input, by PWM interface or by cyclic wake-up. Data Sheet 17 Rev. 1.0, 2017-03-03 TLE9871QXA20 Power Management Unit (PMU) 5 Power Management Unit (PMU) 5.1 Features * * * * * * System modes control (startup, sleep, stop and active) Power management (cyclic wake-up) Control of system voltage regulators with diagnosis (overload, short, overvoltage) Fail safe mode detection and operation in case of system errors (watchdog fail) Wake-up sources configuration and management (PWM Interface, MON, GPIOs) System error logging 5.2 Introduction The power management unit is responsible for generating all required voltage supplies for the embedded MCU (VDDC, VDDP) and the external supply (VDDEXT). The power management unit is designed to ensure fail-safe behavior of the system IC by controlling all system modes including the corresponding transitions. Additionally, the PMU provides well defined sequences for the system mode transitions and generates hierarchical reset priorities. The reset priorities control the reset behavior of all system functionalities especially the reset behavior of the embedded MCU. All these functions are controlled by a state machine. The system master functionality of the PMU make use of an independent logic supply and system clock. For this reason, the PMU has an "Internal logic supply and system clock" module which works independently of the MCU clock. Data Sheet 18 Rev. 1.0, 2017-03-03 TLE9871QXA20 Power Management Unit (PMU) 5.2.1 Block Diagram The following figure shows the structure of the Power Management Unit. Table 4 describes the submodules in more detail. VS Power Down Supply e.g. for WDT 1 e.g. for cyclic wake and sense I N T E R N A L LP_CLK Peripherals LP_CLK2 B U S PMU-PCU MON LIN P0.0...P0.4 P1.0...P1.4 VDDP Power Supply Generation Unit (PGU) VDDC LDO for External Supply VDDEXT VDDEXT PMU-SFR PMU-CMU PMU-WMU PMU-RMU PMU-Control Power Management Unit Power_Management_ 7x.vsd Figure 3 Power Management Unit Block Diagram Table 4 Description of PMU Submodules Mod. Name Modules Functions Power Down Supply Independent supply voltage generation for PMU This supply is dedicated to the PMU to ensure an independent operation from generated power supplies (VDDP, VDDC). LP_CLK (= 18 MHz) - Clock source for all PMU submodules - Backup clock source for System - Clock source for WDT1 This ultra low power oscillator generates the clock for the PMU. This clock is also used as backup clock for the system in case of PLL Clock failure and as an independent clock source for WDT1. LP_CLK2 (= 100 kHz) Clock source for PMU This ultra low power oscillator generates the clock for the PMU in Stop Mode and in the cyclic modes. Peripherals Peripheral blocks of PMU These blocks include the analog peripherals to ensure a stable and fail-safe PMU startup and operation (bandgap, bias). Data Sheet 19 Rev. 1.0, 2017-03-03 TLE9871QXA20 Power Management Unit (PMU) Table 4 Description of PMU Submodules (cont'd) Mod. Name Modules Functions Power Supply Generation Unit (PGU) Voltage regulators for VDDP and VDDC This block includes the voltage regulators for the pad supply (VDDP) and the core supply (VDDC). VDDEXT Voltage regulator for VDDEXT to supply external modules (e.g. sensors) This voltage regulator is a dedicated supply for external modules and can also be used for cyclic sense operations (e.g. with hall sensor). PMU-SFR All Extended Special Function registers that are relevant to the PMU. This module contains all registers needed to control and monitor the PMU. PMU-PCU Power Control Unit of the PMU This block is responsible for controlling all power related actions within the PGU Module. It also contains all regulator related diagnostics such as undervoltage and overvoltage detection as well as overcurrent and short circuit diagnostics. PMU-WMU Wake-Up Management Unit of the PMU This block is responsible for controlling all wake-up related actions within the PMU Module. PMU-CMU Cyclic Management Unit of the PMU This block is responsible for controlling all actions in cyclic mode. PMU-RMU Reset Management Unit of the PMU This block generates resets triggered by the PMU such as undervoltage or short circuit reset, and passes all resets to the relevant modules and their register. Data Sheet 20 Rev. 1.0, 2017-03-03 TLE9871QXA20 Power Management Unit (PMU) 5.2.2 PMU Modes Overview The following state diagram shows the available modes of the device. V S > 4V and VS ramp up or VS < 3V and VS ramp down LIN-wake or MON-wake or cyclic -wake start-up VDDC =stable and error_supp<5 VDDC / VDDP = fail (short circuit) AE error_supp ++ error_supp=5 sleep Sleep command (from MCU) or WDT1_SEQ_FAIL = 1 (AE error_wdt = 5) or VDDC / VDDP = overload active LIN-wake or MON-wake or GPIO-wake or cyclic _wake or PMU_PIN = 1 or SUP_TMOUT = 1 PMU_PIN = 1 or PMU_SOFT = 1 or (PMU_Ext_WDT = 1 and WDT1_SEQ_FAIL = 0 AE error_wdt ++) Stop command (from MCU) stop cyclic -sense Figure 4 Data Sheet Power Management Unit System Modes 21 Rev. 1.0, 2017-03-03 TLE9871QXA20 Power Management Unit (PMU) 5.3 Power Supply Generation Unit (PGU) 5.3.1 Voltage Regulator 5.0V (VDDP) This module represents the 5 V voltage regulator, which provides the pad supply for the parallel port pins and other 5 V analog functions (e.g. PWM Interface). Features * * * * * * * * 5 V low-drop voltage regulator Overcurrent monitoring and shutdown with MCU signaling (interrupt) Overvoltage monitoring with MCU signaling (interrupt) Undervoltage monitoring with MCU signaling (interrupt) Undervoltage monitoring with reset (Undervoltage Reset, VDDPUV) Pre-Regulator for VDDC Regulator GPIO Supply Pull Down Current Source at the output for Sleep Mode only (typ. 5 mA) The output capacitor CVDDP is mandatory to ensure proper regulator functionality. VDDP Regulator VS A VPRE VDDP CVDDP V GND (Pin 39) I 5V LDO Figure 5 Data Sheet PMU_5V_OVERLOAD PMU_5V_OVERVOLT LDO Supervision Module Block Diagram of VDDP Voltage Regulator 22 Rev. 1.0, 2017-03-03 TLE9871QXA20 Power Management Unit (PMU) 5.3.2 Voltage Regulator 1.5V (VDDC) This module represents the 1.5 V voltage regulator, which provides the supply for the microcontroller core, the digital peripherals and other internal analog 1.5 V functions (e.g. ADC2) of the chip. To further reduce the current consumption of the MCU during Stop Mode the output voltage can be lowered to 1.1 V. Features * * * * * * 1.5 V low-drop voltage regulator Overcurrent monitoring and shutdown with MCU signaling (interrupt) Overvoltage monitoring with MCU signaling (interrupt) Undervoltage monitoring with MCU signaling (interrupt) Undervoltage monitoring with reset Pull Down Current Source at the output for Sleep Mode only (typ. 100 A) The output capacitor CVDDC is mandatory to ensure a proper regulator functionality. VDDC Regulator VDDP (5V) VDDC (1.5V) A V CVDDP CVDDC GND (Pin 39) I 1.5V LDO PMU_1V5_OVERVOLT PMU_1V5_OVERLOAD LDO Supervision Figure 6 Data Sheet Module Block Diagram of VDDC Voltage Regulator 23 Rev. 1.0, 2017-03-03 TLE9871QXA20 Power Management Unit (PMU) 5.3.3 External Voltage Regulator 5.0V (VDDEXT) This module represents the 5 V voltage regulator, which serves as a supply for external circuits. It can be used e.g. to supply an external sensor, LEDs or potentiometers. Features * * * * * * * Switchable +5 V, low-drop voltage regulator Switch-on overcurrent blanking time in order to drive small capacitive loads Overcurrent monitoring and shutdown with MCU signaling (interrupt) Overvoltage monitoring with MCU signaling (interrupt) Undervoltage monitoring with MCU signaling (interrupt) Pull Down current source at the output for Sleep Mode only (typ. 100 A) Cyclic sense option together with GPIOs The output capacitor CVDDEXT is mandatory to ensure a proper regulator functionality. VDDEXT Regulator VS A VPRE VDDEXT CVDDEXT V GND (Pin 39) I 5V LDO Figure 7 Data Sheet VDDEXT_OVERLOAD VDDEXT_OVERVOLT VDDEXT_SHORT LDO Supervision Module Block Diagram of External Voltage Regulator 24 Rev. 1.0, 2017-03-03 TLE9871QXA20 System Control Unit - Digital Modules (SCU-DM) 6 System Control Unit - Digital Modules (SCU-DM) 6.1 Features * * * * * * Flexible clock configuration features Reset management of all system resets System modes control for all power modes (active, power down, sleep) Interrupt enabling for many system peripherals General purpose input output control Debug mode control of system peripherals 6.2 Introduction The System Control Unit (SCU) supports all central control tasks in the TLE9871QXA20. The SCU is made up of the following sub-modules: * * * * * * * * * * Clock System and Control Reset Control Power Management Interrupt Management General Port Control Flexible Peripheral Management Module Suspend Control Watchdog Timer Error Detection and Correction in Data Memory Miscellaneous Control Data Sheet 25 Rev. 1.0, 2017-03-03 TLE9871QXA20 System Control Unit - Digital Modules (SCU-DM) 6.2.1 Block Diagram On signals to digital peripherals; status signals from digital peripherals AHB PMCU WDT CGU XTAL1 XTAL2 I N T E R N A L OSC_HP fOSC PLL LP_CLK fSYS f PCLK fMI_CLK fTFILT _CLK fPLL CG fSYS NMI ICU INTISR <9:0> B U S PMU_1V5DidPOR PMU_PIN PMU_ExtWDT PMU_IntWDT PMU_SOFT PMU_Wake RESET_TYPE_3 RESET_TYPE_4 RCU P0_POCONy.PDMx P1_POCONy.PDMx Port Control MISC Control MODPISELx System Control Unit -Digital Modules Figure 8 System Control Unit - Digital Modules Block Diagram AHB (Advanced High-Performance Bus) PMCU (Power Module Control Unit) WDT (Watchdog Timer in SCU-DM) * fSYS System clock CGU (Clock Generation Unit) * * fSYS System clock fPCLK Peripheral clock Data Sheet 26 Rev. 1.0, 2017-03-03 TLE9871QXA20 System Control Unit - Digital Modules (SCU-DM) * * * fMI_CLK Measurement interface clock fTFILT_CLK Analog module filter clock LP_CLK Clock source for all PMU submodules and WDT1 ICU (Interrupt Control Unit) * * NMI (Non-Maskable Interrupt) INTISR<15,13:4,1,0> External interrupt signals RCU (Reset Control Unit) * * * * * * * * PMU_1V5DidPOR Undervoltage reset of power down supply PMU_PIN Reset generated by reset pin PMU_ExtWDT WDT1 reset PMU_IntWDT WDT (SCU) reset PMU_SOFT Software reset PMU_Wake Sleep Mode/Stop Mode exit with reset RESET_TYPE_3 Peripheral reset (contains all resets) RESET_TYPE_4 Peripheral reset (without SOFT and WDT reset) Port Control * * P0_POCONy.PDMx driver strength control P1_POCONy.PDMx driver strength control MISC Control * MODPISELx Mode selection registers for UART (source section) and Timer (trigger or count selection) 6.3 Clock Generation Unit The Clock Generation Unit (CGU) enables a flexible clock generation for TLE9871QXA20. During user program execution, the frequency can be modified to optimize the performance/power consumption ratio, allowing power consumption to be adapted to the actual application state. The CGU in the TLE9871QXA20 consists of one oscillator circuit (OSC_HP), a Phase-Locked Loop (PLL) module with an internal oscillator (OSC_PLL), and a Clock Control Unit (CCU). The CGU can convert a low-frequency input/external clock signal to a high-frequency internal clock. The system clock fSYS is generated from of the following selectable clocks: * * * PLL clock output fPLL Direct clock from oscillator OSC_HP fOSC Low precision clock fLP_CLK (HW-enabled for startup after reset and during power-down wake-up sequence) Data Sheet 27 Rev. 1.0, 2017-03-03 TLE9871QXA20 System Control Unit - Digital Modules (SCU-DM) CGU PLLCON OSC_CON HPOSCCON PLL OSC_HP f XTAL1 SYSCON0 PLL CMCON XTAL2 f OSC CCU fSYS f LP_CLK LP_CLK LP_CLK PMU CGU_block Figure 9 Clock Generation Unit Block Diagram The following sections describe the different parts of the CGU. 6.3.1 Low Precision Clock The clock source LP_CLK is a low-precision RC oscillator (LP-OSC) with a nominal frequency of 18 MHz that is enabled by hardware as an independent clock source for the TLE9871QXA20 startup after reset and during the power-down wake-up sequence. fLP_CLK is not user configurable. 6.3.2 High Precision Oscillator Circuit (OSC_HP) The high precision oscillator circuit, designed to work with both an external crystal oscillator or an external stable clock source, consists of an inverting amplifier with XTAL1 as the input, and XTAL2 as the output. Figure 10 shows the recommended external circuitry for both operating modes, External Crystal Mode and External Input Clock Mode. 6.3.2.1 External Input Clock Mode When supplying the clock signal directly, not using an external crystal and bypassing the oscillator, the input frequency needs to be equal or greater than 4 MHz if the PLL VCO part is used. When using an external clock signal it must be connected to XTAL1. XTAL2 is left open (unconnected). 6.3.2.2 External Crystal Mode When using an external crystal, its frequency can be within the range of 4 MHz to 25 MHz. An external oscillator load circuitry must be used, connected to both pins, XTAL1 and XTAL2. It normally consists of the two load capacitances C1 and C2. A series damping resistor could be required for some crystals. The exact values and the corresponding operating ranges depend on the crystal and have to be determined and optimized in cooperation with the crystal vendor using the negative resistance method. The following load cap values can be used as starting point for the evaluation: Data Sheet 28 Rev. 1.0, 2017-03-03 TLE9871QXA20 System Control Unit - Digital Modules (SCU-DM) Table 5 External CAP Capacitors Fundamental Mode Crystal Frequency (approx., MHz) Load Caps C1, C2 (pF) 4 33 8 18 12 12 16 10 20 10 25 8 External Crystal Mode External Input Clock Mode VDDP VDDP Fundamental Mode Crystal External Clock Signal XTAL1 4 - 25 MHz OSC_HP fOSC XTAL2 C1 f OSC C2 VSS Data Sheet OSC_HP XTAL2 VSS VSS = GND = PIN 39 Figure 10 XTAL1 ext_Osc.vsd TLE9871QXA20 External Circuitry for the OSC_HP 29 Rev. 1.0, 2017-03-03 TLE9871QXA20 System Control Unit - Power Modules (SCU-PM) 7 System Control Unit - Power Modules (SCU-PM) 7.1 Features * * * * Clock Watchdog Unit (CWU): supervision of all clocks with NMI signaling relevant to power modules Interrupt Control Unit (ICU): all interrupt flags and status flags with system relevance Power Control Unit (PCU): takes over control when device enters and exits Sleep and Stop Mode External Watchdog (WDT1): independent system watchdog for monitoring system activity 7.2 Introduction 7.2.1 Block Diagram The System Control Unit of the power modules consists of the sub-modules in the figure shown below: On signals to analog peripherals; status signals from analog peripherals AHB I N T E R N A L PCU WDT1 fsys MI_CLK LP_CLK PREWARN_SUP_NMI B U S CWU TFILT_CLK ICU PREWARN_SUP_INT INT<n:0> System Control Unit -Power Modules Figure 11 Block diagram of System Control Unit - Power Modules AHB (Advanced High-Performance Bus) CWU (Clock Watchdog Unit) * * * fsys system frequency: PLL output MI_CLK measurement interface clock (analog clock): derived from fsys using division factors 1/2/3/4 TFILT_CLK clock used for digital filters: derived from fsys using configurable division factors Data Sheet 30 Rev. 1.0, 2017-03-03 TLE9871QXA20 System Control Unit - Power Modules (SCU-PM) WDT1 (System Watchdog) * LP_CLK clock source for all PMU submodules and WDT1 ICU (Interrupt Control Unit) * * * PREWARN_SUP_NMI supply prewarning NMI request PREWARN_SUP_INT supply prewarning interrupt grouping of peripheral interrupts for external interupt nodes: - grouping single peripheral interrupts for interrupt node INT<2> (Measurement Unit (MU)) - grouping single peripheral interrupts for interrupt node INT<3> (ADC1-VAREF) - grouping single peripheral interrupts for interrupt node INT<10> (UART1-PWM Interface) - grouping single peripheral interrupts for interrupt node INT<14> (Bridge Driver) Data Sheet 31 Rev. 1.0, 2017-03-03 TLE9871QXA20 ARM Cortex-M3 Core 8 ARM Cortex-M3 Core 8.1 Features The key features of the Cortex-M3 implemented are listed below. Processor Core; a low gate count core, with low latency interrupt processing: * * * * * * * * * A subset of the Thumb(R)-2 Instruction Set Banked stack pointer (SP) only 32-bit hardware divide instructions, SDIV and UDIV (Thumb-2 instructions) Handler and Thread Modes Thumb and debug states Interruptible-continued instructions LDM/STM, Push/Pop for low interrupt latency Automatic processor state saving and restoration for low latency Interrupt Service Routine (ISR) entry and exit ARM architecture v7-M Style BE8/LE support ARMv6 unaligned accesses Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to achieve low latency interrupt processing: * * * * * * Interrupts, configurable from 1 to 16 Bits of priority (4) Dynamic reprioritization of interrupts Priority grouping. This enables selection of preemptive interrupt levels and non-preemptive interrupt levels Support for tail-chaining and late arrival of interrupts. This enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts. Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead Bus interfaces * * * Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, DCode, and System bus interface Memory access alignment Write buffer for buffering of write data Data Sheet 32 Rev. 1.0, 2017-03-03 TLE9871QXA20 ARM Cortex-M3 Core 8.2 Introduction The ARM Cortex-M3 processor is a leading 32-bit processor and provides a high-performance and cost-optimized platform for a broad range of applications including microcontrollers, automotive body systems and industrial control systems. Like the other Cortex family processors, the Cortex-M3 processor implements the Thumb(R)-2 instruction set architecture. With the optimized feature set the Cortex-M3 delivers 32-bit performance in an application space that is usually associated with 8- and 16-bit microcontrollers. 8.2.1 Block Diagram Figure 12 shows the functional blocks of the Cortex-M3. Cortex-M3 Processor Interrupt and Power Control Nested Vectored Interrupt Controller (NVIC) Cortex-M3 Processor Core Serial-Wire (SW-DP) AHB Access Port (AHB-AP) Serial-Wire Debug Interface ICode AHB-Lite Instruction Interface Bus Matrix DCode AHB-Lite Data Interface System Bus ICode PBA0 PBA1 Cortex_ M3 _Block_diagram .vsd Figure 12 Data Sheet Cortex-M3 Block Diagram 33 Rev. 1.0, 2017-03-03 TLE9871QXA20 DMA Controller 9 DMA Controller Figure 13 shows the Top Level Block Diagram of the TLE9871QXA20. The bus matrix allows the DMA to access the PBA0, PBA1 and RAM. 9.1 Features The principal features of the DMA Controller are that: * * * * * * * * * * * * * * it is compatible with AHB-Lite for the DMA transfers it is compatible with APB for programming the registers it has a single AHB-Lite master for transferring data using a 32-bit address bus and 32-bit data bus it supports 13 DMA channels each DMA channel has dedicated handshake signals each DMA channel has a programmable priority level each priority level arbitrates using a fixed priority that is determined by the DMA channel number. The DMA also supports multiple transfer types: - memory-to-memory - memory-to-peripheral - peripheral-to-memory it supports multiple DMA cycle types it supports multiple DMA transfer data widths each DMA channel can access a primary, and alternate, channel control data structure all the channel control data is stored in system memory (RAM) in little-endian format it performs all DMA transfers using the single AHB-Lite burst type. The destination data width is equal to the source data width. the number of transfers in a single DMA cycle can be programmed from 1 to 1024 the transfer address increment can be greater than the data width Data Sheet 34 Rev. 1.0, 2017-03-03 TLE9871QXA20 DMA Controller 9.2 Introduction Please also refer to Chapter 9.3, Functional Description. 9.2.1 Block Diagram SSC1 Timer3 DMA requests ADC1 DMA requests DMA requests DMA Controller Bus Matrix M AHB lite S M AHB lite PBA1 S AHB2APB APB Interface interrupts PBA0 M AHB lite M AHB lite S SCU_DM RAM S ARM Core interrupts Figure 13 Data Sheet M AHB lite S M AHB lite S M AHB lite S DMA Controller Top Level Block Diagram 35 Rev. 1.0, 2017-03-03 TLE9871QXA20 DMA Controller 9.3 Functional Description 9.3.1 DMA Mode Overview The DMA controller implements the following 13 hardware DMA requests: * * * * * * * * * * * * * ADC1 complete sequence 1 done: DMA transfer is requested on completion of the ADC1 channel conversion sequence. ADC1 exceptional sequence 2 (ESM) done: DMA transfer is requested on completion of the ADC1 conversion sequence triggered by an exceptional measurement request. SSC1/2 transmit byte: DMA transfer is requested upon the completion of data transmission via SSC1/2 SSC1/2: receive byte: DMA transfer is requested upon the completion of data reception via SSC1/2. ADC1 channel 0 conversion done: DMA transfer is requested on completion of the ADC1 channel 0 conversion. ADC1 channel 1 conversion done: DMA transfer is requested on completion of the ADC1 channel 1 conversion. ADC1 channel 2 conversion done: DMA transfer is requested on completion of the ADC1 channel 2 conversion. ADC1 channel 3 conversion done: DMA transfer is requested on completion of the ADC1 channel 3 conversion. ADC1 channel 4 conversion done: DMA transfer is requested on completion of the ADC1 channel 4 conversion. ADC1 channel 5 conversion done: DMA transfer is requested on completion of the ADC1 channel 5 conversion. ADC1 channel 6 conversion done: DMA transfer is requested on completion of the ADC1 channel 6 conversion. ADC1 channel 7 conversion done: DMA transfer is requested on completion of the ADC1 channel 7 conversion. Timer3 ccu6_int: DMA transfer is requested following a timer trigger. Data Sheet 36 Rev. 1.0, 2017-03-03 TLE9871QXA20 Address Space Organization 10 Address Space Organization The TLE9871QXA20 manipulates operands in the following memory spaces: * * * * 36 KByte of Flash memory in code space 32 KByte Boot ROM memory in code space (used for boot code and IP storage) 3 KByte RAM memory in code space and data space (RAM can be read/written as program memory or external data memory) Special function registers (SFRs) in peripheral space The figure below shows the detailed address alignment of TLE9871QXA20: 00000000H Reserved (BootROM) 00008000H / 10FFFFFFH Flash, 36K 11000000H / 11008FFFH Reserved 11009000H / 17FFFFFFH SRAM, 3K 18000000H / 18000BFFH Reserved 18000C00H / 3FFFFFFFH PBA0 40000000H / 47FFFFFFH PBA1 48000000H / 5FFFFFFFH Reserved 60000000H / DFFFFFFFH Private Peripheral Bus E0000000H / E00FFFFFH Reserved FFFFFFFFH Figure 14 Data Sheet TLE9871QXA20 Memory Map 37 Rev. 1.0, 2017-03-03 TLE9871QXA20 Memory Control Unit 11 Memory Control Unit 11.1 Features * * * * Handles all system memories and their interaction with the CPU Memory protection functions for all system memories (D-Flash, P-Flash, RAM) Address management with access violation detection including reporting Linear address range for all memories (no paging) 11.2 Introduction 11.2.1 Block Diagram The Memory Control Unit (MCU) is divided in the following sub-modules: * * * * * NVM memory module (embedded Flash Memory) RAM memory module BootROM memory module Memory Protection Unit (MPU) module Peripheral Bridge PBA0 Data Sheet 38 Rev. 1.0, 2017-03-03 TLE9871QXA20 Memory Control Unit NVM RAM S0 S1 BROM PBA0 S2 S3 ROM Code/ Data RAM Code/ Data N VM Code/ Data Memory Protection Unit Sx: Bus Slave Mx: Bus Master M0 M1 M2 M3 Bus Matrix MCU_Block_Diagram_overview.vsd Figure 15 Data Sheet MCU Block View 39 Rev. 1.0, 2017-03-03 TLE9871QXA20 Memory Control Unit 11.3 NVM Module (Flash Memory) The Flash Memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data. Features * * * * * * * * * * * In-system programming via PWM Interface (Flash Mode) and SWD Error Correction Code (ECC) for detection of single-bit and double-bit errors and dynamic correction of single Bit errors. Interrupts and signals double-bit error by NMI Program width of 128 byte (page) Minimum erase width of 128 bytes (page) Integrated hardware support for EEPROM emulation 8 byte read access Physical read access time: 75 ns Code read access acceleration integrated; read buffer and automatic pre-fetch Page program time: 3 ms Page erase (128 bytes) and sector erase (4K bytes) time: 4ms Note: The user has to ensure that no flash operations which change the content of the flash get interrupted at any time. The clock for the NVM is supplied with the system frequency fsys. Integrated firmware routines are provided to erase NVM, and other operations including EEPROM emulation are provided as well. Data Sheet 40 Rev. 1.0, 2017-03-03 TLE9871QXA20 Interrupt System 12 Interrupt System 12.1 Features * * * Up to 16 interrupt nodes for on-chip peripherals Up to 8 NMI nodes for critical system events Maximum flexibility for all 16 interrupt nodes 12.2 Introduction Before enabling an interrupt, all corresponding interrupt status flags should be cleared. 12.2.1 Overview The TLE9871QXA20 supports 16 interrupt vectors with 16 priority levels. Fifteen of these interrupt vectors are assigned to the on-chip peripherals: GPT12, SSC, CCU6, DMA, Bridge Driver and A/D Converter are each assigned to one dedicated interrupt vector; while UART1 and Timer2 or UART2, External Interrupt 2 and Timer21 share interrupt vectors. Two vectors are dedicated for External Interrupt 0 and 1. Table 6 Interrupt Vector Table Service Request Node ID Description GPT12 0/1 GPT interrupt (T2-T6, CAPIN) MU- ADC8/T3 2 Measurement Unit, VBG, Timer3, BEMF ADC1 3 ADC1 interrupt / VREF5V Overload / VREF5V OV/UV, 10-bit ADC CCU0 4 CCU6 node 0 interrupt CCU1 5 CCU6 node 1 interrupt CCU2 6 CCU6 node 2 interrupt CCU3 7 CCU6 node 3 interrupt SSC1 8 SSC1 interrupt (receive, transmit, error) SSC2 9 SSC2 interrupt (receive, transmit, error) UART1 10 UART1 interrupt (receive, transmit), Timer2, PWM-Interface UART2 11 UART2 interrupt (receive, transmit), Timer21, External interrupt (EINT2) EXINT0 12 External interrupt (EINT0), MON EXINT1 13 External interrupt (EINT1) BDRV/CP 14 Bridge Driver / Charge Pump DMA 15 DMA Controller Table 7 NMI Interrupt Table Service Request Node Description Watchdog Timer NMI NMI Watchdog Timer overflow PLL NMI NMI PLL Loss-of-Lock NVM Operation Complete NMI NMI NVM Operation Complete Overtemperature NMI NMI System Overtemperature Data Sheet 41 Rev. 1.0, 2017-03-03 TLE9871QXA20 Interrupt System Table 7 NMI Interrupt Table Service Request Node Description Oscillator Watchdog NMI NMI Oscillator Watchdog / MI_CLK Watchdog Timer Overflow NVM Map Error NMI NMI NVM Map Error ECC Error NMI NMI RAM / NVM Uncorrectable ECC Error Supply Prewarning NMI NMI Data Sheet Supply Prewarning 42 Rev. 1.0, 2017-03-03 TLE9871QXA20 Watchdog Timer (WDT1) 13 Watchdog Timer (WDT1) 13.1 Features There are two watchdog timers in the system. The Watchdog Timer (WDT) within the System Control Unit - Digital Modules (see SCU_DM) and the Watchdog Timer (WDT1) located within the System Control Unit - Power Modules (see SCU_PM). The Watchdog Timer WDT1 is described in this section. In Active Mode, the WDT1 acts as a windowed watchdog timer, which provides a highly reliable and safe way to recover from software or hardware failures. The WDT1 is always enabled in Active Mode. In Sleep Mode, Low Power Mode and SWD Mode the WDT1 is automatically disabled. Functional Features * * * * * Windowed Watchdog Timer with programmable timing in Active Mode Long open window (typ. 80ms) after power-up, reset, wake-up Short open window (typ. 30ms) to facilitate Flash programming Disabled during debugging Safety shutdown to Sleep Mode after 5 missed WDT1 services Data Sheet 43 Rev. 1.0, 2017-03-03 TLE9871QXA20 Watchdog Timer (WDT1) 13.2 Introduction The behavior of the Watchdog Timer in Active Mode is illustrated in Figure 16. Power-up Reset RESET Timeout always RESET RESET Timeout or Trigger in closed window Timeout Trigger SOW Maximum number of count_SOW Long Open Window Trigger & count_SOW = 0 Normal windowed" operation Trigger & count_SOW = 0 Figure 16 Data Sheet Trigger SOW & count_SOW++ Trigger & count_SOW = 0 Short open window & SOW Trigger SOW & count_SOW++ Watchdog Timer Behavior 44 Rev. 1.0, 2017-03-03 TLE9871QXA20 GPIO Ports and Peripheral I/O 14 GPIO Ports and Peripheral I/O The TLE9871QXA20 has 15 port pins organized into three parallel ports: Port 0 (P0), Port 1 (P1) and Port 2 (P2). Each port pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. P0 and P1 are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip peripherals. When configured as an output, the open drain mode can be selected. On Port 2 (P2) analog inputs are shared with general purpose input. 14.1 Features Bidirectional Port Features (P0, P1) * * * * * * Configurable pin direction Configurable pull-up/pull-down devices Configurable open drain mode Configurable drive strength Transfer of data through digital inputs and outputs (general purpose I/O) Alternate input/output for on-chip peripherals Analog Port Features (P2) * * * Configurable pull-up/pull-down devices Transfer of data through digital inputs Alternate inputs for on-chip peripherals 14.2 Introduction 14.2.1 Port 0 and Port 1 Figure 17 shows the block diagram of an TLE9871QXA20 bidirectional port pin. Each port pin is equipped with a number of control and data bits, thus enabling very flexible usage of the pin. By defining the contents of the control register, each individual pin can be configured as an input or an output. The user can also configure each pin as an open drain pin with or without internal pull-up/pull-down device. Each bidirectional port pin can be configured for input or output operation. Switching between input and output mode is accomplished through the register Px_DIR (x = 0 or 1), which enables or disables the output and input drivers. A port pin can only be configured as either input or output mode at any one time. In input mode (default after reset), the output driver is switched off (high-impedance). The voltage level present at the port pin is translated into a logic 0 or 1 via a Schmitt trigger device and can be read via the register Px_DATA. In output mode, the output driver is activated and drives the value supplied through the multiplexer to the port pin. In the output driver, each port line can be switched to open drain mode or normal mode (push-pull mode) via the register Px_OD. The output multiplexer in front of the output driver enables the port output function to be used for different purposes. If the pin is used for general purpose output, the multiplexer is switched by software to the data register Px_DATA. Software can set or clear the bit in Px_DATA and therefore directly influence the state of the port pin. If an on-chip peripheral uses the pin for output signals, alternate output lines (AltDataOut) can be switched via the multiplexer to the output driver circuitry. Selection of the alternate output function is defined in registers Px_ALTSEL0 and Px_ALTSEL1. When a port pin is used as an alternate function, its direction must be set accordingly in the register Px_DIR. Data Sheet 45 Rev. 1.0, 2017-03-03 TLE9871QXA20 GPIO Ports and Peripheral I/O Each pin can also be programmed to activate an internal weak pull-up or pull-down device. Register Px_PUDSEL selects whether a pull-up or the pull-down device is activated while register Px_PUDEN enables or disables the pull device. PUDSEL Pull-up / Pull-down Select Register Pull-up / Pull-down Control Logic PUDEN Pull-up / Pull-down Enable Register TCCR Temperature Compensation Control Register I N T E R N A L B U S Px_POCONy Port Output Driver Control Registers OD Open Drain Control Register DIR Direction Register ALTSEL0 Alternate Select Register 0 ALTSEL1 Alternate Select Register 1 Pull Device AltDataOut 3 11 AltDataOut 2 10 AltDataOut 1 Output Driver 01 Out Px_DATA Data Register In 00 Input Driver AltDataIn Schmitt Trigger Figure 17 Data Sheet Pad General Structure of Bidirectional Port (P0, P1) 46 Rev. 1.0, 2017-03-03 TLE9871QXA20 GPIO Ports and Peripheral I/O 14.2.2 Port 2 Figure 18 shows the structure of an input-only port pin. Each P2 pin can only function in input mode. Register P2_DIR is provided to enable or disable the input driver. When the input driver is enabled, the actual voltage level present at the port pin is translated into a logic 0 or 1 via a Schmitt trigger device and can be read via register P2_DATA. Each pin can also be programmed to activate an internal weak pull-up or pull-down device. Register P2_PUDSEL selects whether a pull-up or the pull-down device is activated while register P2_PUDEN enables or disables the pull device. The analog input (AnalogIn) bypasses the digital circuitry and Schmitt trigger device for direct feed-through to the ADC input channels. I N T E R N A L PUDSEL Pull-up / Pull-down Select Register Pull-up / Pull-down Control Logic PUDEN Pull-up / Pull-down Enable Register Pull Device B U S DATA Data Register Input Driver In Schmitt Trigger Pad AltDataIn AnalogIn Figure 18 Data Sheet General Structure of Input Port (P2) 47 Rev. 1.0, 2017-03-03 TLE9871QXA20 GPIO Ports and Peripheral I/O 14.3 TLE9871QXA20 Port Module 14.3.1 Port 0 14.3.1.1 Port 0 Functions Table 8 Port 0 Input/Output Functions Port Pin Input/Output Select P0.0 Input GPI P0_DATA.P0 INP1 SWCLK / TCK_0 SW INP2 T12HR_0 CCU6 INP3 T4INA GPT12T4 INP4 T2_0 Timer 2 INP5 - - INP6 EXINT2_3 SCU GPO P0_DATA.P0 ALT1 T3OUT GPT12T3 ALT2 EXF21_0 Timer 21 ALT3 RXDO_2 UART2 GPI P0_DATA.P1 INP2 T13HR_0 CCU6 INP3 TxD1 PWM_TxD INP4 CAPINA GPT12CAP INP5 T21_0 Timer 21 INP6 T4INC GPT12T4 INP7 MRST_1_2 SSC1 INP8 EXINT0_2 SCU GPO P0_DATA.P1 ALT1 TxD1 UART1 / PWM_TxD ALT2 - - ALT3 T6OUT GPT12T6 Output P0.1 Input Output Data Sheet Connected Signal(s) 48 From/to Module Rev. 1.0, 2017-03-03 TLE9871QXA20 GPIO Ports and Peripheral I/O Table 8 Port 0 Input/Output Functions (cont'd) Port Pin Input/Output Select Connected Signal(s) P0.2 Input GPI P0_DATA.P2 INP1 CCPOS2_1 CCU6 INP2 T2EUDA GPT12T2 INP3 MTSR_1 SSC1 INP4 T21EX_0 Timer 21 INP5 T6INA GPT12T6 GPO P0_DATA.P2 - ALT1 COUT60_0 CCU6 ALT2 MTSR_1 SSC1 ALT3 EXF2_0 Timer 2 GPI P0_DATA.P3 INP1 SCK_1 SSC1 INP2 CAPINB GPT12 INP3 T5INA GPT12T5 INP4 T4EUDA GPT12T4 INP5 CCPOS0_1 CCU6 GPO P0_DATA.P3 ALT1 SCK_1 SSC1 ALT2 EXF21_2 Timer 21 ALT3 T6OUT GPT12T6 Output P0.3 Input Output P0.4 Input Output Data Sheet From/to Module GPI P0_DATA.P4 INP1 MRST_1_0 SSC1 INP2 CC60_0 CCU6 INP3 T21_2 Timer 21 INP4 EXINT2_2 SCU INP5 T3EUDA GPT12T3 INP6 CCPOS1_1 CCU6 GPO P0_DATA.P4 ALT1 MRST_1_0 SSC1 ALT2 CC60_0 CCU6 ALT3 CLKOUT_0 SCU 49 Rev. 1.0, 2017-03-03 TLE9871QXA20 GPIO Ports and Peripheral I/O 14.3.2 Port 1 14.3.2.1 Port 1 Functions Table 9 Port 1 Input / Output Functions Port Pin Input/Output Select Connected Signal(s) P1.0 Input GPI P1_DATA.P0 INP1 T3INC GPT12T3 INP2 T4EUDB GPT12T4 INP3 CC61_0 CCU6 INP4 SCK_2 SSC2 INP5 EXINT1_2 SCU GPO P1_DATA.P0 ALT1 SCK_2 SSC2 ALT2 CC61_0 CCU6 ALT3 EXF21_3 Timer 21 GPI P1_DATA.P1 INP1 - Output P1.1 Input Output P1.2 Input Output Data Sheet From/to Module - INP2 T6EUDA GPT12T6 INP3 - - INP4 MTSR_2 SSC2 INP5 T21_1 Timer 21 INP6 EXINT1_0 SCU GPO P1_DATA.P1 - ALT1 MTSR_2 SSC2 ALT2 COUT61_0 CCU6 UART2 ALT3 TXD2_0 GPI P1_DATA.P2 INP1 T2INA GPT12T2 INP2 T2EX_1 Timer 2 INP3 T21EX_3 Timer 21 INP4 MRST_2_0 SSC2 INP5 RXD2_0 UART2 INP6 CCPOS2_2 CCU6 INP7 EXINT0_1 SCU GPO P1_DATA.P2 ALT1 MRST_2_0 SSC2 ALT2 COUT63_0 CCU6 ALT3 T3OUT GPT12T3 50 Rev. 1.0, 2017-03-03 TLE9871QXA20 GPIO Ports and Peripheral I/O Table 9 Port 1 Input / Output Functions (cont'd) Port Pin Input/Output Select Connected Signal(s) P1.3 Input GPI P1_DATA.P3 INP1 T6INB INP2 - INP3 CC62_0 CCU6 INP4 T6EUDB GPT12T6 INP5 - INP6 CCPOS0_2 CCU6 INP7 EXINT1_1 SCU GPO P1_DATA.P3 ALT1 EXF21_1 Timer 21 ALT2 CC62_0 CCU6 ALT3 TXD2_1 UART2 GPI P1_DATA.P4 INP1 EXINT2_1 SCU INP2 T21EX_1 Timer 21 INP3 T5EUDA GPT12T5 INP4 RxD1 UART1 INP5 T2INB GPT12T2 INP6 CCPOS1_2 CCU6 INP7 MRST_1_3 SSC1 Output P1.4 Input Output Data Sheet From/to Module GPT12T6 GPO P1_DATA.P4 ALT1 CLKOUT_1 SCU ALT2 COUT62_0 CCU6 ALT3 RxD1 UART1 / PWM_RxD 51 Rev. 1.0, 2017-03-03 TLE9871QXA20 GPIO Ports and Peripheral I/O 14.3.3 Port 2 14.3.3.1 Port 2 Functions Table 10 Port 2 Input Functions Port Pin Input/Output Select Connected Signal(s) P2.0 Input GPI P2_DATA.P0 INP1 CCPOS0_3 CCU6 INP2 - - INP3 T12HR_2 CCU6 P2.2 P2.3 P2.4 P2.5 Data Sheet Input Input Input Input From/to Module INP4 EXINT0_0 SCU INP5 CC61_2 CCU6 ANALOG AN0 ADC XTAL (in) XTAL GPI P2_DATA.P2 INP1 CCPOS2_3 CCU6 INP2 T13HR_2 CCU6 INP3 - INP4 CC62_2 CCU6 ANALOG AN2 ADC OUT XTAL (out) XTAL GPI P2_DATA.P3 INP1 CCPOS1_0 CCU6 INP2 CTRAP#_1 CCU6 INP3 T21EX_2 Timer 21 INP4 CC60_1 CCU6 INP5 EXINT0_3 SCU ANALOG AN3 ADC GPI P2_DATA.P4 INP1 CTRAP#_0 CCU6 INP2 T2EUDB GPT12T2 INP3 MRST_1_1 SSC1 INP4 EXINT1_3 SCU ANALOG AN4 ADC GPI P2_DATA.P5 INP1 RXD2_1 UART2 INP2 T3EUDB GPT12T3 INP3 MRST_2_1 SSC2 INP4 T2_1 Timer 2 ANALOG AN5 ADC 52 Rev. 1.0, 2017-03-03 TLE9871QXA20 General Purpose Timer Units (GPT12) 15 General Purpose Timer Units (GPT12) 15.1 Features 15.1.1 Features Block GPT1 The following list summarizes the supported features: * * * * * * fGPT/4 maximum resolution 3 independent timers/counters Timers/counters can be concatenated 4 operating modes: - Timer Mode - Gated Timer Mode - Counter Mode - Incremental Interface Mode Reload and Capture functionality Shared interrupt: Node 0 15.1.2 Features Block GPT2 The following list summarizes the supported features: * * * * * * fGPT/2 maximum resolution 2 independent timers/counters Timers/counters can be concatenated 3 operating modes: - Timer Mode - Gated Timer Mode - Counter Mode Extended capture/reload functions via 16-bit capture/reload register CAPREL Shared interrupt: Node 1 15.2 Introduction The General Purpose Timer Unit blocks GPT1 and GPT2 have very flexible multifunctional timer structures which may be used for timing, event counting, pulse width measurement, pulse generation, frequency multiplication, and other purposes. They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2. Each timer in each block may operate independently in a number of different modes such as Gated timer or Counter Mode, or may be concatenated with another timer of the same block. Each block has alternate input/output functions and specific interrupts associated with it. Input signals can be selected from several sources by register PISEL. The GPT module is clocked with clock fGPT. fGPT is a clock derived from fSYS. Data Sheet 53 Rev. 1.0, 2017-03-03 TLE9871QXA20 General Purpose Timer Units (GPT12) 15.2.1 Block Diagram GPT1 Block GPT1 contains three timers/counters: The core timer T3 and the two auxiliary timers T2 and T4. The maximum resolution is fGPT/4. The auxiliary timers of GPT1 may optionally be configured as reload or capture registers for the core timer. T3CON.BPS1 fGPT Basic clock 2n : 1 U/D T2IN T2EUD T2 Mode Control Interrupt Request (T2IRQ) Aux. Timer T2 Capture Reload Toggle Latch T3IN T3 Mode Control U/D Core Timer T3 T3OUT T3OTL T3EUD Interrupt Request (T3IRQ) Capture Reload T4IN T4EUD T4 Mode Control U/D Interrupt Request (T4IRQ) Aux. Timer T4 MC _GPT 0101_bldiax1.vsd Figure 19 Data Sheet GPT1 Block Diagram (n = 2 ... 5) 54 Rev. 1.0, 2017-03-03 TLE9871QXA20 General Purpose Timer Units (GPT12) 15.2.2 Block Diagram GPT2 Block GPT2 contains two timers/counters: The core timer T6 and the auxiliary timer T5. The maximum resolution is fGPT/2. An additional Capture/Reload register (CAPREL) supports capture and reload operation with extended functionality. T6CON.BPS2 2n : 1 fGPT Basic clock Toggle FF T5IN T2 Mode Control T5EUD U/D Interrupt Request (T5IRQ) GPT2 Timer T5 Clear Capture CAPIN T3IN/ T3EUD CAPREL Mode Control GPT2 CAPREL Interrupt Request (CRIRQ) Reload Interrupt Request (T6IRQ) Clear T6IN T6 Mode Control GPT2 Timer T6 Data Sheet T6OUT T6OUF T6EUD Figure 20 T6OTL U/D GPT2 Block Diagram (n = 1 ... 4) 55 Rev. 1.0, 2017-03-03 TLE9871QXA20 Timer2 and Timer21 16 Timer2 and Timer21 16.1 Features * * 16-bit auto-reload mode - selectable up or down counting One channel 16-bit capture mode 16.2 Introduction The timer modules are general-purpose 16-bit timers. Timer 2/21 can function as a timer or counter in each of its modes. As a timer, it counts with an input clock of fPCLK/12 (if prescaler is disabled). As a counter, Timer 2 counts 1-to-0 transitions on pin T2. In the counter mode, the maximum resolution for the count is fPCLK/24 (if prescaler is disabled). 16.2.1 Timer2 and Timer21 Modes Overview Table 11 Timer2 and Timer21 Modes Mode Description Auto-reload Up/Down Count Disabled * Count up only * Start counting from 16-bit reload value, overflow at FFFFH * Reload event configurable for trigger by overflow condition only, or by negative/positive edge at input pin T2EX as well * Programmable reload value in register RC2 * Interrupt is generated with reload events. Auto-reload Up/Down Count Enabled * Count up or down, direction determined by level at input pin T2EX * No interrupt is generated * Count up - Start counting from 16-bit reload value, overflow at FFFFH - Reload event triggered by overflow condition - Programmable reload value in register RC2 * Count down - Start counting from FFFFH, underflow at value defined in register RC2 - Reload event triggered by underflow condition - Reload value fixed at FFFFH Channel capture * * * * * * * Data Sheet Count up only Start counting from 0000H, overflow at FFFFH Reload event triggered by overflow condition Reload value fixed at 0000H Capture event triggered by falling/rising edge at pin T2EX Captured timer value stored in register RC2 Interrupt is generated by reload or capture events 56 Rev. 1.0, 2017-03-03 TLE9871QXA20 Timer3 17 Timer3 17.1 Features * * * * * * 16-bit incremental timer/counter (counting up) Counting frequency up to fsys Selectable clock prescaler 6 modes of operation Interrupt up on overflow Interrupt on compare 17.2 Introduction The possible applications for the timer include measuring the time interval between events, counting events and generating a signal at regular intervals. Timer3 can function as timer or counter. When functioning as a timer, Timer3 is incremented in periods based on the MI_CLK or LP_CLK clock. When functioning as a counter, Timer3 is incremented in response to a 1-to-0 transition (falling edge) at its respective input. Timer3 can be configured in four different operating modes to use in a variety of applications, see Table 12. Several operating modes can be used for different tasks such as the following: * * * simple time measurement between two events triggering of the measuring unit upon PWM/CCU6 unit measurement of the 100kHz LP_CLK2 17.3 Functional Description Six modes of operation are provided to fulfill various tasks using this timer. In every mode the clocking source can be selected between MI_CLK and LP_CLK. A prescaler provides in addition capability to divide the selected clock source by 2, 4 or 8. The timer counts upwards, starting with the value in the timer count registers, until the maximum count value which depends on the selected mode of operation. Timer 3 provides two individual interrupts upon counter overflow, one for the low-byte and one for the high-byte counter register. 17.3.1 Timer3 Modes Overview The following table provides an overview of the timer modes together with the reasonable configuration options in Table 12. Table 12 Timer3 Modes Mode SubMode Operation 0 No SubMode 13-bit Timer The timer is essentially an 8-bit counter with a divide-by-32 prescaler. 1 a 16-bit Timer The timer registers, TL3 and TH3, are concatenated to form a 16-bit counter. 1 b 16-bit Timer triggered by an event The timer registers, TL3 and TH3, are concatenated to form a 16-bit counter, which is triggered by an event to enable a single shot measurement on a preset channel with the measurement unit. Data Sheet 57 Rev. 1.0, 2017-03-03 TLE9871QXA20 Timer3 Table 12 Timer3 Modes (cont'd) Mode SubMode Operation 2 No SubMode 8-bit Timer with auto-reload The timer register TL3 is reloaded with a user-defined 8-bit value in TH3 upon overflow. 3 a Timer3 operates as two 8-bit timers The timer registers TL3 and TH3, operate as two separate 8-bit counters. 3 b Timer3 operates as Two 8-bit timers for clock measurement The timer registers, TL3 and TH3 operate as two separate 8-bit counters. In this mode the LP_CLK2 Low Power Clock can be measured. TL3 acts as an edge counter for the clock edges and TH3 as a counter which counts the time between the edges. Data Sheet 58 Rev. 1.0, 2017-03-03 TLE9871QXA20 Capture/Compare Unit 6 (CCU6) 18 Capture/Compare Unit 6 (CCU6) 18.1 Feature Set Overview This section gives an overview over the different building blocks and their main features. Timer 12 Block Features * * * * * * * * * * * Three capture/compare channels, each channel can be used either as capture or as compare channel Generation of a three-phase PWM supported (six outputs, individual signals for high-side and low-side switches) 16-bit resolution, maximum count frequency = peripheral clock Dead-time control for each channel to avoid short-circuits in the power stage Concurrent update of T12 registers Center-aligned and edge-aligned PWM can be generated Single-shot mode supported Start can be controlled by external events Capability of counting external events Multiple interrupt request sources Hysteresis-like control mode Timer 13 Block Features * * * * * * * * One independent compare channel with one output 16-bit resolution, maximum count frequency = peripheral clock Concurrent update of T13 registers Can be synchronized to T12 Interrupt generation at period-match and compare-match Single-shot mode supported Start can be controlled by external events Capability of counting external events Additional Specific Functions * * * * * * * * Block commutation for brushless DC-drives implemented Position detection via hall-sensor pattern Noise filter supported for position input signals Automatic rotational speed measurement and commutation control for block commutation Integrated error handling Fast emergency stop without CPU load via external signal (CTRAP) Control modes for multi-channel AC-drives Output levels can be selected and adapted to the power stage 18.2 Introduction The CCU6 unit is made up of a Timer T12 block with three capture/compare channels and a Timer T13 block with one compare channel. The T12 channels can independently generate PWM signals or accept capture triggers, or they can jointly generate control signal patterns to drive DC-motors or inverters. A rich set of status bits, synchronized updating of parameter values via shadow registers, and flexible generation of interrupt request signals provide efficient software-control. Data Sheet 59 Rev. 1.0, 2017-03-03 TLE9871QXA20 Capture/Compare Unit 6 (CCU6) Note: The capture/compare module itself is referred to as CCU6 (capture/compare unit 6). A capture/compare channel inside this module is referred to as CC6x. The timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined (e.g. a channel works in compare mode, whereas another channel works in capture mode). The timer T13 can work in compare mode only. The multi-channel control unit generates output patterns which can be modulated by T12 and/or T13. The modulation sources can be selected and combined for the signal modulation. 18.2.1 Block Diagram CCU6 Module Kernel T12SUSP T13SUSP T12 1 CC61 1 CC62 1 DeadTime Control Multichannel Control Trap Control SR[3:0] 2 2 Trap Input Hall Input Output Select 2 3 1 CTRAP CCPOS2 CCPOS1 CCPOS0 COUT63 CC62 COUT62 COUT61 CC60 COUT60 T13HR Input / Output Control T12HR Interrupt Control 3 Compare Capture 1 Compare CC63 Compare T13 CC61 fCC 6 Compare Clock Control Output Select Start Debug Suspend Compare CC60 Port Control P0.x Figure 21 Data Sheet P1.x P2.x CCU6_MCB05506.vsd CCU6 Block Diagram 60 Rev. 1.0, 2017-03-03 TLE9871QXA20 UART1/UART2 19 UART1/UART2 19.1 Features * * * * * * Full-duplex asynchronous modes - 8-bit or 9-bit data frames, LSB first - fixed or variable baud rate Receive buffered Multiprocessor communication Interrupt generation on the completion of a data transmission or reception Baud-rate generator with fractional divider for generating a wide range of baud rates Hardware logic for break and synch byte detection 19.2 Introduction The UART provides a full-duplex asynchronous receiver/transmitter, i.e., it can transmit and receive simultaneously. It is also receive-buffered, i.e., it can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost. The serial port receive and transmit registers are both accessed at Special Function Register (SFR) SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. 19.2.1 Block Diagram UART disreq from SCU _DM SCU_D M Interrupt Control RI TXD TI RXD TXD URIOS SCU_DM UART Module fUART2 Clock Control P0.x Baud Rate Generator f BR P1.x P2.x RXDO_2 AHB Interface Data Sheet RXD_1 Port Control Address Decoder Figure 22 RXD_0 SCU_DM UART GPIOs UART Block Diagram 61 Rev. 1.0, 2017-03-03 TLE9871QXA20 UART1/UART2 19.3 UART Modes The UART can be used in four different modes. In mode 0, it operates as an 8-bit shift register. In mode 1, it operates as an 8-bit serial port. In modes 2 and 3, it operates as a 9-bit serial port. The only difference between mode 2 and mode 3 is the baud rate, which is fixed in mode 2 but variable in mode 3. The variable baud rate is set by the underflow rate on the dedicated baud-rate generator. The different modes are selected by setting bits SM0 and SM1 to their corresponding values, as shown in Table 13. Table 13 SM0 UART Modes SM1 Operating Mode Baud Rate 0 0 Mode 0: 8-bit shift register fPCLK/2 0 1 Mode 1: 8-bit shift UART Variable 1 0 Mode 2: 9-bit shift UART fPCLK/64 1 1 Mode 3: 9-bit shift UART Variable The UART1 is connected to the integrated PWM interface, and to GPIO for test purpose. The UART2 is connected to GPIO only. Data Sheet 62 Rev. 1.0, 2017-03-03 TLE9871QXA20 High Voltage PWM Interface 20 High Voltage PWM Interface 20.1 Features General Functional Features * Bidirectional High Voltage PWM interface Special Features * PWM interface can be used as a high voltage input/output with dedicated SFR control bits. Operation Modes Features * High Voltage Input / Output Mode (HVIO) Supported Baudrates * up to 57.6 kHz Slope Modes Features * * * Normal Slope Mode (10 kHz) Low Slope Mode (5.2 kHz) Flash Mode (57.6 kHz) Wake-Up Features * High Voltage PWM Interface wake-up 20.2 Introduction The high voltage bidirectional PWM Module is a robust physical layer interface for PWM communication. The bidirectional PWM Module offers two different operation modes, including a Sleep Mode and the High Voltage Input Output Mode. Data Sheet 63 Rev. 1.0, 2017-03-03 TLE9871QXA20 High Voltage PWM Interface 20.2.1 Block Diagram VS High Voltage PWM Interface 30 k LIN_CTRL_STS PWM_IO CTRL Driver + Curr. Limit. + TSD TxD_1 from SFR LIN_CTRL_STS. LIN_TXD PWM-FSM STATUS Transmitter CTRL STATUS GND_PWM Filter RxD_1 to Timer2 & LIN_CTRL_STS .LIN_RXD Receiver Filter PWM_Wake Sleep Comparator GND_PWM Figure 23 Data Sheet PWM_Block_Diagram_Customer.vsd PWM Interface Block Diagram 64 Rev. 1.0, 2017-03-03 TLE9871QXA20 High-Speed Synchronous Serial Interface (SSC1/SSC2) 21 High-Speed Synchronous Serial Interface (SSC1/SSC2) 21.1 Features * * * * * * Master and Slave Mode operation - Full-duplex or half-duplex operation Transmit and receive buffered Flexible data format - Programmable number of data bits: 2 to 16 bits - Programmable shift direction: Least Significant Bit (LSB) or Most Significant Bit (MSB) shift first - Programmable clock polarity: idle low or high state for the shift clock - Programmable clock/data phase: data shift with leading or trailing edge of the shift clock Variable baud rate Compatible with Serial Peripheral Interface (SPI) Interrupt generation - On a transmitter empty condition - On a "receiver full" condition - On an error condition (receive, phase, baud rate, transmission error) Data Sheet 65 Rev. 1.0, 2017-03-03 TLE9871QXA20 High-Speed Synchronous Serial Interface (SSC1/SSC2) 21.2 Introduction The High-Speed Synchronous Serial Interface (SSC) supports both full-duplex and half-duplex serial synchronous communication. The serial clock signal can be generated by the SSC internally (master mode), using its own 16bit baud rate generator, or can be received from an external master (slave mode). Data width, shift direction, clock polarity, and phase are programmable. This allows communication with SPI-compatible devices or devices using other synchronous serial interfaces. Data is transmitted or received on TXD and RXD lines, which are normally connected to the MTSR (MasterTransmit/Slave Receive) and MRST (Master Receive/Slave Transmit) pins. The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin SCLK. Transmission and reception of data are double-buffered. 21.2.1 Block Diagram Figure 24 shows all functional relevant interfaces associated with the SSC Kernel. MRSTA TIR MTSRA SSC Module Clock Control MTSR RIR P0.x MTSRB Slave SCU_DM Interrupt Control MRSTB Master EIR MRST Port Control P1.x fhw_clk P2.x Slave SCLKA AHB Interface SCLKB SCLK Master Address Decoder Module Product Interface SSC_interface_overview.vsd Figure 24 Data Sheet SSC Interface Diagram 66 Rev. 1.0, 2017-03-03 TLE9871QXA20 Measurement Unit 22 Measurement Unit 22.1 Features * * * * * * * 1 x 8-bit ADC with 10 Inputs including attenuator allowing measurement of high voltage input signals Supply Voltage Attenuators with attenuation of VS, VDDP and VDDC. VBG monitoring of 8-bit ADC to guarantee functional safety requirements. Bridge Driver Diagnosis Measurement (VDH, VCP). Temperature Sensor for monitoring the chip temperature and PMU Regulator temperature. BEMF Comparators for commutation triggering inside BLDC Applications. Supplement Block with Reference Voltage Generation, Bias Current Generation, Voltage Buffer for NVM Reference Voltage, Voltage Buffer for Analog Module Reference Voltage and Test Interface. 22.2 Introduction The measurement unit is a functional unit that comprises the following associated sub-modules: Table 14 Measurement Functions and Associated Modules Module Name Modules Functions Central Functions Bandgap reference circuit Unit The bandgap-reference sub-module provides two reference voltages 1. a trimmable reference voltage for the 8-bit ADCs. A local dedicated bandgap circuit is implemented to avoid deterioration of the reference voltage arising e.g. from crosstalk or ground voltage shift. 2. the reference voltage for the NVM module 8-bit ADC (ADC2) 8-bit ADC module with 10 multiplexed inputs, including HV input attenuator 5 high voltage full supply range capable inputs (2.5V...30,7V(FS)) 2 medium voltage inputs (0..5V/7V FS). 3 low voltage inputs (0..1.2V/1.6V FS) (allocation see following overview figure) 10-bit ADC (ADC1) 10-bit ADC module with 8 multiplexed inputs Five (5V) analog inputs from Port 2.x VDH Input Voltage Attenuator VDH input voltage attenuator Scales down V(VDH) to the input voltage range of ADC1.CH6 Temperature Sensor Temperature sensor with two multiplexed sensing elements: * PMU located sensor * Central chip located sensor Generates output voltage which is a linear function of the local chip (junction) temperature. Data Sheet 67 Rev. 1.0, 2017-03-03 TLE9871QXA20 Measurement Unit Table 14 Measurement Functions and Associated Modules Module Name Modules Functions BEMF Comparators Back Electromotive Force Comparators Comparators are used to detect the Back Electromotive Force (Zero Crossing Event), which can be used as a commutation trigger for BLDC applications. Measurement Core Module Digital signal processing and ADC2 1. Generates the control signal for the 8-bit ADC2 and control unit the synchronous clock for the switched capacitor circuits, 2. Performs digital signal processing functions and provides status outputs for interrupt generation. 22.2.1 Block Diagram VS VAGND VAREF P2.0 CH0 5V OP1 OP2 GND_SENSE CH1 OP CH2 G = 10/20/40/60 VREF P2.2 CH3 P2.3 CH4 P2.4 CH5 MUX P2.5 A VDH rfu 10 / SFR Channel sequencer ADC 1 CH6 x 0.226 x 0.166 D CH7 10 Bit ADC + DPP1 Programmable range setting rfu CH0 x 0.055 x 0.039 CH1 VSD x 0.039 CH2 VCP x 0.023 CH3 MON x 0.039 CH4 1.23 V MUX VDDP VAREF x 0.164 CH5 x 0.219 CH6 VDDC x 0.75 Temperature Sensor D 8 / calibration & filter unit with upper / lower threshold detection / interrupt SFR ADC 2 CH7 PMU-VBG A CH8 CH9 8 Bit ADC + DPP2 Measurement-Unit Measurement_Unit_ Overview_TLE987x_no _SD_B1 5.vsd Figure 25 Data Sheet Measurement Unit-Overview (with opamp) 68 Rev. 1.0, 2017-03-03 TLE9871QXA20 Measurement Unit 22.2.1.1 Block Diagram BEMF Comparator V Phase U W V U VS/2 SH3 R SH2 R BEMF-Comp Blank Filter Spike Filter R SH1 BEMF IN BEMF OUT R t Measurement-Unit / BEMF Comparators Figure 26 Data Sheet 3 Times BEMF Comparator 69 Rev. 1.0, 2017-03-03 TLE9871QXA20 Measurement Core Module (incl. ADC2) 23 Measurement Core Module (incl. ADC2) 23.1 Features * * * * * 8 individually programmable channels split into two groups of user configurable and non user configurable Individually programmable channel prioritization scheme for measurement unit Two independent filter stages with programmable low-pass and time filter characteristics for each channel Two channel configurations: - Programmable upper- and lower trigger thresholds comprising a fully programmable hysteresis - Two individually programmable trigger thresholds with limit hysteresis settings Individually programmable interrupts and statuses for all channel thresholds 23.2 Introduction The basic function of this block is the digital postprocessing of several analog digitized measurement signals by means of filtering, level comparison and interrupt generation. The measurement postprocessing block consists of ten identical channel units attached to the outputs of the 10-channel 8-bit ADC (ADC2). It processes ten channels, where the channel sequence and prioritization is programmable within a wide range. 23.2.1 Block Diagram 4 / Measurement Core Module MUX_SEL<3:0> Channel Controller (Sequencer) SQ0 - SQ9 FILT_OUTx.OUT_CHx CNTUP + MMODE THy_z_LOWER. CHx - CNTLOW THy_z_UPPER. CHx HYSUP y= a + (1+b)*x + 8 / HYSLOW CH8 D 10 / FILTENLOW VDDC Temperature Sensor FILTENUP CH7 A 8 / Calibration Unit: FILTENLOW PMU-VBG 1st Order IIR 8 Bit ADC VREF MUX MUX_CTRL CH6 EN CH5 COEFF_IIR VDDP VAREF MUX_CTRL CH4 EN MON COEFF_B CH3 MUX_CTRL CH2 VCP EN CH1 VSD COEFF A CH0 rfu VS CTRL_STS TSENS_SEL ADC2 - SFR 1 / +/- UP_X_STS 1 / +/- LOW_X_STS Digital Signal Processing CH9 TSENSE Figure 27 Data Sheet Module Block Diagram 70 Rev. 1.0, 2017-03-03 TLE9871QXA20 Measurement Core Module (incl. ADC2) 23.2.2 Measurement Core Module Modes Overview The basic function of this unit, is the digital signal processing of several analog digitized measurement signals by means of filtering, level comparison and interrupt generation. The Measurement Core module processes ten channels in a quasi parallel process. As shown in the figure above, the ADC2 postprocessing unit consists of a channel controller (Sequencer), an 10channel demultiplexer and the signal processing block, which filters and compares the sampled ADC2 values for each channel individually. The channel control block controls the multiplexer sequencing on the analog side before the ADC2 and on the digital domain after the ADC2. As described in the following section, the channel sequence can be controlled in a flexible way, which allows a certain degree of channel prioritization. This capability can be used e.g. to set a higher priority to supply voltage channels compared to the other channel measurements. The Measurement Core Module offers additionally two different post-processing measurement modes for over-/undervoltage detection and for two-level threshold detection. The channel controller (sequencer) runs in one of the following modes: "Normal Sequencer Mode" - channels are selected according to the 10 sequence registers which contain individual enablers for each of the 10 channels. "Exceptional Interrupt Measurement" - following a hardware event, a high priority channel is inserted into the current sequence. The current actual measurement is not destroyed. "Exceptional Sequence Measurement" - following a hardware event, a complete sequence is inserted after the current measurement is finished. The current sequence is interrupted by the exception sequence. Data Sheet 71 Rev. 1.0, 2017-03-03 TLE9871QXA20 10-Bit Analog Digital Converter (ADC1) 24 10-Bit Analog Digital Converter (ADC1) 24.1 Features The principal features of the ADC1 are: * * * * * * * * * * Up to 8 analog input channels (channel 7 reserved for future use) Flexible results handling - 8-bit and 10-bit resolution Flexible source selection due to sequencer - insert one exceptional sequence (ESM) - insert one interrupt measurement into the current sequence (EIM), single or up to 128 times - software mode Conversion sample time (separate for each channel) adjustable to adapt to sensors and reference Standard external reference (VAREF) to support ratiometric measurements and different signal scales DMA support, transfer ADC conversion results via DMA into RAM Support of suspend and power saving modes Result data protection for slow CPU access (wait-for-read mode) Programmable clock divider Integrated sample and hold circuitry 24.2 Introduction The TLE9871QXA20 includes a high-performance 10-bit Analog-to-Digital Converter (ADC1) with eight multiplexed analog input channels. The ADC1 uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. The analog input channels of the ADC1 are available at AN0, AN2 - AN5. Data Sheet 72 Rev. 1.0, 2017-03-03 TLE9871QXA20 10-Bit Analog Digital Converter (ADC1) 24.2.1 Block Diagram 3 / 3 / MUX_SEL <2:0> EoC - SoC Channel Controller (Sequencer) Settings Settings ADC1 - SFR P2.0 10 CH0 10 CH1 P2.2 P2.3 CH3 P2.4 CH4 P2.5 CH5 VDH rfu OP1 OP2 Figure 28 10 ADC1 CH2 MUX A 10 10 / D MUX 10 10 10 CH6 10 CH7 10 / ADC1_OUT_CH0 / ADC1_OUT_CH1 / ADC1_OUT_CH2 / ADC1_OUT_CH3 / ADC1_OUT_CH4 / ADC1_OUT_CH5 / ADC1_OUT_CH6 / ADC1_OUT_CH7 / ADC1_RES_OUT_EIM OPA ADC1 Top Level Block Diagram As shown in the figure above, the ADC1 postprocessing consists of a channel controller (Sequencer) and an 8channel demultiplexer. The channel control block controls the multiplexer sequencing on the analog side before the ADC1 and on the digital domain after the ADC1. As described in the following section, the channel sequence can be controlled in a flexible way, which allows a certain degree of channel prioritization. This capability can be used e.g. to give a higher priority to some channels compared to the other channel measurements. Data Sheet 73 Rev. 1.0, 2017-03-03 TLE9871QXA20 High-Voltage Monitor Input 25 High-Voltage Monitor Input 25.1 Features * * * * High-voltage input with VS/2 threshold voltage Integrated selectable pull-up and pull-down current sources Wake capability for power saving modes Level change sensitivity configurable for transitions from low to high, high to low or both directions 25.2 Introduction This module is dedicated to monitor external voltage levels above or below a specified threshold or it can be used to detect a wake-up event at the high-voltage MON pin in low-power mode. The input is sensitive to a input level monitoring, this is available when the module is switched to active mode with the SFR bit EN. To use the Wake function during low power mode of the IC, the monitoring pin is switched to Sleep Mode via the SFR bit EN. 25.2.1 Block Diagram VS MON + Filter to internal circuitry MON Logic SFR MONx_Input _Circuit_ext .vsd Figure 29 Data Sheet Monitoring Input Block Diagram 74 Rev. 1.0, 2017-03-03 TLE9871QXA20 Bridge Driver (incl. Charge Pump) 26 Bridge Driver (incl. Charge Pump) 26.1 Features The MOSFET Driver is intended to drive external normal level NFET transistors in bridge configuration. The driver provides many diagnostic possibilities to detect faults. Functional Features * * * * * * * External Power NFET Transistor Driver Stage with driver capability for max. 100 nC gate charge @ 25 kHz switching frequency. Implemented adjustable cross conduction protection. Supply voltage (VSD) monitoring incl. adjustable over- and undervoltage shutdown with configurable interrupt signalling. VSD operating range down to 5.4 V VDS comparators for short circuit detection in on- and off-state Open-Load detection in off-state Flexible PWM frequency range, rates above 25 kHz require power dissipation and duty cycle resolution analysis 26.2 Introduction The MOSFET Driver Stage can be used for controlling external Power NFET Transistors (normal level). The module output is controlled by SFR or System PWM Machine (CCU6). Data Sheet 75 Rev. 1.0, 2017-03-03 TLE9871QXA20 Bridge Driver (incl. Charge Pump) 26.2.1 Block Diagram VDH VCP PWM-Unit CCU6 (not part of the module ) Pre-Driver DRV.TRIM_DRVx. LSDRV_DS_TFILT_SEL DRV.TRIM_DRVx. LS_HS_BT _TFILT_SEL DRV.CTRL3. DSMONVTH + Spike Filter Blank Filter VDS - High Side Driver 1 GHx 0 R GGND VREF DRV.CTRL1.HSx_PWM SFR SHx 1 0 DRV.CTRL1.LSx_PWM Spike Filter Low Side Driver + Blank Filter VDS GLx - DRV.TRIM_DRVx. LSDRV_DS_TFILT_SEL DRV.TRIM_DRVx. LS_HS_BT _TFILT_SEL DRV.CTRL3. DSMONVTH R GGND VREF SL PreDriver_Customer.vsd Figure 30 Driver Module Block Diagram (incl. system connections) 26.2.2 General The Driver can be controlled in two different ways: * * In Normal Mode the output stage is fully controllable through the SFR registers CTRLx (x = 1,2,3). Protection functions such as overcurrent and open-load detection are available. The PWM Mode can also be enabled by the corresponding bit in CTRL1 and CTRL2. The PWM must be configured in the System PWM Module (CCU6). All protection functions are available in PWM mode as well. Protection Functions * * * Overcurrent detection and shutdown feature for external MOSFET by Drain Source measurement Programmable minimum cross current protection time Open-load detection feature in Off-state for external MOSFET. Data Sheet 76 Rev. 1.0, 2017-03-03 TLE9871QXA20 Current Sense Amplifier 27 Current Sense Amplifier 27.1 Features Main Features * * * * Programmable gain settings: G = 10, 20, 40, 60 Differential input voltage: 1.5V / G Wide common mode input range 2 V Low setting time < 1.4 s 27.2 Introduction The current sense amplifier in Figure 31 can be used to measure near ground differential voltages via the 10-bit ADC. Its gain is digitally programmable through internal control registers. Linear calibration has to be applied to achieve high gain accuracy, e.g. end-of-line calibration including the shunt resistor. Figure 31 shows how the current sense amplifier can be used as a low-side current sense amplifier where the motor current is converted to a voltage by means of a shunt resistor RSH. A differential amplifier input is used in order to eliminate measurement errors due to voltage drop across the stray resistance RStray and differences between the external and internal ground. If the voltage at one or both inputs is out of the operating range, the input circuit is overloaded and requires a certain specified recovery time. In general, the external low pass filter should provide suppression of EMI. 27.2.1 Block Diagram VBAT M VAREF 5V VZ ERO Motor Current VP RSH Amplifier LP Filter ROPAFILT OP2 configurable Gain: 10, 20, 40, 60 Vzero + (VOP2 -VOP1) * G COPAFILT ROPAFILT 10-bit ADC 10 / ADC1_OUT_CH1 OP1 VN RStray CSA_CTRL Ext. GND Figure 31 Data Sheet Current_Sense_Amplifier .vsd Simplified Application Diagram 77 Rev. 1.0, 2017-03-03 TLE9871QXA20 Application Information 28 Application Information 28.1 BLDC Driver Figure 32 shows the TLE9871QXA20 in an electric drive application setup controlling a BLDC motor. Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Rev. Polarity Protection LPF ILT VBAT CPF ILT1 CPF ILT1 CVDDP2 EMC Filter CVDDP1 DVS VS CVS 2 CVDDC1 VDDP VDDC CVS 1 RMON IGN CMON MON CVDDC2 CP1H CP1L CP2H CP2L VCP CCPS1 CCPS2 RVS D VSD CVS D PWM PWM_IO CPWM_IO CVDH GND_PWM D RGA TE G GH1 VAREF CVA REF CVCP RVDH VDH TH1 RGS GND_REF CGS SH1 CPH1 D S G CEM CP1 RVDDPU TLE4946-2K Hall CADC CVDD_EX T2 CVDD_EX T1 TH2 RGS CPH2 CGS SH2 D S G CEM CP2 RVDDPU RGA TE GH3 SH3 P1.4 RADC CADC GH2 P0.3 RADC TLE4946-2K Hall TLE4946-2K Hall VDD_EXT RGA TE TH3 RGS CGS S D P0.2 RADC CADC RGA TE TLE9871 G GL1 TL1 RGS RGA TE CGS G TL2 P2.2 Temp Sensor M D S GL2 RGS CGS D S RGA TE G GL3 TL3 P1.2 RGS SL ROP AFI LT RGA TE RShunt COP AFI LT OP1 P1.0 RGA TE ROP AFI LT P2.0 P2.3 P2.4 TMS P0.0 Debug Connector Input Protection Circuit Input Protection Circuit Input Protection Circuit P0.1 P0.4 P2.5 P1.3 GND RTM S Figure 32 CGS S OP2 BLDC System U V W CEM CP3 RVDDPU CPH 3 GND Simplified Application Diagram Example Note: This is a very simplified example of an application circuit and bill of materials. The function must be verified in the actual application. Data Sheet 78 Rev. 1.0, 2017-03-03 TLE9871QXA20 Application Information Table 15 External Components (BOM) Symbol Function Component CVS1 Blocking capacitor at VS pin 100 nF Ceramic, ESR < 1 CVS2 Blocking capacitor at VS pin > 2.2 F Elco1) CVDDP Blocking capacitor at VDDP pin 470 nF + 100 nF Ceramic, ESR < 1 CVDD_EXT Blocking capacitor at VDDEXT pin 100nF, Ceramic ESR < 1 CVDDC Blocking capacitor at VDDC pin 470 nF + 100 nF Ceramic, ESR < 1 CVAREF Blocking capacitor at VAREF pin 100 nF, Ceramic ESR < 1 CPWM_IO Standard C for PWM Interface slave - CVSD Filter C for charge pump end driver 1 F CCPS1 Charge pump capacitor 220 nF CCP2S Charge pump capacitor 220 nF CVCP Charge pump capacitor 470 nF CMON Filter C for ISO pulses 10 nF CVDH Capacitor 3.3 nF CPH1 Capacitor 220 F CPH2 Capacitor 220 F CPH3 Capacitor 220 F COPAFILT Capacitor 100 nF CEMCP1 Capacitor 1 nF CEMCP2 Capacitor 1 nF CEMCP3 Capacitor 1 nF CPFILT1, CPFILT2 Capacitor RMON Resistor at MON pin RVSD 2 Limitation of reverse current due to transient (-2V, 8ms) max. ratings of the VSD pin has to be met, alternatively the resistor shall be replaced by a diode RVDH Resistor 1 k RGATE Resistor 2 ROPAFILT Resistor 12 RSH1 Resistor optional RSH2 Resistor optional RSH3 Resistor optional 3.9 k LPFILT DVS - Reverse-polarity protection diode - 1) The capacitor must be dimensioned so as to ensure that flash operations modifying the content of the flash are never interrupted (e.g. in case of power loss). Data Sheet 79 Rev. 1.0, 2017-03-03 TLE9871QXA20 Application Information 28.2 ESD Immunity According to IEC61000-4-2 Note: Tests for ESD immunity according to IEC61000-4-2 "Gun test" (150pF, 330) has been performed. The results and test condition will be available in a test report. Table 16 ESD "Gun Test" Performed Test Result Unit Remarks ESD at pin PWM_IO, versus GND1) >6 kV 2) ESD at pin PWM_IO, versus GND1) < -6 kV 2) positive pulse negative pulse 1) ESD test "ESD GUN" is specified with external components; see application diagram: CMON = 100 nF, RMON = 1 k, CPWM_IO = 220 pF, CVS = >20 F ELCO + 100 nF ESR < 1 , CVSD = 1 F, RVSD = 2 . 2) ESD susceptibility "ESD GUN" according to LIN EMC Test Specification, Section 4.3 (IEC 61000-4-2). To be tested by external test house (IBEE Zwickau) Data Sheet 80 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29 Electrical Characteristics This chapter includes all relevant electrical characteristics of the product TLE9871QXA20. 29.1 General Characteristics 29.1.1 Absolute Maximum Ratings Table 17 Absolute Maximum Ratings1) Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Voltages - Supply Pins Supply voltage - VS VS -0.3 - 40 V Load dump P_1.1.1 Supply voltage - VSD VSD -0.3 - 48 V - P_1.1.2 Supply voltage - VSD VSD_max_exten -2.8 - 48 V Series resistor RVSD = P_1.1.32 2.2 , t = 8 ms 2) Voltage range - VDDP VDDP -0.3 - 5.5 V - P_1.1.3 Voltage range - VDDP VDDP_max_ext -0.3 - 7 V In case of voltage transients on VS with dVS/dt 1V/s; duration: t 150s; CVDDP 570 nF P_1.1.41 d end Voltage range - VDDEXT VDDEXT -0.3 - 5.5 V - P_1.1.4 Voltage range - VDDEXT VDDEXT_max_ -0.3 - 7 V In case of voltage transients on VS with dVS/dt 1V/s; duration: t 150s; CVDDEXT 570 nF P_1.1.42 extend Voltage range - VDDC VDDC -0.3 - 1.6 V - P_1.1.5 VPWM_IO -28 - 40 V - P_1.1.7 V 3) P_1.1.8 V 4) P_1.1.38 P_1.1.9 Voltages - High Voltage Pins Input voltage at PWM_IO Input voltage at MON Input voltage at VDH VMON_maxrate -28 VVDH_maxrate -2.8 - - 40 40 Voltage range at GHx VGH -8.0 - 48 V 5) Voltage range at GHx vs. SHx VGHvsSH 14 - - V - P_1.1.44 Voltage range at SHx VSH -8.0 - 48 V - P_1.1.11 Voltage range at GLx VGL -8.0 - 48 V 6) Voltage range at GLx vs. SL VGLvsSL 14 - - V - Data Sheet 81 - P_1.1.13 P_1.1.45 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics Table 17 Absolute Maximum Ratings1) (cont'd) Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Voltage range at charge pump VCPx pins CP1H, CP1L, CP2H, CP2L, VCP Values Unit Note / Test Condition Number Min. Typ. Max. -0.3 - 48 V 7) P_1.1.15 -0.3 - VDDP V VIN < VDDPmax9) P_1.1.16 Voltages - GPIOs Voltage on any port pin8) Vin +0.3 Current at VCP Pin IVCP -15 - - mA - P_1.1.35 Injection current on any port pin IGPIONM -5 - 5 mA 10) P_1.1.34 Sum of all injected currents in Normal Mode IGPIOAM_sum -50 - 50 mA 10) P_1.1.30 -5000 - 50 A 10) P_1.1.36 5 mA 10) P_1.1.37 VDDP V - P_1.1.17 Max. current at VCP pin Injection Current at GPIOs IGPIOPD_sum Sum of all injected currents in Power Down Mode (Stop Mode) Sum of all injected currents in Sleep Mode IGPIOSleep_su -5 - m Other Voltages Input voltage VAREF VAREF -0.3 - +0.3 VOAI -7 - 7 V - P_1.1.23 Junction temperature Tj -40 - 150 C - P_1.1.18 Storage temperature Tstg -55 - 150 C - P_1.1.19 ESD susceptibility all pins VESD1 -2 - 2 kV HBM 11) P_1.1.20 ESD susceptibility pins MON, VS, VSD vs.GND VESD2 -4 - 4 kV HBM 12) P_1.1.21 ESD susceptibility pins PWM_IO vs. GND_PWM VESD3 -6 - 6 kV HBM 11) P_1.1.22 ESD susceptibility CDM all pins vs. GND VESD_CDM1 -500 - 500 V 13) P_1.1.28 VESD_CDM2 ESD susceptibility CDM pins 1, 12, 13, 24, 25, 36, 37, 48 (corner pins) vs. GND -750 - 750 V 13) P_1.1.43 Input voltage OP1, OP2 Temperatures ESD Susceptibility 1) Not subject to production test, specified by design. 2) Conditions and min. value is derived from application condition for reverse polarity event. 3) Min voltage -28V with external 3.9k series resistor only. Data Sheet 82 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 4) Min voltage -2.8V with external 1k series resistor only. 5) To achieve max. ratings on this pin, Parameter P_1.1.44 has to be taken into account resulting in the following dependency: VGH < VSH + VGHvsSH_min and additionally VSH < VGH + 0.3V. 6) To achieve max. ratings on this pin, Parameter P_1.1.45 has to be taken into account resulting in the following dependency: VGL < VSL + VGLvsSL_min and additionally VSL < VGL + 0.3V. 7) These limits can be kept if max current drawn out of pin does not exceed limit of 200 A. 8) See XTAL parameter specification, when GPIOs (Port Pin P2.0 and P2.2) are used as XTAL. 9) Includes TMS and RESET. 10) Maximum rating for injection current of GPIO with VIN respected. 11) ESD susceptibility HBM according to ANSI/ESDA/JEDEC JS-001 (1.5k, 100pF) 12) MON with external circuitry of a series resistor of 3.9k and 10nF (at connector); VS with an external ceramic capacitor of 100nF; VSD with an external capacitor of 470nF; VDH with external circuitry of a series resistor of 1k and 3.3nF (at pin). 13) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JESD22-C101F Notes 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 83 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.1.2 Functional Range Table 18 Functional Range Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number P_1.2.1 Supply voltage in Active Mode VS_AM 5.5 - 28 V - Extended supply voltage in Active Mode VS_AM_exte 28 - 40 V 1) Supply voltage in Active Mode for MOSFET Driver Supply VSD_AM 5.4 - 28 V Extended supply voltage in Active Mode for MOSFET Driver Supply VSD_AM_ext 28 - 32 V 1)3) Functional with parameter deviation P_1.2.17 Specified supply voltage for PWM interface VS_AM_PW 5.5 - 18 V Parameter Specification P_1.2.2 Extended supply voltage for PWM interface VS_AM_PW 4.8 - 28 V Functional with parameter deviation P_1.2.14 3.0 - 5.5 V 2) P_1.2.3 3.0 - 28 V - P_1.2.4 V/s 3) P_1.2.5 mA 3) P_1.2.7 P_1.2.15 P_1.2.9 nd end M_IO M_IO Supply voltage in Active Mode with VS_AMmin reduced functionality (Microcontroller / Flash with full operation) Supply voltage in Sleep Mode Supply voltage transients slew rate Output sum current for all GPIO pins VS_Sleep dVS/dt IGPIO,sum -1 - -50 - 1 50 Functional with P_1.2.16 parameter deviation P_1.2.18 Operating frequency fsys 5 - 24 MHz 4) Junction temperature Tj -40 - 150 C - 1) This operation voltage range is only allowed for a short duration: tmax 400 ms (continuous operation at this voltage is not allowed), fsys = 24 MHz, IVDDP = 10 mA, IVDDEXT = 5 mA. In addition, the power dissipation caused by the Charge Pump + MOSFET driver have to be considered. 2) Reduced functionality (e.g. cranking pulse) - Parameter deviation possible. 3) Not subject to production test, specified by design. 4) Function not specified when limits are exceeded. Data Sheet 84 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.1.3 Current Consumption Table 19 Electrical Characteristics VS = 5.5 V to 28 V, Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - 35 Number Current Consumption @VS pin Current consumption in Active Mode at pin VS IVs Current consumption in Active Mode at pin VSD IVSD - - 40 mA 20 kHz PWM on Bridge Driver P_1.3.8 Current consumption in Slow Down Mode ISDM_3P - - 35 mA fsys = 5 MHz; LIN communication P_1.3.19 Current consumption in Sleep Mode ISleep - 30 35 A System in Sleep Mode, P_1.3.3 microcontroller not powered, Wake capable via PWM interface and MON; MON connected to VS or GND; GPIOs open (no loads) or connected to GND: TJ = -40C to 85C; VS = 5.5 V to 18V;2) Current consumption in Sleep Mode extended range ISleep_exten - 90 200 A System in Sleep Mode, P_1.3.15 microcontroller not powered, Wake capable via PWM interface and MON; MON connected to VS or GND; GPIOs open (no loads) or connected to GND: TJ = -40C to 150C; VS = 5.5 V to 18V;2) Current consumption in Sleep Mode ISleep - 33 A System in Sleep Mode, P_1.3.9 microcontroller not powered, Wake capable via PWM interface and MON; MON connected to VS or GND; GPIOs open (no loads) or connected to GND: TJ = -40C to 40C; VS = 5.5 V to 18V;2) Data Sheet 30 mA fsys = 20 MHz P_1.3.1 no loads on pins, PWM interface in recessive state1) running; charge pump on (reverse polarity FET on), external Low Side FET static on (motor break mode); VDDEXT on; all other module set to power down;VS = 13.5V d - 85 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics Table 19 Electrical Characteristics (cont'd) VS = 5.5 V to 28 V, Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Number Current consumption in Sleep Mode with cyclic wake ICyclic - - 110 A TJ = -40C to 85C; VS = 5.5 V to 18V; tCyclic_ON = 4ms; tCyclic_OFF = 2048 ms;2) Current consumption in Stop Mode IStop - 110 160 A P_1.3.10 System in Stop Mode, microcontroller not clocked, Wake capable via PWM interface and MON; MON connected to VS or GND; GPIOs open (no loads) or connected to GND; TJ = 40C to 85C; VS = 5.5 V to 18V Current consumption in Stop Mode-Extended temperature range 1 IStop_extend - 600 1800 A P_1.3.20 System in Stop Mode, microcontroller not clocked, Wake capable via PWM interface and MON; MON connected to VS or GND; GPIOs open (no loads) or connected to GND; TJ = -40 C to 150 C; VS = 5.5 V to 18 V P_1.3.4 1) Current on VS, ADC1/2 active, timer running, PWM interface active (recessive). 2) Incl. leakage currents form VDH, VSD and MON Note: Within the functional range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Data Sheet 86 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.1.4 Thermal Resistance Table 20 Thermal Resistance Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Junction to Soldering Point RthJSP - 6 - K/W 1) measured to Exposed Pad P_1.4.1 Junction to Ambient RthJA - 33 - K/W 2) P_1.4.2 1) Not subject to production test, specified by design. 2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board. Board: 76.2x114.3x1.5mm with 2 inner copper layers (35m thick), with thermal via array under the exposed pad contacting the first inner copper layer and 300mm2 cooling area on the bottom layer (70m). 29.1.5 Timing Characteristics The transition times between the system modes are specified here. Generally the timings are defined from the time when the corresponding bits in register PMCON0 are set until the sequence is terminated. Table 21 System Timing1) VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number P_1.5.6 Wake-up over battery tstart - - 3 ms Battery ramp-up time to code execution Wake-up over battery tstartSW - - 1.5 ms Battery ramp-up time to till P_1.5.1 MCU reset is released; VS > 3 V and RESET = 1 Sleep-Exit tsleep - exit - - 1.5 ms P_1.5.2 Rising/falling edge of any wake-up signal (PWM interface, MON) till MCU reset is released; Sleep-Entry tsleep - - 330 s 2) - P_1.5.3 entry 1) Not subject to production test, specified by design. 2) Wake events during Sleep-Entry are stored and lead to wake-up after Sleep Mode is reached. Data Sheet 87 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.2 Power Management Unit (PMU) This chapter includes all electrical characteristics of the Power Management Unit 29.2.1 PMU I/O Supply (VDDP) Parameters This chapter describes all electrical parameters which are observable on SoC level. For this purpose only the padsupply VDDP and the transition times between the system modes are specified here. Table 22 Electrical Characteristics VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol IVDDP Specified output current IVDDP Specified output current CVDDP1 Required decoupling capacitance Required buffer capacitance for CVDDP2 stability (load jumps) Values Min. Typ. Max. 0 - 50 0 - 30 Unit Note / Test Condition Number mA 1) P_2.1.1 mA 1)2) P_2.1.22 0.47 - 2.2 F 3)4) 1 - 2.2 F 3)4) P_2.1.2 ESR < 1; the specified capacitor value is a typical value. The specified capacitor value is a typical value. Output voltage including line and load regulation @ Active Mode VDDPOUT 4.9 5.0 5.1 V 5) Output voltage including line and load regulation @ Active Mode VDDPOUT 4.9 5.0 5.1 V 2)5) Output voltage including line and load regulation @ Stop Mode VDDPOUTS 4.5 Output drop @ Active Mode VSVDDPout - P_2.1.20 Iload < 90mA; VS > 5.5V P_2.1.3 Iload < 70mA; VS > P_2.1.23 5.5V 5.0 5.5 V 5) Iload is only internal; VS > 5.5V P_2.1.21 50 400 mV IVDDP = 30mA6); 3.5V < VS < 5.0V P_2.1.4 Load regulation @ Active Mode VVDDPLOR -50 - 50 mV 2 ... 90mA; C = 570nF P_2.1.5 Line regulation @ Active Mode VVDDPLIR -50 - 50 mV VS = 5.5 ... 28V P_2.1.6 5.14 - 5.4 V VS > 5.5V; Overvoltage P_2.1.7 TOP VDDPOV Overvoltage detection leads to SUPPLY_NMI Overvoltage detection filter time tFILT_VDDP - 735 - s 3)7) P_2.1.24 3 - V 3) P_2.1.25 P_2.1.26 OV VDDPOK Voltage OK detection 8) - Voltage stable detection range VDDPSTB - 220 - + 220 mV 3) Undervoltage reset VDDPUV 2.5 2.6 2.7 V - P_2.1.8 Overcurrent diagnostic IVDDPOC 91 - 220 mA - P_2.1.9 Data Sheet 88 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics Table 22 Electrical Characteristics (cont'd) VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Overcurrent diagnostic filter time tFILT_VDDP - Overcurrent diagnostic shutdown time tFILT_VDDP - 1) 2) 3) 4) 5) 6) 7) 8) 9) Unit Note / Test Condition Number Typ. Max. 27 - s 3)7) P_2.1.27 290 - s 3)7)9) P_2.1.28 OC OC_SD Specified output current for port supply and additional other external loads already excluding VDDC current. This use case applies to cases where output current on VDDEXT is max. 40 mA. Not subject to production test, specified by design. Ceramic capacitor. Load current includes internal supply. Output drop for IVDDP without internal supply current. This filter time and its variation is derived from the time base tLP_CLK = 1 / fLP_CLK. The absolute voltage value is the sum of parameters VDDP + VDDPSTB. After tFILT_VDDCOC_SD is passed and the overcurrent condition is still present, the device will enter sleep mode. Data Sheet 89 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.2.2 PMU Core Supply (VDDC) Parameters This chapter describes all electrical parameters which are observable on SoC level. For this purpose only the coresupply VDDC and the transition times between the system modes are specified here. Table 23 Electrical Characteristics VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Required decoupling capacitance CVDDC1 0.1 - 1 F 1)2) ESR < 1; the specified capacitor value is a typical value. P_2.2.1 Required buffer capacitance for stability (load jumps) CVDDC2 0.33 - 1 F 2) the specified capacitor value is a typical value. P_2.2.17 Output voltage including line regulation @ Active Mode VDDCOUT 1.44 1.5 1.56 V Iload < 40mA P_2.2.2 Reduced output voltage including line regulation @ Stop Mode VDDCOUT_ 0.95 1.1 1.3 V with internal VDDC load only: Iload_internal < 1.5mA P_2.2.23 Load Regulation @ Active Mode VDDCLOR -50 - 50 mV 2 ... 40mA; C =430nF P_2.2.3 Line regulation @ Active Mode VDDCLIR -25 - 25 mV VDDP = 2.5 ... 5.5V Overvoltage detection VDDCOV 1.59 1.62 1.68 V Overvoltage leads to P_2.2.5 SUPPLY_NMI Overvoltage detection filter time tFILT_VDDC - 735 - s 1)3) P_2.2.18 Voltage OK detection range4) VDDCOK - + 280 mV 1) P_2.2.19 + 110 mV 1) P_2.2.20 Stop_Red P_2.2.4 OV 5) - 280 Voltage stable detection range VDDCSTB - 110 Undervoltage reset VDDVUV 1.136 1.20 1.264 V - P_2.2.6 Overcurrent diagnostic IVDDCOC 45 100 mA - P_2.2.7 P_2.2.21 P_2.2.22 Overcurrent diagnostic filter time tFILT_VDDC - Overcurrent diagnostic shutdown time tFILT_VDDC - - - 27 - s 1)3) 290 - s 1)3)6) OC 1) 2) 3) 4) 5) 6) OC_SD Not subject to production test, specified by design. Ceramic capacitor. This filter time and its variation is derived from the time base tLP_CLK = 1 / fLP_CLK. The absolute voltage value is the sum of parameters VDDC + VDDCSTB. The absolute voltage value is the sum of parameters VDDC + VDDCOK. After tFILT_VDDCOC_SD is passed and the overcurrent condition is still present the device will enter sleep mode. Data Sheet 90 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.2.3 VDDEXT Voltage Regulator (5.0V) Parameters Table 24 Electrical Characteristics VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Specified output current IVDDEXT 0 - 20 mA - P_2.3.1 Specified output current IVDDEXT 0 - 40 mA 1) P_2.3.21 3) 2) Required decoupling capacitance CVDDEXT1 0.1 - 2.2 F ESR < 1 ; the specified capacitor value is a typical value. P_2.3.22 Required buffer capacitance for stability (load jumps) CVDDEXT2 1 - 2.2 F 3)2) the specified capacitor value is a typical value. P_2.3.20 Output voltage including line and load regulation VDDEXT 4.9 5.0 5.1 V 3) P_2.3.3 Output voltage including line and load regulation VDDEXT Output drop @ Active Mode VS-VDDEXT 50 +300 mV 3) Iload < 20mA; 3V < VS < 5.0V P_2.3.4 Output drop @ Active Mode VS-VDDEXT - +400 mV Iload < 40mA; 3V < VS < 5.0V P_2.3.14 Load regulation @ Active Mode VDDEXTLOR -50 - 50 mV 2 ... 40mA; C =200nF P_2.3.5 Line regulation @ Active Mode VVDDEXTLIR -50 - 50 mV VS = 5.5 ... 28V 3) Iload<20mA; VS > 5.5V 4.8 5.0 5.2 V Iload<40mA; VS > P_2.3.23 5.5V P_2.3.6 Power supply ripple rejection @ Active Mode PSSRVDDEXT 50 - - dB VS = 13.5V; f =0 ... P_2.3.7 1KHz; Vr=2Vpp Overvoltage detection VVDDEXTOV - 5.4 V VS > 5.5V P_2.3.8 P_2.3.24 Overvoltage detection filter time 5.18 tFILT_VDDEXT - 735 - s 3)4) 3 - V 3) P_2.3.25 P_2.3.26 OV VVDDEXTOK Voltage OK detection range 5) - - + 220 mV 3) 2.6 2.8 3.0 V 6) P_2.3.9 50 - 160 mA - P_2.3.10 27 - s 3)4) P_2.3.27 s 3)4) P_2.3.28 Voltage stable detection range VVDDEXTST - 220 Undervoltage trigger VVDDEXTUV Overcurrent diagnostic IVDDEXTOC Overcurrent diagnostic filter time tFILT_VDDCOC - B Overcurrent diagnostic shutdown tFILT_VDDCOC - time _SD 1) 2) 3) 4) 290 - This use case requires the reduced utilization of VDDP output current by 20 mA, see P_2.1.22. Ceramic capacitor. Not subject to production test, specified by design. This filter time and its variation is derived from the time base tLP_CLK = 1 / fLP_CLK. Data Sheet 91 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 5) The absolute voltage value is the sum of parameters VDDEXT + VDDEXTSTB. 6) When the condition is met, the Bit VDDEXT_CTRL.bit.SHORT will be set. Data Sheet 92 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.2.4 VPRE Voltage Regulator (PMU Subblock) Parameters The PMU VPRE Regulator acts as a supply of VDDP and VDDEXT voltage regulators. Table 25 Functional Range Parameter Symbol Specified output current IVPRE Values Min. Typ. Max. - - 110 Unit Note / Test Condition Number mA 1) P_2.4.1 1) Not subject to production test, specified by design. 29.2.4.1 Load Sharing Scenarios of VPRE Regulator The figure below shows the possible load sharing scenarios of VPRE regulator. VS VPRE max. 110 mA VDDEXT VDDEXT - 5V 1: max. 20 mA 2: max. 40 mA VDDP - 5V 1: max. 90 mA 2: max. 70 mA VDDP CVDDEXT CVDDP GND (Pin 39) GND (Pin 39) VDDC VDDC - 1.5V max. 40 mA CVDDC GND (Pin 39) Load Sharing VPRE - Scenarios 1 & 2 Load_Sharing_VPRE.vsd Figure 33 Data Sheet Load Sharing Scenarios of VPRE Regulator 93 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.2.5 Power Down Voltage Regulator (PMU Subblock) Parameters The PMU Power Down voltage regulator consists of two subblocks: * * Power Down Pre regulator: VDD5VPD Power Down Core regulator: VDD1V5_PD (Supply used for GPUDATAxy registers) Both regulators are used as purely internal supplies. The following table contains all relevant parameters: Table 26 Functional Range Parameter Symbol Values Min. Typ. Max. - 1.5 Unit Note / Test Condition Number V 1) VDD1V5_PD Power-On Reset Threshold VDD1V5_PD_ 1.2 P_2.5.1 RSTTH 1) Not subject to production test, specified by design Data Sheet 94 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.3 System Clocks 29.3.1 Oscillators and PLL Parameters Table 27 Electrical Characteristics System Clocks VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Unit Note / Test Condition Number Typ. Max. 14 18 22 MHz This clock is used at startup P_3.1.1 and can be used in case the PLL fails 70 100 130 kHz This clock is used for cyclic P_3.1.2 wake PMU Oscillators (Power Management Unit) Frequency of LP_CLK fLP_CLK Frequency of LP_CLK2 fLP_CLK2 CGU Oscillator (Clock Generation Unit Microcontroller) Short term frequency deviation1) fTRIMST -0.4 - +0.4 % 2)3) Within any 10 ms, e.g. after synchronization to a PWM signal (PLL settings untouched within 10 ms) P_3.1.3 Absolute accuracy fTRIMABSA -1.5 - +1.5 % Including temperature and lifetime deviation P_3.1.4 CGU-OSC Start-up time tOSC - - 10 s 3) P_3.1.5 Startup time OSC from Sleep Mode, power supply stable PLL (Clock Generation Unit Microcontroller) 3) VCO frequency range Mode 0 fVCO-0 48 - 112 MHz VCOSEL ="0" P_3.1.6 VCO frequency range Mode 1 fVCO-1 96 - 160 MHz VCOSEL ="1" P_3.1.7 Input frequency range fOSC 4 - 16 MHz - P_3.1.8 XTAL1 input freq. range fOSC 4 - 16 MHz - P_3.1.9 0.04687 - 80 MHz - P_3.1.10 Free-running frequency fVCOfree_0 Mode 0 - - 38 MHz VCOSEL ="0" P_3.1.11 Free-running frequency fVCOfree_1 Mode 1 - - 76 MHz VCOSEL ="1" P_3.1.12 P_3.1.13 Output freq. range fPLL Input clock high/low time thigh/low 10 - - ns - Peak period jitter tjp -500 - 500 ps 4) for K=1 P_3.1.14 Accumulated jitter jacc - - 5 ns 4) for K=1 P_3.1.15 Lock-in time tL - - 200 s - Data Sheet 95 P_3.1.16 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 1) 2) 3) 4) The typical oscillator frequency is 5 MHz VDDC = 1.5 V, Tj = 25C Not subject to production test, specified by design. This parameter is valid for PLL operation with an external clock source and thus reflects the real PLL performance. 29.3.2 External Clock Parameters XTAL1, XTAL2 Table 28 Functional Range VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)1) Parameter Symbol Values Max. Unit Note / Test Condition -1.7 + VDDC - 1.7 V 2) P_3.2.1 0.3 x VDDC - - V 3) Peak-to-peak voltage P_3.2.2 0 V < VIN < VDDI P_3.2.3 Min. Input voltage range limits for signal on XTAL1 VIX1_SR Input voltage (amplitude) on VAX1_SR XTAL1 Typ. Number XTAL1 input current IIL - - 20 A Oscillator frequency fOSC 4 - 24 MHz Clock signal P_3.2.4 Oscillator frequency fOSC 4 - 16 MHz Crystal or Resonator P_3.2.5 High time t1 6 - - ns - P_3.2.6 Low time t2 6 - - ns - P_3.2.7 Rise time t3 - 8 8 ns - P_3.2.8 Fall time t4 - 8 8 ns - P_3.2.9 1) This parameter table is not subject to production test, specified by design. 2) Overload conditions must not occur on pin XTAL1. 3) The amplitude voltage VAX1 refers to the offset voltage VOFF. This offset voltage must be stable during the operation and the resulting voltage peaks must remain within the limits defined by VIX1. Data Sheet 96 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.4 Flash Memory This chapter includes the parameters for the 36 kByte embedded flash module. 29.4.1 Flash Parameters Table 29 Flash Characteristics1) VS = 3.0 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Programming time per 128 byte page tPR Typ. - Unit Note / Number Test Condition Max. 3 2) 3.5 ms 3V < VS < 28V P_4.1.1 2) 4.5 ms 3V < VS < 28V P_4.1.2 Erase time per sector/page tER - 4 Data retention time tRET 20 - - years 1,000 erase / P_4.1.3 program cycles Data retention time tRET 50 - - years 1,000 erase / P_4.1.9 program cycles Tj = 30C3) Flash erase endurance for user sectors NER 30 - - kcycles Data retention time 5 years Flash erase endurance for security pages NSEC 10 - - cycles 4) Drain disturb limit NDD 32 - - kcycles 5) P_4.1.4 Data retention P_4.1.5 time 20 years P_4.1.6 1) Not subject for production test, specified by design. 2) Programming and erase times depend on the internal Flash clock source. The control state machine needs a few system clock cycles. The requirement is only relevant for extremely low system frequencies. 3) Derived by extrapolation of lifetime tests. 4) Tj = 25 C. 5) This parameter limits the number of subsequent programming operations within a physical sector without a given page in this sector being (re-)programmed. The drain disturb limit is applicable if wordline erase is used repeatedly. For normal sector erase/program cycles this limit will not be violated. For data sectors the integrated EEPROM emulation firmware routines handle this limit automatically, for wordline erases in code sectors (without EEPROM emulation) it is recommended to execute a software based refresh, which may make use of the integrated random number generator NVMBRNG to statistically start a refresh. Data Sheet 97 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.5 Parallel Ports (GPIO) 29.5.1 Description of Keep and Force Current VDDP keeper current PU Device PUDSEL P1.x P0.x \PUDSEL keeper current PD Device VSS Pull- Up- Down.vsd Figure 34 Pull-Up/Down Device UGPIO Logical "1" 7.5 kOhm (equivalent) (1.5V / 200uA) VIH - VDDP Undefined 2.33 kOhm (equivalent) (3.5V / 1.5mA) VIL - VDDP Logical "0" -I PLF Figure 35 Data Sheet I -IPLK Current_Diag.vsd Pull-Up Keep and Forced Current 98 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics UGPIO Logical "1" 2.33 kOhm (equivalent) (3.5V / 1.5mA) VIH Undefined 7.5 kOhm (equivalent) (1.5V / 200uA) VIL Logical "0" IPLK I I PLF Current_Diag-Pull _down.vsd Figure 36 Pull-Down Keep and Force Current 29.5.2 DC Parameters of Port 0, Port 1, TMS and Reset Note: Operating Conditions apply. Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the maximum allowed ocurrent which can be taken out of VDDP. Table 30 Current Limits for Port Output Drivers1) Port Output Driver Mode Maximum Output Current (IOLmax , - IOHmax) VDDP 4.5V Strong driver2) Medium driver Weak driver 3) 3) Maximum Output Current (IOLnom , - IOHnom) Number 2.6V < VDDP < VDDP 4.5V 4.5V 2.6V < VDDP < 4.5V 5 mA 3 mA 1.6 mA 1.0 mA P_5.1.15 3 mA 1.8 mA 1.0 mA 0.8 mA P_5.1.1 0.5 mA 0.3 mA 0.25 mA 0.15 mA P_5.1.2 1) Not subject to production test, specified by design. 2) Not available for port pins P0.4, P1.0, P1.1 and P1.2 3) All P0.x and P1.x Table 31 DC Characteristics Port0, Port1 VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Input hysteresis HYSP0_P1 0.11 x VDDP - - V 1) Input hysteresis HYSP0_P1 - - V 1) _exend Data Sheet 0.09 x VDDP 99 Number P_5.1.5 Series resistance = 0 ; 4.5V VDDP 5.5V P_5.1.16 Series resistance = 0 ; 2.6V VDDP 4.5V Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics Table 31 DC Characteristics Port0, Port1 (cont'd) VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Input low voltage VIL -0.3 - 0.3 x VDDP V 2) 4.5V VDDP 5.5V P_5.1.3 Input low voltage VIL_extend -0.3 0.42 x - V 1) 2.6V VDDP 4.5V P_5.1.17 Input high voltage VIH 0.7 x VDDP - VDDP + 0.3 V 2) 4.5V VDDP 5.5V P_5.1.4 Input high voltage VIH_extend - 0.52 x VDDP + 0.3 V 1) 2.6V VDDP 4.5V P_5.1.18 Output low voltage VOL - - 1.0 V 3) 4) IOL IOLmax P_5.1.6 Output low voltage VOL - - 0.4 V 3) 5) IOL IOLnom P_5.1.7 V 3) 4) IOH IOHmax P_5.1.8 IOH IOHnom P_5.1.9 Output high voltage VOH VDDP VDDP - 1.0 VDDP - - - - V 3) 5) IOZ_extend1 -500 - +500 nA -40C TJ 25C, 0.45 V < VIN < VDDP P_5.1.20 IOZ1 - +5 A 6) P_5.1.10 Output high voltage VOH Input leakage current Input leakage current VDDP - 0.4 -5 25C < TJ 85C, 0.45 V < VIN < VDDP Input leakage current IOZ_extend2 -15 - +15 A 85C < TJ 150C, 0.45 V < VIN < VDDP P_5.1.11 Pull level keep current IPLK -200 - +200 A 7) VPIN VIH (up) VPIN VIL (dn) P_5.1.12 Pull level force current IPLF -1.5 - +1.5 mA 7) VPIN VIL (up) VPIN VIH (dn) P_5.1.13 Pin capacitance CIO - - 10 pF 1) P_5.1.14 - 5 - s 1) P_5.1.19 Reset Pin Timing Reset Pin Input Filter Time tfilt_RESET 1) Not subject to production test, specified by design. 2) Tested at VDDP = 5V, specified for 4.5V < VDDP < 5.5V. 3) The maximum deliverable output current of a port driver depends on the selected output driver mode. The limit for pin groups must be respected. 4) Tested at 4.9V < VDDP < 5.1V, IOL = 4mA, IOH = -4mA, specified for 4.5V < VDDP < 5.5V. 5) As a rule, with decreasing output current the output levels approach the respective supply level (VOLGND, VOHVDDP). Tested at 4.9V < VDDP < 5.1V, IOL = 1mA, IOH = -1mA. Data Sheet 100 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 6) The given values are worst-case values. In production tests, this leakage current is only tested at 150C; other values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating depending on temperature (TJ = junction temperature [C]): IOZ = 0.05 x e(1.5 + 0.028xTJ) [A]. For example, at a temperature of 95C the resulting leakage current is 3.2 A. Leakage derating depending on voltage level (DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 x DV) [A] This voltage derating formula is an approximation which applies for maximum temperature. 7) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level: VPIN VIH for a pull-up; VPIN VIL for a pull-down. Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device: VPIN VIL for a pull-up; VPIN VIH for a pull-down. These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general purpose IO pins. 29.5.3 DC Parameters of Port 2 These parameters apply to the IO voltage range, 4.5 V VDDP 5.5 V. Note: Operating Conditions apply. Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current IOV. Table 32 DC Characteristics Port 2 VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Input low voltage VIL -0.3 - 0.3 x VDDP V 1) 4.5V VDDP 5.5V P_5.2.1 Input low voltage VIL_extend -0.3 0.42 x - V 2) 2.6V VDDP 4.5V P_5.2.10 Input high voltage VIH 0.7 x VDDP - VDDP + 0.3 V 1) 4.5V VDDP 5.5V P_5.2.2 Input high voltage VIH_extend - 0.52 x VDDP + 0.3 V 2) P_5.2.11 - V 2) - V 2) VDDP VDDP 0.11 x VDDP - Input hysteresis HYSP2 Input hysteresis HYSP2_ext - end 0.09 x VDDP 2.6V VDDP 4.5V P_5.2.3 Series resistance = 0 ; 4.5V VDDP 5.5V P_5.2.12 Series resistance = 0 ; 2.6V VDDP < 4.5V Input leakage current IOZ2 -400 - +400 nA TJ 85C, 0 V < VIN < VDDP P_5.2.4 Pull level keep current IPLK -30 - +30 A 3) P_5.2.5 Data Sheet 101 VPIN VIH (up) VPIN VIL (dn) Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics Table 32 DC Characteristics Port 2 (cont'd) VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Pull level force current Symbol IPLF Values Min. Typ. Max. Unit Note / Test Condition -750 - +750 A 3) VPIN VIL (up) VPIN VIH (dn) P_5.2.6 10 pF 2) P_5.2.7 CIO - - Pin capacitance (digital inputs/outputs) 1) Tested at VDDP = 5V, specified for 4.5V < VDDP < 5.5V. Number 2) Not subject to production test, specified by design. 3) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level: VPIN VIH for a pull-up; VPIN VIL for a pull-down. Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device: VPIN VIL for a pull-up; VPIN VIH for a pull-down. Data Sheet 102 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.6 PWM Interface 29.6.1 Electrical Characteristics Table 33 Electrical Characteristics PWM Interface Vs = 5.5V to 18V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note / Test Condition Number Max. Bus Receiver Interface Receiver threshold voltage, Vth_dom recessive to dominant edge Receiver dominant state VBUSdom -27 Receiver threshold voltage, Vth_rec dominant to recessive edge Receiver recessive state 0.4 xVS 0.45 xVS 0.53 x VS V VBUSrec 0.47 x VS SAE J2602 P_6.1.1 0.4 xVS V - P_6.1.2 0.55 xVS 0.6 xVS V SAE J2602 P_6.1.3 1.15 xVS V 1) P_6.1.4 0.525 x VS V 2) P_6.1.5 - 0.6 xVS - Receiver center voltage VBUS_CN 0.475 x VS T Receiver hysteresis VHYS 0.07 VS 0.12 xVS 0.175 x VS V 3) P_6.1.6 Wake-up threshold voltage VBUS,wk 0.4 xVS 0.5 xVS 0.6 xVS V - P_6.1.7 3 - 15 s P_6.1.8 The overall dominant time for bus wake-up is a sum of tWK,bus + adjustable digital filter time. Dominant time for bus wake- tWK,bus up (internal analog filter delay) 0.5 xVS Bus Transmitter Interface Bus recessive output voltage VBUS,ro 0.8 xVS - VS V VTxD = high Level P_6.1.9 Bus short circuit current IBUS,sc 40 100 150 mA Current Limitation for driver dominant state driver on VBUS = 18 V; P_6.1.10 Bus short circuit filter time tBUS,sc - 5 - s 8) Leakage current (loss of ground) IBUS_NO_ -1000 -450 1000 A VS = 12 V; 0 < VBUS < 18 V; P_6.1.11 Leakage current IBUS_NO_ - 10 20 A VS = 0 V; VBUS = 18 V; P_6.1.12 GND The overall bus short P_6.1.71 circuit filter time is a sum of tBUS,sc + digital filter time. The digital filter time is 4 s (typ.) BAT Data Sheet 103 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics Table 33 Electrical Characteristics PWM Interface (cont'd) Vs = 5.5V to 18V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Leakage current IBUS_PAS -1 Leakage current IBUS_PAS - Unit Note / Test Condition Number Typ. Max. - - mA VS = 18 V; VBUS = 0 V; P_6.1.13 - 20 A VS = 8 V; VBUS = 18 V; P_6.1.14 30 47 k Normal mode P_6.1.15 - 7) VS > 5.5 V, Ids = 150 mA, Tj = 27C; P_6.1.72 _dom _rec Bus pull-up resistance ON-State Resistance RBUS RON 20 - 20 AC Characteristics - Transceiver Normal Slope Mode td(L),R 0.1 - 6 s - P_6.1.16 td(H),R Propagation delay bus recessive to RxD HIGH 0.1 - 6 s - P_6.1.17 -2 - 2 s tsym,R = td(L),R - td(H),R; P_6.1.18 4) P_6.1.19 Propagation delay bus dominant to RxD LOW Receiver delay symmetry tsym,R Duty cycle D1 Normal Slope Mode (for worst case at 20 kbit/s) tduty1 0.396 - - duty cycle 1 THRec(max) = 0.744 xVS; THDom(max) = 0.581 xVS; VS = 5.5 ... 18 V; tbit = 50 s; D1 = tbus_rec(min)/2 tbit; Duty cycle D2 Normal Slope Mode (for worst case at 20 kbit/s) tduty2 - - 0.581 4) duty cycle 2 P_6.1.20 THRec(min) = 0.422 xVS; THDom(min) = 0.284 xVS; VS = 5.5 ... 18 V; tbit = 50 s; D2 = tbus_rec(max)/2 tbit; AC Characteristics - Transceiver Low Slope Mode td(L),R 0.1 - 6 s - P_6.1.21 td(H),R Propagation delay bus recessive to RxD HIGH 0.1 - 6 s - P_6.1.22 -2 - 2 s tsym,R = td(L),R - td(H),R; P_6.1.23 Propagation delay bus dominant to RxD LOW Receiver delay symmetry Data Sheet tsym,R 104 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics Table 33 Electrical Characteristics PWM Interface (cont'd) Vs = 5.5V to 18V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. 4) Duty cycle D3 (for worst case at 10.4 kbit/s) tduty1 0.417 - - duty cycle 3 THRec(max) = 0.778 xVS; THDom(max) = 0.616 xVS; VS = 5.5 ... 18 V; tbit = 96 s; D3 = tbus_rec(min)/2 tbit; Duty cycle D4 (for worst case at 10.4 kbit/s) tduty2 - - 0.590 4) Number P_6.1.24 duty cycle 4 P_6.1.25 THRec(min) = 0.389 xVS; THDom(min) = 0.251 xVS; VS = 5.5 ... 18 V; tbit = 96 s; D4 = tbus_rec(max)/2 tbit AC Characteristics - Transceiver Fast Slope Mode td(L),R 0.1 - 6 s - P_6.1.26 td(H),R Propagation delay bus recessive to RxD HIGH 0.1 - 6 s - P_6.1.27 -1.5 - 1.5 s tsym,R = td(L),R - td(H),R; P_6.1.28 td(L),R 0.1 - 6 s - P_6.1.31 Propagation delay td(H),R bus recessive to RxD HIGH 0.1 - 6 s - P_6.1.32 -1.0 - 1.5 s tsym,R = td(L),R - td(H),R; P_6.1.33 Propagation delay bus dominant to RxD LOW Receiver delay symmetry tsym,R AC Characteristics - Flash Mode Propagation delay bus dominant to RxD LOW Receiver delay symmetry tsym,R 5) Duty cycle D7 (for worst case at 115 kbit/s) for +1 s Receiver delay symmetry tduty1 0.399 - - duty cycle D7 P_6.1.34 THRec(max) = 0.744 xVS; THDom(max) = 0.581 xVS; VS = 13.5 V; tbit = 8.7 s; D7 = tbus_rec(min)/2 tbit; Duty cycle D8 (for worst case at 115 kbit/s) for +1 s Receiver delay symmetry tduty2 - - 0.578 6) PWM interface input capacity CPWM_IN - 15 30 Data Sheet 105 P_6.1.35 duty cycle 8 THRec(min) = 0.422 xVS; THDom(min) = 0.284 xVS;VS = 13.5 V; tbit = 8.7 s; D8 = tbus_rec(max)/2 tbit; pF 6) P_6.1.69 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics Table 33 Electrical Characteristics PWM Interface (cont'd) Vs = 5.5V to 18V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter TxD dominant time out Symbol ttimeout Values Unit Note / Test Condition Number Min. Typ. Max. 6 12 20 ms VTxD = 0 V P_6.1.36 200 215 C 7) P_6.1.65 K 7) P_6.1.66 Thermal Shutdown (Junction Temperature) Thermal shutdown temp. Thermal shutdown hyst. 1) 2) 3) 4) TjSD T 190 - 10 - Maximum limit specified by design. VBUS_CNT = (Vth_dom +Vth rec)/2 VHYS = VBUSrec - VBUSdom Bus load : Load 1 = 1 nF / 1 k = CBUS / RBUS Load 2 = 6.8 nF / 660 = CBUS / RBUS Load 3 = 10 nF / 500 = CBUS / RBUS 5) Bus load Load 1 = 1 nF / 500 = CBUS / RBUS 6) Not subject to production test, specified by design. Data Sheet 106 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.7 High-Speed Synchronous Serial Interface 29.7.1 SSC Timing Parameters The table below provides the SSC timing in the TLE9871QXA20. Table 34 SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF) VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Max. Note / Number Test Condition - 2) VDDP > 2.7 V P_7.1.1 - ns 2) VDDP > 2.7 V P_7.1.2 ns 2) VDDP > 2.7 V P_7.1.3 MRST hold from SCLK t3 15 - - ns 1) TSSCmin = TCPU = 1/fCPU. If fCPU = 20 MHz, t0 = 100 ns. TCPU is the CPU clock period. 2) VDDP > 2.7 V P_7.1.4 1) t0 SCLK clock period t1 MTSR delay from SCLK 10 t2 MRST setup to SCLK 2 * TSSC - - 10 - - 2) Not subject to production test, specified by design. t0 SCLK1) t1 t1 MTSR1) t2 t3 Data valid MRST1) t1 1) This timing is based on the following setup: CON.PH = CON.PO = 0. SSC_Tmg1 Figure 37 Data Sheet SSC Master Mode Timing 107 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.8 Measurement Unit 29.8.1 System Voltage Measurement Parameters Table 35 Supply Voltage Signal Conditioning VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. 0 - 5 V - P_8.1.15 0 - 1.23 V - P_8.1.16 ATTVS_1 - 0.055 - SFR setting 1 P_8.1.41 Nominal operating input voltage range VS VS,range1 3 - 22 V 1) P_8.1.1 Accuracy of VS after calibration VS,range1 -220 - 220 mV SFR setting 1, VS = 5.5 V P_8.1.70 to 18V Input to output voltage attenuation: ATTVS_2 - 0.039 - Nominal operating input voltage range VS VS,range2 3 - 31 V 1) Accuracy of VS after calibration VS,range2 -370 - 370 mV SFR setting 2, VS = 5.5V to 18V P_8.1.44 - P_8.1.21 Measurement output VA5 voltage range @ VAREF5 Measurement output voltage range @ VAREF1V2 VA1V2 Battery / Supply Voltage Measurement Input to output voltage attenuation: VS SFR setting 1; Max. value corresponds to typ. ADC full scale input; 3V < VS < 28V SFR setting 2 P_8.1.42 VS P_8.1.40 SFR setting 2; Max. value corresponds to typ. ADC full scale input 3V < VS < 28V Driver Supply Voltage Measurement VSD ATTVSD - 0.039 - Nominal operating input voltage range VSD VSD,range 2.5 - 31 V 1) P_8.1.2 Accuracy of VSD sense after calibration VSD -440 - 440 mV VS = 5.5V to 18V P_8.1.47 Input to output voltage attenuation: VSD Data Sheet 108 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics Table 35 Supply Voltage Signal Conditioning (cont'd) VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. Number Charge Pump Voltage Measurement VCP ATTVCP - 0.023 - Nominal operating input voltage range VCP VCP,range 2.5 - 52 Accuracy of VCP sense after calibration VCP -747 - 747 Input to output voltage attenuation: - P_8.1.56 V 1) P_8.1.7 mV VS = 5.5V to 18V P_8.1.62 - P_8.1.49 VCP Monitoring Input Voltage Measurement VMON ATTVMON - 0.039 - Nominal operating input voltage range VMON VMON,range 2.5 - 31 V 1) P_8.1.8 Accuracy of VMON sense after calibration VMON -440 - 440 mV VS = 5.5V to 18V P_8.1.68 ATTVDDP - 0.164 - - P_8.1.33 Nominal operating input voltage range VDDP VDDP,range 0 - 7.50 V 1) P_8.1.50 Accuracy of VDDP sense after calibration VDDP_SENSE -105 - 105 mV 2) P_8.1.5 - P_8.1.22 Input to output voltage attenuation: VMON Pad Supply Voltage Measurement VVDDP Input-to-output voltage attenuation: VDDP VS = 5.5 to 18V 10-Bit ADC Reference Voltage Measurement VAREF ATTVAREF - 0.219 - Nominal operating input voltage range VAREF VAREF,range 0 - 5.62 V 1) P_8.1.51 Accuracy of VAREF sense after calibration VAREF -79 - 79 mV VS = 5.5V to 18V P_8.1.48 - P_8.1.57 1) P_8.1.52 Input to output voltage attenuation: VAREF 8-Bit ADC Reference Voltage Measurement VBG Input-to-output voltage attenuation: ATTVBG - 0.75 - VBG,range 0.8 - 1.64 VBG Nominal operating input voltage range VBG Data Sheet 109 V Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics Table 35 Supply Voltage Signal Conditioning (cont'd) VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. 1.01 1.07 1.18 ATTVDDC - 0.75 - Nominal operating input voltage range VDDC VDDC,range 0.8 - 1.64 Accuracy of VDDC sense after calibration VDDC_SENSE -22 - 22 Value of ADC2-VBG measurement after calibration VBG_PMU Unit Note / Test Condition Number V P_8.1.73 Core supply Voltage Measurement VDDC Input-to-output voltage attenuation: - P_8.1.34 V 1) P_8.1.53 mV VS = 5.5 to 18V P_8.1.6 VDDC VDH Input Voltage Measurement VVDH10BITADC VDH Input to output voltage attenuation: ATTVDH_1 - 0.166 - SFR setting 1 P_8.1.64 VDH Input to output voltage attenuation: ATTVDH_2 - 0.224 - SFR setting 2 P_8.1.65 VDH Input to output voltage attenuation: ATTVDH_3 - 0.226 - 1) SFR setting 2 Tj = -40..85C P_8.1.75 VVDH,range1 Nominal operating input voltage range VVDH, Range 1 - - 30 SFR setting 1 P_8.1.66 VVDH,range2 Nominal operating input voltage range VVDH, Range 2 - - 20 SFR setting 2 P_8.1.67 VVDH 10-bit ADC, Range 1 VVDHADC10B -300 - 300 mV VDH= 5.5 to 17.5V, Tj = -40..150C P_8.1.39 VVDH 10-bit ADC, Range 3 VVDHADC10B -200 - 200 mV 1) P_8.1.71 VDH= 5.5V to 17.5V, Tj = -40..85C ATTVDH_3 VVDH 10-bit ADC, Range 2 VVDHADC10B_ex -400 - 400 mV VDH= 5.5V to 17.5V, Tj = -40..150C P_8.1.74 390 470 k PD_N=1 (on-state) P_8.1.3 2.0 A PD_N=0 (off-state), P_8.1.10 tend_T 10-Bit ADC measurement input resistance for VDH Rin_VDH,measure Measurement input leakage current for VVDH Ileak_VDH, measure -0.05 - 200 1) Not subject to production test, specified by design. 2) Accuracy is valid for a calibrated device. Data Sheet 110 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.8.2 Central Temperature Sensor Parameters Table 36 Electrical Characteristics Temperature Sensor Module VS = 3.0 V to 28 V, Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Output voltage VTEMP at T0=273 K (0C) a Temperature sensitivity b b Accuracy_1 Accuracy_2 Accuracy_3 Values Min. Typ. Max. - 0.666 - Unit Note / Test Condition Number V 1) P_8.2.2 T0=273 K (0C) Acc_1 Acc_2 Acc_3 - -10 -10 -5 2.31 - - - - 10 10 5 mV/K 1) C 2)1) -40C < Tj < 85C P_8.2.5 C 2)1) 125C < Tj < 150C P_8.2.6 C 2)1) 85C < Tj < 125C P_8.2.7 P_8.2.4 1) Not subject to production test, specified by design 2) Accuracy with reference to on-chip temperature calibration measurement, valid for Mode1 Data Sheet 111 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.8.3 ADC2-VBG 29.8.3.1 ADC2 Reference Voltage VBG Table 37 DC Specifications VS = 3.0 V to 28 V, Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol VBG Reference Voltage Values Min. Typ. Max. 1.199 1.211 1.223 Unit Note / Test Condition Number V 1) P_8.3.1 1) Not subject to production test, spedesign 29.8.3.2 ADC2 Specifications Table 38 DC Specifications VS = 5.5 V to 28 V, Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. - 8 - Bits Full P_8.3.18 0.3 2.0 LSB not calibrated P_8.3.19 0.5 2.0 %FSR not calibrated P_8.3.20 0 0.8 LSB Full P_8.3.21 0 1.2 LSB - P_8.3.22 Resolution RES Guaranteed offset error EAOFF_8 -2.0 Bit Gain error EAGain_8 -2.0 Bit Differential non-linearity (DNL) EADNL_8 -0.8 Bit Integral non-linearity (INL) EAINL_8Bi -1.2 t Data Sheet 112 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.9 ADC1 Reference Voltage - VAREF 29.9.1 Electrical Characteristics VAREF Table 39 Electrical Characteristics VAREF VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Required buffer capacitance CVAREF 0.1 - 1 F ESR < 1 P_9.1.1 Reference output voltage VAREF 4.95 5 5.05 V VS > 5.5V P_9.1.2 P_9.1.3 DC supply voltage rejection DCPSRVAREF 30 - - dB 1) Supply voltage ripple rejection ACPSRVAREF 26 - - dB 1) Turn ON time tso - - 200 s 1) - 100 - k 1) Input resistance at VAREF RIN,VAREF Pin - VS = 13.5V; f = 0 ... 1KHz; P_9.1.4 Vr = 2Vpp Cext = 100nF P_9.1.5 PD_N to 99.9% of final value input impedance in case of P_9.1.20 VAREF is applied from external 1) Not subject to production test, specified by design. Data Sheet 113 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.9.2 Electrical Characteristics ADC1 (10-Bit) These parameters describe the conditions for optimum ADC performance. Note: Operating Conditions apply. Table 40 A/D Converter Characteristics VS = 5.5 V to 28 V, Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Analog reference supply VAREF Values Min. Typ. Max. VAGND - VDDPA + 1.0 Analog reference ground VAGND VSS Unit Note / Test Condition Number V 1) P_9.2.1 + 0.05 - 1.5 V - P_9.2.2 - 0.05 Analog input voltage range VAIN VAGND - VAREF V 2) P_9.2.3 Analog clock frequency fADCI 5 - 24 MHz 3) P_9.2.4 (13 + STC) (13 + STC (13 + STC - x tADCI ) x tADCI ) x tADCI + 2 x tSYS + 2 x tSYS + 2 x tSYS 1)4) P_9.2.5 (11 + STC) (11 + STC (11 + STC - x tADCI ) x tADCI ) x tADCI + 2 x tSYS + 2 x tSYS + 2 x tSYS 1) P_9.2.6 tWAF - - 4 s 1) P_9.2.7 tWAS Wakeup time from analog powerdown, slow mode - - 15 s 1)5) P_9.2.8 Total unadjusted error (8 TUE8B bit) -2 1 +2 counts 6)7) Reference is internal VAREF P_9.2.9 Total unadjusted error (10 bit) TUE10B -12 6 +12 counts 7)8) P_9.2.22 DNL error EADNL -3 0.8 +3 counts - P_9.2.10 INL error EAINL_int_V -5 0.8 +5 counts Reference is internal VAREF P_9.2.11 0.4 +10 counts Reference is internal VAREF P_9.2.12 0.5 +2 counts - P_9.2.13 Conversion time for 10bit result tC10 Conversion time for 8-bit tC8 result Wakeup time from analog powerdown, fast mode AREF Gain error EAGAIN_int_ -10 VAREF Offset error EAOFF -2 Reference is internal VAREF Total capacitance of an analog input CAINT - - 10 pF 1)5)9) Switched capacitance of an analog input CAINS - - 4 pF 1)5)9) P_9.2.15 Resistance of the analog input path RAIN - - 2 k 1)5)9) P_9.2.16 Data Sheet 114 P_9.2.14 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics Table 40 A/D Converter Characteristics (cont'd) VS = 5.5 V to 28 V, Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number Total capacitance of the reference input CAREFT - - 15 pF 1)5)9) P_9.2.17 Switched capacitance of the reference input CAREFS - - 7 pF 1)5)9) P_9.2.18 Resistance of the reference input path RAREF - - 2 k 1)5)9) P_9.2.19 1) Not subject to production test, specified by design. 2) VAIN may exceed VAGND or VAREFx up to the absolute maximum ratings. However, the conversion result in these cases will be 0000H or 03FFH, respectively. 3) The limit values for fADCI must not be exceeded when selecting the peripheral frequency and the prescaler setting. 4) This parameter includes the sample time (also the additional sample time specified by STC), the time to determine the digital result and the time to load the result register with the conversion result. 5) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 500 s. 6) The total unadjusted error TUE is the maximum deviation from the ideal ADC transfer curve, not the sum of individual errors. All error specifications are based on measurement methods standardized by IEEE 1241.2000. 7) The specified TUE is valid only if the absolute sum of input overload currents (see IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the measurement time. 8) The total unadjusted error TUE is the maximum deviation from the ideal ADC transfer curve, not the sum of individual errors. All error specifications are based on measurement methods standardized by IEEE 1241.2000. 9) These parameter values cover the complete operating range. Under relaxed operating conditions (temperature, supply voltage) typical values can be used for calculation. At room temperature and nominal supply voltage the following typical values can be used: CAINTtyp = 12 pF, CAINStyp = 5 pF, RAINtyp = 1.0 k, CAREFTtyp = 15 pF, CAREFStyp = 10 pF, RAREFtyp = 1.0 k. 29.10 Data Sheet Reserved 115 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.11 High-Voltage Monitoring Input 29.11.1 Electrical Characteristics Table 41 Electrical Characteristics Monitoring Input Tj = -40 C to +150 C; VS = 5.5 V to 28 V, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. 0.4*VS 0.5*VS 0.6*VS Unit Note / Test Condition Number MON Input Pin characteristics Wake-up/monitoring threshold voltage VMONth V Without external serial resistor Rs (with Rs:DV = IPD/PU * Rs); VS = 5.5V to 18V P_11.1.1 Wake-up/monitoring threshold voltage extended range VMONth_ext 0.44*VS 0.53*V 0.64*VS V P_11.1.11 end S Without external serial resistor Rs (with Rs:DV = IPD/PU * Rs) Threshold hysteresis VMONth,hys 0.015* VS VS 0.05* 0.1*VS V P_11.1.12 In all modes; without external serial resistor Rs (with Rs:dV = IPD/PU * Rs); VS = 5.5V to 18V; Threshold hysteresis VMONth,hys 0.02*VS 0.06* VS 0.12*VS V P_11.1.2 In all modes; without external serial resistor Rs (with Rs:dV = IPD/PU * Rs); VS = 18V to 28V; Pull-up current IPU, MON -20 -10 -1 A 0.6*VS P_11.1.3 Pull-down current IPD, MON 3 10 20 A 0.4*VS P_11.1.4 Input leakage current ILK,MON -2.5 - 2.5 A 1) P_11.1.5 tFT,MON - 500 - ns 2) 0 V < VMON_IN < 28 V Timing Wake-up filter time (internal analog filter delay) The overall filter time for P_11.1.6 MON wake-up is a sum of tFT,MON + adjustable digital filter time. The digital filter time can be adjusted by PMU.CNF_WAKE_FILTE R.CNF_MON_FT; 1) Input leakage is valid for disabled state. 2) With pull-up, pull down current disabled. Data Sheet 116 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.12 MOSFET Driver 29.12.1 Electrical Characteristics Table 42 Electrical Characteristics MOSFET Driver VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Number MOSFET Driver Output Maximum total charge driver capability Qtot_max - - 100 nC 1) Source current - Charge current - High Side Driver ISoumax_HS 230 345 450 mA VSD 8 V, CLoad = 10 nF, P_12.1.78 ISou = CLoad * slew rate ( = 20%-50% of VGHx1), ICHARGE = IDISCHG = P_12.1.20 Due to Charge Pump currrent capability only 3 x MOSFETs + additional external capacitors with a total charge of max. 100nC can be driven simultaneous at a PWM frequency of 25 kHz. 31(max) Sink current - Discharge current-High Side Driver ISinkmax_HS 230 330 450 mA VSD 8 V, CLoad = 10 nF, P_12.1.79 ISink = CLoad * slew rate ( = 50%-20% of VGHx1), ICHARGE = IDISCHG = 31(max) Source current - Charge current - Low Side Driver ISoumax_LS 200 295 375 mA VSD 8 V, CLoad = 10 nF, P_12.1.80 ISou = CLoad * slew rate ( = 20%-50% of VGLx1), ICHARGE = IDISCHG = 31(max) Sink current - Discharge current-Low Side Driver ISinkmax_LS 200 314 375 mA VSD 8 V, CLoad = 10 nF, P_12.1.81 ISink = CLoad * slew rate ( = 50%-20% of VGHx1), ICHARGE = IDISCHG = 31(max) High level output voltage Gxx vs. Sxx VGxx1 10 - 14 V VSD 8V, CLoad = 10 nF, ICP=2.5 mA2). P_12.1.3 High level output voltage GHx vs. SHx VGxx2 8 - - V VSD = 6.4 V1), CLoad = 10 P_12.1.4 High level output voltage GHx vs. SHx VGxx3 Data Sheet nF, ICP=2.5 mA2) 7 - - 117 V VSD = 5.4 V, CLoad = 10 nF, P_12.1.5 ICP=2.5 mA2) Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics Table 42 Electrical Characteristics MOSFET Driver (cont'd) VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. 8 - VSD = 6.4 V1), CLoad = 10 Number High level output voltage GLx vs. GND VGxx6 High level output voltage GLx vs. GND VGxx7 7 - - V VSD = 5.4 V, CLoad = 10 nF, P_12.1.7 ICP=2.5 mA2) Rise time trise3_3nf - 200 - ns 1) - V P_12.1.6 nF, ICP=2.5 mA2) P_12.1.8 CLoad = 3.3 nF, VSD 8 V, 25-75% of VGxx1, ICHARGE = IDISCHG = 31(max) Fall time tfall3_3nf - 200 - ns 1) Rise time trisemax 100 250 450 ns P_12.1.57 CLoad = 10 nF, VSD 8 V, 25-75% of VGxx1, ICHARGE = IDISCHG = 31(max) Fall time tfallmax 100 250 450 ns P_12.1.58 CLoad = 10 nF, VSD 8 V, 75-25% of VGxx1, ICHARGE = IDISCHG = 31(max) Rise time trisemin 1.25 2.5 5 s 1) Fall time tfallmin 1.25 2.5 5 s 1) Absolute rise - fall time difference for all LSx tr_f(diff)LSx - - 100 ns P_12.1.35 CLoad = 10 nF, VSD 8 V, 25-75% of VGxx1, ICHARGE = IDISCHG = 31(max) Absolute rise - fall time difference for all HSx tr_f(diff)HSx - - 100 ns P_12.1.36 CLoad = 10 nF, VSD 8 V, 25-75% of VGxx1, ICHARGE = IDISCHG = 31(max) Resistor between GHx/GLx and GND RGGND 30 40 50 k 1) Data Sheet 118 P_12.1.9 CLoad = 3.3 nF, VSD 8 V, 75-25% of VGxx1, ICHARGE = IDISCHG = 31(max) P_12.1.14 CLoad = 10 nF, VSD 8 V, 25-75% of VGxx1, ICHARGE = IDISCHG = 3(min) P_12.1.15 CLoad = 10 nF, VSD 8 V, 75-25% of VGxx1, ICHARGE = IDISCHG = 3(min) - P_12.1.11 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics Table 42 Electrical Characteristics MOSFET Driver (cont'd) VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Resistor between SHx and GND RSHGN 30 40 50 k 1)3) Low RDSON mode (boosted discharge mode) RONCCP - 9 12 VVSD = 13.5 V, VVCP = VVSD + 14.0 V; ICHARGE = IDISCHG = Number P_12.1.10 This resistance is the resistance between GHx and GND connected through a diode to SHx. As a consequence, the voltage at SHx can rise up to 0,6V typ. before it is discharged through the resistor. P_12.1.50 31(max); 50mA forced into Gx, Sx grounded Resistance between VDH and VSD IBSH - 4 - k 1) P_12.1.24 Input propagation time (LS on) tP(ILN)min - 1.5 3 s 1) CLoad = 10 nF, ICharge =3(min), 25% of VGxx1 P_12.1.37 Input propagation time (LS off) tP(ILF)min - 1.5 3 s 1) CLoad = 10 nF, P_12.1.38 Input propagation time (HS on) tP(IHN)min - 1.5 3 s 1) CLoad = 10 nF, ICharge =3(min) 25% of VGxx1 P_12.1.39 Input propagation time (HS off) tP(IHF)min - 1.5 3 s 1) CLoad = 10 nF, IDisharge =3(min), 75% of VGxx1 P_12.1.40 Input propagation time (LS on) tP(ILN)max - 200 350 ns CLoad = 10 nF, ICharge =31(max), 25% of VGxx1 P_12.1.26 Input propagation time (LS off) tP(ILF)max - 200 300 ns CLoad = 10 nF, IDischarge =31(max), 75% of VGxx1 P_12.1.27 Input propagation time (HS on) tP(IHN)max - 200 350 ns CLoad = 10 nF, ICharge =31(max), 25% of VGxx1 P_12.1.28 Input propagation time (HS off) tP(IHF)max - 200 300 ns CLoad = 10 nF, IDischarge =31(max), 75% of VGxx1 P_12.1.29 Data Sheet IDischarge =3(min), 75% of VGxx1 119 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics Table 42 Electrical Characteristics MOSFET Driver (cont'd) VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Absolute input propagation tPon(diff)LSx time difference between propagation times for all LSx (LSx on) - - 100 ns CLoad = 10 nF, ICharge =31(max), 25% of VGxx1 P_12.1.30 tPoff(diff)LSx Absolute input propagation time difference between propagation times for all LSx (LSx off) - - 100 ns CLoad = 10 nF, IDischarge =31(max), 75% of VGxx1 P_12.1.41 tPon(diff)HSx Absolute input propagation time difference between propagation times for all HSx (HSx on) - - 100 ns CLoad = 10 nF, ICharge =31(max), 25% of VGxx1 P_12.1.42 tPoff(diff)HSx Absolute input propagation time difference between propagation times for all HSx (HSx off) - - 100 ns CLoad = 10 nF, IDischarge =31(max), 75% of VGxx1 P_12.1.43 - - - V P_12.1.46 0.07 0.35 0.55 0.65 0.90 1.00 1.20 1.40 0.25 0.50 0.75 1.00 1.25 1.5 1.75 2.00 0.40 0.650 0.90 1.25 1.45 1.80 2.10 2.40 DRV_CTRL3.DSMONVT H<2:0> xxx 000 001 010 011 100 101 110 111 Drain source monitoring Drain source monitoring threshold VDSMONVTH Open load diagnosis currents Pull-up diagnosis current IPUDiag -220 -370 -520 A IDISCHG = 1; VSHx = 5.0 V P_12.1.47 Pull-down diagnosis current IPDDiag 650 900 1100 A IDISCHG = 1; VSHx = 5.0 V P_12.1.48 VCPmin1 8.5 - - V VVSD = 5.4V, ICP=5 mA, CCP1, CCP2 = 220 nF, P_12.1.53 Charge pump Output voltage VCP vs. VSD Bridge Driver enabled Regulated output voltage VCP vs. VSD Data Sheet VCP 12 14 120 16 V 8 V VVSD 28, ICP=10mA, CCP1, CCP2=220 nF, fCP=250kHz P_12.1.49 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics Table 42 Electrical Characteristics MOSFET Driver (cont'd) VS = 5.5 V to 28 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Number Turn ON Time tON_VCP 10 24 40 us 8 V VVSD 28, ICP=2.5mA, (25%) of VCP1)4), CCP1, CCP2=220 nF, fCP=250kHz P_12.1.59 Rise time trise_VCP 20 60 88 us 8 V VVSD 28, ICP=2.5mA, (25-75%) of VCP1)5), CCP1, CCP2=220 nF, fCP=250kHz P_12.1.60 1) Not subject to production test. 2) The condition ICP = 2,5 mA emulates an BLDC Driver with 6 MOSFET switching at 20 KHz with a CLoad=3.3nF. Test condition: IGx = - 100 A, ICHARGE = IDISCHARGE = 31(max), IDISCHARGEDIV2_N = 1 and ICHARGEDIV2_N = 1. 3) This resistance is connected through a diode between SHx and GHx to ground. 4) This time applies when Bit DRV_CP_CTRL_STS.bit.CP_EN is set 5) This time applies when Bit DRV_CP_CLK_CTRL.bit.CPCLK_EN is set Data Sheet 121 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics 29.13 Operational Amplifier 29.13.1 Electrical Characteristics Table 43 Electrical Characteristics Operational Amplifier VS = 5.5 V to 28 V, Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Differential gain (uncalibrated) G Differential input operating voltage range OP2 - OP1 VIX Operating. common mode VCM input voltage range (referred to GND (OP2 - GND) or (OP1 - GND) Max. input voltage range (referred to GND (OP_2 GND) or (OP1 - GND) VIX_max Single ended output voltage VOUT range (linear range) Values Unit Min. Typ. Max. 9.5 19 38 57 10 20 40 60 10.5 21 42 63 Note / Test Condition Number Gain settings GAIN<1:0>: P_13.1.6 00 01 10 11 -1.5 / G - 1.5 / G V G is the Gain specified below -2.0 - 2.0 V Input common mode has P_13.1.2 to be checked in evaluation if it fits the required range -7.0 - 7.0 V Max. rating of operational P_13.1.3 amplifier inputs, where measurement is not done VZERO - VZERO V 1)2) typ. output offset voltage 2 V 1.5V - 1.5 + 1.5 P_13.1.1 P_13.1.4 Linearity error EPWM -15 - 15 mV Maximum deviation from P_13.1.5 best fit straight line divided by max. value of differential output voltage range (0.5V - 3.5V); this parameter is determined at G = 10. Linearity error EPWM_% -1.0 - 1.0 % Maximum deviation from P_13.1.24 best fit straight line divided by max. value of differential output voltage range (0.5V - 3.5V); this parameter is determined at G = 10. -1 - 1 % Gain drift after calibration P_13.1.7 at G = 10. -40 10 40 mV VAIP= VAIN = 0 V and Gain drift Adjusted output offset voltage Data Sheet VOOS P_13.1.17 G = 40. 122 Rev. 1.0, 2017-03-03 TLE9871QXA20 Electrical Characteristics Table 43 Electrical Characteristics Operational Amplifier (cont'd) VS = 5.5 V to 28 V, Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number P_13.1.8 DC input voltage common mode rejection ratio DCCMRR 58 80 - dB CMRR (in dB)=-20*log (differential mode gain/ common mode gain) VCMI= -2V... 2V, VAIP-VAIN=0V Settling time to 98% TSET - 800 1400 ns Derived from 80 - 20 % P_13.1.9 rise fall times for 2V overload condition (3 Tau value of settling time constant)2) Current Sense Amplifier Input Resistance @ OP1, OP2 Rin_OP1_ 1 1.25 1.5 k 2) Data Sheet - P_13.1.25 OP2 123 Rev. 1.0, 2017-03-03 TLE9871QXA20 Package Outlines Package Outlines 0.9 MAX. (0.65) 0. 13 +0.03 1) 0.4 x 45 Index Marking C 0.15 0.05 0.1 0.05 48 13 (0 (0.2) 0.05 MAX. 2) 37 1 12 1) Vertical burr 0.03 max., all sides 2) These four metal areas have exposed diepad potential Figure 38 36 25 24 SEATING PLANE 7 0.1 6.8 48x 0.08 0.5 0.5 0.07 0.10.03 B 26 0. 6.8 11 x 0.5 = 5.5 (6) A (5.2) 7 0.1 0. 05 30 .3 0.23 0.05 5) (5.2) Index Marking 48x 0.1 M A B C (6) PG-VQFN-48-29, -31-PO V05 Package outline VQFN-48-31 (with LTI) Notes 1. You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. 2. Dimensions in mm. Data Sheet 124 Rev. 1.0, 2017-03-03 TLE9871QXA20 Revision History 31 Revision History Revision History Page or Item Subjects (major changes since previous revision) Rev. 1.0, 2017-03-03 All Data Sheet Initial release. 125 Rev. 1.0, 2017-03-03 Please read the Important Notice and Warnings at the end of this document Trademarks of Infineon Technologies AG HVICTM, IPMTM, PFCTM, AU-ConvertIRTM, AURIXTM, C166TM, CanPAKTM, CIPOSTM, CIPURSETM, CoolDPTM, CoolGaNTM, COOLiRTM, CoolMOSTM, CoolSETTM, CoolSiCTM, DAVETM, DI-POLTM, DirectFETTM, DrBladeTM, EasyPIMTM, EconoBRIDGETM, EconoDUALTM, EconoPACKTM, EconoPIMTM, EiceDRIVERTM, eupecTM, FCOSTM, GaNpowIRTM, HEXFETTM, HITFETTM, HybridPACKTM, iMOTIONTM, IRAMTM, ISOFACETM, IsoPACKTM, LEDrivIRTM, LITIXTM, MIPAQTM, ModSTACKTM, my-dTM, NovalithICTM, OPTIGATM, OptiMOSTM, ORIGATM, PowIRaudioTM, PowIRStageTM, PrimePACKTM, PrimeSTACKTM, PROFETTM, PRO-SILTM, RASICTM, REAL3TM, SmartLEWISTM, SOLID FLASHTM, SPOCTM, StrongIRFETTM, SupIRBuckTM, TEMPFETTM, TRENCHSTOPTM, TriCoreTM, UHVICTM, XHPTM, XMCTM. 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