SN74LVC14A-EP HEX SCHMITT-TRIGGER INVERTER www.ti.com SCAS732C - NOVEMBER 2003 - REVISED JUNE 2006 FEATURES * * * * * * * * * (1) Controlled Baseline - One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Operates From 2 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 6.4 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C * * Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25C Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D OR PW PACKAGE (TOP VIEW) 1A 1Y 2A 2Y 3A 3Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 6A 6Y 5A 5Y 4A 4Y Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. DESCRIPTION/ORDERING INFORMATION The SN74LVC14A hex Schmitt-trigger inverter is designed for 2.7-V to 3.6-V VCC operation. The device contains six independent inverters and performs the Boolean function Y = A. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. ORDERING INFORMATION PACKAGE (1) TA -40C to 125C -55C to 125C (1) ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC - D Reel of 2500 SN74LVC14AQDREP LVC14AE TSSOP - PW Reel of 2000 SN74LVC14AQPWREP LVC14AE SOIC - D Reel of 2500 SN74LVC14AMDREP LVC14AE Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (EACH INVERTER) INPUT A OUTPUT Y H L L H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2003-2006, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. SN74LVC14A-EP HEX SCHMITT-TRIGGER INVERTER www.ti.com SCAS732C - NOVEMBER 2003 - REVISED JUNE 2006 LOGIC DIAGRAM, EACH INVERTER (POSITIVE LOGIC) A Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range -0.5 6.5 V VI Input voltage range (2) -0.5 6.5 V -0.5 VCC + 0.5 range (2) (3) UNIT VO Output voltage IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA IO Continuous output current 50 mA 100 mA Continuous current through VCC or GND JA Package thermal impedance (4) Tstg Storage temperature range (5) (1) (2) (3) (4) (5) D package 133.5 PW package 113 -65 150 V C/W C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging. Recommended Operating Conditions (1) MIN MAX 2 3.6 UNIT VCC Supply voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V IOH High-level output current IOL Low-level output current TA Operating free-air temperature (1) 2 Operating Data retention only 1.5 VCC = 2.7 V -12 VCC = 3 V -24 VCC = 2.7 V 12 VCC = 3 V 24 -40 125 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004). Submit Documentation Feedback V mA mA C SN74LVC14A-EP HEX SCHMITT-TRIGGER INVERTER www.ti.com SCAS732C - NOVEMBER 2003 - REVISED JUNE 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VT+ Positive-going threshold VT- Negative-going threshold VT Hysteresis (VT+ - VT-) ICC ICC (1) 3V 0.9 2 3.6 V 1.1 2 2.7 V 0.4 1.4 3V 0.6 1.5 3.6 V 0.8 1.7 2.7 V 0.3 1.1 3V 0.3 1.2 0.3 1.2 UNIT V V V VCC - 0.2 2.2 3V 2.4 IOH = -24 mA 3V 2.2 IOL = 100 A 2.7 V to 3.6 V 0.2 IOL = 12 mA 2.7 V 0.4 3V 0.55 V V VI = 5.5 V or GND 3.6 V 5 A VI = VCC or GND, IO = 0 3.6 V 10 A 500 A One input at VCC - 0.6 V, Other inputs at VCC or GND Ci 2 2.7 V IOL = 24 mA II 0.8 2.7 V to 3.6 V IOH = -12 mA VOL MAX 2.7 V 3.6 V IOH = -100 A VOH MIN TYP (1) VCC 2.7 V to 3.6 V VI = VCC or GND 3.3 V 5 pF All typical values are at VCC = 3.3 V, TA = 25C. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) A Y tpd VCC = 2.7 V MIN VCC = 3.3 V 0.3 V MAX MIN MAX 7.5 1 6.4 UNIT ns Operating Characteristics TA = 25C PARAMETER Cpd Power dissipation capacitance per inverter TEST CONDITIONS VCC = 2.5 V VCC = 3.3 V TYP TYP f = 10 MHz 12 15 Submit Documentation Feedback UNIT pF 3 SN74LVC14A-EP HEX SCHMITT-TRIGGER INVERTER www.ti.com SCAS732C - NOVEMBER 2003 - REVISED JUNE 2006 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 2.7 V 3.3 V 0.3 V VI tr/tf 2.7 V 2.7 V 2.5 ns 2.5 ns VM VLOAD CL RL V 1.5 V 1.5 V 6V 6V 50 pF 50 pF 500 500 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V VOL tPHZ VM VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 4 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 31-May-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) SN74LVC14AQDREP ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC14AE SN74LVC14AQPWREP ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC14AE V62/04658-01XE ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC14AE V62/04658-01YE ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC14AE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 31-May-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF SN74LVC14A-EP : * Catalog: SN74LVC14A * Automotive: SN74LVC14A-Q1 * Military: SN54LVC14A NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects * Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVC14AQDREP SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVC14AQPWREP TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC14AQDREP SOIC D 14 2500 333.2 345.9 28.6 SN74LVC14AQPWREP TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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