SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D - JULY 1985 - REVISED APRIL 2003 D D D D D D D D D D D D D Bidirectional Transceivers Meet or Exceed the Requirements of ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations V.11 and X.27 Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments 3-State Driver and Receiver Outputs Individual Driver and Receiver Enables Wide Positive and Negative Input/Output Bus Voltage Ranges Driver Output Capability . . . 60 mA Max Thermal Shutdown Protection Driver Positive and Negative Current Limiting Receiver Input Impedance . . . 12 k Min Receiver Input Sensitivity . . . 200 mV Receiver Input Hysteresis . . . 50 mV Typ Operate From Single 5-V Supply SN65176B . . . D OR P PACKAGE SN75176B . . . D, P, OR PS PACKAGE (TOP VIEW) R RE DE D 1 8 2 7 3 6 4 5 VCC B A GND description/ordering information The SN65176B and SN75176B differential bus transceivers are integrated circuits designed for bidirectional data communication on multipoint bus transmission lines. They are designed for balanced transmission lines and meet ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations V.11 and X.27. The SN65176B and SN75176B combine a 3-state differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, that can be connected together externally to function as a direction control. The driver differential outputs and the receiver differential inputs are connected internally to form differential input/output (I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or VCC = 0. These ports feature wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications. ORDERING INFORMATION PDIP (P) 0C to 70C -40C to 105C ORDERABLE PART NUMBER PACKAGE TA TOP-SIDE MARKING Tube of 50 SN75176BP Tube of 75 SN75176BD Reel of 2500 SN75176BDR SOP (PS) Reel of 2000 SN75176BPSR A176B PDIP (P) Tube of 50 SN65176BP SN65176BP Tube of 75 SN65176BD Reel of 2500 SN65176BDR SOIC (D) SOIC (D) SN75176BP 75176B 65176B Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D - JULY 1985 - REVISED APRIL 2003 description/ordering information (continued) The driver is designed for up to 60 mA of sink or source current. The driver features positive and negative current limiting and thermal shutdown for protection from line-fault conditions. Thermal shutdown is designed to occur at a junction temperature of approximately 150C. The receiver features a minimum input impedance of 12 k, an input sensitivity of 200 mV, and a typical input hysteresis of 50 mV. The SN65176B and SN75176B can be used in transmission-line applications employing the SN75172 and SN75174 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers. Function Tables DRIVER INPUT D ENABLE DE H H L X OUTPUTS A B H L H L H L Z Z RECEIVER DIFFERENTIAL INPUTS A-B ENABLE RE OUTPUT R VID 0.2 V -0.2 V < VID < 0.2 V L H L ? VID -0.2 V X L L H Z Open L ? H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off) logic diagram (positive logic) 3 DE D RE R 2 4 2 6 1 POST OFFICE BOX 655303 7 A B * DALLAS, TEXAS 75265 Bus SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D - JULY 1985 - REVISED APRIL 2003 schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF A AND B I/O PORTS TYPICAL OF RECEIVER OUTPUT VCC VCC R(eq) Input 16.8 k NOM VCC 85 NOM 960 NOM 960 NOM Output GND Driver input: R(eq) = 3 k NOM Enable inputs: R(eq )= 8 k NOM R(eq) = Equivalent Resistor Input/Output Port absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10 V to 15 V Enable input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Package thermal impedance, JA (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97C/W P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85C/W PS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 95C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential input/output bus voltage, are with respect to network ground terminal. 2. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) - TA)/JA. Operating at the absolute maximum TJ of 150C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D - JULY 1985 - REVISED APRIL 2003 recommended operating conditions VCC Supply voltage VI or VIC Voltage at any bus terminal (separately or common mode) VIH VIL High-level input voltage D, DE, and RE Low-level input voltage D, DE, and RE VID Differential input voltage (see Note 4) IOH High level output current High-level IOL Low level output current Low-level TA Operating free free-air air temperature MIN TYP MAX UNIT 4.75 5 5.25 V 12 -7 2 Driver Receiver Driver V 0.8 V 12 V -60 mA -400 A 60 Receiver 8 SN65176B -40 105 SN75176B 0 70 NOTE 4: Differential input/output bus voltage is measured at the noninverting terminal A, with respect to the inverting terminal B. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 V mA C SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D - JULY 1985 - REVISED APRIL 2003 DRIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS PARAMETER VIK VO Input clamp voltage Output voltage II = -18 mA IO = 0 |VOD1| Differential output voltage IO = 0 |VOD2| g Differential output voltage MIN TYP 0 1.5 RL = 100 , See Figure 1 RL = 54 , See Figure 1 VOD3 Differential output voltage See Note 5 |VOD| Change g in magnitude g of differential output voltage RL = 54 or 100 , VOC Common mode output voltage Common-mode |VOC| MAX UNIT -1.5 V 6 V 3.6 6 V 2.5 5 1/2 VOD1 or 2 1.5 V 5 V See Figure 1 0 2 0.2 V RL = 54 or 100 , See Figure 1 +3 -1 V Change g in magnitude g of common-modeoutput voltage RL = 54 or 100 , See Figure 1 0 2 0.2 V IO Output current Output disabled,, See Note 6 VO = 12 V VO = -7 V IIH IIL High-level input current IOS ICC Low-level input current Short circuit output current Short-circuit Supply current (total package) 1.5 1 -0.8 VI = 2.4 V VI = 0.4 V mA 20 A -400 A VO = -7 V VO = 0 -250 VO = VCC VO = 12 V 250 -150 mA 250 No load Outputs enabled 42 70 Outputs disabled 26 35 mA The power-off measurement in ANSI Standard TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs. All typical values are at VCC = 5 V and TA = 25C. |VOD| and |VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low level. The minimum VOD2 with a 100- load is either 1/2 VOD1 or 2 V, whichever is greater. NOTES: 5. See ANSI Standard TIA/EIA-485-A, Figure 3.5, Test Termination Measurement 2. 6. This applies for both power on and off; refer to ANSI Standard TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does not apply for a combined driver and receiver terminal. switching characteristics, VCC = 5 V, RL = 110 , TA = 25C (unless otherwise noted) TYP MAX td(OD) tt(OD) Differential-output delay time PARAMETER RL = 54 , TEST CONDITIONS See Figure 3 15 22 ns Differential-output transition time RL = 54 , See Figure 3 20 30 ns tPZH tPZL Output enable time to high level See Figure 4 85 120 ns Output enable time to low level See Figure 5 40 60 ns tPHZ tPLZ Output disable time from high level See Figure 4 150 250 ns Output disable time from low level See Figure 5 20 30 ns POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MIN UNIT 5 SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D - JULY 1985 - REVISED APRIL 2003 SYMBOL EQUIVALENTS DATA-SHEET PARAMETER TIA/EIA-422-B TIA/EIA-485-A VO |VOD1| Voa, Vob Vo Voa, Vob Vo |VOD2| Vt (RL = 100 ) Vt (RL = 54 ) Vt ((test termination measurement 2) |VOD3| |VOD| | |Vt| - |Vt| | | |Vt - |Vt| | VOC |VOC| |Vos| |Vos - Vos| |Vos| |Vos - Vos| IOS IO |Isa|, |Isb| |Ixa|, |Ixb| Iia, Iib RECEIVER SECTION electrical characteristics over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ VIT- Positive-going input threshold voltage Vhys VIK Input hysteresis voltage (VIT+ - VIT-) Enable Input clamp voltage II = -18 mA VOH High level output voltage High-level VID = 200 mV,, See Figure 2 IOH = -400 A,, VOL Low level output voltage Low-level VID = -200 mV,, See Figure 2 IOL = 8 mA,, IOZ High-impedance-state output current VO = 0.4 V to 2.4 V II Line input current Other input = 0 V,, See Note 7 IIH IIL High-level enable input current Low-level enable input current VIH = 2.7 V VIL = 0.4 V rI Input resistance VI = 12 V IOS Short-circuit output current ICC Negative-going input threshold voltage Supply current (total package) VO = 2.7 V, VO = 0.5 V, IO = -0.4 mA IO = 8 mA MIN TYP MAX 0.2 -0.2 V V 50 mV -1.5 27 2.7 V V VI = 12 V VI = -7 V 0 45 0.45 V 20 A 1 -0.8 mA 20 A -100 12 A k -15 No load UNIT -85 Outputs enabled 42 55 Outputs disabled 26 35 mA mA All typical values are at VCC = 5 V, TA = 25C. The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode input voltage and threshold voltage levels only. NOTE 7: This applies for both power on and power off. Refer to EIA Standard TIA/EIA-485-A for exact conditions. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D - JULY 1985 - REVISED APRIL 2003 switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25C PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low- to high-level output tPZH tPZL Output enable time to high level tPHZ tPLZ Output disable time from high level MIN TYP MAX 21 35 23 35 10 20 12 20 20 35 17 25 V See Figure 6 VID = 0 to 3 V, Propagation delay time, high- to low-level output See Figure 7 Output enable time to low level See Figure 7 Output disable time from low level UNIT ns ns ns PARAMETER MEASUREMENT INFORMATION VID RL VOD2 VOH 2 RL 2 VOL VOC Figure 1. Driver VOD and VOC +IOL -IOH Figure 2. Receiver VOH and VOL 3V Input Generator (see Note B) RL = 54 50 CL = 50 pF (see Note A) 1.5 V 1.5 V 0V td(OD) td(OD) Output Output 3V 50% 10% tt(OD) TEST CIRCUIT 90% 2.5 V 50% 10% -2.5 V tt(OD) VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns, ZO = 50 . Figure 3. Driver Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D - JULY 1985 - REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION Output 3V S1 Input 1.5 V 1.5 V 0 V or 3 V 0V CL = 50 pF (see Note A) Generator (see Note B) RL = 110 50 0.5 V tPZH VOH Output 2.3 V tPHZ TEST CIRCUIT Voff 0 V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns, ZO = 50 . Figure 4. Driver Test Circuit and Voltage Waveforms 5V 3V RL = 110 S1 Input 1.5 V 1.5 V Output 0V 3 V or 0 V CL = 50 pF (see Note A) Generator (see Note B) tPZL tPLZ 50 5V 0.5 V 2.3 V Output VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns, ZO = 50 . Figure 5. Driver Test Circuit and Voltage Waveforms 3V Input Generator (see Note B) 1.5 V 1.5 V Output 51 1.5 V CL = 15 pF (see Note A) 0V tPLH VOH Output 0V tPHL 1.3 V 1.3 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns, ZO = 50 . Figure 6. Receiver Test Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D - JULY 1985 - REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION S1 1.5 V 2 k -1.5 V S2 5V CL = 15 pF (see Note A) Generator (see Note B) 5 k 1N916 or Equivalent 50 S3 TEST CIRCUIT 3V Input 3V Input 1.5 V 0V tPZH S1 to 1.5 V S2 Open S3 Closed 1.5 V S1 to -1.5 V 0 V S2 Closed S3 Open tPZL VOH 4.5 V 1.5 V Output Output 0V 1.5 V VOL 3V 1.5 V Input 3V S1 to 1.5 V S2 Closed S3 Closed Input S1 to -1.5 V S2 Closed S3 Closed 1.5 V 0V tPHZ 0V tPLZ 0.5 V 1.3 V VOH Output Output 0.5 V 1.3 V VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns, ZO = 50 . Figure 7. Receiver Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D - JULY 1985 - REVISED APRIL 2003 TYPICAL CHARACTERISTICS DRIVER DRIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 5 VCC = 5 V TA = 25C 4.5 4 3.5 3 2.5 2 1.5 1 4 3.5 3 2.5 2 1.5 1 0.5 0.5 0 VCC = 5 V TA = 25C 4.5 VOL - Low-Level Output Voltage - V VOH - High-Level Output Voltage - V VOH 5 0 -20 -40 -60 -80 -100 IOH - High-Level Output Current - mA 0 -120 0 20 40 60 80 100 IOL - Low-Level Output Current - mA Figure 8 Figure 9 DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT VOD - Differential Output Voltage - V VOD 4 VCC = 5 V TA = 25C 3.5 3 2.5 2 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 IO - Output Current - mA Figure 10 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 90 100 120 SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D - JULY 1985 - REVISED APRIL 2003 TYPICAL CHARACTERISTICS RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 5 5 VOH - High-Level Output Voltage - V VOH VOH - High-Level Output Voltage - V VOH VID = 0.2 V TA = 25C 4.5 4 3.5 3 2.5 VCC = 5.25 V 2 VCC = 5 V 1.5 VCC = 5 V VID = 200 mV IOH = -440 A 4.5 VCC = 4.75 V 1 4 3.5 3 2.5 2 1.5 1 0.5 0.5 0 -40 -20 0 -5 0 0 -10 -15 -20 -25 -30 -35 -40 -45 -50 40 60 80 100 120 Only the 0C to 70C portion of the curve applies to the SN75176B. IOH - High-Level Output Current - mA Figure 11 Figure 12 RECEIVER RECEIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 0.6 0.6 VCC = 5 V TA = 25C VOL - Low-Level Output Voltage - V VOL VOL - Low-Level Output Voltage - V VOL 20 TA - Free-Air Temperature - C 0.5 0.4 0.3 0.2 0.1 0 0 5 10 15 20 25 30 0.5 VCC = 5 V VID = -200 mV IOL = 8 mA 0.4 0.3 0.2 0.1 0 -40 -20 0 20 40 60 80 100 120 TA - Free-Air Temperature - C IOL - Low-Level Output Current - mA Figure 13 Figure 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS SLLS101D - JULY 1985 - REVISED APRIL 2003 TYPICAL CHARACTERISTICS RECEIVER RECEIVER OUTPUT VOLTAGE vs ENABLE VOLTAGE OUTPUT VOLTAGE vs ENABLE VOLTAGE 5 6 VID = 0.2 V Load = 8 k to GND TA = 25C VCC = 5 V 3 5 VCC = 5.25 V VO - Output Voltage - V VO VO - Output Voltage - V VO 4 VID = -0.2 V Load = 1 k to VCC TA = 25C VCC = 5.25 V VCC = 4.75 V 2 1 VCC = 4.75 V VCC = 5 V 4 3 2 1 0 0 0 0.5 1 1.5 2 2.5 0 3 0.5 1 1.5 2 2.5 3 VI - Enable Voltage - V VI - Enable Voltage - V Figure 15 Figure 16 APPLICATION INFORMATION SN65176B SN75176B SN65176B SN75176B RT RT Up to 32 Transceivers NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept as short as possible. Figure 17. Typical Application Circuit 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 29-Sep-2011 PACKAGING INFORMATION Orderable Device (1) Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp SN65176BD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65176BDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65176BDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65176BDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65176BDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65176BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65176BP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65176BPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75176BD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75176BDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75176BDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75176BDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75176BDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75176BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75176BP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type SN75176BPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) SN75176BPSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75176BPSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM The marketing status values are defined as follows: Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 29-Sep-2011 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN65176BDR SOIC SN75176BDR SN75176BPSR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.0 12.0 Q1 D 8 2500 330.0 12.4 6.4 5.2 2.1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65176BDR SOIC D 8 2500 340.5 338.1 20.6 SN75176BDR SOIC D 8 2500 340.5 338.1 20.6 SN75176BPSR SO PS 8 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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