ADC1002S020 Single 10 bits ADC, up to 20 MHz Rev. 03 -- 2 July 2012 Product data sheet 1. General description The ADC1002S020 is a 10-bit high-speed Analog-to-Digital Converter (ADC) for professional video and other applications. It converts with 3.0 V to 5.25 V operation the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 20 MHz. All digital inputs and outputs are CMOS compatible. A standby mode allows a reduction of the device power consumption to 4 mW. 2. Features 10-bit resolution 3.0 V to 5.25 V operation Sampling rate up to 20 MHz DC sampling allowed High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 1.0 MHz; full-scale input at fclk = 20 MHz) In-Range (IR) CMOS output CMOS/Transistor-Transistor Logic (TTL) compatible digital inputs and outputs External reference voltage regulator Power dissipation only 53 mW (typical value) Low analog input capacitance, no buffer amplifier required Standby mode No sample-and-hold circuit required 3. Applications Video data digitizing Camera Camcorder Radio communication Barcode scanner (R) ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz 4. Quick reference data Table 1. Quick reference data VDDA = V7 to V9 = 3.3 V; VDDD = V4 to V3 = V18 to V19 = 3.3 V; VDDO = V20 to V21 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(p-p) = 1.83 V; CL = 20 pF; Tamb = 0 C to 70 C; typical values measured at Tamb = 25 C unless otherwise specified. Symbol Parameter VDDA Conditions Min Typ Max Unit analog supply voltage 3.0 3.3 5.25 V VDDD1 digital supply voltage 1 3.0 3.3 5.25 V VDDD2 digital supply voltage 2 3.0 3.3 5.25 V VDDO output supply voltage 3.0 3.3 5.25 V IDDA analog supply current - 7.5 10 mA IDDD digital supply current - 7.5 10 mA IDDO output supply current fclk = 20 MHz; ramp input; CL = 20 pF - 1 2 mA INL integral non-linearity ramp input; see Figure 6 - 1 2 LSB DNL differential non-linearity ramp input; see Figure 7 - 0.25 0.7 LSB fclk(max) maximum clock frequency 20 - - MHz Ptot total power dissipation operating; VDDD = 3.3 V - 53 73 mW standby mode - 4 - mW 5. Ordering information Table 2. Ordering information Type number Package Name Description Version ADC1002S020HL LQFP32 plastic low profile quad flat package; 32 leads; body 5 5 1.4 mm SOT401-1 ADC1002S020_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 2 of 18 ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz 6. Block diagram VDDA CLK VDDD2 OE 7 5 18 16 6 CLOCK DRIVER RT 15 STDBY ADC1002S020 1 D9 MSB 31 D8 30 D7 29 D6 Rlad 28 D5 analog voltage input VI 14 ANALOG - TO - DIGITAL CONVERTER CMOS OUTPUTS LATCHES 27 D4 data outputs 26 D3 RM 11 25 D2 23 D1 22 D0 RB 10 CMOS OUTPUT IN - RANGE LATCH LSB 20 VDDO 2 IR output 4 VDDD1 9 19 21 3 VSSA VSSD2 VSSO VSSD1 analog ground digital ground 2 output ground digital ground 1 014aaa482 Fig 1. Block diagram ADC1002S020_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 3 of 18 ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz 7. Pinning information 25 D2 26 D3 27 D4 28 D5 29 D6 30 D7 31 D8 32 n.c. 7.1 Pinning D9 1 24 n.c. IR 2 23 D1 VSSD1 3 22 D0 VDDD1 4 CLK 5 20 VDDO STDBY 6 19 VSSD2 VDDA 7 18 VDDD2 n.c. 8 17 n.c. 21 VSSO OE 16 RT 15 VI 14 n.c. 13 n.c. 12 RM 11 RB 10 VSSA 9 ADC1002S020HL 014aaa483 Fig 2. Pin configuration 7.2 Pin description Table 3. Pin description Symbol Pin Description D9 1 data output; bit 9 (Most Significant Bit (MSB)) IR 2 in-range data output VSSD1 3 digital ground 1 VDDD1 4 digital supply voltage 1 (3.0 V to 5.25 V) CLK 5 clock input STDBY 6 standby mode input VDDA 7 analog supply voltage (3.0 V to 5.25 V) n.c. 8 not connected VSSA 9 analog ground RB 10 reference voltage BOTTOM input RM 11 reference voltage MIDDLE input n.c. 12 not connected n.c. 13 not connected VI 14 analog voltage input RT 15 reference voltage TOP input OE 16 output enable input (active LOW) n.c. 17 not connected VDDD2 18 digital supply voltage 2 (3.0 V to 5.25 V) ADC1002S020_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 4 of 18 ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz Table 3. Pin description ...continued Symbol Pin Description VSSD2 19 digital ground 2 VDDO 20 positive supply voltage for output stage (3.0 V to 5.25 V) VSSO 21 output stage ground D0 22 data output; bit 0 (Least Significant Bit (LSB)) D1 23 data output; bit 1 n.c. 24 not connected D2 25 data output; bit 2 D3 26 data output; bit 3 D4 27 data output; bit 4 D5 28 data output; bit 5 D6 29 data output; bit 6 D7 30 data output; bit 7 D8 31 data output; bit 8 n.c. 32 not connected 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Min Max Unit VDDA analog supply voltage [1] 0.3 +7.0 V digital supply voltage [1] 0.3 +7.0 V VDDO output supply voltage [1] 0.3 +7.0 V VDD supply voltage difference VDDA VDDD VDDD VDDO VDDA VDDO 0.1 +4.0 V VI input voltage referenced to VSSA 0.3 +7.0 V Vi(a)(p-p) peak-to-peak analog input voltage referenced to VSSD - VDDD V IO output current - 10 mA Tstg storage temperature 55 +150 C Tamb ambient temperature 20 +75 C Tj junction temperature - 150 C VDDD [1] Conditions The supply voltages VDDA, VDDD and VDDO may have any value between 0.3 V and +7.0 V provided that the supply voltage VDD remains as indicated. 9. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Condition Value Unit Rth(j-a) thermal resistance from junction to ambient in free air 90 K/W ADC1002S020_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 5 of 18 ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz 10. Characteristics Table 6. Characteristics VDDA = V7 to V9 = 3.3 V; VDDD = V4 to V3 = V18 to V19 = 3.3 V; VDDO = V20 to V21 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(p-p) = 1.83 V; CL = 20 pF; Tamb = 0 C to 70 C; typical values measured at Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDDA analog supply voltage 3.0 3.3 5.25 V VDDD1 digital supply voltage 1 3.0 3.3 5.25 V VDDD2 digital supply voltage 2 3.0 3.3 5.25 V VDDO output supply voltage 3.0 3.3 5.25 V VDD supply voltage difference VDDA VDDD; VDDD VDDO; VDDA VDDO 0.2 - +0.2 V IDDA analog supply current - 7.5 10 mA IDDD digital supply current - 7.5 10 mA IDDO output supply current fclk = 20 MHz; ramp input; CL = 20 pF - 1 2 mA Ptot total power dissipation operating; VDDD = 3.3 V - 53 73 mW standby mode - 4 - mW Inputs Clock input CLK (Referenced to VSSD);[1] VIL LOW-level input voltage 0 - 0.3 VDDD V VIH HIGH-level input voltage VDDD 3.6 V 0.6 VDDD - VDDD V VDDD > 3.6 V 0.7 VDDD - VDDD V VCLK = 0.3 VDDD IIL LOW-level input current 1 0 +1 A IIH HIGH-level input current VCLK = 0.7 VDDD - - 5 A Zi input impedance fclk = 20 MHz - 4 - k Ci input capacitance fclk = 20 MHz - 3 - pF Inputs OE and STDBY (Referenced to VSSD); see Table 7 and 8 VIL LOW-level input voltage 0 - 0.3 VDDD V VIH HIGH-level input voltage VDDD 3.6 V 0.6 VDDD - VDDD V VDDD > 3.6 V 0.7 VDDD - VDDD V VIL = 0.3 VDDD 1 - - A - - 1 A IIL LOW-level input current IIH HIGH-level input current VIH = 0.7 VDDD Analog input VI (Referenced to VSSA) IIL LOW-level input current VI = VRB - 0 - A IIH HIGH-level input current VI = VRT - 35 - A Zi input impedance fi = 1 MHz - 5 - k Ci input capacitance fi = 1 MHz - 8 - pF Reference voltages for the resistor ladder; see Table 8 VRB voltage on pin RB 1.1 1.2 - V VRT voltage on pin RT 3.0 3.3 VDDA V ADC1002S020_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 6 of 18 ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz Table 6. Characteristics ...continued VDDA = V7 to V9 = 3.3 V; VDDD = V4 to V3 = V18 to V19 = 3.3 V; VDDO = V20 to V21 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(p-p) = 1.83 V; CL = 20 pF; Tamb = 0 C to 70 C; typical values measured at Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Vref(dif) differential reference voltage VRT VRB 1.9 2.1 3.0 V Iref reference current - 7.2 - mA Rlad ladder resistance - 290 - TCRlad ladder resistor temperature coefficient - 539 - m/K Voffset Vi(p-p) offset voltage - 1860 - ppm BOTTOM [2] - 135 - mV TOP [2] - 135 - mV [3] 1.66 1.83 2.35 V peak-to-peak input voltage Digital outputs D9 to D0 and IR (Referenced to VSSD) VOL LOW-level output voltage IO = 1 mA 0 - 0.5 V VOH HIGH-level output voltage IO = 1 mA VDDO 0.5 - VCCO V IOZ OFF-state output current 0.5 V < VO < VDDO 20 - +20 A Switching characteristics; Clock input CLK; see Figure 4[1] fclk(max) maximum clock frequency 20 - - MHz tw(clk)H HIGH clock pulse width 15 - - ns tw(clk)L LOW clock pulse width 15 - - ns Analog signal processing (fclk = 20 MHz) Linearity INL integral non-linearity ramp input; see Figure 6 - 1 2 LSB DNL differential non-linearity ramp input; see Figure 7 - 0.25 0.7 LSB Input set response; see Figure 8[4] ts(LH) LOW to HIGH settling time full-scale square wave - 4 6 ns ts(HL) HIGH to LOW settling time full-scale square wave - 4 6 ns fi = 1 MHz - 63 - dB without harmonics; fi = 1 MHz - 60 - dB fi = 300 KHz - 9.5 - bits fi = 1 MHz - 9.3 bits fi = 3.58 MHz - 8.0 bits Harmonics; see Figure 9[5] THD total harmonic distortion Signal-to-Noise ratio; see Figure 9[5] S/N signal-to-noise ratio Effective bits; see Figure 9[5] ENOB effective number of bits ADC1002S020_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 7 of 18 ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz Table 6. Characteristics ...continued VDDA = V7 to V9 = 3.3 V; VDDD = V4 to V3 = V18 to V19 = 3.3 V; VDDO = V20 to V21 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(p-p) = 1.83 V; CL = 20 pF; Tamb = 0 C to 70 C; typical values measured at Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Timing (fclk = 20 MHz; CL = 20 pF); see Figure4[6] td(s) sampling delay time - - 5 ns th(o) output hold time 5 - - ns td(o) output delay time VDDO = 4.75 V 8 12 15 ns VDDO = 3.15 V 8 17 20 ns 3-state output delay times; see Figure 5 tdZH float to active HIGH delay time - 14 18 ns tdZL float to active LOW delay time - 16 20 ns tdHZ active HIGH to float delay time - 16 20 ns tdLZ active LOW to float delay time - 14 18 ns Standby mode output delay times tTLH LOW to HIGH transition time stand-by - - 200 ns tTHL HIGH to LOW transition time start-up - - 500 ns [1] In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. [2] Analog input voltages producing code 0 up to and including code 1023: a) Voffset BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB (VRB) at Tamb = 25 C. b) Voffset TOP is the difference between the reference voltage on pin RT (VRT) and the analog input which produces data outputs equal to code 1023 at Tamb = 25 C. [3] To ensure the optimum linearity performance of such a converter architecture the lower and upper extremities of the converter reference resistor ladder are connected to pins RB and RT via offset resistors ROB and ROT as shown in Figure 3. V RT - V RB R OB + R L + R OT a) The current flowing into the resistor ladder is I = --------------------------------------- and the full-scale input range at the converter, to cover code 0 RL R OB + R L + R OT to 1023 is V I = R L I L = --------------------------------------- V RT + V RB = 0.871 V RT - V RB RL R OB + R L + R OT b) Since RL, ROB and ROT have similar behavior with respect to process and temperature variation, the ratio --------------------------------------will be kept reasonably constant from device to device. Consequently variation of the output codes at a given input voltage depends mainly on the difference VRT VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is optimized. [4] The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square wave signal) in order to sample the signal and obtain correct output data. [5] Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half the clock frequency (Nyquist frequency). Conversion to SIgnal-to-Noise And Distortion (SINAD) ratio: SINAD = ENOB 6.02 + 1.76 dB. [6] Output data acquisition: the output data is available after the maximum delay time of td(o). ADC1002S020_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 8 of 18 ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz 11. Additional information relating to Table 6 RT ROT code 1023 RL RL RM IL RL Rlad RL code 0 ROB RB 014aaa480 Fig 3. Converter reference resistor ladder Table 7. Mode selection OE D9 to D0 IR 1 high impedance high impedance 0 active; binary active Table 8. Standby selection STBY D9 to D0 ICCA + ICCD 1 last logic state 1.2 mA (typical value) 0 active 15 mA (typical value) Table 9. Output coding and input voltage (typical values; referenced to VSSA) Code Vi(a)(p-p) (V) IR Binary outputs D9 to D0 Underflow < 1.335 0 00 0000 0000 0 1.335 1 00 0000 0000 1 - 1 00 0000 0001 - 1022 - 1 11 1111 1110 1023 3.165 1 11 1111 1111 Overflow > 3.165 0 11 1111 1111 ADC1002S020_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 9 of 18 ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz sample N sample N + 1 sample N + 2 tw(clk)L tw(clk)H 50% CLK sample N sample N + 1 sample N + 2 VI td(s) th(o) VDDO DATA D0 to D9 DATA N-2 DATA N-1 DATA N DATA N+1 50% 0V td(o) 014aaa481 Fig 4. Timing diagram ADC1002S020_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 10 of 18 ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz VDDD 50 % OE tdHZ tdZH HIGH 90 % output data 50 % tdLZ LOW tdZL HIGH output data 50 % LOW 10 % VDDO 3.3 k ADC1002S020 S1 20 pF OE TEST S1 tdLZ VDDO tdZL VDDO tdHZ VSSO tdZH VSSO 014aaa484 frequency on pin OE= 100 kHz. Fig 5. Timing diagram and test conditions of 3-state output delay time 014aaa491 0.6 A (LSB) 0.2 -0.2 -0.6 1023 0 200 400 600 800 1000 1200 f (MHZ) Fig 6. Typical Integral Non-Linearity (INL) performance ADC1002S020_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 11 of 18 ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz 014aaa492 0.25 A (LSB) 0.15 0.05 -0.05 -0.15 1023 -0.25 0 200 400 600 800 1000 1200 f (MHZ) Fig 7. Typical Differential Non-Linearity (DNL) performance ts(LH) ts(HL) code 1023 VI 50 % 50 % code 0 5 ns CLK 5 ns 50 % 50 % 2 ns 2 ns 014aaa479 Fig 8. Analog input settling time diagram ADC1002S020_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 12 of 18 ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz 014aaa493 0 A (dB) -40 -80 -120 0 2.5 5.01 7.51 10 f (MHz) Effective bits: 9.59; THD = 76.60 dB. Harmonic levels (dB): 2nd = 81.85; 3rd = 87.56; 4th = 88.81; 5th = 88.96; 6th = 79.58. Fig 9. Typical fast Fourier transform (fclk = 20 MHz; fi = 1 MHz) ADC1002S020_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 13 of 18 ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz VDDO VDDA D9 to D0 IR VI VSSO VSSA 014aaa486 014aaa485 Fig 10. D9 to D0 and IR outputs Fig 11. VI analog input VDDA VDDO RT Rlad Rlad RM OE STDBY Rlad Rlad RB VSSO VSSA 014aaa487 Fig 12. OE and STDBY inputs 014aaa488 Fig 13. RB, RM and RT inputs VDDD 1/ V 2 DDD CLK VSSD 014aaa489 Fig 14. CLK input ADC1002S020_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 14 of 18 ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz 12. Application information 12.1 Application diagram n.c.(2) D9 IR VSSD1 VDDD1 32 D8 D7 31 D6 30 29 D5 28 D4 D3 27 26 D2 1 25 24 2 23 3 22 4 21 n.c.(2) D1 D0 VSSO ADC1002S020 CLK STDBY VDDA n.c.(2) 5 20 6 19 7 18 8 17 16 9 10 VSSA 11 RB(1) RM(1) 12 n.c.(2) 13 n.c.(2) 14 15 VI(4) RT(1) VDDO VSSD2 VDDD2 n.c.(2) OE (3) 100 nF VSSA 100 nF VSSA 100 nF 014aaa490 VSSA The analog and digital supplies should be separated and decoupled. The external voltage reference generator must be built in such a way that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the reference ladder voltages can be derived from a well regulated VDDA supply through a resistor bridge and a decoupling capacitor. (1) RB, RM and RT are decoupled to VSSA (2) Pins 8, 12, 13, 17, 24 and 32 should be connected to the closest ground pin in order to prevent noise influence (3) When RM is not used, pin 11 can be left open circuit, avoiding the decoupling capacitor. In any case, pin 11 must not be grounded. (4) When the analog input signal is AC coupled, an input bias or a clamping level must be applied to VI input (pin 14). Fig 15. Application diagram ADC1002S020_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 15 of 18 ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz 13. Package outline SOT401-1 LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm c y X A 17 24 ZE 16 25 e A A2 E HE (A 3) A1 w M pin 1 index bp 32 Lp 9 L 1 8 detail X ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.15 0.05 1.5 1.3 0.25 0.27 0.17 0.18 0.12 5.1 4.9 5.1 4.9 0.5 7.15 6.85 7.15 6.85 1 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) 0.95 0.55 7o o 0 0.95 0.55 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT401-1 136E01 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-20 Fig 16. Package outline SOT401-1 (LQFP32) ADC1002S020_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 16 of 18 ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes ADC1002S020_3 20120702 Product data sheet - ADC1002S020_2 ADC1002S020_2 20080813 Product data sheet - ADC1002S020_1 Modifications: ADC1002S020_1 * Corrections made to cross references and note 3 a) in Table 6. 20080612 Product data sheet - - 15. Contact information For more information or sales office addresses, please visit: http://www.idt.com ADC1002S020_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 17 of 18 ADC1002S020 Integrated Device Technology Single 10 bits ADC, up to 20 MHz 16. Contents 1 2 3 4 5 6 7 7.1 7.2 8 General description . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quick reference data . . . . . . . . . . . . . . . . . . . . . Ordering information . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . Pinning information . . . . . . . . . . . . . . . . . . . . . . Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 2 2 3 4 4 4 5 9 10 11 12 12.1 13 14 15 16 ADC1002S020_3 Product data sheet Thermal characteristics . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 6 Additional information relating to Table 6 . . . 9 Application information . . . . . . . . . . . . . . . . . 15 Application diagram . . . . . . . . . . . . . . . . . . . . 15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information . . . . . . . . . . . . . . . . . . . . 17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 18 of 18