CC1
+VOUT
+
-
-
CF
VIN
+
-
RB1
V+
RB2
CC2
R2
R1
AV = -
R2
100 k:
R1
1 k:
= -100
120
100 10k 1M 100M
FREQUENCY (Hz)
-40
0
60
GAIN (dB)
10M100k
1k
100
80
40
20
-20
PHASE (q)
120
-40
0
60
100
80
40
20
-20
PHASE
GAIN
V+ = 5V
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV651
,
LMV652
,
LMV654
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
LMV65x 12-MHz, Low Voltage, Low Power Amplifiers
1
1 Features
1 Typical 5-V Supply, Unless Otherwise Noted
Specified 3-V and 5-V Performance
Low Power Supply Current
LMV651: 116 μA
LMV652: 118 μA per Amplifier
LMV654: 122 μA per Amplifier
High Unity-Gain Bandwidth: 12 MHz
Maximum Input Offset Voltage: 1.5 mV
CMRR: 100 dB
PSRR: 95 dB
Input Referred Voltage Noise: 17 nV/Hz
Output Swing With 2-kLoad, 120 mV from Rail
Total Harmonic Distortion: 0.003% at 1 kHz, 2 k
Temperature Range: 40°C to 125°C
2 Applications
Portable Equipment
Automotive
Battery-Powered Systems
Sensors and Instrumentation
3 Description
TI’s LMV65x devices are high-performance, low-
power operational amplifier ICs implemented with TI's
advanced VIP50 process. This family of parts
features 12 MHz of bandwidth while consuming only
116 μA of current, which is an exceptional bandwidth
to power ratio in this operational amplifier class. The
LMV65x devices are unity-gain stable and provide an
excellent solution for general-purpose amplification in
low-voltage, low-power applications.
This family of low-voltage, low-power amplifiers
provides superior performance and economy in terms
of power and space usage. These operational
amplifiers have a maximum input offset voltage of 1.5
mV, a rail-to-rail output stage, and an input common-
mode voltage range that includes ground. The
LMV65x provide a PSRR of 95 dB, a CMRR of 100
dB, and a total harmonic distortion (THD) of 0.003%
at 1-kHz frequency and 2-kload.
The operating supply voltage range for this family of
parts is from 2.7 V and 5.5 V. These operational
amplifiers can operate over a wide temperature range
(40°C to 125°C), making them ideal for automotive
applications, sensor applications, and portable
equipment applications. The LMV651 is offered in the
ultra-tiny 5-pin SC70 and 5-pin SOT-23 package. The
LMV652 is offered in an 8-pin VSSOP package. The
LMV654 is offered in a 14-pin TSSOP package.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LMV651 SOT-23 (5) 2.90 mm × 1.60 mm
SC70 (5) 2.00 mm × 1.25 mm
LMV652 VSSOP (8) 3.00 mm × 3.00 mm
LMV654 TSSOP (14) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
High Gain Wide Bandwidth Inverting Amplifier Open-Loop Gain and Phase vs Frequency
2
LMV651
,
LMV652
,
LMV654
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
www.ti.com
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 3-V DC Electrical Characteristics.............................. 5
6.6 5-V DC Electrical Characteristics.............................. 6
6.7 Typical Characteristics.............................................. 7
7 Detailed Description............................................ 13
7.1 Overview................................................................. 13
7.2 Functional Block Diagram....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 14
8 Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Applications ................................................ 16
8.3 Dos and Don'ts ....................................................... 18
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support................. 20
11.1 Device Support .................................................... 20
11.2 Documentation Support ....................................... 20
11.3 Related Links ........................................................ 20
11.4 Community Resources.......................................... 20
11.5 Trademarks........................................................... 20
11.6 Electrostatic Discharge Caution............................ 20
11.7 Glossary................................................................ 21
12 Mechanical, Packaging, and Orderable
Information........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (March 2013) to Revision K Page
Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
Changes from Revision I (March 2012) to Revision J Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 18
3
LMV651
,
LMV652
,
LMV654
www.ti.com
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated
5 Pin Configuration and Functions
LMV651 DBV or DCK Package
5-Pin SC70 or SOT-23
Top View LMV652 DGK Package
8-Pin VSSOP
Top View
LMV654 PW Package
14-Pin TSSOP
Top View
Pin Functions: LMV651
PIN I/O DESCRIPTION
NAME NO.
–IN 3 I Inverting Input
+IN 1 I Noninverting Input
OUT 4 O Output
V– 2 P Negative supply input
V+ 5 P Positive Supply Input
Pin Functions: LMV652, LMV654
PIN I/O DESCRIPTION
NAME VSSOP TSSOP
–IN A 2 2 I Inverting input, channel A
+IN A 3 3 I Noninverting input, channel A
–IN B 6 6 I Inverting input, channel B
+IN B 5 5 I Noninverting input, channel B
–IN C 9 I Inverting input, channel C
+IN C 10 I Noninverting input, channel C
–IN D 13 I Inverting input, channel D
+IN D 12 I Noninverting input, channel D
OUT A 1 1 O Output, channel A
OUT B 7 7 O Output, channel B
OUT C 8 O Output, channel C
OUT D 14 O Output, channel D
V– 4 11 P Negative (lowest) power supply
V+ 8 4 P Positive (highest) power supply
4
LMV651
,
LMV652
,
LMV654
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
www.ti.com
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The maximum power dissipation is a function of TJ(MAX,θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
MIN MAX UNIT
Differential input VID ±0.3
Supply voltage (VS= V+- V) 6
Input or output pin voltage V0.3 V++ 0.3 V
Soldering information Infrared or convection (20 sec) 235 °C
Wave soldering lead temperature (10 sec) 260
Junction temperature(3) 150 °C
Storage temperature, Tstg 65 150 °C
(1) Human Body Model, applicable std. MIL-STD-883, Method 3015.7
(2) Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-
C101-C (ESD FICDM std. of JEDEC).
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic
discharge Human-body model (HBM)(1) ±2000 V
Machine model(2) ±100
6.3 Recommended Operating Conditions MIN MAX UNIT
Temperature 40 125 °C
Supply voltage 2.7 5.5 V
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.4 Thermal Information
THERMAL METRIC(1)
LMV651 LMV652 LMV653
UNIT
DCK
(SC70) DBV
(SOT-23) DGK
(VSSOP) PW
(TSSOP)
5 PINS 5 PINS 8 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 303.5 214.2 200.3 134.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 135.5 173.3 89.1 60.9 °C/W
RθJB Junction-to-board thermal resistance 81.1 72.5 120.9 77.3 °C/W
ψJT Junction-to-top characterization parameter 8.4 56.7 21.7 11.5 °C/W
ψJB Junction-to-board characterization parameter 80.4 71.9 119.4 76.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a °C/W
5
LMV651
,
LMV652
,
LMV654
www.ti.com
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using
Statistical Quality Control (SQC) method.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) Positive current corresponds to current flowing into the device.
(4) Slew rate is the average of the rising and falling slew rates.
(5) The part is not short-circuit protected and is not recommended for operation with low resistive loads. Typical sourcing and sinking output
current curves are provided in Typical Characteristics and should be consulted before designing for heavy loads.
6.5 3-V DC Electrical Characteristics
Unless otherwise specified, all limits are specified for TA= 25°C, V+= 3 V, V= 0 V, VO= VCM = V+/2, and RL> 1 M.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
VOS Input offset voltage 0.1 ±1.5 mV
Over specified temperature range 2.7
TC VOS Input offset average drift 6.6 μV/°C
IBInput bias current(3) 80 120 nA
IOS Input offset current 2.2 15 nA
CMRR Common-mode rejection ratio 0 VCM2 V 87 100 dB
Over specified temperature range 80
PSRR Power supply rejection ratio 3V+5 V, VCM = 0.5 87 95
dB
Over specified temperature range 81
2.7 V+5.5 V,
VCM = 0.5 87 95
Over specified temperature range 81
CMVR Input common-mode voltage
range CMRR 75 dB 0 2.1 V
CMRR 60 dB, over specified temperature range 0 2.1
AVOL Large signal voltage gain
0.3 VO2.7, RL= 2 kto V+/2 80 85
dB
0.4 VO2.6, RL= 2 kto V+/2, over specified temperature range 76
0.3 VO2.7, RL= 10 kto V+/2 86 93
0.4 VO2.6, RL= 10 kto V+/2, over specified temperature
range 83
VO
Output swing high RL= 2 kto V+/2 80 95
mV from
rail
Over specified temperature range 120
RL= 10 kto V+/2 45 50
Over specified temperature range 60
Output swing low RL= 2 kto V+/2 95 110
Over specified temperature range 125
RL= 10 kto V+/2 60 65
Over specified temperature range 75
ISC Maximum continuous output
current Sourcing(4) 17 mA
Sinking(4) 25
ISSupply current per amplifier
LMV651 115 140
μA
Over specified temperature range 175
LMV652 118 140
Over specified temperature range 175
LMV654 122 140
Over specified temperature range 175
SR Slew rate AV= +1, 10% to 90%(5) 3.0 V/μs
GBW Gain bandwidth product 12 MHz
enInput-referred voltage noise f = 100 kHz 17 nV/Hz
f = 1 kHz 17
inInput-referred current noise f = 100 kHz 0.1 pA/Hz
f = 1 kHz 0.15
THD Total harmonic distortion f = 1 kHz, AV= 2, RL= 2 k0.003%
6
LMV651
,
LMV652
,
LMV654
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
www.ti.com
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using
Statistical Quality Control (SQC) method.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) Positive current corresponds to current flowing into the device.
(4) The part is not short-circuit protected and is not recommended for operation with low resistive loads. Typical sourcing and sinking output
current curves are provided in Typical Characteristics and should be consulted before designing for heavy loads.
(5) Slew rate is the average of the rising and falling slew rates.
6.6 5-V DC Electrical Characteristics
Unless otherwise specified, all limits are specified for TJ= 25°C, V+= 5 V, V= 0 V, VO= VCM = V+/2, and RL> 1 M.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
VOS Input offset voltage 0.1 ±1.5 mV
Over specified temperature range 2.7
TC VOS Input offset average drift 6.6 μV/°C
IBInput bias current See(3) 80 120 nA
IOS Input offset current 2.2 15 nA
CMRR Common-mode rejection ratio 0 VCM4 V 90 100 dB
Over specified temperature range 83
PSRR Power supply rejection ratio 3 V V+5 V, VCM = 0.5 V 87 95
dB
Over specified temperature range 81
2.7 V V+5.5 V, VCM =
0.5 V 87 95
Over specified temperature range 81
CMVR Input common-mode voltage
range CMRR 80 dB 0 4.1 V
CMRR 68 dB, over specified temperature range 0 4.1
AVOL Large signal voltage gain
0.3 VO4.7 V, RL= 2 kto V+/2 79 84
dB
0.4 VO4.6 V, RL= 2 kto V+/2, over specified temperature range 76
0.3 VO4.7 V, RL= 10 kto V+/2 87 94
0.4 VO4.6 V, RL= 10 kto V+/2, over specified temperature
range 84
VO
Output swing high RL= 2 kto V+/2 120 140
mV from
rail
Over specified temperature range 185
RL= 10 kto V+/2 75 90
Over specified temperature range 120
Output swing low RL= 2 kto V+/2 110 130
Over specified temperature range 150
RL= 10 kto V+/2 70 80
Over specified temperature range 95
ISC Maximum continuous output
current Sourcing(4) 18.5 mA
Sinking(4) 25
ISSupply current per amplifier
LMV651 116 140
μA
Over specified temperature range 175
LMV652 118 140
Over specified temperature range 175
LMV654 122 140
Over specified temperature range 175
SR Slew rate AV= +1, VO= 1 VPP, 10% to 90%(5) 3.0 V/μs
GBW Gain bandwidth product 12 MHz
enInput-referred voltage noise f = 100 kHz 17 nV/Hz
f = 1 kHz 17
inInput-referred current noise f = 100 kHz 0.1 pA/Hz
f = 1 kHz 0.15
THD Total harmonic distortion f = 1 kHz, AV= 2, RL= 2 k0.003%
0 1 2 3 4 5
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
VOS (mV)
VCM (V)
125°C
25°C
-40°C
VS = 5V
-40°C
2.7 3.2 3.7 4.2 4.7 5.2
-1
-0.75
-0.5
-0.25
0
0.25
1
VOS (mV)
VS (V)
0.5
0.75 125°C
25°C
5.5
0 0.5 1 1.5 2 2.5
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
VOS (mV)
VCM (V)
125°C
25°C
-40°C
VS = 3V
7
LMV651
,
LMV652
,
LMV654
www.ti.com
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated
6.7 Typical Characteristics
Unless otherwise specified, TA= 25°C, VS= 5 V, V+= 5 V, V= 0 V, VCM= VS/2
Figure 1. Supply Current vs Supply Voltage (LMV651) Figure 2. Supply Current per Channel vs Supply Voltage
(LMV652)
Figure 3. Supply Current per Channel vs Supply Voltage
(LMV654) Figure 4. VOS vs VCM
Figure 5. VOS vs VCM Figure 6. VOS vs Supply Voltage
33.4 3.8 4.2 4.6 5
0
30
60
90
120
150
VOUT FROM RAIL (mV)
VS (V)
-40°C 25°C
125°C
RL = 2 k:
25°C
33.4 3.8 4.2 4.6 5
0
20
40
60
80
100
VOUT FROM RAIL (mV)
VS (V)
-40°C
125°C
RL = 10 k:
33.4 3.8 4.2 4.6 5
0
30
60
90
120
150
VOUT FROM RAIL (mV)
VS (V)
-40°C
25°C
125°C
RL = 2 k:
2.7 3.2 3.7 4.2 4.7 5.2
VS (V)
50
60
70
80
90
100
IBIAS (nA)
-40°C
25°C
125°C
5.5
8
LMV651
,
LMV652
,
LMV654
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
www.ti.com
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated
Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C, VS= 5 V, V+= 5 V, V= 0 V, VCM= VS/2
Figure 7. IBIAS vs VCM Figure 8. IBIAS vs VCM
Figure 9. IBIAS vs Supply Voltage Figure 10. Positive Output Swing vs Supply Voltage
Figure 11. Negative Output Swing vs Supply Voltage Figure 12. Positive Output Swing vs Supply Voltage
180
100 10k 1M 100M
FREQUENCY (Hz)
-60
0
90
GAIN (dB)
10M100k
1k
150
120
60
30
-30
180
-60
0
90
150
120
60
30
-30
PHASE (°)
PHASE
GAIN
CL = 20 pF
CL = 100 pF
RL = 2 k:
CL = 100 pF
CL = 50 pF
CL = 50 pF
00.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
VOUT FROM RAIL (V)
0
10
20
30
40
50
ISINK (mA)
VS = 5V
125°C
25°C
-40°C
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
0
10
20
30
40
50
ISINK (mA)
VOUT FROM RAIL (V)
25°C
-40°C
125°C
VS = 5V
3 3.4 3.8 4.2 4.6 5
0
15
30
45
60
75
90
VOUT FROM RAIL (mV)
VS (V)
-40°C 25°C
125°C
RL = 10 k:
125°C
-40°C
00.25 0.5 0.75 1 1.25 1.5
VOUT FROM RAIL (V)
0
5
10
15
20
25
30
ISOURCE (mA)
25°C
VS = 5V
9
LMV651
,
LMV652
,
LMV654
www.ti.com
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated
Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C, VS= 5 V, V+= 5 V, V= 0 V, VCM= VS/2
Figure 13. Negative Output Swing vs Supply Voltage Figure 14. Sourcing Current vs Output Voltage
Figure 15. Sinking Current vs Output Voltage (LMV651) Figure 16. Sinking Current vs Output Voltage (LMV652)
Figure 17. Sinking Current vs Output Voltage (LMV654) Figure 18. Open-Loop Gain and Phase With Capacitive Load
0.001 0.01 0.1 1 10
VOUT (V)
0.0001
0.001
0.01
0.1
1
THD+N (%)
VS = 3V
VIN = 1 kHz
AV = +2
RL = 2 k:
RL = 100 k:
SINE WAVE
110 100 10k 100k
FREQUENCY (Hz)
1
10
100
1k
INPUT REFERRED VOLTAGE NOISE
HZ)
(nV/
110 100 1k 100k
FREQUENCY (Hz)
0.01
0.10
1
10
10k
INPUT REFERRED CURRENT NOISE
HZ)
(pA/
180
100 10k 1M 100M
FREQUENCY (Hz)
-60
0
90
GAIN (dB)
10M100k
1k
150
120
60
30
-30
180
-60
0
90
150
120
60
30
-30
PHASE (°)
PHASE
GAIN
RL = 2 k:
CL = 20 pF
RL = 10:
RL = 2 k:
CL (pF)
10 100 1000
0
10
20
30
40
50
60
PHASE MARGIN (°)
VS = 3V
VS = 5V
RL = 2 k:
10
LMV651
,
LMV652
,
LMV654
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
www.ti.com
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated
Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C, VS= 5 V, V+= 5 V, V= 0 V, VCM= VS/2
Figure 19. Open-Loop Gain and Phase With Resistive Load Figure 20. Phase Margin vs Capacitive Load (Stability)
Figure 21. Input-Referred Voltage Noise vs Frequency Figure 22. Input-Referred Current Noise vs Frequency
Figure 23. Slew Rate vs Supply Voltage Figure 24. THD+N vs VOUT
-30
-25
-20
-15
-10
-5
30
VOUT (mV)
0
5
10
15
20
25
TIME (Ps)
020 40 60 70 80
VS = 5V
CL = 125 pF, AV = +1
VIN = 20 mVPP, 20 kHz
10 100 1k 10k 100k
FREQUENCY (Hz)
0.0001
0.001
0.01
0.1
THD+N (%)
VS = 5V
VIN = 2 VPP
AV = +2 RL = 2 k:
RL = 100 k:
0.001 0.01 0.1 1 10
VOUT (V)
0.001
0.01
0.1
1
THD+N (%)
VS = 5V
VIN = 1 kHz
AV = +2
RL = 2 k:
RL = 100 k:
SINE WAVE
10 100 1k 10k 100k
FREQUENCY (Hz)
0.001
0.01
0.1
1
THD+N (%)
VS = 3V
VIN = 1 VPP
AV = +2
RL = 2 k:
RL = 100 k:
11
LMV651
,
LMV652
,
LMV654
www.ti.com
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated
Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C, VS= 5 V, V+= 5 V, V= 0 V, VCM= VS/2
Figure 25. THD+N vs VOUT Figure 26. THD+N vs Frequency
Figure 27. THD+N vs Frequency Figure 28. Small Signal Transient Response
Figure 29. Small Signal Transient Response Figure 30. Large Signal Transient Response
10 1k 1M
0.01
100
1000
ZOUT (W)
10M
10k
100 100M
FREQUENCY (Hz)
100k
10
1
0.1
120
10 1k 100k 10M
FREQUENCY (Hz)
0
80
PSRR (dB)
1M
10k
100
100
60
40
20
VS = 3V, -PSRR
VS = 5V, -PSRR
VS = 3V, +PSRR
VS = 5V, +PSRR
10 1k 1M
FREQUENCY (Hz)
0
40
120
CMRR (dB)
100k
10k
100
100
60
20
80
12
LMV651
,
LMV652
,
LMV654
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
www.ti.com
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated
Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C, VS= 5 V, V+= 5 V, V= 0 V, VCM= VS/2
Figure 31. PSRR vs Frequency Figure 32. CMRR vs Frequency
Figure 33. Closed-Loop Output Impedance vs Frequency
13
LMV651
,
LMV652
,
LMV654
www.ti.com
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
TI’s LMV65x devices have 12 MHz of bandwidth, are unity-gain stable, and consume only 116 μA of current.
They also have a maximum input offset voltage of 1.5 mV, a rail-to-rail output stage, and an input common-mode
voltage range that includes ground. Lastly, these operational amplifiers provide a PSRR of 95 dB, a CMRR of
100 dB, and a total harmonic distortion (THD) of 0.003% at 1-kHz frequency and 2-kload.
7.2 Functional Block Diagram
(Each Amplifier)
7.3 Feature Description
7.3.1 Low Voltage and Low Power Operation
The LMV65x have performance specified at supply voltages of 3 V and 5 V. These parts are specified to be
operational at all supply voltages between 2.7 V and 5.5 V. The LMV651 draws a low supply current of 116 μA,
the LMV652 draws 118 μA/channel and the LMV654 draws 122 μA/channel. This family of operational amplifiers
provides the low voltage and low power amplification that is essential for portable applications.
7.3.2 Wide Bandwidth
Despite drawing the very low supply current of 116 µA, the LMV65x manage to provide a wide unity-gain
bandwidth of 12 MHz. This is easily one of the best bandwidth to power ratios ever achieved, and allows these
operational amplifiers to provide wideband amplification while using the minimum amount of power. This makes
this family of parts ideal for low-power signal processing applications such as portable media players and other
accessories.
7.3.3 Low Input Referred Noise
The LMV65x provides a flatband input referred voltage noise density of 17 nV/Hz, which is significantly better
than the noise performance expected from a low-power operational amplifiers. These operational amplifiers also
feature exceptionally low 1/f noise, with a very low 1/f noise corner frequency of 4 Hz. This makes these parts
ideal for low power applications which require decent noise performance, such as PDAs and portable sensors.
7.3.4 Ground Sensing and Rail-to-Rail Output
The LMV65x each have a rail-to-rail output stage, which provides the maximum possible output dynamic range.
This is especially important for applications requiring a large output swing. The input common-mode range of this
family of devices includes the negative supply rail which allows direct sensing at ground in a single-supply
operation.
7.3.5 Small Size
The small footprint of the packages for the LMV65x saves space on printed-circuit boards, and enables the
design of smaller and more compact electronic products. Long traces between the signal source and the
operational amplifier make the signal path susceptible to noise. By using a physically smaller package, these
operational amplifiers can be placed closer to the signal source, reducing noise pickup and enhancing signal
integrity.
ROUT
-
+
VIN
RF
CF
RIN
RL
CL
RS
0
UNSTABLE
ROC = 40 dB/decade
STABLE
ROC ± 20 dB/decade
FREQUENCY (Hz)
GAIN
14
LMV651
,
LMV652
,
LMV654
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
www.ti.com
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated
7.4 Device Functional Modes
7.4.1 Stability and Capacitive Loading
If the phase margin of the LMV65x is plotted with respect to the capacitive load (CL) at its output, it is seen that
the phase margin reduces significantly if CLis increased beyond 100 pF. This is because the operational
amplifier is designed to provide the maximum bandwidth possible for a low supply current. Stabilizing it for higher
capacitive loads would have required either a drastic increase in supply current, or a large internal compensation
capacitance, which would have reduced the bandwidth of the operational amplifier. Hence, if these devices are to
be used for driving higher capacitive loads, they would have to be externally compensated.
Figure 34. Gain vs Frequency for an Operational Amplifiers
An operational amplifier, ideally, has a dominant pole close to DC, which causes its gain to decay at the rate of
20 dB/decade with respect to frequency. If this rate of decay, also known as the rate of closure (ROC), remains
the same until the unity-gain bandwidth of the operational amplifiers is stable. If, however, a large capacitance is
added to the output of the operational amplifier, it combines with the output impedance of the operational
amplifier to create another pole in its frequency response before its unity-gain frequency (see Figure 34). This
increases the ROC to 40 dB/decade and causes instability.
In such a case a number of techniques can be used to restore stability to the circuit. The idea behind all these
schemes is to modify the frequency response such that it can be restored to an ROC of 20 dB/decade, which
ensures stability.
7.4.2 In The Loop Compensation
Figure 35 illustrates a compensation technique, known as in-the-loop compensation, that employs an RC
feedback circuit within the feedback loop to stabilize a noninverting amplifier configuration. A small series
resistance, RS, is used to isolate the amplifier output from the load capacitance, CL, and a small capacitance, CF,
is inserted across the feedback resistor to bypass CLat higher frequencies.
Figure 35. In-the-Loop Compensation
CF = ¨
¨
©
§RF + 2RIN
RF2
¨
¨
©
§
CLROUT
RS = ROUTRIN
RF
15
LMV651
,
LMV652
,
LMV654
www.ti.com
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated
Device Functional Modes (continued)
The values for RSand CFare decided by ensuring that the zero attributed to CFlies at the same frequency as the
pole attributed to CL. This ensures that the effect of the second pole on the transfer function is compensated for
by the presence of the zero, and that the ROC is maintained at 20 dB/decade. For the circuit shown in Figure 35
the values of RSand CFare given by Equation 1. Values of RSand CFrequired for maintaining stability for
different values of CL, as well as the phase margins obtained, are shown in Table 1. RFand RIN are taken to be
10 k, RLis 2 k, while ROUT is taken as 340 .
(1)
Table 1. Loop Compensation Values
CL(pF) RS() CF(pF) PHASE MARGIN (°)
150 340 15 39.4
200 340 20 34.6
250 340 25 31.1
Although this methodology provides circuit stability for any load capacitance, it does so at the price of bandwidth.
The closed-loop bandwidth of the circuit is now limited by RFand CF.
7.4.3 Compensation By External Resistor
In some applications, it is essential to drive a capacitive load without sacrificing bandwidth. In such a case, in the
loop compensation is not viable. A simpler scheme for compensation is shown in Figure 36. A resistor, RISO, is
placed in series between the load capacitance and the output. This introduces a zero in the circuit transfer
function, which counteracts the effect of the pole formed by the load capacitance, and ensures stability. The
value of RISO to be used should be decided depending on the size of CLand the level of performance desired.
Values ranging from 5 to 50 are usually sufficient to ensure stability. A larger value of RISO results in a
system with lesser ringing and overshoot, but it also limits the output swing and the short-circuit current of the
circuit.
Figure 36. Compensation by Isolation Resistor
CC1
+VOUT
+
-
-
CF
VIN
+
-
RB1
V+
RB2
CC2
R2
R1
AV = -
R2
100 k:
R1
1 k:
= -100
16
LMV651
,
LMV652
,
LMV654
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
www.ti.com
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
With a low supply current, low power operation, and low harmonic distortion, the LMV65x devices are ideal for
wide-bandwidth, high gain amplification.
8.2 Typical Applications
8.2.1 High Gain, Low Power Inverting Amplifiers
Figure 37. High Gain Inverting Amplifier
8.2.1.1 Design Requirements
The wide unity-gain bandwidth allows these parts to provide large gain over a wide frequency range, while
driving loads as low as 2 kwith less than 0.003% distortion.
8.2.1.2 Detailed Design Procedure
Figure 37 is an inverting amplifier, with a 100-kfeedback resistor, R2, and a 1-kinput resistor, R1, and
provides a gain of 100. With the LMV65x, these circuits can provide gain of 100 with a 3-dB bandwidth of
120 kHz, for a quiescent current as low as 116 μA. Coupling capacitors CC1 and CC2 can be added to isolate the
circuit from DC voltages, while RB1 and RB2 provide DC biasing. A feedback capacitor CFcan also be added to
improve compensation.
CC2 RB1
RB2
CF
CC1
V+
AV = 1 + R2
R1
+
-
VIN
+
-
R1
1 k:
R2
1 M:
VOUT
+
-
= 1001
0 50 100 150 200
Signal Amplitudee
Time (us)
Vout (1V/div)
Vin (10mV/div)
C001
17
LMV651
,
LMV652
,
LMV654
www.ti.com
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated
Typical Applications (continued)
8.2.1.3 Application Curve
Figure 38. High Gain Inverting Amplifier Results
8.2.2 High Gain, Low Power Noninverting Amplifiers
With a low supply current, low power operation, and low harmonic distortion, the LMV65x devices are ideal for
wide-bandwidth, high gain amplification. The wide unity-gain bandwidth allows these parts to provide large gain
over a wide frequency range, while driving loads as low as 2 kwith less than 0.003% distortion. Figure 39 is a
noninverting amplifier with a gain of 1001, can provide that gain with a 3-dB bandwidth of 12 kHz, for a similar
low quiescent power dissipation. With the LMV65x, these circuits can provide gain of 100 with a 3-dB
bandwidth of 120 kHz, for a quiescent current as low as 116 μA. Coupling capacitors CC1 and CC2 can be added
to isolate the circuit from DC voltages, while RB1 and RB2 provide DC biasing. A feedback capacitor CFcan also
be added to improve compensation.
Figure 39. High Gain Noninverting Amplifier
8.2.3 Active Filters
With a wide unity-gain bandwidth of 12 MHz, low input-referred noise density, and a low power supply current,
the LMV65x devices are well suited for low-power filtering applications. Active filter topologies, like the Sallen-
Key low-pass filter shown in Figure 40, are very versatile, and can be used to design a wide variety of filters
(Chebyshev, Butterworth, or Bessel). The Sallen-Key topology, in particular, can be used to attain a wide range
of Q, by using positive feedback to reject the undesired frequency range.
-
+
C
R
C
m2R
VIN VOUT
R1
RG
18
LMV651
,
LMV652
,
LMV654
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
www.ti.com
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated
Typical Applications (continued)
In the circuit shown in Figure 40, the two capacitors appear as open circuits at lower frequencies and the signal
is simply buffered to the output. At high frequencies the capacitors appear as short circuits and the signal is
shunted to ground by one of the capacitors before it can be amplified. Near the cutoff frequency, where the
impedance of the capacitances is on the same order as Rgand Rf, positive feedback through the other capacitor
allows the circuit to attain the desired Q. The ratio of the two resistors, m2, provides a knob to control the value of
Q obtained.
Figure 40. Sallen-Key Low-Pass Filter
8.3 Dos and Don'ts
Do properly bypass the power supplies.
Do add series resistence to the output when driving capacitive loads, particularly cables, Muxes, and ADC inputs.
Do add series current limiting resistors and external Schottky clamp diodes if input voltage is expected to exceed
the supplies. Limit the current to 1 mA or less (1 kΩper volt).
9 Power Supply Recommendations
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI
recommends that 10-nF capacitors be placed as close as possible to the operational amplifier power supply pins.
For single supply, place a capacitor between V+and Vsupply leads. For dual supplies, place one capacitor
between V+and ground, and one capacitor between Vand ground.
19
LMV651
,
LMV652
,
LMV654
www.ti.com
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated
10 Layout
10.1 Layout Guidelines
To properly bypass the power supply, several locations on a printed-circuit board need to be considered. A
6.8-µF or greater tantalum capacitor must be placed at the point where the power supply for the amplifier is
introduced onto the board. Another 0.1-µF ceramic capacitor must be placed as close as possible to the power
supply pin of the amplifier. If the amplifier is operated in a single power supply, only the V+pin needs to be
bypassed with a 0.1-µF capacitor. If the amplifier is operated in a dual power supply, both V+and Vpins must
be bypassed.
It is good practice to use a ground plane on a printed-circuit board to provide all components with a low inductive
ground connection.
Surface mount components in 0805 size or smaller are recommended in the LMV651-N application circuits.
Designers can take advantage of the VSSOP miniature sizes to condense board layout in order to save space
and reduce stray capacitance.
10.2 Layout Example
Figure 41. LMV65x Layout Example
20
LMV651
,
LMV652
,
LMV654
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
www.ti.com
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LMV651 PSPICE Model http://www.ti.com/lit/zip/snom064
LMV652 PSPICE Model http://www.ti.com/lit/zip/snom065
LMV654 PSPICE Model http://www.ti.com/lit/zip/snom066
TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
TI Filterpro Software, http://www.ti.com/tool/filterpro
11.2 Documentation Support
11.2.1 Related Documentation
For additional applications, see the following:
AN-31 Op Amp Circuit Collection,SNLA140
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
LMV651 Click here Click here Click here Click here Click here
LMV652 Click here Click here Click here Click here Click here
LMV654 Click here Click here Click here Click here Click here
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
21
LMV651
,
LMV652
,
LMV654
www.ti.com
SNOSAI7K SEPTEMBER 2005REVISED MAY 2016
Product Folder Links: LMV651 LMV652 LMV654
Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated
11.7 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2016
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMV651MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM AY2A
LMV651MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM AY2A
LMV651MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A93
LMV651MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A93
LMV652MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AB3A
LMV652MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AB3A
LMV654MT/NOPB ACTIVE TSSOP PW 14 94 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV65
4MT
LMV654MTX/NOPB ACTIVE TSSOP PW 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV65
4MT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2016
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMV651MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV651MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV651MG/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV651MGX/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV652MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMV652MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMV654MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV651MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV651MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV651MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0
LMV651MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0
LMV652MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LMV652MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LMV654MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
LMV654MT/NOPB LMV654MTX/NOPB