M28V430-150N1 - SGS-Thomson

AI01854

A0-A17

DQ0-DQ14

VPP

VCC

M28V430

M28V440

VSS

BYTE

DQ15A-1

Figure 1. Logic Diagram

June 1996

M28V430

M28V440

LOW VOLTAGE

4 Megabit (x8 or x16, Block Erase) FLASH MEMORY

PRODUCT PREVIEW

DUAL x8 and x16 ORGANIZATION

SMALLSIZE PLASTIC PACKAGESTSOP48

and SO44

MEMORYERASE in BLOCKS

– One 16K Byte or 8K Word Boot Block (top or

bottom location)

– Two 8K Byte or 4K Word Key Parameter

Blocks

– One 96K Byte or 48K WordMain Block

– Three 128KByte or 64K Word Main Blocks

3.3V ±

0.3VSUPPLY VOLTAGE

12V

±5% PROGRAMMINGVOLTAGE

10,000PROGRAM/ERASE CYCLES

PROGRAM/ERASECONTROLLER

AUTOMATIC STATICMODE

LOW POWER CONSUMPTION

– 2mATypical in Static Operation

–55µATypical in Standby

– 0.2µA Typical in Deep Power Down

– 15/20mATypical Operating Consumption

(Byte/Word)

HIGH SPEED ACCESS TIME: 120ns

EXTENDEDTEMPERATURE RANGES

A0-A17 Address Inputs

DQ0-DQ7 Data Input / Outputs

DQ8-

DQ14 Data Input / Outputs

DQ15A-1 Data Input/Output or Address Input

E Chip Enable

G Output Enable

W Write Enable

BYTE Byte/Word Organization

RP Reset/Power Down

VPP Program & Erase Supply Voltage

VCC Supply Voltage

VSS Ground

Table 1. Signal Names

This ispreliminaryinformationon a new product now in development.Detailsare subjectto change without notice.

SO44 (M)

TSOP48 (N)

12 x 20mm

1/27

VSS

DQ9

DQ2

A1 E

A16A15

DQ5NC

BYTE

DQ4

DQ10

DQ3

VCC

DQ12NC

VPP

AI01855

M28V430

M28V440

(Normal)

24 25

A13

A14

DQ15A-1

DQ11

DQ0

VSS

A11

A12

A10 DQ14

DQ6

DQ13

DQ7

A17

A5 DQ8

DQ1

Figure 2A. TSOP Pin Connections

Warning: NC = Not Connected, DU = Don’t Use

DQ0

DQ8

VSS

A13

VSS

A14

A15

DQ7

A12

A16

BYTE

DQ15A-1

DQ5DQ2

DQ3 VCC

DQ11 DQ4

DQ14

WDU

VPP RP

AI01856

M28V430

M28V440

2322

17DQ1

DQ9

DQ6

DQ13

A11

A10

DQ10 21 DQ12

A17 A8

Figure 2B. SO Pin Connections

Warning: DU = Don’t Use

Symbol Parameter Value Unit

TAAmbient Operating Temperature –40 to 125 °C

TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2, 3) Input or Output Voltages –0.6 to 7 V

VCC Supply Voltage –0.6 to 7 V

VA9 (2) A9 Voltage –0.6 to 13.5 V

VPP (2) Program Supply Voltage, during Erase

or Programming –0.6 to 14 V

VRP (2) RP Voltage –0.6 to 13.5 V

Notes: 1. Exceptfor the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions abovethose indicated in the Operating sectionsof this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability.Refer also to the SGS-THOMSON SURE Programand other

relevant quality documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

3. Maximum DC voltage on I/O is VCC + 0.5V, overshoot to 7V allowedfor less than 20ns.

Table 2. Absolute Maximum Ratings (1)

2/27

M28V430, M28V440

Operation E G W RP BYTE DQ0 - DQ7 DQ8 - DQ14 DQ15A-1

Read Word VIL VIL VIH VIH VIH Data Output Data Output Data Output

Read Byte VIL VIL VIH VIH VIL Data Output Hi-Z Address Input

Write Word VIL VIH VIL VIH VIH Data Input Data Input Data Input

Write Byte VIL VIH VIL VIH VIL Data Input Hi-Z Address Input

Output Disable VIL VIH VIH VIH X Hi-Z Hi-Z Hi-Z

Standby VIH XXV

IH X Hi-Z Hi-Z Hi-Z

Power Down X X X VIL X Hi-Z Hi-Z Hi-Z

Note: X=V

IL or VIH,V

PP =V

PPL or VPPH

Table 3. Operations

DESCRIPTION

The M28V430and M28V440FLASH MEMORIES

are non-volatile memories that may be erased

electrically at the block level and programmed by

byte or word. The interface is directly compatible

with most microprocessors. SO44 and TSOP48

packagesare used.

Organization

The organization, as 512K x 8 or 256K x 16, is

selectable by an external BYTE signal. When

BYTEis Low and the x8 organizationis selected,

the Data Input/OutputsignalDQ15actsasAddress

line A-1 and selects the lower or upper byte of the

memorywordfor outputon DQ0-DQ7,DQ8-DQ14

remain high impedance. When BYTE is High the

memory uses the Addressinputs A0-A17 and the

Data Input/OutputsDQ0-DQ15. Memory control is

provided by Chip Enable,Output Enableand Write

Enable inputs. A Reset/PowerDown,two-level in-

put, places the memory in deep power down or

normal operation.

Organis

ation Code Device E G W BYTE A0 A9 A1-A8 &

A10-A17 DQ0 -

DQ7 DQ8 -

DQ14 DQ15

A-1

Word-

wide

Manufact.

Code VIL VIL VIH VIH VIL VID Don’t

Care 20h 00h 0

Device

Code

M28V430 VIL VIL VIH VIH VIH VID Don’t

Care 0F3h 00h 0

M28V440 VIL VIL VIH VIH VIH VID Don’t

Care 0FBh 00h 0

Byte-

wide

Manufact.

Code VIL VIL VIH VIL VIL VID Don’t

Care 20h Hi-Z Don’t

Care

Device

Code

M28V430 VIL VIL VIH VIL VIH VID Don’t

Care 0F3h Hi-Z Don’t

Care

M28V440 VIL VIL VIH VIL VIH VID Don’t

Care 0FBh Hi-Z Don’t

Care

Note: RP= VIH

Table 4. ElectronicSignature

3/27

M28V430, M28V440

Mnemo

nic Instruction Cycles 1st Cycle 2nd Cycle

Operation Address (1) Data (4) Operation Address Data

RD Read

Memory

Array 1+ Write X 0FFh Read (2) Read

Address Data

RSR Read

Status

RSIG Read

Electronic

Signature 3 Write X 90h Read (2) Signature

Adress (3) Signature

EE Erase 2 Write X 20h Write Block

Address 0D0h

PG Program 2 Write X 40h or 10h Write Address Data Input

CLRS Clear

Status

ES Erase

Suspend 1 Write X 0B0h

ER Erase

Resume 1 Write X 0D0h

Notes: 1. X =Don’t Care.

2. The first cycle of the RD, RSRor RSIG instruction is followedby read operations toread memory array, Status Register

or Electronic Signaturecodes. Any numberof Read cycle can occur after onecommand cycle.

3. Signatureaddress bit A0=VIL will outputManufacturer code.Address bit A0=VIH will output Device code. Other address bits are

ignored.

4.When word organizationis used, upper byte is don’t care for command input.

Table 5. Instructions

Hex Code Command

00h Invalid/Reserved

10h Alternative Program Set-up

20h Erase Set-up

40h Program Set-up

50h Clear Status Register

70h Read Status Register

90h Read Electronic Signature

0B0h Erase Suspend

0D0h Erase Resume/Erase Confirm

0FFh Read Array

Table 6. Commands

Blocks

Erasure of the memoriesis in blocks.There are 7

blocks in the memory address space, one Boot

Blockof 16KBytesor8K Words, two’KeyParame-

ter Blocks’ of 8K Bytes or 4K Words, one ’Main

Block’of 96K Bytesor 48KWords, and three ’Main

Blocks’of128KBytesor64KWords. TheM28V430

memory has the BootBlock at thetop of the mem-

ory address space (3FFFFh) and the M28V440

locates the Boot Block starting at the bottom

(00000h). Erasure of each block takes typically 1

second and each block can be programmed and

erased over 10,000 cycles.Block erasure maybe

suspendedwhile data is read from other blocks of

the memory, then resumed.

Bus Operations

Sixoperationscanbeperformedbytheappropriate

bus cycles, Read Byte or Word from the Array,

Read Electronic Signature, Output Disable,

Standby,Power Downand Writethe Commandof

an Instruction.

Command Interface

Commandscanbewrittentoa CommandInterface

(C.I.) latch toperform read,programming, erasure

and to monitorthe memory’s status. When power

is first applied, on exit from power down or if VCC

fallsbelow VLKO, the command interfaceis reset to

Read Memory Array.

4/27

M28V430, M28V440

Mnemon

ic Bit Name Logic

Level Definition Note

P/ECS 7 P/E.C. Status ’1’ Ready Indicates the P/E.C. status, check during Program

or Erase, and on completion before checkingbits

b4 orb5 for Program orErase Success

’0’ Busy

ESS 6 Erase

Suspend

Status

’1’ Suspended On an Erase Suspend instruction P/ECS and

ESS bits are set to ’1’. ESS bit remains ’1’until an

Erase Resume instruction is given.

’0’ In progress or

Completed

ES 5 Erase Status ’1’ Erase Error ES bit is set to ’1’if P/E.C. has appliedthe

maximum number of erase pulses to the block

without achieving an erase verify.

’0’ Erase Success

PS 4 Program

Status

’1’ Program Error PS bit set to ’1’ if the P/E.C. has failed to program

a byte orword.

’0’ Program

Success

VPPS 3 VPP Status ’1’ VPP Low, Abort VPPS bit is set if the VPP voltage is below

VPPH(min) when a Program or Erase instruction

has been executed.

’0’ VPP OK

2 Reserved

1 Reserved

0 Reserved

Notes: Logic level ’1’ is High, ’0’ is Low.

Table 7. Status Register

Instructions and Commands

Eight Instructions are defined to perform Read

Memory Array, Read Status Register, Read Elec-

tronic Signature, Erase, Program, Clear Status

internalProgram/EraseController(P/E.C.)handles

alltiming andverificationof the ProgramandErase

instructions and provides status bits to indicateits

operation and exit status. Instructions are com-

posed of a first command write operation followed

by either second command write, to confirm the

commands for programming or erase, or a read

operationtoreaddatafromthearray,theElectronic

Signatureor the StatusRegister.

For added data protection, theinstructionsfor byte

or word program and block erase consist of two

commands that are written to the memory and

which start theautomaticP/E.C. operation.Byte or

wordprogrammingtakestypically9µs, blockerase

typically1 second.Erasureofa memoryblockmay

be suspended in order to read data from another

blockandthenresumed.AStatusRegistermaybe

read atanytime, includingduringthe programming

or erase cycles, to monitor the progress of the

operation.

Power Saving

The M28V430 and M28V440 have a number of

power saving features. Following a Read access

the memory enters a static mode in which the

supply current is typically 2mA. A CMOS standby

mode is entered when the ChipEnable E and the

Reset/PowerDown (RP) signals are at VCC, when

the supply current drops to typically60µA. Adeep

power down mode is enabled when the Re-

set/Power Down (RP) signal is at VSS, when the

supply current drops to typically 0.2µA. The time

requiredto awakefromthedeeppowerdownmode

is 700ns maximum, with instructions to the C.I.

recognised afteronly 580ns.

5/27

M28V430, M28V440

SRAM Interface Levels EPROM Interface Levels

Input Rise and Fall Times ≤10ns ≤10ns

Input PulseVoltages 0 to 3V 0.45V to 2.4V

Input and Output TimingRef. Voltages 1.5V 0.8Vand 2V

Table 8. AC Measurement Conditions

AI01275

SRAM Interface

1.5V

2.4V

EPROM Interface

0.45V

2.0V

0.8V

Figure3. ACTesting Input Output Waveform

AI01276

1.3V

OUT

CL= 30pF or 100pF

CL= 30pF for SRAM Interface

CL= 100pF for EPROM Interface

CLincludes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

Figure 4. ACTesting Load Circuit

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN =0V 6 pF

OUT Output Capacitance VOUT =0V 12 pF

Note: 1. Sampled only, not 100% tested.

Table 9. Capacitance(1) (TA=25°C, f = 1 MHz )

DEVICE OPERATION

Signal Descriptions

A0-A17 Address Inputs. The address signals,

inputs for the memory array, are latched during a

writeoperation.

A9 Address Input is also used for the Electronic

SignatureOperation.WhenA9 is raisedto 12Vthe

ElectronicSignaturemay be read.The A0signal is

used to read two words or bytes, when A0 is Low

the Manufacturercode isreadand whenA0 isHigh

the Device code. When BYTE is Low DQ0-DQ7

output the codes and DQ8-DQ15 are don’t care,

when BYTE is High DQ0-DQ7 output the codes

and DQ8-DQ15 output 00h.

DQ0-DQ7 DataInput/Outputs. Thedata inputs, a

byte orthe lower byteof a word to be programmed

or a command to the C.I., are latched when both

ChipEnable EandWrite EnableW areactive.The

data output from the memory Array, the Electronic

Signature or Status Register is valid when Chip

Enable E and Output Enable G are active. The

output is high impedance when the chip is dese-

lected or the outputs are disabled.

DQ8-DQ14 and DQ15A-1 Data Input/Outputs.

These input/outputs are used in the word-wide

organization. When BYTE is High for the most

significant byte of the input or output, functioning

as described for DQ0-DQ7 above. When BYTE is

Low, DQ8-DQ14 are high impedance, DQ15A-1is

the Address A-1 input.

6/27

M28V430, M28V440

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤VIN ≤VCC ±1µA

ILO Output Leakage Current 0V ≤VOUT ≤VCC ±10 µA

ICC (1, 3) Supply Current (Read Byte-wide) TTL E = VIL,G=V

IL, f = 5MHz 25 mA

ICC (1, 3) Supply Current (Read Word-wide) TTL E = VIL,G=V

IL, f = 5MHz 25 mA

ICC (1, 3) Supply Current (Read Byte-wide) CMOS E = VSS,G=V

SS, f = 5MHz 20 mA

Supply Current (Read Word-wide) CMOS E = VSS,G=V

SS, f = 5MHz 25 mA

ICC1 (3) Supply Current (Standby) TTL E = VIH,RP=V

IH 200 µA

Supply Current (Standby) CMOS E=V

CC ±0.2V,

RP = VCC ±0.2V,

BYTE= VCC ±0.2V or VSS 80 µA

ICC2 (3) Supply Current (Power Down) RP = VSS ±0.2V 5 µA

ICC3 Supply Current (Program Byte-wide) Byte program in progress 50 mA

Supply Current (Program Word-wide) Word program in progress 60 mA

ICC4 Supply Current (Erase) Erase in progress 30 mA

ICC5 (2) Supply Current (Erase Suspend) E = VIH, Erasesuspended 10 mA

IPP Program Current (Reador Standby) VPP >V

CC 200 µA

IPP1 Program Leakage Current (Read or

Standby) VPP ≤VCC ±15 µA

IPP2 Program Current (Power Down) RP = VSS ±0.2V 5 µA

IPP3 Program Current (Program Byte-wide) Byte program in progress 30 mA

IPP3 Program Current (Program Word-wide) Word program in progress 40 mA

IPP4 Program Current (Erase) Erase in progress 30 mA

IPP5 Program Current (Erase Suspend) Erase suspended 200 µA

VIL Input Low Voltage –0.5 0.6 V

VIH Input High Voltage 2 VCC + 0.5 V

VOL Output Low Voltage IOL = 2mA 0.4 V

VOH Output High Voltage IOH = –2mA 2.4 V

VPPL Program Voltage(Normal operation) 0 4.1 V

VPPH Program Voltage(Program or Erase

operations) 5% range 11.4 12.6 V

VID A9 Voltage(Electronic Signature) 11.4 13 V

IID A9 Current (Electronic Signature) A9 = VID 500 µA

VLKO Supply Voltage(Erase and Program lock-

out) 2V

Notes: 1. Automatic Power Savingreduces ICC to ≤2mAtypical in static operation.

2. Currentincreases to ICC +I

CC5 during aread operation.

3. CMOS levels VCC ±0.2V and VSS ±0.2V. TTL levels VIH and VIL.

Table 10. DC Characteristics

(TA= 0 to70°C; VCC = 3.3V

±0.3V;VPP = 12V±5%)

7/27

M28V430, M28V440

Symbol Alt Parameter TestCondition

M28V430/440

Unit

-120 -150 -180

SRAM

Interface EPROM

Interface

Min Max Min Max Min Max

tAVAV tRC Address Validto

Next Address Valid E=V

IL,G=V

IL 120 150 180 ns

tAVQV tACC Address Valid to

Output Valid E=V

IL,G=V

IL 120 150 180 ns

tPHQV tPWH Power Down High

to Output Valid E=V

IL,G=V

IL 700 700 700 ns

tELQX (1) tLZ Chip Enable Low to

Output Transition G=V

IL 000ns

ELQV (2) tCE Chip Enable Low to

Output Valid G=V

IL 120 150 180 ns

tGLQX (1) tOLZ Output Enable Low

to Output Transition E=V

IL 000ns

GLQV (2) tOE Output Enable Low

to Output Valid E=V

IL 60 65 70 ns

tEHQX Chip Enable High

to Output Transition G=V

IL 000ns

EHQZ (1) tDF Chip Enable High

to Output Hi-Z G=V

IL 50 55 60 ns

tGHQX tOH Output Enable High

to Output Transition E=V

IL 000ns

GHQZ (1) tDF Output Enable High

to Output Hi-Z E=V

IL 45 50 55 ns

tAXQX tOH Address Transition

to Output Transition E=V

IL,G=V

IL 000ns

Notes: 1. Sampled only, not 100% tested.

2. G may bedelayed by up to tELQV -t

GLQV after the fallingedge of E without increasingtELQV.

Table 11. Read AC Characteristics

(TA= 0 to70°C; VCC = 3.3V

±0.3V;VPP = 12V±5%)

8/27

M28V430, M28V440

DQ0-DQ15

AI01281B

VALID

tAXQX

tAVAV

VALID

tGHQX

tGHQZ

tEHQX

tEHQZ

tAVQV

tELQV

tELQX

tGLQV

tGLQX

tPHQV

POWER-UP

AND STANDBY ADDRESS VALID

AND CHIP ENABLE OUTPUTS

ENABLED DATA VALID STANDBY

A-1, A0-A17

Figure5. Read Mode ACWaveforms

Note: Write Enable (W) = High

9/27

M28V430, M28V440

Symbol Alt Parameter

M28V430/440

Unit

-120 -150 -180

SRAM

Interface EPROM

Interface

Min Max Min Max Min Max

tAVAV tWC Write Cycle Time 120 150 180 ns

tPHWL tPS Power Down High to Write Enable

Low 111µs

ELWL tCS Chip Enable Low to Write Enable

Low 000ns

WLWH tWP Write Enable Low to Write Enable

High 100 100 100 ns

tDVWH tDS Input Validto WriteEnable High 100 100 100 ns

tWHDX tDH Write Enable High to Input

Transition 000ns

WHEH tCH Write Enable High to Chip Enable

High 10 10 10 ns

tWHWL tWPH Write Enable High to Write Enable

Low 50 50 50 ns

tAVWH tAS Address Validto Write Enable High 95 95 95 ns

tVPHWH tVPS VPP High to Write Enable High 200 200 200 ns

tWHAX tAH Write Enable High to Address

Transition 10 10 10 ns

tWHQV1 (1, 2) Write Enable High to Output Valid

(Word/Byte Program) 666µs

WHQV2 (1, 2) Write Enable High to Output Valid

(Boot Block Erase) 0.3 0.3 0.3 sec

tWHQV3 (1) Write Enable High to Output Valid

(Parameter Block Erase) 0.3 0.3 0.3 sec

tWHQV4 (1) Write Enable High to Output Valid

(Main Block Erase) 0.6 0.6 0.6 sec

tQVVPL Output Validto VPP Low 0 0 0 ns

Notes: 1. Time is measured to Status Register Read giving bit b7 =’1’.

2. For Program or Erase of the Boot Block RP must be at VHH.

Table 12. WriteAC Characteristics,Write Enable Controlled

(TA= 0 to70°C; VCC = 3.3V

±0.3V;VPP = 12V±5%)

10/27

M28V430, M28V440

DQ0-DQ15 COMMAND CMD or DATA STATUS REGISTER

VPP

VALIDA0-A17

tAVAV

tQVVPL

tAWVH tWHAX

PROGRAM OR ERASE

tELWL tWHEH

tWHDXtDVWH

tWLWH

tPHWL

tWHWL

tVPHWH

POWER-UP AND

SET-UP COMMAND CONFIRM

COMMAND

OR DATA INPUT STATUS REGISTER

READ

tWHQV1,2,3,4

AI01857

Figure 6. Program & EraseAC Waveforms, W Controlled

Note: Word-wide Address Data shown, for Byte-wide DQ15 becomes A-1. Command Input and Status Register Read output is on DQ0-DQ7 only.

11/27

M28V430, M28V440

Symbol Alt Parameter

M28V430/440

Unit

-120 -150 -180

SRAM

Interface EPROM

Interface

Min Max Min Max Min Max

tAVAV tWC Write Cycle Time 120 150 180 ns

tPHEL tPS Power Down High to Chip

Enable Low 111µs

WLEL tCS Write Enable Low to Chip

Enable Low 000ns

ELEH tWP Chip Enable Low to Chip Enable

High 100 100 100 ns

tDVEH tDS Input Valid to Chip Enable High 100 100 100 ns

tEHDX tDH Chip Enable High to Input

Transition 000ns

EHWH tCH Chip Enable High to Write

Enable High 10 10 10 ns

tEHEL tWPH Chip Enable High to Chip

Enable Low 50 50 50 ns

tAVEH tAS Address Validto Chip Enable

High 95 95 95 ns

tVPHEH tVPS VPP High to Chip Enable High 200 200 200 ns

tEHAX tAH Chip Enable Highto Address

Transition 10 10 10 ns

tEHQV1 (1, 2) Chip Enable High to Output

Valid (Word/Byte Program) 666µs

EHQV2 (1, 2) Chip Enable High to Output

Valid(Boot Block Erase) 0.3 0.3 0.3 sec

tEHQV3 (1) Chip Enable High to Output

Valid(Parameter Block Erase) 0.3 0.3 0.3 sec

tEHQV4 (1) Chip Enable High to Output

Valid(Main Block Erase) 0.6 0.6 0.6 sec

tQVVPL Output Validto VPP Low 0 0 0 ns

Note: 1. Time is measured to Status Register Read giving bit b7 =’1’.

2. For Program or Erase of the Boot Block RP must be at VHH.

Table 13. Write AC Characteristics,Chip Enable Controlled

(TA= 0 to70°C; VCC = 3.3V

±0.3V;VPP = 12V±5%)

12/27

M28V430, M28V440

DQ0-DQ15 COMMAND CMD or DATA STATUS REGISTER

VPP

VALIDA0-A17

tAVAV

tQVVPL

tAVEH tEHAX

PROGRAM OR ERASE

tWLEL tEHWH

tEHDXtDVEH

tELEH

tPHEL

tEHEL

tVPHEH

POWER-UP AND

SET-UP COMMAND CONFIRM COMMAND

OR DATA INPUT STATUS REGISTER

READ

tEHQV1,2,3,4

AI01858

Figure 7. Program & EraseAC Waveforms, E Controlled

13/27

M28V430, M28V440

Parameter Test Conditions M28V430/440 Unit

Min Typ Max

Main Block Program (Byte) VPP = 12V ±5% 2 6 sec

Main Block Program (Word) VPP = 12V ±5% 1 3 sec

Boot or Parameter Block Erase VPP = 12V ±5% 1 7 sec

Main Block Erase VPP = 12V ±5% 1.5 10 sec

Table 14. Word/Byte Program, Erase Times

(TA= 0 to70°C; VCC = 3.3V ±0.3V)

E Chip Enable. The Chip Enable activates the

memory control logic, input buffers, decoders and

sense amplifiers. E High de-selects the memory

andreducesthepowerconsumptiontothestandby

level. E can also be used to control writing to the

command register and to the memoryarray, while

W remains at a low level.Both addressesand data

inputs are then latched on the rising edge of E.

RP Reset/Power Down. This is a two-level input

which allows the memory to be putin deep power

down.

When RP is at VIH the deviceis in ”active” mode.

With RP Low the memoryis in deep powerdown,

and if RP is within VSS+0.2V the lowest supply

currentis absorbed.

G Output Enable. The Output Enable gates the

outputs through the data buffers during a read

operation.

W Write Enable. It controls writing to the Com-

mand Register and Input Address and Data

latches. Both Addresses and Data Inputs are

latched on the rising edge of W.

BYTE Byte/WordOrganizationSelect. Thisinput

selects either byte-wide or word-wideorganization

of the memory. When BYTEis Low the memory is

organized x8 or byte-wide and data input/output

uses DQ0-DQ7 while A-1 acts as the additional,

LSB, of the memory address that multiplexes the

upper or lower byte. In the byte-wideorganization

DQ8-DQ14 are high impedance. When BYTE is

High the memory is organized x16 and data in-

put/output uses DQ0-DQ15 with the memory ad-

dressedbyA0-A17.

VPP ProgramSupply Voltage.Thissupplyvoltage

is used for memory Programming and Erase.

VPP ±10% toleranceoptionis providedfor applica-

tionrequiringmaximum100writeanderasecycles.

VCC SupplyVoltage. Itis the maincircuit supply.

VSS Ground. It is the reference for all voltage

measurements.

Memory Blocks

Thememoryblocksof theM28V430and M28V440

are shown in Figure8. The difference betweenthe

twoproductsissimplyaninversionoftheblockmap

to position the Boot Block at the top or bottom of

the memory.The selection of the Boot Block atthe

top or bottom of the memory depends on the

microprocessor needs.

Each block of the memory can be erased sepa-

rately, but only by one block at a time. The erase

operation is managed by the P/E.C. but can be

suspendedinorder to readfromanother blockand

then resumed.

Programming and erasure of the memory is dis-

abled when the program supply is at VPPL. For

successfulprogrammingand erasurethe program

supplymust be at VPPH.

DEVICE OPERATION (cont’d)

14/27

M28V430, M28V440

Operations

Operationsare definedas specificbus cycles and

signals which allow memory Read, Command

Write, OutputDisable, Standby,Power Down, and

ElectronicSignature Read. They are shown in Ta-

ble 3.

Read. Read operations are used to output the

contentsof the Memory Array, the Status Register

or the Electronic Signature. Both Chip Enable E

and OutputEnable G must be low in order to read

the output of the memory. The Chip Enable input

alsoprovidespowercontrolandshouldbe usedfor

device selection.Output Enable shouldbe usedto

gatedataontotheoutputindependentofthedevice

selection.Aread operationwill outputeither abyte

or a word depending on the BYTE signal level.

WhenBYTEisLowtheoutputbyteisonDQ0-DQ7,

DQ8-DQ14 are Hi-Z and A-1 is an additional ad-

dress input.When BYTEis High the outputword is

on DQ0-DQ15.

The data read depends onthe previouscommand

written to the memory (see instructions RD, RSR

and RSIG).

Write. Writeoperationsareusedto giveInstruction

Commands to the memory or to latch input data to

be programmed.Awrite operation isinitiated when

Chip Enable E is Low and Write Enable W is Low

withOutputEnableGHigh.Commands,InputData

and Addressesare latchedon therisingedge of W

orE. Asfor the Read operation,when BYTEisLow

a byte is input,DQ8-DQ14 are ’don’tcare’ and A-1

is an additional address. When BYTE is High a

word is input.

Output Disable. Thedata outputsarehighimped-

ance when the Output Enable G is High with Write

EnableW High.

Standby.Thememoryis instandbywhentheChip

Enable E is High. The power consumption is re-

ducedto thestandbyleveland theoutputsarehigh

impedance, independent of the Output Enable G

or Write EnableW inputs.

PowerDown. ThememoryisinPowerDownwhen

RP is low. The power consumption is reduced to

the Power Down level, and Outputs are in high

impedance, independant of the Chip Enable E,

OutputEnable G or Write Enable W inputs.

8K BOOT BLOCK

AI01859

3FFFFh

3E000h

3DFFFh

3D000h

3CFFFh

3C000h

3BFFFh

00000h

4K PARAMETERBLOCK

48K MAIN BLOCK

64K MAIN BLOCK

30000h

2FFFFh

20000h

1FFFFh

10000h

0FFFFh

A0-A17 Word Wide

M28V430 TOPBOOT BLOCK

8K BOOT BLOCK

3FFFFh

30000h

2FFFFh

20000h

1FFFFh

10000h

0FFFFh

00000h

4K PARAMETER BLOCK

48K MAIN BLOCK

64K MAIN BLOCK

04000h

03FFFh

03000h

02FFFh

02000h

01FFFh

A0-A17 Word Wide

M28V440 BOTTOM BOOT BLOCK

Figure8. Memory Map, Word-wide Addresses

15/27

M28V430, M28V440

Electronic Signature. Two codes identifying the

manufacturerand the device can be read from

the memories, the manufacturer code for SGS-

THOMSONis 20h, and thedevicecodes are 0F3h

fortheM28V430(Top BootBlock) and0FBhforthe

M28V440(BottomBootBlock).These codesallow

programming equipment or applications to auto-

maticallymatchtheirinterfacetothecharacteristics

of the particular manufacturer’sproduct.

TheElectronicSignatureis outputby a ReadArray

operationwhen the voltage appliedto A9 isat VID,

the manufacturercodeis output when the Address

inputA0isLowandthedevicecodewhenthis input

is High. Other Address inputs are ignored. The

codes are output on DQ0-DQ7. When the BYTE

signal is High the outputs DQ8-DQ15 output 00h,

when Low these outputs are high impedance and

Addressinput A-1 is ignored.

The ElectronicSignaturecanalsobe read,without

raising A9 to VID, after giving the memory the

instruction RSIG (see below).

Instructions and Commands

The memories include aCommand Interface(C.I.)

which latches commands written to the memory.

Instructionsare made up from one or more com-

mands to perform memory Read, Read Status

gram, Clear Status Register, Erase Suspend and

Erase Resume. These instructions require from 1

to 3 operations,the firstof whichis always a write

operation and is followed by either a further write

operation to confirm the first command or a read

operation(s) to output data.

A Status Register indicates the P/E.C. status

Ready or Busy, the suspend/in-progressstatus of

erase operations, the failure/successof erase and

program operations and the low/correct value of

the ProgramSupply voltage VPP.

The P/E.C. automatically sets bits b3 to b7 and

clears bit b6 & b7. It cannotclearbits b3 to b5.The

(RSR) instructionand cleared by the Clear Status

bits b3 tob7 isshown in Table 7. Bitsb0 to b2 are

reserved for futureuse (and shouldbemasked out

duringstatus checks).

Read (RD) instruction. TheRead instruction con-

sists of one write operation giving the command

0FFh. Subsequent read operations will read the

addressedmemoryarraycontentandoutputabyte

or word depending on the level of the BYTEinput.

Read Status Register (RSR) instruction. The

Read Status Register instruction may be given at

any time, including while the Program/EraseCon-

troller is active. It consists of one write operation

givingthecommand 70h.SubsequentReadopera-

tions output the contents of the Status Register.

The contents of the status register are latched on

the fallingedge of E or G signals, and can be read

until E or G returns to its initial high level. Either E

or G must be toggled to VIH to update the latch.

Additionally, any read attempt during program or

erase operation will automaticallyoutput the con-

tents of the StatusRegister.

Read Electronic Signature (RSIG) instruction.

Thisinstructionuses3operations.Itconsistsofone

write operation giving the command 90h followed

by two read operations to output the manufacturer

and devicecodes. The manufacturercode, 20h, is

output when the address line A0 is Low, and the

devicecode,0F3hfortheM28V430or0FBhforthe

M28V440, when A0 is High.

Erase (EE) instruction. This instructionuses two

write operations.The first command written is the

Erase Set-up command 20h. The second com-

mand isthe Erase Confirm command0D0h.During

the inputofthe second command anaddressof the

block to be erased is given and thisis latched into

the memory. If the second command given is not

the EraseConfirmcommandthen the statusregis-

ter bitsb4andb5areset andtheinstructionaborts.

Read operations output the status register after

erasure hasstarted.

Duringtheexecutionof theerasebytheP/E.C.,the

memory acceptsonly the RSR (ReadStatus Reg-

ister) and ES(Erase Suspend)instructions.Status

progressand ’1’ whenit hascompleted.Aftercom-

pletion the StatusRegister bit b5 returns ’1’ if there

has been an Erase Failure because erasure has

not been verified evenafter the maximumnumber

of erase cycles have been executed.Status Reg-

isterbitb3returns’1’ifVPP doesnotremain atVPPH

level when the erasureis attemptedand/orproced-

ing.

VPP must be at VPPH when erasing, erase should

not be attempted when VPP <VPPH as the results

willbeuncertain.IfVPP fallsbelowVPPH orRP goes

Low the erase aborts and must be repeated, after

having cleared the Status Register(CLRS).

The BootBlockcanonlybeerasedwhenRPis also

at VHH.

Program (PG) instruction. This instruction uses

two write operations. The first command written is

the Program Set-up command 40h (or 10h). A

secondwriteoperationlatchestheAddressandthe

Data to be written and starts the P/E.C. Read

operationsoutput the statusregister afterthe pro-

gramming has started.

Memory programmingis onlymadeby writing ’0’in

place of’1’ in a byteor word.

16/27

M28V430, M28V440

During the execution of the programming by the

P/E.C., the memory accepts only the RSR (Read

StatusRegister)instruction.TheStatusRegisterbit

b7 returns’0’ while the programming is in progress

and’1’when ithascompleted.After completionthe

Status register bitb4 returns ’1’ if therehas been a

Program Failure. Status Register bit b3 returns a

’1’ if VPP does not remain at VPPH when program-

mingis attemptedand/orduring programming.

VPP mustbeatVPPH whenprogramming,program-

ming should not be attempted when VPP <V

PPH

as the results will be uncertain. Programming

abortsif VPP dropsbelowVPPH or RP goes Low. If

aborted the data may be incorrect. Then after

having cleared the Status Register (CLRS), the

memory must be erased and re-programmed.

The BootBlockcan onlybe programmed when RP

is at VIH.

Clear Status Register (CLRS) instruction. The

Clear StatusRegister usesa single writeoperation

which clears bits b3, b4 and b5, if latched to ’1’ by

the P/E.C., to ’0’. Its use is necessary before any

new operation when an error has been detected.

Erase Suspend (ES) instruction. The Erase op-

erationmay besuspendedbythisinstructionwhich

consistsof writing the command 0B0h.TheStatus

actually been suspended,b6 =’1’, or whether the

P/E.C. cycle was the last and the erase is com-

pleted,b6 = ’0’.

During the suspension the memory will respond

only to Read (RD), Read Status Register (RSR) or

Erase Resume (ER) instructions.Read operations

initially output the status register while erase is

suspendedbut, following a Read instruction,data

fromother blocksof the memory can be read. VPP

must be maintained at VPPH while erase is sus-

pended.If VPP does not remain at VPPH or the RP

signal goes Low while erase is suspended then

erase is aborted while bits b5 and b3 of the status

after having cleared the status register, to be cer-

tain to erase the block.

Erase Resume(ER) instruction. If anErase Sus-

pend instruction was previously executed, the

erase operation may be resumed by giving the

command 0D0h. The status register bit b6 is

cleared when erasure resumes. Read operations

output the status register after the erase is re-

sumed.

The suggested flow charts for programs that use

the programming, erasure and erase suspend/re-

sumefeaturesofthememoriesareshowninFigure

9 to Figure11.

Programming. The memory can be programmed

byte-by-byte(orword-by-wordinx16organization).

The Program Supply voltage VPP must be applied

before program instructions are given, and if the

programmingis inthe BootBlock, RPmustalso be

raisedtoVIH tounlocktheBootBlock.TheProgram

Supplyvoltage maybeappliedcontinuouslyduring

programming.

The program sequenceis startedby writing a Pro-

gram Set-up command (40h) to the Command

Interface,thisisfollowedbywritingtheaddressand

data byte or word to the memory. The Pro-

gram/EraseControllerautomaticallystartsandper-

forms the programming after the second write

operation,providing that the VPP voltage(and RP

voltageifprogramming theBootBlock)arecorrect.

During the programming the memory status is

checkedby readingthe statusregister bit b7which

showsthe statusof the P/E.C.Bit b7 = ’1’ indicates

that programming is completed.

A full status check can be made after each

byte/word or after a sequence of data has been

programmed. The status check is made on bit b3

for any possible VPP error and on bit b4 for any

possibleprogramming error.

Erase. The memorycan be erasedby blocks. The

ProgramSupply voltage VPP must be applied be-

fore the Erase instructionis given, and if the Erase

is of the Boot Block RP must also be raised to VIH

to unlock the Boot Block. The Erase sequence is

startedby writing an Erase Set-upcommand (20h)

to the Command Interface, this is followed by an

address in the block to be erased and the Erase

Confirm command (0D0h).

TheProgram/Erase Controllerautomaticallystarts

and performs the block erase, providing the VPP

voltage (and the RP voltage if the erase is of the

BootBlock) iscorrect.Duringtheerasethememory

statusis checked by reading the status register bit

b7 which shows the status of the P/E.C. Bit b7 =

’1’ indicates that erase is completed.

A full status check can be made after the block

erasebycheckingbit b3for anypossibleVPP error,

bits b5 and b6 for any command sequence errors

(erase suspended) and bit b5 alone for an erase

error.

Reset. Note that after any program or erase in-

struction has completed with an errorindication or

after any VPP transitions down to VPPL the Com-

mand Interface must be reset by a Clear Status

DEVICE OPERATION (cont’d)

17/27

M28V430, M28V440

Automatic Power Saving

The M28V430 and M28V440 memories place

themselvesin a lowerpowerstate when not being

accessed. Following a Read operation, after a

delay equalto the memoryaccesstime,the Supply

Current is reduced from a typical read current of

20mA (CMOS inputs, word-wide organization) to

less than 2mA.

Power Down

The memories provide a powerdown control input

RP. When this signal is taken to below VSS + 0.2V

all internal circuits are switchedoff and the supply

current drops to typically 0.2µA and the program

current to typically 0.1µA. If RP is takenlow during

a memoryread operation then the memory is de-

selectedand theoutputs become highimpedance.

If RP is taken low during a program or erase

sequence then it is abortedand the memory con-

tent is no longervalid.

Recovery from deep power down requires 700ns

to a memory read operation, or 580ns to a com-

mand write. On return from power down the status

PowerUp

The Supplyvoltage VCC and the Program Supply

voltageVPP can beappliedinany order. Themem-

ory Command Interface is reset on power up to

Read Memory Array, but a negative transition of

Chip Enable E or a change of the addresses is

required to ensure valid data outputs. Care must

be taken to avoid writes to the memorywhen VCC

is aboveVLKO and VPP powersup first.Writes can

be inhibited by driving either E or W to VIH. The

memory is disabled until RP is up to VIH.

Supply Rails

Normal precautionsmust be takenfor supply volt-

age decoupling, each device in a system should

have theVCC andVPP rails decoupledwitha 0.1µF

capacitor close to the VCC and VSS pins. The PCB

trace widths should be sufficient to carry the VPP

program and erase currents required.

18/27

M28V430, M28V440

Write

40h

Command

AI01278

Start

Write

Address

& Data

Read Status

YES

b7=1

YES

b3=0

YES

b4=0

End

VPP

Low

Error (1, 2)

Program

Error (1, 2)

instruction:

– write 40h

command

– write Address &

Data

(memory enters read status

state after the PG instruction)

do:

– read status

(E or G must be toggled)

while b7 = 1

If b3 = 0, VPP low

error:

– error handler

If b4 = 0, Program

error:

– error handler

Figure9. Program Flow-chart and Pseudo Code

Notes: 1. Status check of b3 (VPP Low) and b4 (Program Error) can be made after each byte/word programming or after a sequence.

2. Ifa VPP Low or Program Erase is found,the StatusRegister mustbe cleared (CLRS instruction) before further P/E.C.operations.

19/27

M28V430, M28V440

Write

20h

Command

AI01279

Start

Write Block

Address

& 0D0h Command

Read Status

YES

b7=1

YES

b3=0

YES

b4, b5 = 1

End

VPP

Low

Error (1)

Command

Sequence Error

instruction:

– write 20h

command

– write Block

Address

(A12-A17) & command

0D0h

(memory enters read status

state after the EE instruction)

do:

– read status

(E or G must be

toggled)

if EE instruction given

execute

suspend erase loop

while b7 = 1

If b3 = 0, VPP low

error:

– error handler

If b4, b5 = 0, Command Sequence

error:

– error handler

YES

b5=0

Erase

Error (1)

YES

Suspend

Loop

If b5 = 0, Erase

error:

– error handler

Figure 10. Erase Flow-chart and Pseudo Code

Note: 1. If VPP Low or Erase Error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.

20/27

M28V430, M28V440

Write

0B0h

Command

AI01280

Start

Read Status

YES

b7=1

YES

b6=1

Erase Continues

Erase

Complete

Write

0FFh

Command

instruction:

– write 0B0h

command

(memory enters read register

state after the ES instruction)

do:

– read status

(E or G must be toggled)

while b7 = 1

If b6 = 0, Erase

completed

(at this point the memory

wich

accept only the RD or ER instruction)

instruction:

– write 0FFh

command

– one o more data

reads

from another block

Write

0D0h

Command ER

instruction:

– write 0D0h

command

to resume erasure

Read data

from

another block

Figure 11. EraseSuspend & Resume Flow-chart and PseudoCode

21/27

M28V430, M28V440

AI01286C

BYTE

IDENTIFIER

YES

90h

READ

STATUS

YES

70h NO

CLEAR

STATUS

YES

50h NO

PROGRAM

SET-UP

YES

40h

10h NO

ERASE

SET-UP

YES

20h NO

ERASE

COMMAND

ERROR

YES

0FFh

WAIT FOR

COMMAND

WRITE (1)

READ

STATUS

READ

ARRAY

PROGRAM

READ

STATUS

YES READY

(2)

NO YES

OD0h NO

Figure12. Command Interface and ProgramErase Controller Flow-diagram (a)

Notes: 1. If no command is written, the Command Interface remains in its previous valid state. Upon power-up, on exit from power-down or

ifVCC falls below VLKO, the Command Interface defaults to ReadArray mode.

2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.

22/27

M28V430, M28V440

AI01287B

READ

STATUS

YES

70h

ERASE

YES READY

(2)

0B0h NO

READ

STATUS

YES READY

(2)

ERASE

SUSPEND

YES

0D0h

READ

STATUS

READ

ARRAY

YES

ERASE

SUS PENDED

READ

STATUS

(READ STATUS)

YES

(ERASE RESUME)

Figure13. Command Interface and ProgramErase Controller Flow-diagram (b)

Note: 2. P/E.C. status(Ready or Busy) is read on Status Register bit 7.

23/27

M28V430, M28V440

ORDERING INFORMATION SCHEME

For a list of availableoptions (Op. Voltage, Array Organisation,Speed, etc...) refer to the current Memory

Shortformcatalogue.

For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office

nearestto you.

Operating Voltage

V 3.3V

Speed

-120 120ns

-150 150ns

-180 180ns

Array Org.

3 Top Boot

4 Bottom Boot

Temp.Range

1 0 to 70 °C

3 –40 to 125 °C

6 –40 to 85 °C

Option

TR Tape & Reel

Packing

Package

M SO44

N TSOP48

12 x 20mm

Example: M28V430 -120 N 1 TR

24/27

M28V430, M28V440

TSOP-a

N/2

DIE

LA1 α

Symb mm inches

Typ Min Max Typ Min Max

A 1.20 0.047

A1 0.05 0.15 0.002 0.006

A2 0.95 1.05 0.037 0.041

B 0.17 0.27 0.007 0.011

C 0.10 0.21 0.004 0.008

D 19.80 20.20 0.780 0.795

D1 18.30 18.50 0.720 0.728

E 11.90 12.10 0.469 0.476

e 0.50 - - 0.020 - -

L 0.50 0.70 0.020 0.028

α0°5°0°5°

N48 48

CP 0.10 0.004

TSOP56

TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm

Drawing is not to scale

25/27

M28V430, M28V440

SO-b

LA1 α

Symb mm inches

Typ Min Max Typ Min Max

A 2.42 2.62 0.095 0.103

A1 0.22 0.23 0.009 0.010

A2 2.25 2.35 0.089 0.093

B 0.50 0.020

C 0.10 0.25 0.004 0.010

D 28.10 28.30 1.106 1.114

E 13.20 13.40 0.520 0.528

e 1.27 0.050

H 15.90 16.10 0.626 0.634

L 0.80 0.031

α3°3°

N44 44

CP 0.10 0.004

SO44

SO44 - 44 lead Plastic Small Outline, 525 mils body width

Drawing is not to scale

26/27

M28V430, M28V440

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the

consequences of use of such information nor for any infringementof patents or other rights ofthird parties which may result from its use. No

license is granted by implication or otherwise under anypatent or patent rights ofSGS-THOMSON Microelectronics. Specificationsmentioned

in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronics products are not authorized for useas critical components in life supportdevices or systemswithout express

written approval of SGS-THOMSON Microelectronics.

1996 SGS-THOMSON Microelectronics - AllRights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China -France - Germany - Hong Kong - Italy -Japan - Korea- Malaysia -Malta - Morocco - The Netherlands -

Singapore- Spain - Sweden - Switzerland - Taiwan- Thailand - United Kingdom- U.S.A.

27/27

M28V430, M28V440