M28V430 M28V440 LOW VOLTAGE 4 Megabit (x8 or x16, Block Erase) FLASH MEMORY PRODUCT PREVIEW DUAL x8 and x16 ORGANIZATION SMALL SIZE PLASTIC PACKAGES TSOP48 and SO44 MEMORY ERASE in BLOCKS - One 16K Byte or 8K Word Boot Block (top or bottom location) - Two 8K Byte or 4K Word Key Parameter Blocks - One 96K Byte or 48K Word Main Block - Three 128K Byte or 64K Word Main Blocks 3.3V 0.3V SUPPLY VOLTAGE 12V 5% PROGRAMMING VOLTAGE 10,000 PROGRAM/ERASE CYCLES PROGRAM/ERASE CONTROLLER AUTOMATIC STATIC MODE LOW POWER CONSUMPTION - 2mA Typical in Static Operation - 55A Typical in Standby - 0.2A Typical in Deep Power Down - 15/20mA Typical Operating Consumption (Byte/Word) HIGH SPEED ACCESS TIME: 120ns EXTENDED TEMPERATURE RANGES 44 1 SO44 (M) TSOP48 (N) 12 x 20mm Figure 1. Logic Diagram VCC VPP 18 Table 1. Signal Names A0-A17 Address Inputs DQ0-DQ7 Data Input / Outputs DQ8DQ14 Data Input / Outputs DQ15A-1 Data Input/Output or Address Input E Chip Enable G Output Enable W Write Enable BYTE Byte/Word Organization RP Reset/Power Down VPP Program & Erase Supply Voltage VCC Supply Voltage VSS Ground DQ15A-1 A0-A17 15 RP W DQ0-DQ14 M28V430 M28V440 BYTE E G VSS AI01854 June 1996 This is preliminary infor mationon a new product now in developmen t. Details are subjectto change without not ice. 1/27 M28V430, M28V440 Figure 2A. TSOP Pin Connections 1 A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP VPP NC DU NC A17 A7 A6 A5 A4 A3 A2 A1 12 13 Figure 2B. SO Pin Connections 48 M28V430 M28V440 (Normal) 24 A16 BYTE VSS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 37 36 25 VPP DU A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 M28V430 34 12 M28V440 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 24 21 22 23 RP W A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC AI01856 AI01855 Warning: NC = Not Connected, DU = Don't Use Warning: DU = Don't Use Table 2. Absolute Maximum Ratings (1) Symbol TA Parameter Ambient Operating Temperature Value -40 to 125 Unit C TBIAS Temperature Under Bias -50 to 125 C TSTG Storage Temperature -65 to 150 C Input or Output Voltages -0.6 to 7 V VIO (2, 3) VCC Supply Voltage -0.6 to 7 V VA9 (2) A9 Voltage -0.6 to 13.5 V VPP (2) Program Supply Voltage, during Erase or Programming -0.6 to 14 V VRP (2) RP Voltage -0.6 to 13.5 V Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns. 3. Maximum DC voltage on I/O is VCC + 0.5V, overshoot to 7V allowed for less than 20ns. 2/27 M28V430, M28V440 Table 3. Operations Operation E G W RP BYTE DQ0 - DQ7 DQ8 - DQ14 DQ15A-1 Read Word VIL VIL VIH VIH VIH Data Output Data Output Data Output Read Byte VIL VIL VIH VIH VIL Data Output Hi-Z Address Input Write Word VIL VIH VIL VIH VIH Data Input Data Input Data Input Write Byte VIL VIH VIL VIH VIL Data Input Hi-Z Address Input Output Disable VIL VIH VIH VIH X Hi-Z Hi-Z Hi-Z Standby VIH X X VIH X Hi-Z Hi-Z Hi-Z X X X VIL X Hi-Z Hi-Z Hi-Z Power Down Note: X = VIL or VIH, VPP = VPPL or VPPH Table 4. Electronic Signature Organis ation Code Device Manufact. Code Wordwide Device Code Device Code G W BYTE A0 A9 A1-A8 & A10-A17 DQ0 DQ7 DQ8 DQ14 DQ15 A-1 VIL VIL VIH VIH VIL VID Don't Care 20h 00h 0 VIL VIH VIH VID Don't Care 0F3h 00h 0 VIL VIH VIH VID Don't Care 0FBh 00h 0 VIL VIH VIL VID Don't Care 20h Hi-Z Don't Care VIL VIH VIH VID Don't Care 0F3h Hi-Z Don't Care VIL VIH VIH VID Don't Care 0FBh Hi-Z Don't Care M28V430 VIL M28V440 VIL Manufact. Code Bytewide E VIL M28V430 VIL M28V440 VIL VIH VIH VIL VIL VIL Note: RP = VIH DESCRIPTION The M28V430 and M28V440 FLASH MEMORIES are non-volatile memories that may be erased electrically at the block level and programmed by byte or word. The interface is directly compatible with most microprocessors. SO44 and TSOP48 packages are used. Organization The organization, as 512K x 8 or 256K x 16, is selectable by an external BYTE signal. When BYTE is Low and the x8 organization is selected, the Data Input/Outputsignal DQ15 acts as Address line A-1 and selects the lower or upper byte of the memory word for output on DQ0-DQ7, DQ8-DQ14 remain high impedance. When BYTE is High the memory uses the Address inputs A0-A17 and the Data Input/OutputsDQ0-DQ15. Memory control is provided by Chip Enable, Output Enable and Write Enable inputs. A Reset/Power Down, two-level input, places the memory in deep power down or normal operation. 3/27 M28V430, M28V440 Table 5. Instructions Mnemo nic Instruction 1st Cycle Cycles Operation Address (1) 2nd Cycle Data (4) Operation Address Data Read Address Data X Status Register Signature (3) Adress Signature RD Read Memory Array 1+ Write X 0FFh RSR Read Status Register 1+ Write X 70h Read (2) RSIG Read Electronic Signature 3 Write X 90h Read EE Erase 2 Write X 20h Write Block Address 0D0h PG Program 2 Write X 40h or 10h Write Address Data Input CLRS Clear Status Register 1 Write X 50h ES Erase Suspend 1 Write X 0B0h ER Erase Resume 1 Write X 0D0h Read (2) (2) Notes: 1. X = Don't Care. 2. The first cycle of the RD, RSR or RSIG instruction is followed by read operations to read memory array, Status Register or Electronic Signature codes. Any number of Read cycle can occur after one command cycle. 3. Signature address bit A0=VIL will output Manufacturer code. Address bit A0=VIH will output Device code. Other address bits are ignored. 4. When word organization is used, upper byte is don't care for command input. 00h Invalid/Reserved 10h Alternative Program Set-up 20h Erase Set-up 40h Program Set-up 50h Clear Status Register ter Blocks' of 8K Bytes or 4K Words, one 'Main Block' of 96K Bytes or 48K Words, and three 'Main Blocks'of 128K Bytes or 64K Words. The M28V430 memory has the Boot Block at the top of the memory address space (3FFFFh) and the M28V440 locates the Boot Block starting at the bottom (00000h). Erasure of each block takes typically 1 second and each block can be programmed and erased over 10,000 cycles. Block erasure may be suspended while data is read from other blocks of the memory, then resumed. 70h Read Status Register Bus Operations 90h Read Electronic Signature Six operationscan beperformed by the appropriate bus cycles, Read Byte or Word from the Array, Read Electronic Signature, Output Disable, Standby, Power Down and Write the Command of an Instruction. Table 6. Commands Hex Code Command 0B0h Erase Suspend 0D0h Erase Resume/Erase Confirm 0FFh Read Array Blocks Erasure of the memories is in blocks. There are 7 blocks in the memory address space, one Boot Block of 16K Bytes or 8K Words, two 'Key Parame- 4/27 Command Interface Commands can be written to a Command Interface (C.I.) latch to perform read, programming, erasure and to monitor the memory's status. When power is first applied, on exit from power down or if VCC falls below VLKO, the command interface is reset to Read Memory Array. M28V430, M28V440 Table 7. Status Register Mnemon ic Bit Name P/ECS 7 P/E.C. Status ESS ES PS VPPS 6 5 4 3 Erase Suspend Status Logic Level Definition Note '1' Ready Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits b4 or b5 for Program or Erase Success '0' Busy '1' Suspended '0' In progress or Completed '1' Erase Error '0' Erase Success '1' Program Error '0' Program Success '1' VPP Low, Abort '0' VPP OK On an Erase Suspend instruction P/ECS and ESS bits are set to '1'. ESS bit remains '1' until an Erase Resume instruction is given. Erase Status Program Status VPP Status 2 Reserved 1 Reserved 0 Reserved ES bit is set to '1' if P/E.C. has applied the maximum number of erase pulses to the block without achieving an erase verify. PS bit set to '1' if the P/E.C. has failed to program a byte or word. VPPS bit is set if the VPP voltage is below VPPH(min) when a Program or Erase instruction has been executed. Notes: Logic level '1' is High, '0' is Low. Instructions and Commands Eight Instructions are defined to perform Read Memory Array, Read Status Register, Read Electronic Signature, Erase, Program, Clear Status Register, Erase Suspend and Erase Resume. An internalProgram/EraseController (P/E.C.) handles all timing and verification of the Program and Erase instructions and provides status bits to indicate its operation and exit status. Instructions are composed of a first command write operation followed by either second command write, to confirm the commands for programming or erase, or a read operationto read data from the array, the Electronic Signature or the Status Register. For added data protection, the instructions for byte or word program and block erase consist of two commands that are written to the memory and which start the automatic P/E.C. operation. Byte or word programming takes typically 9s, block erase typically 1 second. Erasure of a memory block may be suspended in order to read data from another block and then resumed. A Status Register may be read at any time, including during the programming or erase cycles, to monitor the progress of the operation. Power Saving The M28V430 and M28V440 have a number of power saving features. Following a Read access the memory enters a static mode in which the supply current is typically 2mA. A CMOS standby mode is entered when the Chip Enable E and the Reset/Power Down (RP) signals are at VCC, when the supply current drops to typically 60A. A deep power down mode is enabled when the Reset/Power Down (RP) signal is at VSS, when the supply current drops to typically 0.2A. The time required to awake from the deep power down mode is 700ns maximum, with instructions to the C.I. recognised after only 580ns. 5/27 M28V430, M28V440 Table 8. AC Measurement Conditions SRAM Interface Levels EPROM Interface Levels Input Rise and Fall Times 10ns 10ns Input Pulse Voltages 0 to 3V 0.45V to 2.4V 1.5V 0.8V and 2V Input and Output Timing Ref. Voltages Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit 1.3V SRAM Interface 1N914 3V 1.5V 3.3k 0V DEVICE UNDER TEST EPROM Interface 2.4V OUT CL = 30pF or 100pF 2.0V 0.8V 0.45V CL = 30pF for SRAM Interface CL = 100pF for EPROM Interface AI01275 CL includes JIG capacitance AI01276 Table 9. Capacitance (1) (TA = 25 C, f = 1 MHz ) Symbol CIN COUT Parameter Test Condition Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Input Capacitance Output Capacitance Min Note: 1. Sampled only, not 100% tested. DEVICE OPERATION Signal Descriptions A0-A17 Address Inputs. The address signals, inputs for the memory array, are latched during a write operation. A9 Address Input is also used for the Electronic Signature Operation. When A9 is raised to 12V the Electronic Signature may be read. The A0 signal is used to read two words or bytes, when A0 is Low the Manufacturercode is read and when A0 is High the Device code. When BYTE is Low DQ0-DQ7 output the codes and DQ8-DQ15 are don't care, when BYTE is High DQ0-DQ7 output the codes and DQ8-DQ15 output 00h. 6/27 DQ0-DQ7 Data Input/Outputs. The data inputs, a byte or the lower byte of a word to be programmed or a command to the C.I., are latched when both Chip Enable E and Write Enable W are active. The data output from the memory Array, the Electronic Signature or Status Register is valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected or the outputs are disabled. DQ8-DQ14 and DQ15A-1 Data Input/Outputs. These input/outputs are used in the word-wide organization. When BYTE is High for the most significant byte of the input or output, functioning as described for DQ0-DQ7 above. When BYTE is Low, DQ8-DQ14 are high impedance, DQ15A-1 is the Address A-1 input. M28V430, M28V440 Table 10. DC Characteristics (TA = 0 to 70C; VCC = 3.3V 0.3V; VPP = 12V5%) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current Test Condition Min Max Unit 0V VIN VCC 1 A 0V VOUT VCC 10 A ICC (1, 3) Supply Current (Read Byte-wide) TTL E = VIL, G = VIL, f = 5MHz 25 mA ICC (1, 3) Supply Current (Read Word-wide) TTL E = VIL, G = VIL, f = 5MHz 25 mA ICC (1, 3) Supply Current (Read Byte-wide) CMOS E = VSS, G = VSS, f = 5MHz 20 mA Supply Current (Read Word-wide) CMOS E = VSS, G = VSS, f = 5MHz 25 mA E = VIH, RP = VIH 200 A E = VCC 0.2V, RP = VCC 0.2V, BYTE = VCC 0.2V or VSS 80 A RP = VSS 0.2V 5 A Supply Current (Program Byte-wide) Byte program in progress 50 mA Supply Current (Program Word-wide) Word program in progress 60 mA Erase in progress 30 mA E = VIH, Erase suspended 10 mA Supply Current (Standby) TTL ICC1 (3) Supply Current (Standby) CMOS ICC2 (3) ICC3 ICC4 ICC5 (2) Supply Current (Power Down) Supply Current (Erase) Supply Current (Erase Suspend) IPP Program Current (Read or Standby) VPP > VCC 200 A IPP1 Program Leakage Current (Read or Standby) VPP VCC 15 A IPP2 Program Current (Power Down) RP = VSS 0.2V 5 A IPP3 Program Current (Program Byte-wide) Byte program in progress 30 mA IPP3 Program Current (Program Word-wide) Word program in progress 40 mA IPP4 Program Current (Erase) Erase in progress 30 mA IPP5 Program Current (Erase Suspend) Erase suspended 200 A VIL Input Low Voltage -0.5 0.6 V VIH Input High Voltage 2 VCC + 0.5 V VOL Output Low Voltage IOL = 2mA 0.4 V VOH Output High Voltage IOH = -2mA VPPL Program Voltage (Normal operation) 0 4.1 V VPPH Program Voltage (Program or Erase operations) 5% range 11.4 12.6 V VID A9 Voltage (Electronic Signature) 11.4 13 V IID A9 Current (Electronic Signature) 500 A VLKO 2.4 A9 = VID Supply Voltage (Erase and Program lockout) 2 V V Notes: 1. Automatic Power Saving reduces ICC to 2mA typical in static operation. 2. Current increases to ICC + ICC5 during a read operation. 3. CMOS levels VCC 0.2V and VSS 0.2V. TTL levels VIH and VIL. 7/27 M28V430, M28V440 Table 11. Read AC Characteristics (TA = 0 to 70C; VCC = 3.3V 0.3V; VPP = 12V5%) M28V430/440 Symbol Alt Parameter -120 -150 -180 SRAM Interface EPROM Interface EPROM Interface Test Condition Min Max Min Max Min Unit Max tAVAV tRC Address Valid to Next Address Valid E = VIL, G = VIL tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL 120 150 180 ns tPHQV tPWH Power Down High to Output Valid E = VIL, G = VIL 700 700 700 ns (1) tLZ Chip Enable Low to Output Transition G = VIL tELQV (2) tCE Chip Enable Low to Output Valid G = VIL tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL (2) tOE Output Enable Low to Output Valid E = VIL Chip Enable High to Output Transition G = VIL tDF Chip Enable High to Output Hi-Z G = VIL tOH Output Enable High to Output Transition E = VIL tDF Output Enable High to Output Hi-Z E = VIL tOH Address Transition to Output Transition E = VIL, G = VIL tELQX tGLQV tEHQX tEHQZ (1) tGHQX tGHQZ (1) tAXQX 120 150 0 0 120 0 0 0 0 0 45 0 0 ns ns 55 0 ns ns 60 50 ns ns 70 55 Notes: 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. 8/27 0 0 0 ns 180 65 50 ns 0 150 60 0 180 ns ns POWER-UP AND STANDBY Note: Write Enable (W) = High RP DQ0-DQ15 G E A-1, A A0-A17 ADDRESS VALID AND CHIP ENABLE tPHQV tGLQX tGLQV OUTPUTS ENABLED tELQV tELQX tAVQV VALID tAVAV DATA VALID VALID STANDBY tGHQZ tGHQX tEHQZ tEHQX AI01281B tAXQX M28V430, M28V440 Figure 5. Read Mode AC Waveforms 9/27 M28V430, M28V440 Table 12. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70C; VCC = 3.3V 0.3V; VPP = 12V5%) M28V430/440 Symbol Alt -120 -150 -180 SRAM Interface EPROM Interface EPROM Interface Parameter Min tAVAV tWC Write Cycle Time tPHWL tPS tELWL Max Min Max Min Unit Max 120 150 180 ns Power Down High to Write Enable Low 1 1 1 s tCS Chip Enable Low to Write Enable Low 0 0 0 ns tWLWH tWP Write Enable Low to Write Enable High 100 100 100 ns tDVWH tDS Input Valid to Write Enable High 100 100 100 ns tWHDX tDH Write Enable High to Input Transition 0 0 0 ns tWHEH tCH Write Enable High to Chip Enable High 10 10 10 ns tWHWL tWPH Write Enable High to Write Enable Low 50 50 50 ns tAVWH tAS Address Valid to Write Enable High 95 95 95 ns tVPHWH tVPS VPP High to Write Enable High 200 200 200 ns tWHAX tAH Write Enable High to Address Transition 10 10 10 ns tWHQV1 (1, 2) Write Enable High to Output Valid (Word/Byte Program) 6 6 6 s tWHQV2 (1, 2) Write Enable High to Output Valid (Boot Block Erase) 0.3 0.3 0.3 sec (1) Write Enable High to Output Valid (Parameter Block Erase) 0.3 0.3 0.3 sec tWHQV4 (1) Write Enable High to Output Valid (Main Block Erase) 0.6 0.6 0.6 sec 0 0 0 ns tWHQV3 tQVVPL Output Valid to VPP Low Notes: 1. Time is measured to Status Register Read giving bit b7 = '1'. 2. For Program or Erase of the Boot Block RP must be at VHH. 10/27 tPHWL tWLWH COMMAND POWER-UP AND SET-UP COMMAND tDVWH tELWL tWHDX tWHWL tWHEH CMD or DATA CONFIRM COMMAND OR DATA INPUT tVPHWH tAWVH VALID tWHQV1,2,3,4 tWHAX tQVVPL STATUS REGISTER STATUS REGISTER READ Note: Word-wide Address Data shown, for Byte-wide DQ15 becomes A-1. Command Input and Status Register Read output is on DQ0-DQ7 only. VPP RP DQ0-DQ15 W G E A0-A17 tAVAV PROGRAM OR ERASE AI01857 M28V430, M28V440 Figure 6. Program & Erase AC Waveforms, W Controlled 11/27 M28V430, M28V440 Table 13. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70C; VCC = 3.3V 0.3V; VPP = 12V5%) M28V430/440 Symbol Alt -120 -150 -180 SRAM Interface EPROM Interface EPROM Interface Parameter Min tAVAV tWC Write Cycle Time tPHEL tPS tWLEL Max Min Max Min Unit Max 120 150 180 ns Power Down High to Chip Enable Low 1 1 1 s tCS Write Enable Low to Chip Enable Low 0 0 0 ns tELEH tWP Chip Enable Low to Chip Enable High 100 100 100 ns tDVEH tDS Input Valid to Chip Enable High 100 100 100 ns tEHDX tDH Chip Enable High to Input Transition 0 0 0 ns tEHWH tCH Chip Enable High to Write Enable High 10 10 10 ns tEHEL tWPH Chip Enable High to Chip Enable Low 50 50 50 ns tAVEH tAS Address Valid to Chip Enable High 95 95 95 ns tVPHEH tVPS VPP High to Chip Enable High 200 200 200 ns tEHAX tAH Chip Enable High to Address Transition 10 10 10 ns (1, 2) Chip Enable High to Output Valid (Word/Byte Program) 6 6 6 s tEHQV2 (1, 2) Chip Enable High to Output Valid (Boot Block Erase) 0.3 0.3 0.3 sec Chip Enable High to Output Valid (Parameter Block Erase) 0.3 0.3 0.3 sec Chip Enable High to Output Valid (Main Block Erase) 0.6 0.6 0.6 sec 0 0 0 ns tEHQV1 tEHQV3 (1) tEHQV4 (1) tQVVPL Output Valid to VPP Low Note: 1. Time is measured to Status Register Read giving bit b7 = '1'. 2. For Program or Erase of the Boot Block RP must be at VHH. 12/27 VPP RP DQ0-DQ15 E G W A0-A17 tPHEL tELEH COMMAND POWER-UP AND SET-UP COMMAND tDVEH tWLEL tEHDX tEHEL tEHWH CMD or DATA CONFIRM COMMAND OR DATA INPUT tVPHEH tAVEH VALID tAVAV tEHQV1,2,3,4 tEHAX PROGRAM OR ERASE STATUS REGISTER READ tQVVPL STATUS REGISTER AI01858 M28V430, M28V440 Figure 7. Program & Erase AC Waveforms, E Controlled 13/27 M28V430, M28V440 Table 14. Word/Byte Program, Erase Times (TA = 0 to 70C; VCC = 3.3V 0.3V) Parameter M28V430/440 Test Conditions Min Unit Typ Max Main Block Program (Byte) VPP = 12V 5% 2 6 sec Main Block Program (Word) VPP = 12V 5% 1 3 sec Boot or Parameter Block Erase VPP = 12V 5% 1 7 sec Main Block Erase VPP = 12V 5% 1.5 10 sec DEVICE OPERATION (cont'd) E Chip Enable. The Chip Enable activates the memory control logic, input buffers, decoders and sense amplifiers. E High de-selects the memory and reduces the powerconsumption to the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at a low level. Both addresses and data inputs are then latched on the rising edge of E. RP Reset/Power Down. This is a two-level input which allows the memory to be put in deep power down. When RP is at VIH the device is in "active" mode. With RP Low the memory is in deep power down, and if RP is within VSS+0.2V the lowest supply current is absorbed. G Output Enable. The Output Enable gates the outputs through the data buffers during a read operation. W Write Enable. It controls writing to the Command Register and Input Address and Data latches. Both Addresses and Data Inputs are latched on the rising edge of W. BYTE Byte/Word Organization Select. This input selects either byte-wide or word-wide organization of the memory. When BYTE is Low the memory is organized x8 or byte-wide and data input/output uses DQ0-DQ7 while A-1 acts as the additional, LSB, of the memory address that multiplexes the upper or lower byte. In the byte-wide organization 14/27 DQ8-DQ14 are high impedance. When BYTE is High the memory is organized x16 and data input/output uses DQ0-DQ15 with the memory addressed by A0-A17. VPP Program Supply Voltage. This supply voltage is used for memory Programming and Erase. VPP 10% tolerance option is provided for application requiring maximum 100 write and erase cycles. VCC Supply Voltage. It is the main circuit supply. VSS Ground. It is the reference for all voltage measurements. Memory Blocks The memory blocks of the M28V430 and M28V440 are shown in Figure 8. The difference between the two products is simply an inversion of the block map to position the Boot Block at the top or bottom of the memory. The selection of the Boot Block at the top or bottom of the memory depends on the microprocessor needs. Each block of the memory can be erased separately, but only by one block at a time. The erase operation is managed by the P/E.C. but can be suspended in order to read from another block and then resumed. Programming and erasure of the memory is disabled when the program supply is at VPPL. For successful programming and erasure the program supply must be at VPPH. M28V430, M28V440 Figure 8. Memory Map, Word-wide Addresses M28V430 TOP BOOT BLOCK A0-A17 Word Wide 3FFFFh M28V440 BOTTOM BOOT BLOCK A0-A17 Word Wide 3FFFFh 8K BOOT BLOCK 3E000h 3DFFFh 64K MAIN BLOCK 30000h 2FFFFh 4K PARAMETER BLOCK 3D000h 3CFFFh 64K MAIN BLOCK 20000h 1FFFFh 4K PARAMETER BLOCK 3C000h 3BFFFh 64K MAIN BLOCK 10000h 0FFFFh 48K MAIN BLOCK 30000h 2FFFFh 48K MAIN BLOCK 04000h 03FFFh 64K MAIN BLOCK 20000h 1FFFFh 4K PARAMETER BLOCK 03000h 02FFFh 64K MAIN BLOCK 10000h 0FFFFh 4K PARAMETER BLOCK 02000h 01FFFh 64K MAIN BLOCK 00000h 8K BOOT BLOCK 00000h AI01859 Operations Operations are defined as specific bus cycles and signals which allow memory Read, Command Write, Output Disable, Standby, Power Down, and Electronic Signature Read. They are shown in Table 3. Read. Read operations are used to output the contents of the Memory Array, the Status Register or the Electronic Signature. Both Chip Enable E and Output Enable G must be low in order to read the output of the memory. The Chip Enable input also provides power control and should be used for device selection. Output Enable should be used to gate data onto the output independentof the device selection. A read operation will output either a byte or a word depending on the BYTE signal level. When BYTE is Low the output byte is on DQ0-DQ7, DQ8-DQ14 are Hi-Z and A-1 is an additional address input. When BYTE is High the output word is on DQ0-DQ15. The data read depends on the previous command written to the memory (see instructions RD, RSR and RSIG). Write. Write operations are used to give Instruction Commands to the memory or to latch input data to be programmed. A write operation is initiated when Chip Enable E is Low and Write Enable W is Low with Output EnableG High. Commands, Input Data and Addresses are latched on the rising edge of W or E. As for the Read operation, when BYTE is Low a byte is input, DQ8-DQ14 are 'don't care' and A-1 is an additional address. When BYTE is High a word is input. Output Disable. The data outputs are high impedance when the Output Enable G is High with Write Enable W High. Standby. The memory is in standby when the Chip Enable E is High. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs. Power Down. The memory is in Power Down when RP is low. The power consumption is reduced to the Power Down level, and Outputs are in high impedance, independant of the Chip Enable E, Output Enable G or Write Enable W inputs. 15/27 M28V430, M28V440 Electronic Signature. Two codes identifying the manufacturer and the device can be read from the memories, the manufacturer code for SGSTHOMSON is 20h, and the device codes are 0F3h for the M28V430 (Top Boot Block) and 0FBh for the M28V440 (Bottom Boot Block). These codes allow programming equipment or applications to automatically match their interfaceto the characteristics of the particular manufacturer's product. The Electronic Signature is output by a Read Array operation when the voltage applied to A9 is at VID, the manufacturer code is output when the Address input A0 is Low and the device code when this input is High. Other Address inputs are ignored. The codes are output on DQ0-DQ7. When the BYTE signal is High the outputs DQ8-DQ15 output 00h, when Low these outputs are high impedance and Address input A-1 is ignored. The Electronic Signature can also be read, without raising A9 to VID, after giving the memory the instruction RSIG (see below). Instructions and Commands The memories include a Command Interface (C.I.) which latches commands written to the memory. Instructions are made up from one or more commands to perform memory Read, Read Status Register, Read Electronic Signature, Erase, Program, Clear Status Register, Erase Suspend and Erase Resume. These instructions require from 1 to 3 operations, the first of which is always a write operation and is followed by either a further write operation to confirm the first command or a read operation(s) to output data. A Status Register indicates the P/E.C. status Ready or Busy, the suspend/in-progressstatus of erase operations, the failure/success of erase and program operations and the low/correct value of the Program Supply voltage VPP. The P/E.C. automatically sets bits b3 to b7 and clears bit b6 & b7. It cannot clear bits b3 to b5. The register can be read by the Read Status Register (RSR) instruction and cleared by the Clear Status Register (CLRS) instruction. The meaning of the bits b3 to b7 is shown in Table 7. Bits b0 to b2 are reserved for future use (and should be masked out during status checks). Read (RD) instruction. The Read instruction consists of one write operation giving the command 0FFh. Subsequent read operations will read the addressedmemory array content and output a byte or word depending on the level of the BYTE input. Read Status Register (RSR) instruction. The Read Status Register instruction may be given at any time, including while the Program/Erase Controller is active. It consists of one write operation 16/27 giving the command 70h.SubsequentRead operations output the contents of the Status Register. The contents of the status register are latched on the falling edge of E or G signals, and can be read until E or G returns to its initial high level. Either E or G must be toggled to VIH to update the latch. Additionally, any read attempt during program or erase operation will automatically output the contents of the Status Register. Read Electronic Signature (RSIG) instruction. This instruction uses 3 operations.It consists of one write operation giving the command 90h followed by two read operations to output the manufacturer and device codes. The manufacturer code, 20h, is output when the address line A0 is Low, and the device code, 0F3h for the M28V430 or 0FBh for the M28V440, when A0 is High. Erase (EE) instruction. This instruction uses two write operations. The first command written is the Erase Set-up command 20h. The second command is the Erase Confirm command 0D0h. During the input of the second command an address of the block to be erased is given and this is latched into the memory. If the second command given is not the Erase Confirm command then the status register bits b4 and b5 are set and the instruction aborts. Read operations output the status register after erasure has started. During the execution of the erase by the P/E.C., the memory accepts only the RSR (Read Status Register) and ES (Erase Suspend) instructions. Status Register bit b7 returns '0' while the erasure is in progress and '1' when it has completed. After completion the Status Register bit b5 returns '1' if there has been an Erase Failure because erasure has not been verified even after the maximum number of erase cycles have been executed. Status Register bit b3 returns '1' if VPP does not remain at VPPH level when the erasure is attempted and/or proceding. VPP must be at VPPH when erasing, erase should not be attempted when VPP < V PPH as the results will be uncertain. If VPP falls below VPPH or RP goes Low the erase aborts and must be repeated, after having cleared the Status Register (CLRS). The Boot Block can only be erased when RP is also at VHH. Program (PG) instruction. This instruction uses two write operations. The first command written is the Program Set-up command 40h (or 10h). A second write operation latches the Address and the Data to be written and starts the P/E.C. Read operations output the status register after the programming has started. Memory programming is only made by writing '0' in place of '1' in a byte or word. M28V430, M28V440 DEVICE OPERATION (cont'd) During the execution of the programming by the P/E.C., the memory accepts only the RSR (Read Status Register) instruction. The Status Register bit b7 returns '0' while the programming is in progress and '1' when it has completed. After completion the Status register bit b4 returns '1' if there has been a Program Failure. Status Register bit b3 returns a '1' if VPP does not remain at VPPH when programming is attempted and/or during programming. VPP must be at VPPH when programming, programming should not be attempted when VPP < VPPH as the results will be uncertain. Programming aborts if VPP drops below VPPH or RP goes Low. If aborted the data may be incorrect. Then after having cleared the Status Register (CLRS), the memory must be erased and re-programmed. The Boot Block can only be programmed when RP is at VIH. Clear Status Register (CLRS) instruction. The Clear Status Register uses a single write operation which clears bits b3, b4 and b5, if latched to '1' by the P/E.C., to '0'. Its use is necessary before any new operation when an error has been detected. Erase Suspend (ES) instruction. The Erase operation may be suspended by this instruction which consists of writing the command 0B0h. The Status Register bit b6 indicates whether the erase has actually been suspended, b6 = '1', or whether the P/E.C. cycle was the last and the erase is completed, b6 = '0'. During the suspension the memory will respond only to Read (RD), Read Status Register (RSR) or Erase Resume (ER) instructions. Read operations initially output the status register while erase is suspended but, following a Read instruction, data from other blocks of the memory can be read. VPP must be maintained at VPPH while erase is suspended. If VPP does not remain at VPPH or the RP signal goes Low while erase is suspended then erase is aborted while bits b5 and b3 of the status register are set. Erase operation must be repeated after having cleared the status register, to be certain to erase the block. Erase Resume (ER) instruction. If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 0D0h. The status register bit b6 is cleared when erasure resumes. Read operations output the status register after the erase is resumed. The suggested flow charts for programs that use the programming, erasure and erase suspend/re- sume features of the memories are shown in Figure 9 to Figure 11. Programming. The memory can be programmed byte-by-byte(or word-by-word in x16 organization). The Program Supply voltage VPP must be applied before program instructions are given, and if the programming is in the Boot Block, RP must also be raised to VIH to unlock the Boot Block. The Program Supplyvoltage may be applied continuously during programming. The program sequence is started by writing a Program Set-up command (40h) to the Command Interface,this is followed by writing the address and data byte or word to the memory. The Program/Erase Controllerautomaticallystarts and performs the programming after the second write operation, providing that the V PP voltage (and RP voltage if programming the Boot Block) are correct. During the programming the memory status is checked by reading the status register bit b7 which shows the status of the P/E.C. Bit b7 = '1' indicates that programming is completed. A full status check can be made after each byte/word or after a sequence of data has been programmed. The status check is made on bit b3 for any possible V PP error and on bit b4 for any possible programming error. Erase. The memory can be erased by blocks. The Program Supply voltage VPP must be applied before the Erase instruction is given, and if the Erase is of the Boot Block RP must also be raised to VIH to unlock the Boot Block. The Erase sequence is started by writing an Erase Set-up command (20h) to the Command Interface, this is followed by an address in the block to be erased and the Erase Confirm command (0D0h). The Program/Erase Controller automatically starts and performs the block erase, providing the VPP voltage (and the RP voltage if the erase is of the Boot Block) iscorrect. During the erase the memory status is checked by reading the status register bit b7 which shows the status of the P/E.C. Bit b7 = '1' indicates that erase is completed. A full status check can be made after the block erase by checking bit b3 for any possible VPP error, bits b5 and b6 for any command sequence errors (erase suspended) and bit b5 alone for an erase error. Reset. Note that after any program or erase instruction has completed with an error indication or after any VPP transitions down to VPPL the Command Interface must be reset by a Clear Status Register Instruction before data can be accessed. 17/27 M28V430, M28V440 Automatic Power Saving The M28V430 and M28V440 memories place themselves in a lower power state when not being accessed. Following a Read operation, after a delay equal to the memory access time, the Supply Current is reduced from a typical read current of 20mA (CMOS inputs, word-wide organization) to less than 2mA. Power Down The memories provide a power down control input RP. When this signal is taken to below VSS + 0.2V all internal circuits are switched off and the supply current drops to typically 0.2A and the program current to typically 0.1A. If RP is taken low during a memory read operation then the memory is deselected and the outputs become high impedance. If RP is taken low during a program or erase sequence then it is aborted and the memory content is no longer valid. Recovery from deep power down requires 700ns to a memory read operation, or 580ns to a command write. On return from power down the status register is cleared to 00h. 18/27 Power Up The Supply voltage VCC and the Program Supply voltage VPP can be applied in any order. The memory Command Interface is reset on power up to Read Memory Array, but a negative transition of Chip Enable E or a change of the addresses is required to ensure valid data outputs. Care must be taken to avoid writes to the memory when VCC is above VLKO and VPP powers up first. Writes can be inhibited by driving either E or W to VIH. The memory is disabled until RP is up to VIH. Supply Rails Normal precautions must be taken for supply voltage decoupling, each device in a system should have the VCC and VPP rails decoupled with a 0.1F capacitor close to the VCC and VSS pins. The PCB trace widths should be sufficient to carry the VPP program and erase currents required. M28V430, M28V440 Figure 9. Program Flow-chart and Pseudo Code Start Write 40h Command PG instruction: - write 40h command - write Address & Data (memory enters read status state after the PG instruction) Write Address & Data Read Status Register b7 = 1 do: - read status register (E or G must be toggled) NO while b7 = 1 YES b3 = 0 NO VPP Low Error (1, 2) If b3 = 0, VPP low error: - error handler NO Program Error (1, 2) If b4 = 0, Program error: - error handler YES b4 = 0 YES End AI01278 Notes: 1. Status check of b3 (VPP Low) and b4 (Program Error) can be made after each byte/word programming or after a sequence. 2. If a VPP Low or Program Erase is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations. 19/27 M28V430, M28V440 Figure 10. Erase Flow-chart and Pseudo Code Start Write 20h Command Write Block Address & 0D0h Command Suspend Loop NO Read Status Register Suspend b7 = 1 YES NO EE instruction: - write 20h command - write Block Address (A12-A17) & command 0D0h (memory enters read status state after the EE instruction) do: - read status register (E or G must be toggled) if EE instruction given execute suspend erase loop while b7 = 1 YES b3 = 0 NO VPP Low Error (1) NO Command Sequence Error NO Erase Error (1) If b3 = 0, VPP low error: - error handler YES b4, b5 = 1 If b4, b5 = 0, Command Sequence error: - error handler YES b5 = 0 If b5 = 0, Erase error: - error handler YES End AI01279 Note: 1. If VPP Low or Erase Error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations. 20/27 M28V430, M28V440 Figure 11. Erase Suspend & Resume Flow-chart and Pseudo Code Start Write 0B0h Command ES instruction: - write 0B0h command (memory enters read register state after the ES instruction) do: - read status register (E or G must be toggled) Read Status Register b7 = 1 NO while b7 = 1 YES b6 = 1 NO Erase Complete If b6 = 0, Erase completed (at this point the memory wich accept only the RD or ER instruction) YES Write 0FFh Command RD instruction: - write 0FFh command - one o more data reads from another block Read data from another block Write 0D0h Command Erase Continues ER instruction: - write 0D0h command to resume erasure AI01280 21/27 M28V430, M28V440 Figure 12. Command Interface and Program Erase Controller Flow-diagram (a) WAIT FOR COMMAND WRITE (1) 90h NO YES BYTE IDENTIFIER 70h NO YES READ STATUS READ ARRAY NO 50h YES CLEAR STATUS 40h or 10h NO YES PROGRAM SET-UP 20h NO YES READ STATUS PROGRAM ERASE SET-UP NO 0FFh YES YES READY (2) OD0h NO B READ STATUS NO YES A ERASE COMMAND ERROR AI01286C Notes: 1. If no command is written, the Command Interface remains in its previous valid state. Upon power-up, on exit from power-down or if VCC falls below VLKO, the Command Interface defaults to Read Array mode. 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7. 22/27 M28V430, M28V440 Figure 13. Command Interface and Program Erase Controller Flow-diagram (b) A B (READ STATUS) ERASE YES READY (2) NO 0B0h NO YES READ STATUS ERASE SUSPEND YES READY (2) NO ERASE NO SUSPENDED ? READ STATUS YES YES 70h NO READ STATUS NO READ ARRAY 0D0h YES READ STATUS (ERASE RESUME) AI01287B Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7. 23/27 M28V430, M28V440 ORDERING INFORMATION SCHEME Example: Array Org. Operating Voltage V 3.3V M28V430 -120 N 1 TR Option Temp. Range 3 Top Boot 1 0 to 70 C 4 Bottom Boot 3 -40 to 125 C 6 -40 to 85 C TR Tape & Reel Packing Package Speed -120 120ns M SO44 -150 150ns N TSOP48 12 x 20mm -180 180ns For a list of available options (Op. Voltage, Array Organisation, Speed, etc...) refer to the current Memory Shortform catalogue. For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you. 24/27 M28V430, M28V440 TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm mm Symb Typ inches Min Max A Typ Min 1.20 Max 0.047 A1 0.05 0.15 0.002 0.006 A2 0.95 1.05 0.037 0.041 B 0.17 0.27 0.007 0.011 C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728 E 11.90 12.10 0.469 0.476 - - - - L 0.50 0.70 0.020 0.028 0 5 0 5 N 48 e 0.50 0.020 48 CP 0.10 0.004 TSOP56 A2 1 N e E B N/2 D1 A CP D DIE C TSOP-a A1 L Drawing is not to scale 25/27 M28V430, M28V440 SO44 - 44 lead Plastic Small Outline, 525 mils body width mm Symb Typ inches Min Max A 2.42 A1 A2 Min Max 2.62 0.095 0.103 0.22 0.23 0.009 0.010 2.25 2.35 0.089 0.093 B Typ 0.50 0.020 C 0.10 0.25 0.004 0.010 D 28.10 28.30 1.106 1.114 E 13.20 13.40 0.520 0.528 0.626 0.634 e 1.27 0.050 H 15.90 16.10 L 0.80 0.031 3 3 N 44 CP 44 0.10 0.004 SO44 A2 A C B CP e D N E H 1 A1 SO-b Drawing is not to scale 26/27 L M28V430, M28V440 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 27/27