Order Now Product Folder Support & Community Tools & Software Technical Documents Reference Design LP3982 SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 LP3982 Micropower, Ultra-Low-Dropout, Low-Noise, 300-mA CMOS Regulator 1 Features 3 Description * * The LP3982 low-dropout (LDO) CMOS linear regulator is available in 1.8-V, 2.5-V, 2.82-V, 3-V, 3.3-V, and adjustable versions. They deliver 300 mA of output current. Packaged in an 8-pin VSSOP, the LP3982 is pin- and package-compatible with Maxim's MAX8860. The LM3982 is also available in the small footprint WSON package. 1 * * * * * * * * * * * 2.5-V to 6-V Input Range MAX8860 Pin, Package, and Specification Compatible 300-mA Output Current 120-mV Typical Dropout at 300 mA 90-A Typical Quiescent Current 1-nA Typical Shutdown Mode 60-dB Typical PSRR 120-s Typical Turnon Time Stable With Small Ceramic Output Capacitors 37-VRMS Output Voltage Noise (10 Hz to 100 kHz) Overtemperature/Overcurrent Protection 2% Output Voltage Tolerance Create a Custom Design Using the LP3982 With the WEBENCH(R) Power Designer The LP3982 suits battery-powered applications because of its shutdown mode (1 nA typical), low quiescent current (90 A typical), and LDO voltage (120 mV typical). The low dropout voltage allows for more utilization of a battery's available energy by operating closer to its end-of-life voltage. The LP3982 device's PMOS output transistor consumes relatively no drive current compared to PNP LDO regulators. This PMOS regulator is stable with small ceramic capacitive loads (2.2 F typical). These devices also include regulation fault detection, a bandgap voltage reference, constant current limiting, and thermal-overload protection. 2 Applications * * * * Device Information(1) Wireless Handsets DSP Core Power Battery Powered Electronics Portable Information Appliances PART NUMBER LP3982 PACKAGE BODY SIZE (NOM) WSON (8) 2.50 mm x 3.00 mm VSSOP (8) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Application Circuit (Fixed VOUT Version) VO VIN OUT IN 2.2 PF 100 kY SHDN 2.2 PF CERAMIC FAULT GND CC 33 nF 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP3982 SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 7.2 7.3 7.4 Overview ................................................................... 9 Functional Block Diagram ......................................... 9 Feature Description................................................... 9 Device Functional Modes........................................ 10 8 Application and Implementation ........................ 11 8.1 Application Information............................................ 11 8.2 Typical Application ................................................. 11 9 Power Supply Recommendations...................... 16 10 Layout................................................................... 17 10.1 Layout Guidelines ................................................. 17 10.2 Layout Example .................................................... 17 10.3 WSON Mounting ................................................... 17 11 Device and Documentation Support ................. 18 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ....................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 18 19 12 Mechanical, Packaging, and Orderable Information ........................................................... 19 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (October 2015) to Revision F * Page Added links for Webench and changed top navigator icon for TI Designs ........................................................................... 1 Changes from Revision D (April 2013) to Revision E Page * Added Device Information and Pin Configuration and Functions sections, ESD Ratings table, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections; update Thermal Information... 1 * Deleted lead temperature from Abs Max table (in POA); revised wording for footnote 4 ..................................................... 4 Changes from Revision C (April 2013) to Revision D * 2 Page Changed layout of National Data Sheet to TI format ............................................................................................................. 9 Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 LP3982 www.ti.com SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 5 Pin Configuration and Functions DGK Package 8-Pin VSSOP Top View OUT IN GND OUT 1 8 2 7 3 6 4 5 FAULT SHDN CC SET * The SET pin is internally disconnected for the fixed versions. NGM Package 8-Pin WSON With Thermal Pad Top View OUT 1 IN 2 8 FAULT 7 SHDN DAP GND 3 6 CC OUT 4 5 SET* The SET pin is internally disconnected for the fixed versions. Pin Functions PIN NAME NO. I/O DESCRIPTION Connect a capacitor between CC pin and ground to reduce the output noise. The optimum value for CC is 33 nF. CC 6 -- FAULT 8 Output FAULT pin goes low during out of regulation conditions like current limit and thermal shutdown, or when it approaches dropout. Requires a pullup resistor because it is an activelow, open-drain output. GND 3 Ground Ground IN 2 Input OUT 1, 4 Output SET 5 Input In the adjustable version a resistor divider connected to this pin sets the output voltage. The SET pin is internally disconnected for the fixed versions. SHDN 7 Input The SHDN pin allows the part to be turned to an ON or OFF state by pulling SHDN pin high or low. DAP -- WSON Only - The DAP (Die Attached Pad) is an exposed pad that does not have an internal connection; it functions as a thermal relief when soldered to a copper plane. It is recommend that the DAP be connected to GND. See WSON Mounting section for more information. This is the input supply voltage to the regulator. Regulated output voltage Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 3 LP3982 SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) VIN, VOUT, VSHDN, VSET, VCC, VFAULT MIN MAX UNIT -0.3 6.5 V 20 mA 150 C 160 C Fault sink current See (4) Power dissipation Junction temperature, TJ Storage temperature, Tstg (1) (2) (3) (4) -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pin. If Military/Aerospace-specified devices are required, contact Texas Instruments Sales Office/Distributors for availability and specifications. In applications where high power dissipation and/or poor thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(MAX)) is dependant on the maximum operating junction temperature (TJ(MAX-OP)), the maximum power dissipation (PD(MAX)), and the junction-to-ambient thermal resistance in the application (RJA). This relationship is given by: TA(MAX) = TJ(MAX-OP) - (PD(MAX) x RJA).The value of the RJA for the WSON package is specifically dependent on the PCB trace area, trace material, and the number of layers and thermal vias. For improved thermal resistance and power dissipation for the WSON package, refer to TI Application Note AN-1187 Leadless Leadframe Package (LLP) (SNOA401). 6.2 ESD Ratings V(ESD) (1) Electrostatic discharge VALUE UNIT Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 V Machine model 200 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions (1) (2) MIN NOM MAX UNIT Operating temperature -40 85 C Supply voltage 2.5 6 V (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pin. 6.4 Thermal Information LP3982 THERMAL METRIC (1) DGK (VSSOP) NGM (WSON) (2) UNIT 8 PINS 8 PINS RJA (3) Junction-to-ambient thermal resistance, High-K 175.2 52.6 C/W RJC(top) Junction-to-case (top) thermal resistance 66.0 66.2 C/W RJB Junction-to-board thermal resistance 95.6 16.7 C/W JT Junction-to-top characterization parameter 9.7 1.9 C/W JB Junction-to-board characterization parameter 94.2 16.7 C/W RJC(bot) Junction-to-case (bottom) thermal resistance n/a 11.1 C/W (1) (2) (3) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. The PCB for the WSON/NGN package RJA includes thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5. Thermal resistance value RJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 LP3982 www.ti.com SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 6.5 Electrical Characteristics Unless otherwise specified, all limits are specified for VIN = VOUT + 0.5 V (1), VSHDN = VIN, CIN = COUT = 2.2 F, CCC = 33 nF, TJ = 25C. PARAMETER VIN Input voltage VOUT Output voltage tolerance Output adjust range VOUT Maximum output current IOUT MIN (2) TEST CONDITIONS 2.5 6 100 A IOUT 300 mA VIN = VOUT + 0.5 V (1) SET = OUT for the ADJ Versions -2 2 For operating temperature extremes: -40C to 85C -3 3 ADJ version only; for operating temperature extremes: -40C to 85C 1.25 6 Average DC current rating; For operating temperature extremes: -40C and 85C 300 VDO Dropout voltage VOUT en Line regulation V mA 330 90 IOUT = 300 mA (1) (4) % of VOUT mA IOUT = 0 mA; for operating temperature extremes: -40C to 85C Shutdown supply current V 770 For operating temperature extremes: -40C to 85C Supply current UNIT (NOM) IOUT = 0 mA IQ MAX (2) For operating temperature extremes: -40C to 85C Output current limit ILIMIT TYP (3) 270 A 1 A 225 VO = 0 V, SHDN = GND 0.001 IOUT = 1 mA 0.4 IOUT = 200 mA 80 IOUT = 200 mA; for operating temperature extremes: -40C to 85C IOUT = 300 mA 120 IOUT = 1 mA, (VOUT + 0.5 V) VI 6 V (1) 0.01 IOUT = 1 mA, (VOUT + 0.5 V) VI 6 V (1); for operating temperature extremes: -40C to 85C mV 220 %/V -0.1 0.1 Load regulation 100 A IOUT 300 mA 0.002 %/mA Output voltage noise IOUT = 10 mA, 10 Hz f 100 kHz 37 VRMS Output voltage noise density 10 Hz f 100 kHz, COUT = 10 F 190 nV/Hz (1) VSHDN SHDN input threshold VIH, (VOUT + 0.5 V) VIN 6 V ; for operating temperature extremes: -40C to 85C 2 V VIL, (VOUT + 0.5 V) VIN 6 V (1); for operating temperature extremes:-40C to 85C 0.4 ISHDN SHDN input bias current SHDN = GND or IN 0.1 100 nA ISET SET input leakage SET = 1.3 V, ADJ version only (5) 0.1 2.5 nA (1) (2) (3) (4) (5) Condition does not apply to input voltages below 2.5 V because this is the minimum input operating voltage. All limits are verified by testing or statistical analysis. Typical values represent the most likely parametric norm. Dropout voltage is measured by reducing VIN until VOUT drops 100 mV from its nominal value at VIN - VOUT = 0.5 V. Dropout voltage does not apply to the 1.8-V version. The SET pin is not externally connected for the fixed versions. Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 5 LP3982 SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 www.ti.com Electrical Characteristics (continued) Unless otherwise specified, all limits are specified for VIN = VOUT + 0.5 V(1), VSHDN = VIN, CIN = COUT = 2.2 F, CCC = 33 nF, TJ = 25C. PARAMETER TEST CONDITIONS VO 2.5 V, IOUT = 200 mA (6) FAULT detection voltage VFAULT IFAULT TSD TON (6) 6 TYP (3) FAULT output low voltage ISINK = 2 mA; for operating temperature extremes: -40C to 85C FAULT off-leakage current FAULT = 3.6 V, SHDN = 0 V Thermal shutdown temperature MAX (2) 280 0.25 0.1 100 10 COUT = 10 F, VOUT at 90% of final value mV 0.115 160 Thermal shutdown hysteresis UNIT 120 VOUT 2.5 V, IOUT = 200 mA (6); for operating temperature extremes: -40C to 85C ISINK = 2 mA Start-up time MIN (2) 120 V nA C s The FAULT detection voltage is specified for the input-to-output voltage differential at which the FAULT pin goes active low. Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 LP3982 www.ti.com SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 6.6 Typical Characteristics Unless otherwise specified, VIN = VO + 0.5 V, CIN = COUT = 2.2 F, CCC = 33 nF, TJ = 25C, VSHDN = VIN. 160 140 VO = 2.77V 140 25C DROPOUT VOLTAGE (mV) DROPOUT VOLTAGE (mV) 120 100 VO = 2.5V 80 VO = 3.3V 60 40 120 85C 100 80 -40C 60 40 20 20 0 0 0 50 100 200 150 250 300 0 100 150 200 250 300 LOAD CURRENT (mA) LOAD CURRENT (mA) Figure 1. Dropout Voltage vs Load Current (for Different Output Voltages) Figure 2. Dropout Voltage vs Load Current (for Different Output Temperatures) 240 180 IL = 0mA 220 160 200 140 SUPPLY CURRENT (PA) FAULT DETECT THRESHOLD (mV) 50 FAULT = HIGH 120 100 80 FAULT = LOW 60 40 180 TA = 85C 160 TA = 25C 140 120 100 80 60 TA = -40C 40 20 20 0 0 0 50 100 150 200 250 300 0 1 2 3 4 5 6 LOAD CURRENT (mA) INPUT VOLTAGE (V) Figure 3. FAULT Detect Threshold vs Load Current Figure 4. Supply Current vs Input Voltage 0 250 85C 25C -20 PSRR (dB) SUPPLY CURRENT (PA) -10 200 150 -40C 100 -30 -40 -50 50 -60 0 0 50 250 200 150 100 LOAD CURRENT (mA) 300 Figure 5. Supply Current vs Load Current -70 10 10k 100 1k FREQUENCY (Hz) 100k Figure 6. Power Supply Rejection Ratio vs Frequency Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 7 LP3982 SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 www.ti.com Typical Characteristics (continued) Unless otherwise specified, VIN = VO + 0.5 V, CIN = COUT = 2.2 F, CCC = 33 nF, TJ = 25C, VSHDN = VIN. NOISE (PV/ Hz) 10 100 PV/DIV 1 COUT = 10PF 0.1 COUT = 2.2PF 0.01 100 10 k FREQUENCY (Hz) 100k 1k 1 ms/DIV Figure 8. Output Noise (10 Hz to 100 kHz) Figure 7. Output Noise Spectral Density 2 2 V/DIV 1.6 VSHDN 1.4 0V 1.2 1 0.8 VOUT 0.6 1 V/DIV OUTPUT IMPEDANCE (:) 1.8 0.4 0.2 0 10 100 1k 10k 0V 100k 500 Ps/DIV FREQUENCY (Hz) Figure 10. Shutdown Response VIN 1 V/DIV VIN VO 2 V/DIV FAULT 1 V/DIV 2 V/DIV Figure 9. Output Impedance vs Frequency FAULT VIN VO VIN VO VO 5 ms/DIV 5 mS/DIV Figure 12. Power-Down Response Figure 11. Power-Up Response 8 Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 LP3982 www.ti.com SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 7 Detailed Description 7.1 Overview The LP3982 is package, pin, and performance compatible with Maxim's MAX8860, excluding reverse battery protection and dual-mode function (fixed and adjustable combined). A 1.25-V bandgap reference, an error amplifier, and a PMOS pass transistor perform voltage regulation while being supported by shutdown, fault, and the usual temperature and current protection circuitry (see Functional Block Diagram). The regulator topology is the classic type with negative feedback from the output to one of the inputs of the error amplifier. Feedback resistors R1 and R2 are either internal or external to the device, depending on whether it is the fixed-voltage version or the adjustable version. The negative feedback and high open loop gain of the error amplifier cause the two inputs of the error amplifier to be virtually equal in voltage. If the output voltage changes due to load changes, the error amplifier provides the appropriate drive to the pass transistor to maintain the error amplifier's inputs as virtually equal. In short, the error amplifier keeps the output voltage constant in order to keep its inputs equal. 7.2 Functional Block Diagram IN OUT FAST START-UP CIRCUIT CURRENT LIMIT FAULT FAULT COMPARATORS R1 + SET - CC ERROR AMP OFF SHDN R2 THERMAL PROTECTION 1.25-V BANDGAP GND 7.3 Feature Description 7.3.1 No-Load Stability The LP3982 remains stable during no-load conditions, a necessary feature for CMOS RAM keep-alive applications. 7.3.2 Fast Start-Up The LP3982 provides fast start-up time for better system efficiency. The start-up speed is maintained when using the optional noise bypass capacitor. An internal 500-A current source charges the capacitor until it reaches about 90% of its final value. Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 9 LP3982 SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 www.ti.com 7.4 Device Functional Modes 7.4.1 Shutdown The LP3982 goes into sleep mode when the SHDN pin is in a logic low condition. During this condition, the pass transistor, error amplifier, and bandgap are turned off, reducing the supply current to 1 nA typical. The maximum voltage for a logic low at the SHDN pin is 0.4 V. A minimum voltage of 2 V at the SHDN pin turns the LP3982 back on. The SHDN pin may be directly tied to VIN to keep the part on. The SHDN pin may exceed VIN but not the maximum of 6.5 V. Figure 13 shows an application that uses the SHDN pin. It detects when the battery is too low and disconnects the load by turning off the regulator. A micropower comparator (LMC7215) and reference (LM385) are combined with resistors to set the minimum battery voltage. At the minimum battery voltage, the comparator output goes low and tuns off the LP3982 and corresponding load. Hysteresis is added to the minimum battery threshold to prevent the battery's recovery voltage from falsely indicating an above minimum condition. When the load is disconnected from the battery, it automatically increases in terminal voltage because of the reduced IR drop across its internal resistance. The minimum battery detector of Figure 13 has a low detection threshold (VLT) of 3.6 V that corresponds to the minimum battery voltage. The upper threshold (VUT) is set for 4.6 V to exceed the recovery voltage of the battery. VB OUT IN R1 768k R4 180k + 4 Cells NiMH R2 2.2PF 2.74M 100k 2.2PF CERAMIC VB LMC7215 FAULT SHDN GND R3 301k LP3982 VREF LM385A-1.2V Figure 13. Minimum Battery Detector that Disconnects the Load Via the SHDN Pin of the LP3982 Resistor value for VUT and VLT are determined as follows: GT = 1 + 1 + R2 R1 1 R3 VUT = R1 (VREF) GT VLT = R1 // R2 (VREF) GT (1) (The application of Figure 13 used a GT of 5 mho.) R1 = VUT1 VREF (GT) 1 R2 = VREF (GT) VLT (2) - 1 R1 (3) 1 R3 = GT - 1 1 + R2 R1 (4) The above procedure assumes a rail-to-rail output comparator. Essentially, R2 is in parallel with R1 prior to reaching the lower threshold, then R2 becomes parallel with R3 for the upper threshold. Note that the application requires rail-to-rail input as well. The resistor values shown in Figure 13 are the closest practical to calculated values. 10 Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 LP3982 www.ti.com SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LP3982 can provide 300-mA output current with 2.5-V to 6-V input. It is stable with a 2.2-F ceramic output capacitor. An optional external bypass capacitor reduces the output noise without slowing down the load transient response. Typical output noise is 37 VRMS at frequencies from 10 Hz to 100 kHz. Typical PSSR is 60 dB at 1 kHz. 8.2 Typical Application VO VIN OUT IN 2.2 PF 100 kY SHDN 2.2 PF CERAMIC FAULT GND CC 33 nF Figure 14. LP3982 Typical Application (Fixed VOUT Version) 8.2.1 Design Requirements For typical ultra low-dropout CMOS-regulator applications, use the parameters listed in Table 1. Table 1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Minimum input voltage VOUT + 0.5 V Nominal output voltage 3.3 V Maximum output current 300 mA RMS noise, 10 Hz to 100 kHz 37 VRMS PSRR at 1 kHz 60 dB 8.2.2 Detailed Design Procedure 8.2.2.1 Custom Design With WEBENCH(R) Tools Click here to create a custom design using the LP3982 device with the WEBENCH(R) Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 11 LP3982 SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 www.ti.com In most cases, these actions are available: * Run electrical simulations to see important waveforms and circuit performance * Run thermal simulations to understand board thermal performance * Export customized schematic and layout into popular CAD formats * Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 8.2.2.2 Output Voltage Setting (ADJ Version Only) The output voltage is set according to the amount of negative feedback (the pass transistor inverts the feedback signal.) Figure 15 simplifies the topology of the LP3982. This type of regulator can be represented as an op amp configured as non-inverting amplifier and a fixed DC Voltage (VREF) for its input signal. The special characteristic of this op amp is its extra-large output transistor that only sources current. In terms of its non-inverting configuration, the output voltage equals VREF times the closed loop gain: VO = VREF R1 R2 +1 (5) Use Equation 6 for adjusting the output to a particular voltage: e V u R1 = R2 e O - 1u e1.25V u (6) Choose R2 = 100 k to optimize accuracy, power supply rejection, noise, and power consumption. VIN VREF + VOUT - R1 R2 Figure 15. Regulator Topology Simplified Similarity in the output capabilities exists between op amps and linear regulators. Just as rail-to-rail output op amps allow their output voltage to approach the supply voltage, low dropout regulators (LDOs) allow their output voltage to operate close to the input voltage. Both achieve this by the configuration of their output transistors. Standard operational amplifiers and regulator outputs are at the source (or emitter) of the output transistor. Railto-rail op amp and LDO regulator outputs are at the drain (or collector) of the output transistor. This replaces the threshold (or diode drop) limitations on the output with the less restrictive source-to-drain (or VSAT) limitations. There is a trade-off; the output impedance become significantly higher, thus providing a critically lower pole when combined with the capacitive load. That is why rail-to-rail operational amplifiers are usually poor at driving capacitive loads and a series output resistor recommended when doing so. LDOs require the same series resistance except that the internal resistance of the output capacitor will usually suffice. Refer to the Output Capacitance section for more information. 8.2.2.3 Output Capacitance The LP3982 is specifically designed to employ ceramic output capacitors as low as 2.2 F. Ceramic capacitors below 10 F offer significant cost and space savings, along with high frequency noise filtering. Higher values and other types and of capacitor may be used, but their equivalent series resistance (ESR) must be maintained below 0.5 . 12 Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 LP3982 www.ti.com SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 Ceramic capacitor of the value required by the LP3982 are available in the following dielectric types: Z5U, Y5V, X5R, and X7R. The Z5U and Y5V types exhibit a 50% or more drop in capacitance value as their temperature increases from 25C, an important consideration. The X5R generally maintain their capacitance value within 20%. The X7R type are desirable for their tighter tolerance of 10% over temperature. Ceramic capacitors pose a challenge because of their relatively low ESR. Like most other LDOs, the LP3982 relies on a zero in the frequency response to compensate against excessive phase shift in the feedback loop of the regulator. If the phase shift reaches 360 (that is, becomes positive), the regulator oscillates. This compensation usually resides in the zero generated by the combination of the output capacitor with its ESR. The zero is intended to cancel the effects of the pole generated by the load capacitance (CL) combined with the parallel combination of the load resistance (RL) and the output resistance (RO) of the regulator. The challenge posed by low ESR capacitors is that the zero it generates can be too high in frequency for the pole it is intended to compensate. The LP3982 overcomes this challenge by internally generating a strategically placed zero. - LOOP GAIN RO VREF ESR + CL RL Figure 16. Simplified Model of Regulator Loop Gain Components Figure 16 shows a basic model for the linear regulator that helps describe what happens to the output signal as it is processed through its feedback loop; that is, describe its loop gain (LG). The LG includes two main transfer functions: the error amplifier and the load. The error amplifier provides voltage gain and a dominant pole, while the load provides a zero and a pole. The LG of the model in Figure 16 is described by Equation 7: LG (j) = AO 1+j POLE 1 + j (ESR x CL) * 1 + j ((ESR + RO // RL) CL) (7) The first term of Equation 7 expresses the voltage gain (numerator) and a single pole role-off (denominator) of the error amplifier. The second term expresses the zero (numerator) and pole (denominator) of the load in combination with the RO of the regulator. Figure 17 shows a Bode plot that represents a case where the zero contributed by the load is too high to cancel the effect of the pole contributed by the load and RO. The solid line represents the loop gain while the dashed line represents the corresponding phase shift. Notice that the phase shift at unity gain is a total 360, the criteria for oscillation. Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 13 LP3982 SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 www.ti.com ERROR AMP POLE: ZPOLE 0 dB LOOP PHASE SHIFT LOOP GAIN -180 LOAD POLE 1/(2S (ESR + RO // RL)CL) -360 LOAD ZERO 1/(2S (ESR x CL) Figure 17. Loop Gain Bode Plot Illustrating Inadequately High Zero for Stability Compensation The LP3982 generates an internal zero that makes up for the inadequately high zero of the low ESR ceramic output capacitor. This internally generated zero is strategically placed to provide positive phase shift near unity gain, thus providing a stable phase margin. 8.2.2.4 Input Capacitor The LP3982 requires a minimum input capacitance of about 1 F. The value may be increased indefinitely. The type is not critical to stability. However, instability may occur with bench set-ups where long supply leads are used, particularly at near dropout and high current conditions. This is attributed to the lead inductance coupling to the output through the gate oxide of the pass transistor; thus, forming a pseudo LCR network within the loop gain. A 10-F tantalum input capacitor remedies this non-situ condition; its larger ESR acts to dampen the pseudo-LCR network. This may only be necessary for some bench setups. A 1-F ceramic input capacitor are fine for most end-use applications. If a tantalum input capacitor is intended for the final application, it is important to consider their tendency to fail in short circuit mode, thus potentially damaging the part. 8.2.2.5 Noise Bypass Capacitor The noise bypass capacitor (CC) significantly reduces output noise of the LP3982. It connects between pin 6 and ground. The optimum value for CC is 33 nF. Pin 6 directly connects to the high impedance output of the bandgap. The DC leakage of the CC capacitor must be considered; loading down the reference reduces the output voltage. NPO and COG ceramic capacitors typically offer very low leakage. Polypropylene and polycarbonate film carbonate capacitor offer even lower leakage currents. CC does not affect the transient response; however, it does affect turnon time. The smaller the CC value, the faster the turnon time. 8.2.2.6 Fault Detection The LP3982 provides a FAULT pin that goes low during out of regulation conditions like current limit and thermal shutdown, or when it approaches dropout. The latter monitors the input-to-output voltage differential and compares it against a threshold that is slightly above the dropout voltage. This threshold also tracks the dropout voltage as it varies with load current. Refer to Figure 3 in the Typical Characteristics section. The FAULT pin requires a pullup resistor because it is an open-drain output. This resistor must be large in value to reduce energy drain. A 100-k pullup resistor works well for most applications. Figure 18 shows the LP3982 with delay added to the FAULT pin for the reset pin of a microprocessor. The output of the comparator stays low for a preset amount of time after the regulator comes out of a fault condition. 14 Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 LP3982 www.ti.com SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 VIN VO = 3V OUT IN LP3982 SHDN + FAULT CDELAY GND CC 0.1PF LMC7225 RESET - MICROPROCESSOR RP 100k Figure 18. Power-On Delayed Reset Application The delay time for the application of Figure 18 is set by Equation 8: CDELAY = -t RPln 1 - VREF VO (8) The application is set for a reset delay time of 8.8 ms. The comparator must have high impedance inputs so as to not load down the VREF at the CC pin of the LP3982. 8.2.2.7 Power Dissipation Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and load conditions and can be calculated with Equation 9: PD(MAX) = (VIN(MAX) - VOUT) x IOUT(MAX) (9) Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available voltage drop option that would still be greater than the dropout voltage (VDO). However, keep in mind that higher voltage drops result in better dynamic (that is, PSRR and transient) performance. On the WSON (NGM) package, the primary conduction path for heat is through the exposed power pad to the PCB. To ensure the device does not overheat, connect the exposed pad, through thermal vias, to an internal ground plane with an appropriate amount of copper PCB area. On the VSSOP (DGK) package, the primary conduction path for heat is through the pins to the PCB. The maximum allowable junction temperature (TJ(MAX)) determines maximum power dissipation allowed (PD(MAX)) for the device package. Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to Equation 10 or Equation 11: (TJ(MAX) = TA(MAX) + (RJA xPD(MAX)) PD(MAX) = (TJ(MAX) - TA(MAX)) / RJA (10) (11) RJA is highly dependent on the heat-spreading capability of the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RJA recorded in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper-spreading area, and is to be used only as a relative measure of package thermal performance. For a well-designed thermal layout, RJA is the sum of the package junction-to-case (bottom) thermal resistance (RJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink. Improvements and absolute measurements of the RJA can be estimated by utilizing the thermal shutdown circuitry that is internal to the device. The thermal shutdown turns off the pass transistor of the device when its junction temperature reaches 160C (typical). The pass transistor does not turn on again until the junction temperature drops about 10C (hysteresis). Using the thermal shutdown circuit to estimate, RJA can be as follows: with a low input-to-output voltage differential, set the load current to 300 mA. Increase the input voltage until the thermal shutdown begins to cycle on and off. Then slowly decrease VIN (100-mV increments) until the device stays on. Record the resulting voltage differential (VD) and use it in Equation 12: Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 15 LP3982 SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 RTJA www.ti.com (160 - TA) (0.300 x VD) (12) 8.2.2.8 Estimating Junction Temperature The EIA/JEDEC standard recommends the use of psi () thermal characteristics to estimate the junction temperatures of surface mount devices on a typical PCB board application. These characteristics are not true thermal resistance values, but rather package specific thermal characteristics that offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of copper-spreading area. The key thermal characteristics (JT and JB) are given in Thermal Information and are used in accordance with Equation 13 or Equation 14. TJ(MAX) = TTOP + (JT x PD(MAX)) where * * PD(MAX) is explained in Equation 9. TTOP is the temperature measured at the center-top of the device package. (13) TJ(MAX) = TBOARD + (JB x PD(MAX)) where * * PD(MAX) is explained in Equation 9. TBOARD is the PCB surface temperature measured 1-mm from the device package and centered on the package edge. (14) For more information about the thermal characteristics JT and JB, see the TI Application Report Semiconductor and IC Package Thermal Metrics (SPRA953), available for download at www.ti.com. For more information about measuring TTOP and TBOARD, see the TI Application Report Using New Thermal Metrics (SBVA025), available for download at www.ti.com. For more information about the EIA/JEDEC JESD51 PCB used for validating RJA, see the TI Application Report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017), available for download at www.ti.com. IL = 300mA 4.3V 20 mV/DIV VIN (V) 8.2.3 Application Curves IL = 300mA VOUT 100 mA/DIV VO (10 mV/DIV) 3.3V 500 Ps/DIV IOUT 500 Ps/DIV Figure 19. Line Transient Response Figure 20. Load Transient 9 Power Supply Recommendations The LP3982 is designed to operate from an input voltage supply range between 2.5 V and 6 V. The input voltage range provides adequate headroom in order for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help to improve the output noise performance. 16 Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 LP3982 www.ti.com SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 10 Layout 10.1 Layout Guidelines Best performance is achieved by placing CIN, COUT, and CCC on the same side of the PCB as the LP3982 device, and as close as is practical to the package. The ground connections for CIN and COUT must be back to the LP3982 device GND pin using as wide and as short of a copper trace as is practical. Avoid connections using long trace lengths and narrow trace widths. These add parasitic inductances and resistance that results in inferior performance especially during transient conditions. 10.2 Layout Example VIA connect to ground layer VIA connect to VOUT COUT RPULLUP OUT IN 1 2 8 FAULT 7 SHDN DAP (GND) CIN CCC GND 3 6 CC OUT 4 5 SET R1 R2 Figure 21. WSON Package Adjustable Version (Not to Scale) 10.3 WSON Mounting The WSON package requires specific mounting techniques which are detailed in TI Application Report Leadless Leadframe Package (LLP) (SNOA401). Referring to the section PCB Design Recommendations, the pad style which must be used with the WSON package is the NSMD (non-solder mask defined) type. Additionally, it is recommended the PCB terminal pads be 0.2 mm longer than the package pads to create a solder fillet to improve reliability and inspection. The thermal dissipation of the WSON package is directly related to the printed circuit board construction and the amount of additional copper area connected to the DAP. The DAP (exposed pad) on the bottom of the WSON package is connected to the die substrate with a conductive die attach adhesive. The DAP has no direct electrical (wire) connection to any of the pins. There is a parasitic PN junction between the die substrate and the device ground. As such, it is strongly recommend that the DAP be connected directly to the ground at device pin 3 (GND). Alternately, but not recommended, the DAP may be left floating (no electrical connection). The DAP must not be connected to any potential other than ground. Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 17 LP3982 SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For additional information, see the following: * AN-1187 Leadless Leadframe Package (LLP) * Semiconductor and IC Package Thermal Metrics * Using New Thermal Metrics * Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs 11.1.2 Development Support 11.1.2.1 Custom Design With WEBENCH(R) Tools Click here to create a custom design using the LP3982 device with the WEBENCH(R) Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: * Run electrical simulations to see important waveforms and circuit performance * Run thermal simulations to understand board thermal performance * Export customized schematic and layout into popular CAD formats * Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 18 Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 LP3982 www.ti.com SNVS185F - FEBRUARY 2002 - REVISED APRIL 2017 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2002-2017, Texas Instruments Incorporated Product Folder Links: LP3982 19 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LP3982ILD-1.8/NOPB ACTIVE WSON NGM 8 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LNB LP3982ILD-2.5/NOPB ACTIVE WSON NGM 8 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LPB LP3982ILD-3.0/NOPB ACTIVE WSON NGM 8 1000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-3-260C-168 HR -40 to 85 LTB LP3982ILD-3.3/NOPB ACTIVE WSON NGM 8 1000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-3-260C-168 HR -40 to 85 LUB LP3982ILD-ADJ/NOPB ACTIVE WSON NGM 8 1000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-3-260C-168 HR -40 to 85 LVB LP3982ILDX-1.8/NOPB ACTIVE WSON NGM 8 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LNB LP3982ILDX-3.3/NOPB ACTIVE WSON NGM 8 4500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-3-260C-168 HR -40 to 85 LUB LP3982ILDX-ADJ/NOPB ACTIVE WSON NGM 8 4500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-3-260C-168 HR -40 to 85 LVB LP3982IMM-1.8 NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 LENB LP3982IMM-1.8/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LENB LP3982IMM-2.5/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LEPB LP3982IMM-3.0 NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 LETB LP3982IMM-3.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LETB LP3982IMM-3.3 NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 LEUB LP3982IMM-3.3/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LEUB LP3982IMM-ADJ ACTIVE VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 LEVB LP3982IMM-ADJ/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LEVB LP3982IMMX-1.8/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LENB Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Oct-2017 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LP3982IMMX-2.5/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LEPB LP3982IMMX-2.82/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LESB LP3982IMMX-ADJ/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LEVB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2017 Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP3982ILD-1.8/NOPB WSON NGM 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982ILD-2.5/NOPB WSON NGM 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982ILD-3.0/NOPB WSON NGM 8 1000 180.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982ILD-3.3/NOPB WSON NGM 8 1000 180.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982ILD-ADJ/NOPB WSON NGM 8 1000 180.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982ILDX-1.8/NOPB WSON NGM 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982ILDX-3.3/NOPB WSON NGM 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982ILDX-ADJ/NOPB WSON NGM 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982IMM-1.8 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMM-1.8/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMM-2.5/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMM-3.0 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMM-3.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMM-3.3 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMM-3.3/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMM-ADJ VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMM-ADJ/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMMX-1.8/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 Device LP3982IMMX-2.5/NOPB Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMMX-2.82/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMMX-ADJ/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3982ILD-1.8/NOPB WSON NGM 8 1000 210.0 185.0 35.0 LP3982ILD-2.5/NOPB WSON NGM 8 1000 210.0 185.0 35.0 LP3982ILD-3.0/NOPB WSON NGM 8 1000 195.0 200.0 45.0 LP3982ILD-3.3/NOPB WSON NGM 8 1000 195.0 200.0 45.0 LP3982ILD-ADJ/NOPB WSON NGM 8 1000 195.0 200.0 45.0 LP3982ILDX-1.8/NOPB WSON NGM 8 4500 367.0 367.0 35.0 LP3982ILDX-3.3/NOPB WSON NGM 8 4500 370.0 355.0 55.0 LP3982ILDX-ADJ/NOPB WSON NGM 8 4500 370.0 355.0 55.0 LP3982IMM-1.8 VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMM-1.8/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMM-2.5/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMM-3.0 VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMM-3.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMM-3.3 VSSOP DGK 8 1000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3982IMM-3.3/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMM-ADJ VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMM-ADJ/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMMX-1.8/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LP3982IMMX-2.5/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LP3982IMMX-2.82/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LP3982IMMX-ADJ/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 3 MECHANICAL DATA NGM0008C LDA08C (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). 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