MCP3204-CI/SLG - Microchip Technology

MCP3204/3208

Features

• 12-bit resolution

• ± 1 LSB max DNL

• ± 1 LSB max INL (MCP3204/3208-B)

• ± 2 LSB max INL (MCP3204/3208-C)

• 4 (MCP3204) or 8 (MCP3208) input channels

• Analog inputs programmable as single-ended or

pseudo-differential pairs

• On-chip sample and hold

• SPI serial interface (modes 0,0 and 1,1)

• Single supply operation: 2.7V - 5.5V

• 100 ksps max . sampling rate at VDD = 5V

• 50 ksps max. sampling rate at VDD = 2.7V

• Low power CMOS technology:

- 500 nA typical standby current, 2 µA max.

- 400 µA max. active current at 5V

• Industrial temp range: -40°C to +85°C

• Available in PDIP, SOIC and TSSOP packages

Applications

• Sensor Interface

• Process Control

• Data Acquisition

• Bat ter y Operated Systems

Package Types

Description

The Microchip Technology Inc. MCP3204/3208

devices are successive approximation 12-bit Analog-

to-Digital (A/D) Converters with on-board sample and

hold circuitry. The MCP3204 is programmable to pro-

vide two pseudo-differential input pairs or four single-

ended inputs. The MCP3208 is programmable to pro-

vide four pseudo-differential input pairs or eight single-

ended inputs. Differential Nonlinearity (DNL) is speci-

fied at ±1 LSB, while Integral Nonlinearity (INL) is

offered in ±1 LSB (MCP3204/3208-B) and ±2 LSB

(MCP3204/3208-C) versions.

Communication with the devices is accomplished using

a simple serial interface compatible with the SPI proto-

col. T he devi ce s ar e capab l e of con ve r si on ra t e s of up

to 100 ksps. The MCP32 04/320 8 devi ce s operat e over

a broad voltage range (2.7V - 5.5V). Low current

design permits operation with typical standby and

active currents of only 500 nA and 320 µA, respec-

tively. The MCP3204 is offered in 14-pin PDIP, 150 mil

SOIC and TSSOP packages. The MCP3208 is offered

in 16-pin PDI P and SOIC packages.

Functional Block Diagram

VDD

CLK

DOUT

MCP3204

VREF

DIN

CH0

CH1

CH2

CH3

CS/SHDN

DGND

AGND

VDD

CLK

DOUT

MCP3208

VREF

DIN

CS/SHDN

DGND

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

AGND

PDIP, SOIC, TSSOP

PDIP, SOIC

Comparator

Sample

and

Hold

12-Bit SAR

DAC

Control Logic

CS/SHDN

VREF

VSS

VDD

CLK DOUT

Shift

CH0

Channel

Mux

Input

CH1

CH7*

* Note: Channels 5-7 available on MCP3208 Only

DIN

2.7V 4-Channel/8-Channel 12-Bit A/D Converters

with SPI™ Serial Interface

MCP3204/3208

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings*

VDD...................................................................................7.0V

All inputs and outputs w.r.t. VSS ............... -0.6V to VDD +0.6V

Storage temperature ................. .. .... .. .. .. .. ......-65°C to +150°C

Ambient temp. with power applied................- 65°C to +125°C

Soldering temperature of leads (10 seconds).............+300°C

ESD protec tio n o n all pin s.............................................> 4 kV

*Notice: Stresses above those listed under "Maximum

Ratings" may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operation listings of this specification is not implied. Exposure

to maximum rating conditions for extended periods may af fect

device reliability.

PIN FUNCTION TABLE

Name Function

VDD +2.7V to 5.5V Power Supply

DGND Digital Ground

AGND Analog Ground

CH0-CH7 Analog Inputs

CLK Serial Clock

DIN Serial Data In

DOUT Serial Data Out

CS/SHDN Chip Select/Shutdown Input

VREF Referenc e Volt age Input

ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, VREF = 5V,

TAMB = -40°C to +85°C,fSAMPLE = 100 ksps and fCLK = 20*fSAMPLE

Parameters Sym Min Typ Max Units Conditions

Conversion Rate

Conve r si on Time tCONV — — 12 clock

cycles

Analog Input Sample Time tSAMPLE 1.5 clock

cycles

Throughput Rate fSAMPLE —

——

—100

50 ksps

ksps VDD = VREF = 5V

VDD = VREF = 2.7V

DC Accuracy

Resolution 12 bits

Integral Nonl ine ari ty INL —

—±0.75

±1.0 ±1

±2 LSB MCP3204/3208-B

MCP3204/3208-C

Differential Nonlinearity DNL — ±0.5 ±1 LSB No missing codes

over-temperature

Offset Error — ±1.25 ±3 LSB

Gain Error — ±1.25 ±5 LSB

Dynamic Performance

Total Harmonic Distortion — -82 — dB VIN = 0.1V to 4.9V@1 kHz

Signal to N oise and D istortion

(SINAD) —72 —dBV

IN = 0.1V to 4.9V@1 kHz

Spurious Free Dynamic

Range —86 —dBV

IN = 0.1V to 4.9V@1 kHz

Reference Input

Volta ge R ang e 0.25 — VDD VNote 2

Current Drain —

—100

0.001 150

3.0 µA

µA CS = VDD = 5V

Note 1: This parameter is established by characterization and not 100% tested.

2: See graphs that relate linearity performance to VREF level s.

3: Because the sample cap will eventually lose charge, effec tive clock rates below 10 kHz can affect linearit y

perfor ma nce , p a rtic ul arly at el ev ate d tem pe ratures. See Section 6.2, “Maintain ing Mi nim um C lo ck S pee d”,

for more information.

© 2007 Microchip Technology Inc. DS21298D-page 3
MCP3204/3208
Analog Inputs
Input Voltage Range for CH0-
CH7 in Single-En de d Mode   VSS —V
REF V
Input Voltage  Range for IN+  in 
pseudo-differential Mode IN- — VREF+IN-
Input Voltage Ra nge  for  IN - i n 
pseudo-differential Mode VSS-100 — VSS+100 mV
Leakage Current — 0.001 ±1 µA
Switch Resistance — 1000 — ΩSee Figure 4-1
Sample C apacitor — 20 — pF See Figure 4-1
Digital Input/Output
Data Coding Format Straight Binary
High Level Input Voltage VIH 0.7 VDD ——V
Low Level Input Voltage VIL ——0.3 V
DD V
High Level Output Voltage VOH 4.1 — — V IOH = -1 mA, VDD = 4.5V
Low Level Output Voltage VOL ——0.4 VI
OL = 1 mA , VDD = 4.5V
Input Leakage Current ILI -10 — 10 µA VIN = VSS or VDD
Output Lea ka ge Cu rren t ILO -10 — 10 µA VOUT = VSS or VDD
Pin Capacitance
(All Inputs/Outputs) CIN,COUT —— 10pFV
DD = 5.0V (Note 1)
TAMB = 25°C, f = 1 MHz
Timing Parameters
Clock Frequency fCLK —
——
—2.0
1.0 MHz
MHz VDD = 5V (Note 3)
VDD = 2.7V (Note 3)
Clock High Time tHI 250 — — ns
Clock Low Time tLO 250 — — ns
CS Fall To First Rising CLK 
Edge tSUCS 100 — — ns
Data Input Setup Time tSU —— 50ns
Data Input Hold Time tHD —— 50ns
CLK Fall To Output Data Valid tDO — — 200 ns See Figures 1-2 and  1-3
CLK Fall To Output Enable tEN — — 200 ns See Figures 1-2 and  1-3
CS Rise To Output Disable tDIS — — 100 ns See Figures 1-2 and  1-3
CS Disable Time tCSH 500 — — ns
DOUT Rise Time tR— — 100 ns See Figures 1-2 and  1-3 (Note 1)
DOUT Fall Time tF— — 100 ns See Figures 1-2 and  1-3 (Note 1)
Power Requireme nts
Operati ng Voltage VDD 2.7 — 5.5 V
Operati ng Curren t IDD —
—320
225 400
—µA VDD=VREF = 5V, DOUT unloaded
VDD=VREF = 2.7V, DOUT unloaded
Standby Current IDDS —0.52.0µACS = VDD = 5.0V 
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, 
TAMB = -40°C to +85°C,fSAMPLE = 100 ksps and fCLK = 20*fSAMPLE
Parameters Sym Min Typ Max Units Conditions
Note 1: This parameter is established by characterization and not 100% tested.
2: See graphs that relate linearity performance to VREF levels.
3: Because the sample cap will eventually lose charge, effec tive clock rates below 10 kHz can affect linearit y  
perfor ma nce , p a rtic ul arly  at el ev ate d tem pe ratures. See Section 6.2, “Maintain ing  Mi nim um  C lo ck S pee d”, 
for more information.

MCP3204/3208

FIGURE 1-1: Serial Interface Timing.

Temperature Ranges

Specified Temperature Range TA-40 — +85 °C

Operati ng Temperatu re

Range TA-40 — +85 °C

Storage Temperature Range TA-65 — +150 °C

Thermal Package Resistance

Thermal Resistance,

14L-PDIP θJA —70 —°C/W

Thermal Resistance,

14L-SOIC θJA — 108 — °C/W

Thermal Resistance,

14L-TSSOP θJA — 100 — °C/W

Thermal Resistance,

16L-PDIP θJA —70 —°C/W

Thermal Resistance,

16L-SOIC θJA —90 —°C/W

ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, VREF = 5V,

TAMB = -40°C to +85°C,fSAMPLE = 100 ksps and fCLK = 20*fSAMPLE

Parameters Sym Min Typ Max Units Conditions

Note 1: This parameter is established by characterization and not 100% tested.

2: See graphs that relate linearity performance to VREF level s.

3: Because the sample cap will eventually lose charge, effec tive clock rates below 10 kHz can affect linearit y

perfor ma nce , p a rtic ul arly at el ev ate d tem pe ratures. See Section 6.2, “Maintain ing Mi nim um C lo ck S pee d”,

for more information.

CLK

DIN MSB IN

tSU tHD

tSUCS

tCSH

tHI tLO

DOUT

tEN tDO tRtF

LSB

MSB OUT

tDIS

Null Bit

MCP3204/3208

FIGURE 1-2: Load Circuit for tR, tF, tDO.

FIGURE 1-3: Load circuit for tDIS and tEN.

Test Point

1.4V

DOUT

3kΩ

CL = 100 pF

DOUT

Voltage Waveforms for tR, tF

CLK

DOUT

tDO

Voltage Waveforms for tDO

VOH

VOL

90%

10%

*Waveform 1 is for an output with internal

conditions such that the output is high,

unless disabled by the output control.

†Waveform 2 is for an output with internal

conditions such that the output is low ,

unless disabled by the output control.

Test Point

DOUT

3kΩ

100 pF

DIS

Waveform 2

DIS

Wa veform 1

CLK

DOUT

tEN

B11

Voltage Waveforms for tEN

tEN Waveform

VDD

VDD/2

VSS

Voltage Waveforms for tDIS

DOUT

CS VIH

TDIS

Waveform 1*

Waveform 2†

MCP3204/3208

2.0 TYPICAL PERFORMANCE CHARACTERISTICS

Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE,TA = 25°C.

FIGURE 2-1: Integral Nonlinearity (INL)

vs. Sample Rate.

FIGURE 2-2: Integral Nonlinearity (INL)

vs. VREF.

FIGURE 2-3: Integral Nonlinearity (INL)

vs. Code (Representative Part).

FIGURE 2-4: Integral Nonlinearity (INL)

vs. Sample Rate (VDD = 2.7V).

FIGURE 2-5: Integral Nonlinearity (INL)

vs. VREF (V DD = 2.7V).

FIGURE 2-6: Integral Nonlinearity (INL)

vs. Code (Representative Part, VDD = 2 .7V ).

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 25 50 75 100 125 150

Sample Rate (ksps)

INL (LSB)

Positive INL

Negative INL

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

01234

VREF (V)

INL (LSB)

Positive INL

Negative INL

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 512 1024 1536 2048 2560 3072 3584 409

Digital Code

INL (LSB)

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

0 1020304050607080

Sample Rate (ksps)

INL (LSB)

Positive INL

Negative INL

VDD = V REF = 2.7 V

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

VREF (V)

INL (LSB)

Positive INL

Negative INL

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 512 1024 1536 2048 2560 3072 3584 409

Digital Code

INL (LSB)

VDD = VREF = 2.7 V

FSAMPLE = 50 ksps

MCP3204/3208

Note: Unless otherwise indicated, VDD = VREF = 5 V, VSS = 0 V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE,TA = 25°C.

FIGURE 2-7: Integral Nonlinearity (INL)

vs. Temperature.

FIGURE 2-8: Differential Nonlinearity

(DNL) vs. Sample Rate.

FIGURE 2-9: Differential Nonlinearity

(DNL) vs. VREF.

FIGURE 2-10: Integral Nonlinearity (INL)

vs. Temperature (VDD = 2.7V).

FIGURE 2-11: Differential Nonlinearity

(DNL) vs. Sample Rate (VDD = 2.7V).

FIGURE 2-12: Differential Nonlinearity

(DNL) vs. VREF (VDD = 2.7V).

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-50-250 25507510

Temperature (°C)

INL (LSB)

Positive INL

Negat i ve INL

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 25 50 75 100 125 150

Sample Rate (ksps)

DNL (LSB)

Positive DNL

Negative DNL

-3.0

-2.0

-1.0

0.0

1.0

2.0

3.0

012345

VREF (V)

DNL (LSB)

Positive DNL

Negative DNL

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-50-250 25507510

Temperature (°C)

INL (LSB)

Positive INL

VDD = VREF = 2.7 V

FSAMPLE = 50 ksps

Negative INL

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

0 1020304050607080

Sample Rate (ksps)

DNL (LSB)

Positive DNL

Negative DNL

VDD = VREF = 2.7 V

-3.0

-2.0

-1.0

0.0

1.0

2.0

3.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

VREF (V)

DNL (LSB)

VDD = V REF = 2.7 V

FSAMPLE = 50 ksps

Positive DNL

Negative DNL

MCP3204/3208

Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE,TA = 25°C.

FIGURE 2-13: Differential Nonlinearity

(DNL) vs. Code (Representative Part).

FIGURE 2-14: Differential Nonlinearity

(DNL) vs. Temperature.

FIGURE 2-15: Gain Error vs . VREF.

FIGURE 2-16: Differential Nonlinearity

(DNL) vs. Code (Representative Part, VDD =

2.7V).

FIGURE 2-17: Differential Nonlinearity

(DNL) vs. Temperature (VDD = 2.7V ).

FIGURE 2-18: Offset Error vs. VREF.

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 512 1024 1536 2048 2560 3072 3584 409

Digital Code

DNL (LSB)

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-50 -25 0 25 50 75 100

Temperature (°C)

DNL (LSB)

Positive DNL

Negative DNL

-4

-3

-2

-1

012345

VREF (V)

Gain Error (LSB)

VDD = VREF = 2.7 V

FSAMPLE = 50 ksps

VDD = VREF = 5 V

FSAMPLE = 100 ksps

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 512 1024 1536 2048 2560 3072 3584 409

Digital Code

DNL (LSB)

VDD = VREF = 2.7 V

FSAMPLE = 50 ksps

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-50-250 25507510

Temperature (°C)

DNL (LSB)

Positive DNL

VDD = VREF = 2.7 V

FSAMPLE = 50 ksps

Negative DNL

012345

VREF (V)

Offset Error (LSB)

VDD = VREF = 2.7V

FSAMPLE = 50 ksps

VDD = VREF = 5V

FSAMPLE = 100 ksps

MCP3204/3208

Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE,TA = 25°C.

FIGURE 2-19: Gain Error vs. Temperature.

FIGURE 2-20: Signal to Noise (SNR) vs.

Input Frequency.

FIGURE 2-21: Total Harmonic Distortion

(THD) vs. Input Frequency.

FIGURE 2-22: Offset Error vs.

Temperature.

FIGURE 2-23: Signal to Noise and

Distortion (SINAD) vs. Input Frequency.

FIGURE 2-24: Signal to Noise and

Distortion (SINAD) vs. Input Signal Level.

-1.8

-1.6

-1.4

-1.2

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

-50-250 25507510

Temperatu re (°C)

Gain Error (LSB)

VDD = VREF = 5 V

FSAMPLE = 100 ksps

VDD = VREF = 2.7 V

FSAMPLE = 50 ksps

100

1 10 100

Input Frequency (kHz)

SNR (dB)

VDD = V REF = 2.7V

FSAMPLE = 50 ksps

VDD = VREF = 5 V

FSAMPLE = 100 ksps

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

1 10 100

Input Frequency (kHz)

THD (dB)

VDD = VREF = 5V

FSAMPLE = 100 ksps

VDD = VREF = 2.7V

FSAMPLE = 50 ksps

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-50 -25 0 25 50 75 10

Temperature (°C)

Offset Error (LSB)

VDD = VREF = 5 V

FSAMPLE = 100 ksps

VDD = VREF = 2.7 V

FSAMPLE = 50 ksps

100

1 10 100

Input Frequency (kHz)

SFDR (dB)

VDD = VREF = 5 V

FSAMPLE = 100 ksps

VDD = VREF = 2.7 V

FSAMPLE = 50 ksps

-40 -35 -30 -25 -20 -15 -10 -5 0

Input Signal Level (dB)

SINAD (dB)

VDD = V REF = 2.7 V

FSAMPLE = 50 ksps

VDD = VREF = 5 V

FSAMPLE = 100 ksps

MCP3204/3208

Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE,TA = 25°C.

FIGURE 2-25: Effective Number of Bits

(ENOB) vs. VREF.

FIGURE 2-26: Sp urio us F re e Dynam ic

Range (SFDR) vs. Input Frequency.

FIGURE 2-27: Frequency Spectrum of

10 kHz input (Representative Part).

FIGURE 2-28: Effective Number of Bits

(ENOB) vs. Input Frequency.

FIGURE 2-29: Power Supply Rejection

(PSR) vs. Ripple Frequency.

FIGURE 2-30: F reque nc y Spe ctrum of

1 kHz input (Representative Part, VDD = 2.7 V).

9.00

9.25

9.50

9.75

10.00

10.25

10.50

10.75

11.00

11.25

11.50

11.75

12.00

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

VREF (V )

ENOB (rms)

VDD = VREF = 2.7 V

FSAMPLE = 50 ksps

VDD = V REF = 5 V

FSAMPLE =100 ksps

100

1 10 100

Input Frequency (kHz)

SFDR (dB)

VDD = VREF = 5 V

FSAMPLE = 100 ksps

VDD = VREF = 2.7 V

FSAMPLE = 50 ksps

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0 10000 20000 30000 40000 50000

Frequency (Hz)

Amplitude (dB)

VDD = VREF = 5 V

FSAMPLE = 100 ksps

FINPUT = 9.985 kHz

4096 points

8.0

8.5

9.0

9.5

10.0

10.5

11.0

11.5

12.0

1 10 100

Input Frequ ency (kHz)

ENOB (rms)

VDD = VREF = 2.7 V

FSAMPLE = 50 ksps

VDD = VREF = 5 V

FSAMPLE = 100 ksps

-80

-70

-60

-50

-40

-30

-20

-10

1 10 100 1000 1000

Ripple Frequency (kHz)

Power Supply Rejection (dB)

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0 5000 10000 15000 20000 2500

Frequency (Hz)

Amplitude (dB)

VDD = VREF = 2.7 V

FSAMPLE = 50 ksps

FINPUT = 998.76 Hz

4096 points

MCP3204/3208

Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE,TA = 25°C.

FIGURE 2-31: IDD vs. VDD.

FIGURE 2-32: IDD vs. Clock Frequency.

FIGURE 2-33: IDD vs. Temperature.

FIGURE 2-34: IRE F vs. VDD.

FIGURE 2-35: IRE F vs. Clock Frequency.

FIGURE 2-36: IRE F vs. Temperature.

100

150

200

250

300

350

400

450

500

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.

VDD (V)

IDD (µA)

VREF = VDD

All points at FCLK = 2 MHz, except

at VREF = VDD = 2.5 V, FCLK = 1 MHz

100

150

200

250

300

350

400

10 100 1000 10000

Clock Frequ ency (kHz)

IDD (µA)

VDD = V REF = 5 V

VDD = VREF = 2.7 V

100

150

200

250

300

350

400

-50-250 25507510

Temperature (°C)

IDD (µA)

VDD = VREF = 5 V

FCLK = 2 MHz

VDD = VREF = 2.7 V

FCLK = 1 MHz

100

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.

VDD (V)

IREF (µA)

VREF = VDD

All po ints at FCLK = 2 MHz except

at VREF = VDD = 2.5 V, FCLK = 1 MHz

100

10 100 1000 1000

Clock Frequency (kHz)

IREF (µA)

VDD = V REF = 5 V

VDD = VREF = 2.7 V

100

-50-250 25507510

Temperatu re (°C)

IREF (µA)

VDD = VREF = 5 V

FCLK = 2 MHz

VDD = VREF = 2.7 V

FCLK = 1 MHz

MCP3204/3208

Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE,TA = 25°C.

FIGURE 2-37: IDDS vs. VDD.

FIGURE 2-38: IDDS vs. Temperature.

FIGURE 2-39: Analog Input Leakage

Current vs. Temperature.

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.

VDD (V)

IDDS (pA)

VREF = CS = VDD

0.01

0.10

1.00

10.00

100.00

-50 -25 0 25 50 75 100

Temperature (°C)

IDDS (nA)

VDD = VREF = CS = 5 V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-50 -25 0 25 50 75 10

Temperatu re (°C)

Analog Input Leakage (nA)

VDD = V REF = 5 V

FCLK = 2 MHz

MCP3204/3208

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

3.1 DGND

Digital ground connection to internal digital circuitry.

3.2 AGND

Analog ground connection to internal analog circuitry.

3.3 CH0 - CH7

Analog inputs for channels 0 - 7 for the multiplexed

input s. Each pair of channe ls can be programmed to be

used as two independent channels in single-ended

mode or as a single pseudo-differential input, where

one channel is IN+ and one channel is IN. See

Section 4.1, “Analog Inputs”, and Section 5.0, “Serial

Communications”, for information on programming the

channel configuration.

3.4 Serial Clock (CLK)

The SPI clock pin is used to initiate a conversion and

clock out each bit of the conversion as it takes place.

See Section 6.2, “Maintaining Minimum Cloc k Speed”,

for constraints on clock speed.

3.5 Serial Data Input (DIN)

The SPI port serial data input pin is used to load

channel configuration data into the device.

3.6 Serial Data Output (DOUT)

The SPI serial data output pin is used to shift out the

results of the A/D conversion. Data will always change

on the falling edge of each clock as the conversion

takes place.

3.7 Chip Select/Shutdown (CS/SHDN)

The CS/SHDN pin is used to initiate communication

with the device when pulled low and will end a conver-

sion and put the device in low power standby when

pulled high. The CS/SHDN pin must be pulled high

between conversions.

4.0 DEVICE OPERATION

The MCP3204/3208 A/D converters employ a conven-

tional SAR architecture. With this architecture, a sam-

ple is ac quired on an in ternal s ample /hold capacitor for

1.5 cloc k cycles starti ng on the fourth rising edg e of the

serial clock after the start bit has been received. Fol-

lowing this sample time, the device uses the collected

charge on the internal sample/hold capacitor to pro-

duce a serial 12-bit digital output code. Conversion

rates of 100 ksps are possible on the MCP3204/3208.

See Section 6.2, “Maintaining Minimum Clock Speed”,

for information on minimum clock rates. Communica-

tion with the dev ice is accomplished using a 4-wire SPI-

compatible interface.

4.1 Analog Inputs

The MCP3204/3208 devices offer the choice of using

the analog input channels configured as single-ended

inputs or pseudo-differential pairs. The MCP3204 can

be configured to provide two pseudo-differential input

pairs or four single-ended inputs, while the MCP3208

can be configured to provide four pseudo-differential

input pairs or eight single-ended inputs. Configuration

is done as p art of the s erial com mand before each con-

version begins. When used in the pseudo-differential

mode, e ac h c han nel p a ir (i.e ., CH 0 and CH 1, CH2 an d

CH3 etc.) is programmed to be the IN+ and IN- inputs

as part of the command string transmitted to the

device . The IN+ input ca n range from IN- to (VREF + IN-

). The IN- input is limited to ±100 mV from the VSS rail.

The IN- input can be used to cancel small signal com-

mon-mode noise which is present on both the IN+ and

IN- inputs.

When operating in the pseudo-differential mode, if the

voltage level of IN+ is equal to or less than IN-, the

resultant code will be 000h. If the voltage at IN+ is

equal to or greater than {[VREF + (IN-)] - 1 LSB}, then

the output code will be FFFh. If the voltage level at IN-

is more than 1 LSB below VSS, the voltage level at the

IN+ input will have to go below VSS to see the 000h

output code. Conversely, if IN- is more than 1 LSB

above V SS, then the FFFh code will not be s een unles s

the IN+ input level goes above VREF level.

For the A/D converte r to mee t specifi catio n, the c harge

holding capacitor (CSAMPLE) must be given enough

time to acquire a 12-bit accurate voltage level during

the 1.5 cloc k cycle sampling period. The analog input

model is shown in Figure 4-1.

Name Function

VDD +2.7V to 5.5V Power Supply

DGND Digital Ground

AGND Analog Ground

CH0-CH7 Analog Inputs

CLK S erial Clock

DIN Serial Data In

DOUT Serial Data Out

CS/SHDN Chip Select/Shutdown Input

VREF Referen ce Volt age Input

MCP3204/3208

This diagram illustrates that the source impedance (RS)

adds to the intern al sampling switch (RSS) imped ance,

directly effecti ng the time that is requir ed to charge th e

capacitor (Csample). Consequently, larger source

impedances increase the offset, gain and integral

lineari ty errors of the conversion (see Figure 4-2).

4.2 Reference Input

For each device in the family, the reference input

(VREF) determines the analog input voltage range. As

the refere nce i nput i s redu ced, t he LSB s ize is red uced

accordingly. The theoretical digital output code pro-

duced by the A/D converter is a function of the analog

input signal and the reference input, as shown below.

EQUATION

When using an external voltage reference device, the

system designer should always refer to the manufac-

turer’s recom mendations for circ uit layo ut. Any in stabi l-

ity in the operation of the reference device will have a

direct effect on the operation of the A/D converter.

FIGURE 4-1: Analog Input Model.

FIGURE 4-2: Maximum Clock Frequency

vs. Input resistance (RS) to maintain less than a

0.1 LSB deviation in INL from nominal

conditions.

Digital Output Code 4096 VIN

VREF

---------------------------

VIN = analog input voltage

VREF = re fe rence voltage

CPIN

RSS CHx

7pF

VT = 0.6V

VT = 0.6V ILEAKAGE

Sampling

Switch

SS RS = 1 kΩ

CSAMPLE

= DAC capacitance

VSS

VDD

= 20 pF

±1 nA

Legend

VA =Signal Source Ileakage =Leakage Current At The Pin

Due To Various Junctions

Rss =Source Impedance SS =Sampling switch

CHx =Input Channel Pad Rs=Sampling switch resistor

Cpin =Input Pin Capacitance Csample =Sample/hold capacitance

Vt=Threshold V oltage

0.0

0.5

1.0

1.5

2.0

2.5

100 1000 1000

Input Resistance (Ohms)

Clock Frequency (MHz)

VDD = 5 V

VDD = 2.7 V

MCP3204/3208

5.0 SERIAL COMMUNICATIONS

Communication with the MCP3204/3208 devices is

accomplished using a standard SPI-compatible serial

inter fac e. I nit iating communic atio n w i th e ith er d ev ic e i s

done b y bring ing the CS line lo w (see Figu re 5-1). If the

device was powered up with the CS pin low, it must be

brought high and back low to initiate communication.

The first clock received with CS low and DIN high will

consti tute a st art bit. The SGL/DIFF bit follows the start

bit and will determine if the conversion will be done

using s ing le-e nd ed o r differential inp ut m ode . The nex t

three bits (D0, D1 and D2) are used to select the input

channel configuration. Table 5-1 and Table 5-2 show

the configuration bits for the MCP3204 and MCP3208,

respectively. The device will begin to sample the ana-

log inpu t on th e fourth rising edge of the c loc k after th e

start bit has bee n re ce ive d. The sample peri od will end

on the falling edge of the fifth clock following the start

bit.

Once t h e D0 b it is i n pu t, o ne m or e c loc k is r e qui r ed to

complete the sample and hold period (DIN is a “don’t

care” for this clock). On the falling edge of the next

clock, the device will output a low null bit. The next 12

clock s will output the res ult o f the c onvers ion wi th MSB

first, as shown in Figure 5-1. Data is always output from

the devi ce on the f alling edge o f the cl ock. If all 12 da ta

bit s have been tra ns mi tted an d t he device continues to

receive clocks while the CS is held low, the device will

output the conversion result LSB first, as shown in

Figure 5-2. If more clocks are provided to the device

while CS is still low (after the LSB first data has been

transmi tted), th e devi ce will cloc k out z eros i ndefin itely.

If necessary, it is possible to bring CS low and cloc k in

leading zeros on the D IN line before the start b it. This is

often done when dealing with microcontroller-based

SPI ports that must send 8 bits at a time. Refer to

Section 6.1 for more details on using the MCP3204/

3208 devices with hardware SPI ports.

TABLE 5-1: CONFIGURATION BITS FOR

THE MCP320 4

TABLE 5-2: CONFIGURATION BITS FOR

THE MCP320 8

Control Bit

Selections Input

Configuration Channel

Selection

Single/

Diff D2* D1 D0

1 X 0 0 single-ended CH0

1 X 0 1 single-ended CH1

1 X 1 0 single-ended CH2

1 X 1 1 single-ended CH3

0 X 0 0 differential CH0 = IN+

CH1 = IN-

0 X 0 1 differential CH0 = IN-

CH1 = IN+

0 X 1 0 differential CH2 = IN+

CH3 = IN-

0 X 1 1 differential CH2 = IN-

CH3 = IN+

* D2 is a “don’t care” for MCP3204

Control Bit

Selections Input

Configuration Channel

Selection

Single

/Diff D2 D1 D0

1 0 0 0 single-ended CH0

1 0 0 1 single-ended CH1

1 0 1 0 single-ended CH2

1 0 1 1 single-ended CH3

1 1 0 0 single-ended CH4

1 1 0 1 single-ended CH5

1 1 1 0 single-ended CH6

1 1 1 1 single-ended CH7

0 0 0 0 differential CH0 = IN+

CH1 = IN-

0 0 0 1 differential CH0 = IN-

CH1 = IN+

0 0 1 0 differential CH2 = IN+

CH3 = IN-

0 0 1 1 differential CH2 = IN-

CH3 = IN+

0 1 0 0 differential CH4 = IN+

CH5 = IN-

0 1 0 1 differential CH4 = IN-

CH5 = IN+

0 1 1 0 differential CH6 = IN+

CH7 = IN-

0 1 1 1 differential CH6 = IN-

CH7 = IN+

MCP3204/3208

FIGURE 5-1: Communication with the MCP3204 or MCP3208.

FIGURE 5-2: Communication with MCP3204 or MCP3208 in LSB First Format.

CLK

DIN

DOUT

D1D2 D0

HI-Z

Don’t Care

Null

Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*HI-Z

tSAMPLE

tCONV

SGL/

DIFF

Start

tCYC

tCSH

tCYC

SGL/

DIFF

Start

* After com pletin g the d ata transfe r, if further clock s are a pplie d with CS low, the A/ D con verter will out put LSB

first data, followed by zeros indefinitely (see Figure 5-2 below).

** tDATA: during this time, the bias current and the comparator power down while the reference input becomes

a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.

tDATA **

tSUCS

Null

Bit B11B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10B11

CLK

DOUT HI-Z HI-Z

(MSB) tCONV tDATA **

Power Down

tSAMPLE

Start

SGL/

DIFF

DIN

tCYC

tCSH

D0D1D2

* After com pleting the data trans fer , if furt her clocks are applied w ith CS low , the A/D conver ter will out put zeros

indefinitely.

** tDATA: During this time, the bi as circui t and the com pa rator pow er down whil e the refere nce inp ut becomes a

high impedance node, leaving the CLK running to clock out LSB first data or zeroes.

tSUCS

Don’t Care

MCP3204/3208

6.0 APPLICATIONS INFORMATION

6.1 Using the MCP3204/3208 with

Microcontroller (MCU) SPI Ports

With most microcontroller SPI ports, it is required to

send groups of eight bits. It is also required that the

microc ontroller SPI p ort be confi gured to cl ock out da ta

on the fal ling edge of clock and lat ch d at a in on the ris-

ing edge. Because communication with the MCP3204/

3208 dev ic es may not need mult ipl es of ei ght clocks, it

will be necessary to provide more clocks than are

required. This is usually done by sending ‘leading

zeros’ before the start bit. As an example, Figure 6-1

and Figure 6-2 illustrate how the MCP3204/3208 can

be interfaced to a MCU with a hardware SPI port.

Figure 6-1 depicts the operation shown in SPI Mode

0,0, which requires that the SCLK from the MCU idles

in the ‘low’ state, while Figure 6-2 shows the similar

case of SPI Mode 1 ,1, where the clock idles in the ‘high’

state.

As is shown in Figure 6-1, the first byte transmitted to

the A/D converter contains five leading zeros before

the start bit. Arranging the leading zeros this way

allows the output 12 bits to fall in positions easily

manipulated by the MCU. The MSB is clocked out of

the A/D converter on the falling edge of clock number

12. Once the second eight clocks have been sent to the

device, the MCU’s receive buffer will contain three

unknown bits (the output is at high impedance for the

first two clocks), the null bit and the highest order four

bits of the conversion. Once the third byte has been

sent to the device, the receive register will contain the

lowest order eight bits of the conversion results.

Employing this method ensures simpler manipulation

of the converted data.

Figure 6-2 shows the same thing in SPI Mode 1,1,

which requires that the clock idles in the high state. As

with mode 0,0, the A/D converter outputs data on the

falling edge of the clock and th e MCU latches data from

the A/D converter in on the rising edge of the clock.

MCP3204/3208

FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).

FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

SCLK

DIN

X = “Don’t Care” Bits

17 18 19 20 21 22 23 24

DOUT NULL

BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

HI-Z

MCU latches data from A/D

Data is clocked out of A/D

converter on falling edges

converter on rising edges of SCLK

DO Don’t Care

SGL/

DIFF D1

Start

000001XX XXX

DO XXXXXXXX

B7 B6 B5 B4 B3 B2 B1 B0

B11 B10 B9 B80

???????? ???

SGL/

DIFF

Start

Bit

(Null)

MCU Transmitted Data

(Aligned with falling

edge of clock)

MCU Received Data

(Aligned with rising

edge of clock)

Data stored into MCU receive

regist er after tr ansmission o f first

8 bits

Data stored into MCU receive

second 8 bits

Data stored into MCU receive

8 bits

Don’t Care

000001 XXXXX

DO XXXXXXXX

B7 B6 B5 B4 B3 B2 B1 B0B11 B10 B9 B8

???????? ???

SGL/

DIFF

(Null)

1 2 3 4 5 6 7 8 9 101112131415 16

SCLK

X = “Don’t Care” Bits

17 18 19 20 21 22 23 24

OUT

DO Don’t Care

NULL

BIT B11 B10 B9

B8 B6 B5 B4 B3 B2 B1 B0

HI-Z

000001 XXXXX

SGL/

DIFF

XXXXXXXX

B7 B6 B5 B4 B3 B2 B1 B0B11 B10 B9 B8

???????? ???

MCU latches data from A/D converter

on rising edges of SCLK

Data is clocked out of A/D

converter on falling edges

SGL/

DIFF

Start

Bit

(Null)

Start

MCU T ransmitted Data

(Alig ne d with falling

edge of clock)

MCU Received Data

(Aligned with rising

edge of clock)

Data stored into MCU receive

8 bits

Data stored into MCU receive

second 8 bits

Data stored into MCU receive

8 bits

MCP3204/3208

6.2 Maintaining Minimum Clock

Speed

When the MCP3204/3208 initiates the sample period,

charge is stored on the sample capacitor. When the

sample period is complete, the device converts one bit

for each clock that is received. It is important for the

user to note that a slow clock rate will allow charge to

bleed off the sample capacitor while the conversion is

taking place. At 85°C (worst case condition), the part

will maint ain proper charge on the s ample c apa citor for

at leas t 1.2 ms after the s ample pe riod has e nded. Thi s

means that the time between the end of the sample

period and the time that all 12 data bits have been

clocked out must not exceed 1.2 ms (effective clock

frequenc y of 10 kHz). Fai lure to mee t this crit erio n ma y

introduce linearity errors into the conversion outside

the rated specifications. It should be noted that during

the ent ire conversion cycle, the A/D co nverter does not

require a const ant clock s peed or duty c ycle, as lon g as

all timing spec ifi ca t ion s are met .

6.3 Buffering/Filtering the Analog

Inputs

If the signal source for the A/D converter is not a low

impeda nce sou rce, it will ha ve to b e buf fered or inacc u-

rate conv ersion result s may occur (see Fi gure 4-2). It is

also reco mmended that a filter be used to eliminate an y

signals that may be aliased back into the conversion

result s, as i s i llustra ted in Figure 6-3, where an op amp

is used to drive the analog input of the MCP3204/3208.

This a mpl ifi er prov id es a lo w i mp eda nce s ou rce fo r the

converter input, and a low pass filter, which eliminates

unwanted high frequency noise.

Low pass (anti-aliasing) filters can be designed using

Microc hip’ s free in teracti ve Fil terLab™ s oftware. F ilter-

Lab will calculate ca pac itor and res istor va lues, as well

as determine the number of poles that are required for

the application. For more information on filtering sig-

nals, see AN699, “Anti-Aliasing Analog Filters for Data

Acquisition Systems”.

FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a second order anti-aliasing

filter for the signal being converted by the MCP3204.

MCP3204

VDD

10 µF

IN-

IN+

VIN

VREF

4.096V

Reference

1µF

0.1 µF

MCP601

R3R4

MCP1541

MCP3204/3208

6.4 Layout Considerations

When laying out a printed circuit board for use with

analog components, care should be taken to reduce

noise wherever possible. A bypass capacitor should

always be used with this device, placed as close as

pos s ible to the device pin. A bypass capacitor value of

1 µF is recommended.

Digit al and analog trac es should be sep arated as much

as pos sible on the board, with no trac es running under-

neath the device or the bypass capacitor. Extra precau-

tions should be taken to keep traces with high

frequency signals (such as clock lines) as far as

possible from analog traces.

Use of an analog ground plane is recommended in

order to keep the ground potential the same for all

devices on the board. Providing VDD connections to

devices in a “star” configuration can also reduce noise

by eliminating return current paths and associated

errors (s ee F igu re 6-4). For more i nfo rma tio n on la yo ut

tips when using A/D converters, refer to AN688,

“Layout Tip s for 12-Bit A/ D conve r ter Applic ati ons ”.

FIGURE 6-4: VDD traces arranged in a

‘S tar’ configuration in order to reduce errors

caused by current return paths.

6.5 Utilizing the Digi tal and Analog

Ground Pins

The MCP3204/3208 devices provide both digital and

analog ground connections to provide another means

of noise reduction. As shown in Figure 6-5, the analog

and d igi tal c ircui tr y is separa ted inte rn al to th e de vice .

This redu ces noise f rom the dig ital portio n of the devic e

being coupled into the analog portion of the device. The

two grounds are connected internally through the sub-

strate, which has a resistance of 5 -10Ω.

If no ground plane is utilized, then both grounds must

be connected to VSS on the boa rd. If a grou nd pl ane is

available, both digital and analog ground pins should

be connected to the analog ground plane. If both an

analog and a digital ground plane are available, both

the digital and the analog ground pins should be con-

nected to the analog ground plane. Following these

steps will reduce the amount of digital noise from the

rest of the board being coupled into the A/D converter.

FIGURE 6-5: Separation of Analog and

Digital Ground Pins.

Connection

Device 1

Device 2

Device 3

Device 4

MCP3204/08

Analog Ground Plane

DGND AGND

VDD

0.1 µF

Substrate

5 - 10Ω

Digital Side

-SPI Interface

-Shift Register

-Control Logic

Analog Side

-Sample Cap

-Capacitor Array

-Comparator

MCP3204/3208

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This pa ckage is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the eve nt the ful l Micro chip pa rt num ber cannot be ma rked on o ne line, it wi

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

14-Lead PDIP (300 mil) Example:

14-Lead SOIC (150 mil) Example:

XXXXXXXXXXXXXX

YYWWNNN

XXXXXXXXXXX

YYWWNNN

MCP3204-B

I/P

0723NNN

XXXXXXXXXXX MCP3204-B

0723NNN

XXXXXXXXXXX

XXXXXXXX

NNN

YYWW

14-Lead TSSOP (4.4mm) * Example:

3204-C

NNN

0723

MCP3204/3208

Package Marking Information (Continued)

16-Lead PDIP (300 mil) (MCP3304)Example:

16-Lead SOIC (150 mil) (MCP3304)Example:

XXXXXXXXXXXXXX

YYWWNNN

XXXXXXXXXXXXX

YYWWNNN

MCP3208-B

I/P

0723NNN

XXXXXXXXXXXXX MCP3208-B

IYWWNNN

XXXXXXXXXX

MCP3204/3208

14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

otes:

. Pin 1 visual index feature may vary, but must be located with the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 14

Pitch e .100 BSC

Top to Seating Plane A – – .210

Molded Package Thickness A2 .115 .130 .195

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .290 .310 .325

Molded Package Width E1 .240 .250 .280

Overall Length D .735 .750 .775

Tip to Seating Plane L .115 .130 .150

Lead Thickness c .008 .010 .015

Upper Lead Width b1 . 045 .060 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

123

Microchip Technology Drawing C04-005

MCP3204/3208

14-Lead Plastic Small Outli ne (SL) – Narrow, 3.90 mm Body [SOIC]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 14

Pitch e 1.27 BSC

Overall Height A – – 1.75

Molded Package Thickness A2 1.25 – –

Standoff § A1 0.10 – 0. 25

Overall Width E 6.00 BSC

Molded Package Width E1 3.90 BSC

Overall Length D 8.65 BSC

Chamfer (optional) h 0.25 – 0.50

Foot Length L 0.40 – 1.27

Footprint L1 1.04 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.17 – 0.25

Lead Width b 0.31 – 0. 51

Mold Draft Angle Top α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

123

hα

Microchip Technology Drawing C04-065

MCP3204/3208

14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 14

Pitch e 0.65 BSC

Overall Height A – – 1.20

Molded Package Thickness A2 0.80 1.00 1.05

Standoff A1 0.05 – 0.15

Overall Width E 6.40 BSC

Molded Package Width E1 4.30 4.40 4.50

Molded Package Length D 4.90 5.00 5.10

Foot Length L 0.45 0.60 0.75

Footprint L1 1.00 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.09 – 0.20

Lead Width b 0.19 – 0. 30

NOTE 1

L1 L

Microchip Technology Drawing C04-087

MCP3204/3208

16-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 16

Pitch e .100 BSC

Top to Seating Plane A – – .210

Molded Package Thickness A2 .115 .130 .195

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .290 .310 .325

Molded Package Width E1 .240 .250 .280

Overall Length D .735 .755 .775

Tip to Seating Plane L . 115 .130 .150

Lead Thickness c .008 . 010 .015

Upper Lead Width b1 . 045 .060 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

12 3

A1 b1

Microchip Technology Drawing C04-017

MCP3204/3208

16-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 16

Pitch e 1.27 BSC

Overall Height A – – 1.75

Molded Package Thickness A2 1.25 – –

Standoff § A1 0.10 – 0. 25

Overall Width E 6.00 BSC

Molded Package Width E1 3.90 BSC

Overall Length D 9.90 BSC

Chamfer (optional) h 0.25 – 0.50

Foot Length L 0.40 – 1.27

Footprint L1 1.04 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.17 – 0.25

Lead Width b 0.31 – 0. 51

Mold Draft Angle Top α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

A1 β

Microchip Technology Drawing C04-108

MCP3204/3208

NOTES:

MCP3204/3208

APPENDIX A: REVISION HISTORY

Revision D (January 2007)

This revision includes updates to the packaging dia-

grams.

MCP3204/3208

NOTES:

MCP3204/3208

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP3204: 4-Channel 12-Bit Serial A/D Converter

MCP3204T: 4-Channel 12-Bit Serial A/D Converter

(Ta pe and Ree l)

MCP3208: 8-Channel 12-Bit Serial A/D Converter

MCP3208T: 8-Channel 12-Bit Serial A/D Converter

(Ta pe and Ree l)

Grade: B = ±1 LSB INL

C=±2LSB INL

Temperatu re Range: I = -40° C to +85°C

Package: P = Plastic DIP (300 mil Body), 14-lead, 16-lead

SL = Plastic SOIC (150 mil Body), 14-lead, 16-lead

ST = Plastic TSSOP (4.4mm), 14-lead

Examples:

a) MCP3204-BI/P: ± 1 LSB INL, I ndustrial Tem-

perature, PDIP package.

b) MCP3204-BI/SL: ±1 LSB INL, Industrial

Temperature, SOIC package.

c) MCP3204-CI/ST: ±2 LSB INL, Industrial

Temperature, TSSOP package.

a) MCP3208-BI/P: ±1 LSB INL, Industrial

Temperature, PDIP package.

b) MCP3208-BI/SL: ±1 LSB INL, Industrial

Temperature , SOIC pack age.

c) MCP3208-CI/ST: ±2 LSB INL, Industrial

Temperature, TSSOP package.

PART NO. X/XX

PackageTemperature

Range

Device

Grade

MCP3204/3208

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is pro vid ed only fo r yo ur c onvenien ce

and may be supers eded by updates. It is y our resp o ns i bil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART ,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLI NK, PIC kit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInf o, PowerMate, PowerTool, REAL ICE , rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporat ed in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in t heir particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure famili es of its kind on the market today, when used in t he

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microchip are commit ted to continuously improving the code protect ion f eatures of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

T empe, Arizona, Gresham, Oregon and Mountain View , California. The

Company’s quality system processes and procedures are for its PIC®

MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

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12/08/06