2
Precision Edge®
SY89832U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
August 2007
IN /IN EN Q /Q
0 1101
1 0110
XX00
(1) 1(1)
Note 1. On next negative transition of the input signal (IN).
TRUTH TABLE
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package Operating Package Lead
Part Number Type Range Marking Finish
SY89832UMI MLF-16 Industrial 832U Sn-Pb
SY89832UMITR(2) MLF-16 Industrial 832U Sn-Pb
SY89832UMG(3) MLF-16 Industrial 832U with Pb-Free NiPdAu
bar line indicator Pb-Free
SY89832UMGTR(2, 3) MLF-16 Industrial 832U with Pb-Free NiPdAu
bar line indicator Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
Pin Number Pin Name Pin Function
15, 16 Q0, /Q0 LVDS Differential (Outputs): Normally terminated with 100ý across the pair (Q, /Q). See “LVDS
1, 2 Q1, /Q1 Outputs” section, Figure 2a. Unused outputs should be terminated with a 100ý resistor across
3, 4 Q2, /Q2 each pair.
5, 6 Q3, /Q3
8 EN This single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The
synchronous enable ensures that enable/disable will only occur when the outputs are in a logic
LOW state. Note that this input is internally connected to a 25ký pull-up resistor and will default
to logic HIGH state (enabled) if left open.
9, 12 /IN, IN Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
accept AC- or DC-Coupled differential signs as small as 100mV. Each pin of a pair internally
terminates to a VT pin through 50ý. Note that these inputs will default to an intermediate state if
left open. Pleae refer to the “Input Interface Applications” section for more details.
10 VREF–AC Reference Voltage: These outputs bias to VCC–1.4V. They are used when AC coupling the
inputs (IN, /IN). For AC-Coupled applications, connect VREF-AC to VT pin and bypass with
0.01µF low ESR capacitor to VCC. See “Input Interface Applications” section for more details.
Maximum sink/source current is ±1.5mA. Due to the limited drive capability, each VREF-AC pin
is only intended to drive its respective VT pin.
11 VT Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The
VT pins provide a center-tap to a termination network for maximum interface flexibility. See “Input
Interface Applications” section for more detaiils.
13 GND Ground. GND pins and exposed pad must be connected to the most negative potential of the
device ground.
7, 14 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors and place as close to
each VCC pin as possible.
PIN DESCRIPTION
13141516
12
11
10
9
1
2
3
4
8765
Q1
/Q1
Q2
Q2
IN
VT
VREF-AC
/IN
/Q0
Q0
VCC
GND
Q3
/Q3
VCC
EN
16-Pin MLF® (MLF-16)