+
±R4
+
±R3
+
±R2
+
±R1 ROUT1
ROUT2
ROUT3
ROUT4
EN
EN*
RIN4-
RIN4+
RIN3+
RIN3-
RIN2+
RIN2-
RIN1+
RIN1-
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90LV032A
SNLS011D –JULY 1999–REVISED AUGUST 2016
DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver
1
1 Features
1• >400 Mbps (200 MHz) Switching Rates
• 0.1-ns Channel-to-Channel Skew (Typical)
• 0.1-ns Differential Skew (Typical)
• 3.3-ns Maximum Propagation Delay
• 3.3-V Power Supply Design
• Power Down High Impedance on LVDS Inputs
• Low Power Design (40 mW at 3.3 V Static)
• Interoperable With Existing 5-V LVDS Networks
• Accepts Small Swing (350 mV Typical) VID
• Supports Open, Short, and Terminated Input Fail-
Safe
• Compatible With ANSI/TIA/EIA-644
• Industrial Temperature Operating Range (–40°C
to 85°C)
• Available in SOIC and TSSOP Packaging
2 Applications
• Building And Factory Automation
• Grid Infrastructure
3 Description
The DS90LV032A is a quad CMOS differential line
receiver designed for applications requiring ultra-low
power dissipation and high data rates. The device is
designed to support data rates in excess of 400 Mbps
(200 MHz) using Low Voltage Differential Signaling
(LVDS) technology.
The DS90LV032A accepts low voltage (350 mV
typical) differential input signals and translates them
to 3-V CMOS output levels. The receiver supports a
TRI-STATE function that may be used to multiplex
outputs. The receiver also supports open, shorted,
and terminated (100 Ω) input Fail-safe. The receiver
output is HIGH for all fail-safe conditions.
The DS90LV032A and companion LVDS line driver
(for example, DS90LV031A) provide a new
alternative to high power PECL or ECL devices for
high speed point-to-point interface applications.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
DS90LV032A SOIC (16) 9.90 mm × 3.91 mm
TSSOP (16) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics .......................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Dissipation Ratings ................................................... 6
6.8 Typical Characteristics.............................................. 7
7 Parameter Measurement Information .................. 8
8 Detailed Description............................................ 10
8.1 Overview................................................................. 10
8.2 Functional Block Diagram....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 11
9 Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application.................................................. 12
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 15
12 Device and Documentation Support................. 16
12.1 Documentation Support ....................................... 16
12.2 Receiving Notification of Documentation Updates 16
12.3 Community Resources.......................................... 16
12.4 Trademarks........................................................... 16
12.5 Electrostatic Discharge Caution............................ 16
12.6 Glossary................................................................ 16
13 Mechanical, Packaging, and Orderable
Information........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2013) to Revision D Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
• Added Thermal Information table........................................................................................................................................... 4
Changes from Revision B (April 2013) to Revision C Page
• Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 7
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5 Pin Configuration and Functions
D or PW Package
16-Pin SOIC or TSSOP
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
EN 4 I Active high enable pin, OR-ed with EN
EN 12 I Active low enable pin, OR-ed with EN
GND 8 — Ground pin
RIN– 1, 7, 9, 15 I Inverting receiver input pin
RIN+ 2, 6, 10, 14 I Noninverting receiver input pin
ROUT 3, 5, 11, 13 O Receiver output pin
VCC 16 — Power supply pin, 3.3 V ± 0.3 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage VCC –0.3 4 V
Input voltage RIN+, RIN– –0.3 3.9 V
Enable input voltage EN, EN* –0.3 VCC + 0.3 V
Output voltage ROUT –0.3 VCC + 0.3 V
Lead temperature, soldering (4 s) 260 °C
Maximum junction temperature, TJ150 °C
Storage temperature, Tstg –65 150 °C
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(1) ESD Ratings: HBM (1.5 kΩ, 100 pF) ≥4.5 kV and EIAJ (0 Ω, 200 pF) ≥250 V
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge(1) Human-body model (HBM)(1) ±4500 V
Machine model (MM), EIAJ ±250
6.3 Recommended Operating Conditions MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
Receiver input voltage GND 3 V
TAOperating free-air temperature –40 25 85 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1) DS90LV032A
UNITPW (TSSOP) D (SOIC)
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 110 75 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 47 36 °C/W
RθJB Junction-to-board thermal resistance 55 32 °C/W
ψJT Junction-to-top characterization parameter 6 6 °C/W
ψJB Junction-to-board characterization parameter 54 31.7 °C/W
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(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
unless otherwise specified.
(2) VCC is always higher than RIN+ and RIN– voltage. RIN– and RIN+ are allowed to have a voltage range –0.2 V to VCC – VID / 2. However,
to be compliant with AC specifications, the common voltage range is 0.1 V to 2.3 V
(3) The VCMR range is reduced for larger VID. Example: if VID = 400 mV, the VCMR is 0.2 V to 2.2 V. The fail-safe condition with inputs
shorted is valid over a common mode range of 0 V to 2.3 V. A VID up to VCC – 0 V may be applied to the RIN+/ RIN– inputs with the
common mode voltage set to VCC / 2. Propagation delay and differential pulse skew decrease when VID is increased from 200 mV to
400 mV. Skew specifications apply for 200 mV ≤VID ≤800 mV over the common mode range.
(4) Output short-circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output must be shorted at
a time, do not exceed maximum junction temperature specification.
6.5 Electrical Characteristics
over supply voltage and operating temperature ranges (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VTH Differential input high threshold VCM = 1.2 V, RIN+, RIN– pin(2) 20 100 mV
VTL Differential input low threshold –100 –20 mV
VCMR Common mode voltage range VID = 200 mV peak to peak, RIN+, RIN– pin(3) 0.1 2.3 V
IIN Input current VCC = 3.6 V or 0 V,
RIN+, RIN– pin VIN = 2.8 V –10 ±1 10 µA
VIN = 0 V –10 ±1 10 µA
VCC = 0 V, VIN = 3.6 V, RIN+, RIN– pin –20 20 µA
VOH Output high voltage IOH = –0.4 mA, VID = 200 mV, ROUT pin 2.7 3 V
IOH = –0.4 mA, input terminated, ROUT pin 2.7 3 V
IOH = –0.4 mA, input shorted, ROUT pin 2.7 3 V
VOL Output low voltage IOL = 2 mA, VID = –200 mV, ROUT pin 0.1 0.25 V
IOS Output short-circuit current Enabled, VOUT = 0 V, ROUT pin(4) –15 –48 –120 mA
IOZ Output TRI-STATE current Disabled, VOUT = 0 V or VCC –10 ±1 10 µA
VIH Input high voltage EN, EN* pins 2 VCC V
VIL Input low voltage EN, EN* pins GND 0.8 V
IIInput current VIN = 0 V or VCC, other input = VCC or GND,
EN, EN* pins –10 ±1 10 µA
VCL Input clamp voltage ICL = –18 mA, EN, EN* pins –1.5 –0.8 V
ICC No load supply current EN, EN* = VCC or GND, inputs open, VCC pin 10 15 mA
Receivers enabled EN, EN* = 2.4 V or 0.5 V, inputs open, VCC pin 10 15 mA
ICCZ No load supply current Receivers disabled, EN = GND, EN* = VCC,
inputs open, VCC pin 3 5 mA
6
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(1) All typicals are given for: VCC = 3.3 V, TA= 25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO= 50 Ω, trand tf(0% to 100%) ≤3 ns for RIN.
(3) tSKD1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel
(4) tSKD2, channel-to-channel skew, is defined as the difference between the propagation delay of one channel and that of the others on the
same chip with any event on the inputs.
(5) tSKD3, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
at the same VCC, and within 5°C of each other within the operating temperature range.
(6) tSKD4, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Maximum –
Minimum| differential propagation delay.
(7) fMAX generator input conditions: tr= tf< 1 ns (0% to 100%), 50% duty cycle, differential (1.05-V to 1.35-V peak-to-peak). Output criteria:
60% / 40% duty cycle, VOL (maximum: 0.4 V), VOH (minimum: 2.7 V), load = 10 pF (stray plus probes).
6.6 Switching Characteristics
over supply voltage and operating temperature ranges (unless otherwise noted)(1)(2)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
tPHLD Differential propagation delay,
high to low CL= 10 pF 1.8 3.3 ns
tPLHD Differential propagation delay,
low to high VID = 200 mV 1.8 3.3 ns
tSKD1 Differential pulse skew(3)
|tPHLD – tPLHD|See Figure 4 and Figure 5 0 0.1 0.35 ns
tSKD2 Differential channel-to-channel skew(4) Same device 0 0.1 0.5 ns
tSKD3 Differential part-to-part skew(5) 1 ns
tSKD4 Differential part-to-part skew(6) 1.5 ns
tTLH Rise time 0.35 1.2 ns
tTHL Fall time 0.35 1.2 ns
tPHZ Disable time high to Z RL= 2 kΩ8 12 ns
tPLZ Disable time low to Z CL= 10 pF 6 12 ns
tPZH Enable time Z to high See Figure 6 and Figure 7 11 17 ns
tPZL Enable time Z to low 11 17 ns
fMAX Maximum operating frequency(7) All channels switching 200 250 MHz
6.7 Dissipation Ratings MAXIMUM PACKAGE POWER DISSIPATION AT 25°C
D package 1025 mW
PW package 866 mW
Derate D package 8.2 mW/°C above 25°C
Derate PW package 6.9 mW/°C above 25°C
7
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6.8 Typical Characteristics
Figure 1. Typical Pulse Skew Variation
vs Common Mode Voltage Figure 2. Variation in High-to-Low Propagation Delay
vs VCM
Figure 3. Variation in Low-to-High Propagation Delay vs VCM
8
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7 Parameter Measurement Information
Figure 4. Receiver Propagation Delay and Transition Time Test Circuit
Figure 5. Receiver Propagation Delay and Transition Time Waveforms
CLincludes load and test jig capacitance.
S1= VCC for tPZL, and tPLZ measurements.
S1= GND for tPZH and tPHZ measurements.
Figure 6. Receiver TRI-STATE Delay Test Circuit
9
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Parameter Measurement Information (continued)
Figure 7. Receiver TRI-STATE Delay Waveforms
+
±R4
+
±R3
+
±R2
+
±R1 ROUT1
ROUT2
ROUT3
ROUT4
EN
EN*
RIN4-
RIN4+
RIN3+
RIN3-
RIN2+
RIN2-
RIN1+
RIN1-
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10
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8 Detailed Description
8.1 Overview
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 8. This configuration provides a clean signaling environment for the fast edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the
range of 100 Ω. A termination resistor of 100 Ω(selected to match the media) is located as close to the receiver
input pins as possible. Other configurations are possible such as a multi-receiver configuration, but the effects of
a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise
margin limits, and total termination loading must be considered.
The DS90LV032A differential line receiver is capable of detecting signals as low as 100 mV, over a ±1-V
common-mode range centered around 1.2 V. This is related to the driver offset voltage which is typically 1.2 V.
The driven signal is centered around this voltage and may shift ±1 V around this center point. The ±1-V shifting
may be the result of a ground potential difference between the ground reference of the driver and the ground
reference of the receiver, the common-mode effects of coupled noise, or a combination of the two. The AC
parameters of both receiver input pins are optimized for a recommended operating input voltage range of 0 V to
2.4 V (measured from each pin to ground). The device operates for receiver input voltages up to VCC, but
exceeding VCC turns on the ESD protection circuitry which clamps the bus voltages.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Fail-Safe Feature
The LVDS receiver is a high-gain, high-speed device that amplifies a small differential signal (20 mV) to CMOS
logic levels. Due to the high gain and tight threshold of the receiver, take care to prevent noise from appearing as
a valid signal.
The internal fail-safe circuitry of the receiver is designed to source or sink a small amount of current, providing
fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated, or shorted receiver
inputs.
11
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Feature Description (continued)
1. Open input pins: The DS90LV032A is a quad receiver device, and if an application requires only 1, 2, or 3
receivers, the unused channel(s) inputs must be left OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high value pullup and pulldown resistors to set the output
to a HIGH state. This internal circuitry ensures a HIGH, stable output state for open inputs.
2. Terminated input: If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or power-
off condition, the receiver output is in a HIGH state, even with the end of cable 100-Ωtermination resistor
across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the
cable picks up more than 10 mV of differential noise, the receiver may see the noise as a valid signal and
switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect must
be used. Twisted pair cable offers better balance than flat ribbon cable.
3. Shorted inputs: If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0-V
differential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (GND to 2.4 V). It is only supported with inputs shorted and no
external common-mode voltage applied.
External lower value pullup and pulldown resistors (for a stronger bias) may be used to boost fail-safe in the
presence of higher noise levels. The pullup and pulldown resistors must be in the 5-kΩto 15-kΩrange to
minimize loading and waveform distortion to the driver. The common-mode bias point must be set to
approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry.
The footprint of the DS90LV032A is the same as the industry standard 26LS32 Quad Differential (RS-422)
Receiver.
8.4 Device Functional Modes
Table 1 lists the functional modes of the DS90LV032A.
Table 1. Truth Table
ENABLES INPUTS OUTPUT
EN EN* RIN+ – RIN– ROUT
L H X Z
All other combinations of ENABLE inputs
VID ≥0.1 V H
VID ≤–0.1 V L
Full Fail-safe
OPEN/SHORT or
Terminated H
Copyright © 2016, Texas Instruments Incorporated
ENABLE
DATA
INPUT
¼ DS90LV031
+
±
RT
100Ÿ
¼ DS90LV032
DATA
OUTPUT
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS90LV032A LVDS receiver and DS90LV031A driver are intended to be primarily used in an uncomplicated
point-to-point configuration as shown in Figure 8. This configuration provides a clean signaling environment for
the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may
be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic
impedance of the media is in the range of 100 Ω.
9.1.1 Probing LVDS Transmission Lines
Always use high impedance (>100 kΩ), low capacitance (<2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing gives deceiving results.
9.1.2 Cables and Connectors, General Comments
When choosing cable and connectors for LVDS it is important to remember:
• Use controlled impedance media.
The cables and connectors you use must have a matched differential impedance of about 100 Ω. They must
not introduce major impedance discontinuities.
• Balanced cables (that is, twisted pair) are usually better than unbalanced cables (such as ribbon cable or
simple coax) for noise reduction and signal quality.
Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up
electromagnetic radiation as common-mode (not differential mode) noise which is rejected by the receiver.
For cable distances <0.5 m, most cables can be made to work effectively. For distances 0.5 m ≤d≤10 m,
Category 3 (CAT 3) twisted pair cable works well, is readily available, and relatively inexpensive.
9.2 Typical Application
Figure 8. Balanced System Point-to-Point Application
9.2.1 Design Requirements
When using LVDS devices, it is important to remember to specify controlled impedance PCB traces, cable
assemblies, and connectors. All components of the transmission media must have a matched differential
impedance of about 100 Ω. They must not introduce major impedance discontinuities. Balanced cables (for
example, twisted pair) are usually better than unbalanced cables (ribbon cable) for noise reduction and signal
quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up
electromagnetic radiation as common-mode (not differential mode) noise which is rejected by the LVDS receiver.
For cable distances < 0.5 m, most cables work effectively. For distances 0.5 m ≤d≤10 m, Category 5 (CAT5)
twisted pair cable works well, is readily available, and relatively inexpensive.
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Typical Application (continued)
9.2.2 Detailed Design Procedure
9.2.2.1 Probing LVDS Transmission Lines
Always use high impedance (>100 kΩ), low capacitance (<2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing gives deceiving results.
9.2.3 Application Curves
Figure 9. ICC vs Frequency, Four Channels Switching Figure 10. Typical Common Mode Range Variation
With Respect to Amplitude of Differential Input
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10 Power Supply Recommendations
Although the DS90LV032A draws very little power, there is a dynamic current component which increases the
overall power consumption at higher switching frequencies. The DS90LV032A power supply connection must
take this additional current consumption into consideration for maximum power requirements.
11 Layout
11.1 Layout Guidelines
• Use at least 4 PCB layers (top to bottom): LVDS signals, ground, power, and TTL signals.
• Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put
TTL and LVDS signals on different layers which are isolated by power or ground plane(s).
• Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
11.1.1 Power Decoupling Recommendations
Bypass capacitors must be used on power pins. High-frequency ceramic (surface-mount recommended) 0.1-µF
in parallel with 0.01-µF, in parallel with 0.001-µF at the power supply pin as well as scattered capacitors over the
printed-circuit board. Multiple vias must be used to connect the decoupling capacitors to the power planes. A 10-
µF, 35-V (or greater) solid tantalum capacitor must be connected at the power entry point on the printed-circuit
board.
11.1.2 Differential Traces
Use controlled impedance traces which match the differential impedance of your transmission medium (that is,
cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they
leave the IC (stubs must be <10 mm long). This helps eliminate reflections and ensure noise is coupled as
common-mode. Lab experiments show that differential signals which are 1 mm apart radiate far less noise than
traces 3 mm apart because magnetic field cancellation is much better with the closer traces. Plus, noise induced
on the differential lines is much more likely to appear as common-mode which is rejected by the receiver.
Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase
difference between signals which destroys the magnetic field cancellation benefits of differential signals and
results in EMI. Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997 mm/ps or 0.0118
in/ps. Do not rely solely on the auto-route function for differential traces. Carefully review dimensions to match
differential impedance and provide isolation for the differential lines. Minimize the number of vias and other
discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces must be minimized to maintain common-mode
rejection of the receivers. On the printed-circuit board, this distance must remain constant to avoid discontinuities
in differential impedance. Minor violations at connection points are allowable.
11.1.3 Termination
Use a resistor which best matches the differential impedance of your transmission line. The resistor must be
between 90 Ωand 130 Ω. Remember that the current mode outputs need the termination resistor to generate the
differential voltage. LVDS does not work without resistor termination. Typically, connect a single resistor across
the pair at the receiver end.
Surface-mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination
to the receiver inputs must be minimized. The distance between the termination resistor and the receiver must be
<10 mm (12 mm maximum).
8
7
Decoupling Cap
6
5
4
3
2
1
9
10
11
12
13
14
15
16
VCC
EN
EN*
GND
DS90LV032A
ROUT2
ROUT1
ROUT3
ROUT4
RIN4-
RIN4+
RIN3+
RIN3-
RIN2-
RIN2+
RIN1+
RIN1-
Series Termination (optional)
Control Signals
Input Termination
(Required)
LVCMOS Outputs
Input Termination (Required)
Input Termination (Required)
Series Termination (optional)
LVCMOS Outputs
Input Termination (Required)
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11.2 Layout Example
Figure 11. DS90LV032A Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
General application guidelines and hints for LVDS drivers and receivers may be found in the following application
notes:
•LVDS Owner's Manual
•AN-808 Long Transmission Lines and Data Signal Quality (SNLA028)
•AN-977 LVDS Signal Quality: Jitter Measurements Using Eye Patterns Test Report #1 (SNLA166)
•AN-971 An Overview of LVDS Technology (SNLA165)
•AN-916 A Practical Guide to Cable Selection (SNLA219)
•AN-805 Calculating Power Dissipation for Differential Line Drivers (SNOA233)
•AN-903 A Comparison of Differential Termination Techniques (SNLA034)
•AN-1035 PCB Design Guidelines for LVDS Technology (SNOA355)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS90LV032ATM NRND SOIC D 16 48 Non-RoHS
& Green Call TI Call TI -40 to 85 DS90LV032A
TM
DS90LV032ATM/NOPB ACTIVE SOIC D 16 48 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS90LV032A
TM
DS90LV032ATMTC NRND TSSOP PW 16 92 Non-RoHS
& Green Call TI Call TI -40 to 85 DS90LV
032AT
DS90LV032ATMTC/NOPB ACTIVE TSSOP PW 16 92 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS90LV
032AT
DS90LV032ATMTCX/NOPB ACTIVE TSSOP PW 16 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS90LV
032AT
DS90LV032ATMX NRND SOIC D 16 2500 Non-RoHS
& Green Call TI Call TI -40 to 85 DS90LV032A
TM
DS90LV032ATMX/NOPB ACTIVE SOIC D 16 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS90LV032A
TM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 2
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS90LV032ATMTCX/NO
PB TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
DS90LV032ATMX SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1
DS90LV032ATMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS90LV032ATMTCX/NOP
BTSSOP PW 16 2500 367.0 367.0 35.0
DS90LV032ATMX SOIC D 16 2500 367.0 367.0 35.0
DS90LV032ATMX/NOPB SOIC D 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
BNOTE 4
4.5
4.3
A
NOTE 3
5.1
4.9
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
89
16
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
89
16
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