Advance Datasheet SEPTEMBER 1999 Revision 278298-001 Level One(TM) IXP1200 Network Processor General Description Features The Level OneTM IXP1200 Network Processor delivers high-performance processing power and flexibility to a wide variety of networking and telecommunications products. Providing the best attributes of a custom network ASIC and an embedded microprocessor, the IXP1200 Network Processor combines an ARM(R) architecture compatible Intel(R) StrongARM(R) microprocessor with six programmable multithreaded microengines that together can switch 2.5 million packets/second in a single chip. * Access to the IX Bus Interface Unit, PCI Unit and SDRAM Unit via the ARM(R) AMBA Bus * High Bandwidth I/O Bus * Intel 64-bit, 66 MHz IX Bus * 4.2 Gb/s peak bandwidth * 64-bit or dual 32-bit IX Bus options * Integrated 32-bit, 66 MHz PCI Interface * PCI 2.1 compliant Bus Master * 264 Mbytes/s peak burst mode operation * Applications * I2O support for StrongARM(R) Core * LAN-WAN Switches * Dual DMA channels * WAN Switches * Industry Standard 64-bit SDRAM Interface * Telecommunications Systems * Peak bandwidth 648 Mbytes/s * Broadband Cable Products * Address up to 128 Mbytes of SDRAM * Remote Access Switches * Memory bandwidth optimization through bank switching * Six Integrated Programmable Microengines * Operating frequency at 162 MHz * Multi-thread microengine support of four * Read-modify-write support threads per * Byte aligner/merger * Single-cycle ALU and shift operations * Industry Standard 32-bit SRAM Interface * Zero context swap overhead * Large register set: 128 General Purpose and 128 Transfer Registers * 1K x 32-bit instruction Control Store * Access to the IX Bus Unit, PCI DMA channels, SRAM, and SDRAM (R) * ARM architecture StrongARM(R) Core compatible * Parity protected data (R) Intel * High performance, low-power, 32-bit RISC processor * Operating frequency at 162 MHz * 16 Kbyte instruction cache * 8 Kbyte data cache * 1 Kbyte mini-cache for data that is used once and then discarded * Peak bandwidth of 334 Mbytes/s * Address up to 8 Mbytes of SRAM * 8 Mbytes FlashROM for booting StrongARM(R) Core * Supports atomic push/pop operations * Supports atomic bit set and bit clear operations * Memory bandwidth improvement by reduced read/write turnaround bus cycles * Other Integrated Features * Hardware Hash Unit for generating 48 or 64-bit adaptive polynomial hash keys * Serial UART port * Real Time Clock * Four general purpose I/O pins * Write buffer * Four 24-bit timers with CPU watchdog support * Memory management unit * JTAG Support for IEEE 1149.1 Notice: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Level One sales office that you have the latest datasheet before finalizing a design. * 4 Kbyte Scratchpad Memory * 432-pin, ESBGA package * 2 V CMOS device * 3.3 V tolerant I/O * IXP1200 Network Environment Processor Development * Integrated Development Environment * Text Editor * Microcode Assembler * StrongARM(R) and Microcode Linker * Cycle- and data-accurate simulator of the IXP1200 Network Processor Information in this document is provided in connection with Level One products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Level One's Terms and Conditions of Sale for such products, Level One assumes no liability whatsoever, and Level One disclaims any express or implied warranty, relating to sale and/or use of Level One products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Level One products are not intended for use in medical, life saving, or life sustaining applications. Copyright (c) 1999 Level One Communications, Inc., an Intel company. Specifications subject to change without notice. All rights reserved. Printed in the United States of America. The Level One IXP1200 Network Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Level One sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Level One literature may be obtained by sending electronic mail to litreq@Level1.com or by visiting Level One's website at http://www.level1.com. *Third-party brands and names are the property of their respective owners. ARM and StrongARM are registered trademarks of ARM, Ltd. 2 TABLE OF CONTENTS Processor Description ..........................................5 Introduction .........................................................6 Related Documents .............................................6 Functional Units..................................................... 7 IXP1200 Network Processor ..............................7 Microengines .......................................................8 IX Bus Interface Unit and IX Bus ..................... 10 IX Bus Access Behavior ...................................10 SDRAM, SRAM Units ...........................................11 SDRAM Unit ..................................................... 11 SDRAM Bus Access Behavior .........................12 SDRAM Configurations ....................................13 SRAM Unit ........................................................13 SRAM Types Supported.............................. 14 SRAM Configurations.................................. 14 BootROM Configurations ............................15 SRAM Bus Access Behavior .......................15 PCI Unit 15 Device Reset ........................................................16 Hardware Initiated Reset ..................................16 Software Initiated Reset ...................................16 PCI Initiated Reset ...........................................16 Watchdog Timer Initiated Reset .......................16 Signal Description ................................................17 Pinout Diagram .................................................17 Pin Type Legend ...............................................18 Pin Description, Grouped by Function ...........18 Processor Support Pins.................................... 18 SRAM Interface Pins ........................................ 19 SDRAM Interface Pins .....................................21 IX Bus Interface Pins........................................ 23 General Purpose I/Os....................................... 26 Serial Port (UART) Pins ................................... 27 PCI Interface Pins ............................................27 Power Supply Pins ........................................... 30 JTAG Interface Pins .........................................31 Miscellaneous Test Pins .................................. 31 Pin Usage Summary ........................................ 31 Pin/Signal List ................................................... 32 Signals Listed in Alphabetical Order .............. 36 IX Bus Pins Function Listed by Operating Mode ............................................................................... 40 IX Bus Decode Table Listed by Operating Mode Type ...................................................................... 49 Pin State During Reset ..................................... 51 Pullup/Pulldown and Unused Pin, Drive Guidelines ........................................................... 51 Electrical Specifications ..................................... 52 Absolute Maximum Ratings ............................ 52 DC Specifications ............................................. 53 Type 1 Driver DC Specifications ...................... 53 Type 2 Driver DC Specifications ...................... 53 AC Specifications ............................................. 54 Clock Timing Specifications ............................. 54 PXTAL Clock Input........................................... 55 PXTAL Clock Oscillator Specifications ............ 55 PCI ................................................................... 56 PCI Electrical Specification Conformance .. 56 PCI Clock Signal AC Parameter Measurements .......................................................... 56 PCI Bus Signals Timing .............................. 57 Reset ................................................................ 58 Reset Timings Specification ....................... 58 JTAG................................................................. 59 JTAG Timing Specifications ........................ 59 IX Bus .............................................................. 59 FCLK Signal AC Parameter Measurements .... 59 IX Bus Signals Timing ...................................... 59 IX Bus Protocol ................................................ 60 RDYBus ........................................................... 79 TK_IN/TK_OUT ............................................... 81 SRAM Interface ............................................... 81 3 SRAM SCLK Signal AC Parameter Measurements .......................................................... 81 SRAM Bus Signal Timing ........................... 82 SRAM Bus - SRAM Signal Protocol and Timing ..................................................................... 83 SRAM Bus - BootROM and SlowPort Timings ..................................................................... 86 SRAM Bus - BootRom Signal Protocol and Timing ......................................................... 87 SRAM Bus - Slow-Port Device Signal Protocol and Timing .................................................. 90 SDRAM Interface ............................................. 93 SDCLK AC Parameter Measurements ....... 93 SDRAM Bus Signal Timing ......................... 94 SDRAM Signal Protocol .............................. 95 Asynchronous Signal Timing Descriptions ... 97 Mechanical Specifications ................................. 98 Package Dimensions ......................................... 8 IXP1200 Network Processor Package Dimensions (mm) ................................................ 99 Package Pin Layout with Power and Ground 101 4 SECTION 1 - PROCESSOR DESCRIPTION The Level OneTM IXP1200 Network Processor is a highly integrated, hybrid data processor that delivers highperformance parallel processing power and flexibility to a wide variety of networking, communications, and other data-intensive products. The IXP1200 Network Processor is designed specifically as a data control element for applications that require access to a fast memory subsystem, a fast interface to I/O devices such as network MAC devices, and processing power to perform efficient manipulation on bits, bytes, words, and doubleword (Dword) data. The IXP1200 Network Processor is combined with six independent 32-bit RISC data engines with hardware multithread support that provide over 1 giga-operations per second. The microengines contain the processing power to perform tasks typically reserved for high speed ASICs. In LAN switching applications, the six microengines are capable of performing 100% of the packet forwarding at Layer-3 for 2.5 million Ethernet packets per second. The IXP1200 Network Processor can then be used for more complex tasks such as address learning, building and maintaining forwarding tables, and network management. Figure 1: Level OneTM IXP1200 Network Processor Block Diagram PCI MAC Devices Host CPU (Optional) PCI Bus 66 MHz 32 SDRAM (up to 256 MB) SRAM (up to 8 MB) 64 32 PCI Bus Unit StrongARM(R) * Core SDRAM Memory Unit Microengine 1 Microengine 2 Microengine 3 Microengine 4 Microengine 5 Microengine 6 SRAM Memory Unit Boot ROM (up to 8 MB) IXP1200 Network Processor IX Bus Interface Unit Peripherals (ex. MAC control) 64 FIFO Bus 66 MHz 10 Mb/100 Mb/1Gb Ethernet MAC * StrongARM is a registered trademark of ARM Limited ** ARM architecture compatible ATM, T1/E1, Other MAC Another IXP-1200 A7006-02 5 1.1 Introduction * ARM V4.0 Architecture Reference The Level OneTM IXP1200 Network Processor is a highly integrated, hybrid data processor that delivers highperformance parallel processing power and flexibility to a wide variety of networking, communications, and other data-intensive products. The IXP1200 Network Processor is designed specifically as a data control element for applications that require access to a fast memory subsystem, a fast interface to I/O devices such as network MAC devices, and processing power to perform efficient manipulation on bits, bytes, words, and doubleword (Dword) data. The IXP1200 Network Processor technology is defined as a loosely-coupled, hybrid parallel processor set, integrating an ARM(R) architecture compatible Intel(R) StrongARM(R) Core with an array of RISC data engines. Maximum throughput can be maintained by isolating them from memory accesses and the resulting latencies. This is done by decoupling the functional units for the IX Bus, PCI Bus, SDRAM, and SRAM interfaces from the execution pipelines through the extensive use of FIFO queues, and event task signaling. Semaphore mechanisms and thread-level support are implemented in hardware, allowing for zero-overhead context switching between threads executing on the microengines. Up to four thread-level tasks can be allocated per microengine for a total of twenty-four threads in a single IXP1200 Network Processor. Multiple IXP1200 Network Processor devices can be aggregated in a serial or parallel fashion, or in serial-parallel combinations to support diverse applications. Support chips can assist the system designer in using the IXP1200 Network Processor in these multiprocessor designs. A full suite of software tools is available from Level OneTM for microengine code development, simulation and target hardware debug. These tools and can be used in conjunction with third-party StrongARM(R) software tools and Realtime Operating Systems to build a complete embedded solution. 1.2 Related Documents * Level One(R) IXP1200 Network Programmer's Reference Manual Processor * Level One(R) IXP1200 Network Development Tools User's Guide Processor * Level One(R) IXP1200 Network Processor Hardware Reference Manual * Level One(R) IXP1200 Network Processor Software Reference Manual 6 Important clarification: In this and related IXP1200 Network Processor documents, a Word is equal to 16 bits, a doubleword (Dword) is equal to 32 bits, and a quadword (Qword) is equal to 64 bits. StrongARM(R) documents and the ARM V4.0 Architecture Reference typically refer to a Word as being equal to 32 bits, and a halfword as being equal to 16-bits. A future release of the IXP1200 Network Processor document set will incorporate consistent terminology for all data sizes. SECTION 2 - FUNCTIONAL UNITS 2.1 IXP1200 Network Processor The IXP1200 Network Processor is the same industry standard 32-bit RISC processor as used in applications such as network computers, PDAs, palmtop computers and portable telephones. The differentiating feature of the IXP1200 Network Processor is that it provides very high performance in a low-power, compact design. This makes is feasible to combine it with a collection of other dedicated execution units on the same silicon die. The IXP1200 Network Processor and six RISC microengines provide the processing power required to forward 2.5 million Ethernet packets per second through the IXP1200 Network Processor using 16, 10/100 ports at full line rate, full-duplex. A multi-IXP1200 Network Processor system scales linearly so that, for example, a system comprised of eight IXP1200 Network processors (128, 10/100Mb Ethernet ports total) can process over 19 million packets per second. The designer can partition his application by allocating microengines, threads, and network processor tasks. If necessary, multiple IXP1200 Network Processor devices can be used to aggregate CPU MIPs, increase data bandwidth, increase port fanout and density, or some combination of all three metrics. When used with an input clock frequency of 3.6864 MHz, the network processor operates at a core speed (Fcore) of 162 MHz. 7 Figure 2: StrongARM(R) Core Block Diagram 3.686 MHz OSC PLL Clock Generator JTAG/Test Instruction 16K Instruction Cache IMMU PC SA-1 RISC Core 8K Data Cache DMMU Addr Mini cache Load Store Data SDRAM Unit SRAM Unit PCI Unit AMBA Translation Unit (ATU) Write Buffer Read Buffer StrongARM(R)* Core AMBA Cmd_bus[57:0] Sbus[63:0] Mbus[31:0] *StrongARM is a registered trademark of ARM Limited. ** ARM architecture compatible 2.2 Microengines Six 32-bit, multithreaded RISC microengines perform data movement and processing without assistance from the IXP1200 Network Processor. Each microengine has four independent program counters, zero overhead context switching and hardware semaphores from other hardware units to ensure that each microengine can be fully utilized. 8 A6301-02 A microengine's powerful ALU and shifter perform both ALU and shift operations in a single cycle. The instruction set was specifically designed for networking and communications applications that require bit, byte, word and Dword operations to forward data quickly and efficiently. Each microengine contains a large amount of local memory and registers: 4 Kbytes organized as 1024 by 32 bits of high-speed RAM Control Store for microcode execution, 128 32-bit General Purpose Registers, and 128 32-bit transfer registers to service the SRAM and SDRAM units. When used with an input clock frequency of 3.6864 MHz, the microengines operate at a core speed (Fcore) of 162 MHz. Figure 3: IXP1200 Network Processor Microengine Block Diagram Cmd_bus[57:0] Sbus[63:0] Sbus_pull[31:0] Sbus_push[31:0] Mbus[31:0] Mbus_pull[31:0] Mbus_push[31:0] SEQ#_event_response mbus_event_response sbus_event_response amba_event_response FBI_event_response PCI_event_response Ping Pong Context Event Arbiter Command FIFO 32 SDRAM Read Xfer Registers Other CSRs uPC_1/cc1 32 SDRAM Read Xfer Registers uPC_2/cc2 32 SDRAM Write Xfer Registers 32 SRAM Write Xfer Registers uPC_3/cc3 uPC_3/cc3 decode Engine Controller 64 A-Side GPRs 64 B-Side GPRs immed data address Control Store 1024 words (32-bit words) A B Registers per context Shifter ALU 16 GPR A-side 16 GPR B-side 8 SRAM read xfer 8 SRAM write xfer 8 SDRAM read xfer 8 SDRAM write xfer condition codes A7008-01 9 2.3 IX Bus Interface Unit and IX Bus The IX Bus Interface Unit is responsible for servicing fast peripherals, such as MAC-layer devices, on the IX Bus (FIFO Bus). This includes moving data to and from the IXP1200 Network Processor Receive and Transmit FIFOs. Network Processor will always drive and receive all 64-bits of the IX Bus in this mode. Valid bytes are indicated on FBE[7:0] driven by the IXP1200 Network Processor during writes, and by the target IX Bus resource on reads. * 32-bit Unidirectional Mode The IX Bus is split into independent 32-bit Transmit and 32-bit Receive data paths. Transmit data is driven on FDAT[63:32] and Receive data is input on FDAT[31:0]. In this mode, the Transmit path is always driven, and the Receive path is always an input. Valid bytes are identified for the Transmit path by FBE[7:4] signals. Valid bytes are identified for the Receive path by FBE[3:0]. The IX Bus provides a 4.2 Gb/s interface to peripheral devices. The IX Bus was specifically designed to provide a simple and efficient interface. The IX Bus can be configured as either a 64-bit, bidirectional bus or as two 32-bit, unidirectional buses operating at up to 66 MHz. The IX Bus Interface Unit contains the Transmit and Receive FIFO elements, chip-level Control Status Registers (CSRs), a 4 Kbyte Scratchpad RAM, and a Hash Unit for generating 48- and 64-bit hash keys. The IX Bus consists of 64 data pins, 23 control pins, and a clock input pin with a typical operating frequency of 66 MHz. A sideband control bus operating in parallel to the IX Bus, called the ReadyBus, consists of eight additional data pins and five control pins. The ReadyBus is synchronous to the IX Bus clock, but it's operation is controlled by a programmable hardware sequencer. ReadyBus cycles are separate and distinct from IX Bus cycles. Up to twelve sequencer commands are loaded at chip initialization time, and run in a continuous loop. The commands can consist of sampling FIFO status for the IX Bus devices, sending Flow Control messages to MAC devices, and reads/writes to other IXP1200 Network Processor devices as required by the application design. Refer to the IXP1200 Network Processor Hardware Reference Manual for specific details on using the ReadyBus. 2.3.1 IX Bus Access Behavior There are two basic modes of IX Bus operation. This is a configuration option only and is not intended to be used "on the fly" to switch between modes. * 64-Bit Bidirectional Mode The entire 64-bit data path FDAT[63:0] is used for reads, or writes to IX Bus devices. The IXP1200 Table 1: In addition, a shared IX Bus mode is supported in 64-bit Bidirectional mode. Refer to the list at the bottom of Table 20 for the signals that the IX Bus masters must drive and IX Bus slaves must tri-state. The IX Bus, and Level OneTM devices using the IX Bus such as the IXF440 Octal Fast Ethernet Media Access Controller and the IXF1002 Dual Port Gigabit Ethernet Media Access Controller observe a pipelined bus protocol. When cycles are ended early on receive cycles, the pipeline continues to cause several extra bus cycles depending on when the EOP signal was asserted. Data is a "don't care" for these trailing bus cycles, except in the case of a status transfer where the IX Bus burst includes a possible status transfer if the device were programmed to support it. The tables below show the number of total IX Bus data cycles that will occur for a burst with EOP asserted at specific clocks for 64 bit and 32 bit IX Bus modes. In each case, the tables show IX Bus cycles with and without the optional status transfer cycle. Refer to the IX Bus Protocol Timing diagrams (Figure 17 through Figure 37) when interpreting these tables. 64-bit IX Bus Receive Remainder Cycles, No Status Transfer EOP signaled on this cycle: 10 Each basic mode has two additional modes depending on the number of IX Bus devices and ports being used. 1-2 MAC mode for a one or two devices, and 3+ MAC mode when using three to seven devices. Bus timing, and the functions of the IX Bus signals are slightly different in each mode. These functional definitions per IX Bus mode are listed in Section 3.6 and Section 3.7. 1 2 3 4 5 6 7 8 # of bus cycles in burst: 5 6 7 8 8 8 8 8 # of Don't Care cycles: 4 4 4 4 3 2 1 0 Table 2: 64-bit IX Bus Receive Remainder Cycles, with Status Transfer EOP signaled on this cycle: 1 2 3 4 5 6 7 8 # of bus cycles in burst: 5 6 7 8 8 8 8 8 Status transfer 1 1 1 1 1 1 1 Note 1 # of Don't Care cycles: 3 3 3 3 2 1 0 0 NOTE: 1. Status transfer cycle occurs on a subsequent dedicated IX Bus status cycle. Table 2: 32-bit IX Bus Receive Remainder Cycles, No Status Transfer EOP signaled on this cycle: Table 3: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 # of bus cycles in burst: 5 6 7 8 9 10 11 12 13 14 15 16 16 16 16 16 # of Don't Care cycles: 4 4 4 4 4 4 4 4 4 4 4 4 3 2 1 0 32-bit IX Bus Receive Remainder Cycles, with Status Transfer EOP signaled on this cycle: # of bus cycles in burst: Status transfer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 5 6 7 8 9 10 11 12 13 14 15 16 16 16 16 16 1 N o t e 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOTE: 1. Status transfer cycle occurs on a subsequent IX Bus cycle. In both 32-bit and 64-bit modes, all of the associated FBE# signals (four Transmit FBE#s and four Receive FBE#s in 32 bit mode, and eight Transmit/Receive FBE#s for 64-bit mode) are driven low on a transmit. The last bus transfer, identified by the assertion of EOP, indicates the number of valid bytes of this last transfer by driving only the valid FBE# signals. Similarly for Receive cycles, in both 32-bit and 64-bit modes, all associated FBE# signals must be driven low by the peripheral or MAC device, and must identify the number of valid bytes on the last transfer driven with EOP. The IXP1200 Network Processor uses this information to update the RCV_CTL register's Valid Bytes field. Driving fewer than the four or eight FBE#s except for the last transfer with EOP may cause undefined behavior. 2.4 SDRAM, SRAM Units The IXP1200 Network Processor supports two high performance memory units. The SRAM Unit provides fast memory that can be used to store look-up tables. The SDRAM Unit provides lower cost memory for forwarding information and transmit queues. Both units contain features that improve memory bandwidth utilization. 2.4.1 SDRAM Unit The IXP1200 Network Processor provides an SDRAM Unit to access low cost, high bandwidth memory for mass data storage. The StrongARM(R) processor address space allows up to 256 Mbytes of SDRAM to be addressed, although the IXP1200 Network Processor allows only up to 128 Mbytes. The SDRAM interface operates at 81 MHz, providing a peak bandwidth of 648 Mbytes per second. 11 Bus cycles are generated by requests from the PCI Unit including PCI DMA cycles, the StrongARM(R) Core, and the microengines. The SDRAM is operated by commands that are loaded into command queues within the unit. The SDRAM unit decodes the command, reads or writes the data, then deletes the command from the head of the queue. The read and write sources may be SDRAM memory locations, transfer registers, or the transmit and receive FIFOs in the IX Bus Interface Unit. Refer to the IXP1200 Network Processor Hardware Reference Manual for details on how these requests are queued, prioritized, and serviced by the SDRAM Unit. Figure 4 details the major components of the SDRAM Unit. Figure 4: SDRAM Unit Block Diagram Service Service Priority Priority (Arbitration) (Arbitration) Machine Machine & & Registers Registers SDRAM SDRAM up up to to 256 256 MB MB WE#,RAS# WE#,RAS# CAS#, CAS#, DQM DQM Addr[13:0] Addr[13:0] SDRAM SDRAM Pin Pin Interface Interface Data[63:0] Data[63:0] Memory/ Memory/ AMBA AMBA Data Data FIFO FIFO data data AMBA AMBA Bus Bus Interface Interface Logic Logic AMBA[31:0] AMBA[31:0] (from (from Intel(R) (R) ** StrongARM(R) StrongARM Core) Core) SDCLK SDCLK addr addr Command Command Decoder Decoder & & Address Address Generator Generator AMBA AMBA Address Address Rd/Wr Rd/Wr Queue Queue PCI PCI Address Address RD/Wr RD/Wr Queue Queue Microengine Microengine Address Address & & Command Command Queues Queues (High (High Priority, Priority, Even, Even, Odd & Order) Odd & Order) PCI PCI Commands Commands and and Addresses Addresses Microengine Microengine Commands Commands & & Addresses Addresses Microengine Microengine Data Data [63:0] [63:0] ** StrongARM StrongARM is is a a registered registered trademark trademark of of ARM ARM Limited. Limited. ** ARM architecture compatible A7013-01 The SDRAM bus consists of 14 Row/Column address bits, 64 data bits, 1 parity data bit, RAS#, CAS#, Write Enable, Buffer Direction Control, and a synchronous output clock running at one-half the IXP1200 Network Processor core frequency, typically 81 MHz. The PCI, microengines, and StrongARM(R) Core require single byte, word, and longword write capabilities. The SDRAM unit supports this using a read-modify-write technique. As data is written from the PCI or StrongARM(R) Core to SDRAM, a quadword is read from SDRAM. The IXP1200 Network Processor then updates only the bytes that were enabled and writes the entire quadword of data back to SDRAM memory. (Note that the bytes do not have to be consecutive.) These three steps are performed automatically. The SDRAM Unit has parity protection across the 64-bit data. If parity generation and checking is enabled via a control status register, writes will generate parity into the array, and reads will check parity. A Parity error interrupt can be enabled to signal the StrongARM(R) Core. 12 SDRAMs with an access time of 6 ns are required with an Fcore frequency of 162 MHz. 2.4.2 SDRAM Bus Access Behavior * The number of quadwords transferred by the SDRAM Unit is determined by the requesting interface (Core, microengine, or PCI). No speculative cycles are generated. The SDRAM unit may reorder SDRAM accesses for best performance. * Accesses are always Quadword (64-bit) cycles on the SDRAM bus. * Accesses from the StrongARM(R) Core - byte, word and Lword accesses generated from the StrongARM(R) Core are supported. Byte, word, and Lword writes result in Read-Modify-Write cycles to SDRAM memory space. Consecutive Lword writes over the AMBA bus to the same Quadword address are buffered and aggregated into Quadword writes to the SDRAM. Read accesses using the Prefetch Memory supported. Less than 8 bytes can be written when using the byte mask within an instruction, but result in R-M-W cycles. address space allow the SDRAM Unit to prefetch Quadword data to be supplied to the AMBA bus using 32-bit burst cycles. * Accesses from the microengines - the microcode SDRAM instruction defines the number of 64-bit accesses to make, up to 16 Qwords with one microengine command. Only Qword accesses are Table 2: 2.4.3 SDRAM Configurations SDRAM Configurations Total Memory # of Chips Size DRAM Configuration (per bank) Internal Banks Bank Bits RAS Bits CAS Bits 8 Mbytes 4 16 Mbit 512 K x 16-bit 2 1 11 8 16 Mbytes 8 16 Mbit 1 M x 8-bit 2 1 11 9 32 Mbytes 4 64 Mbit 2 M x 16-bit 2 1 13 8 64 Mbytes 8 64 Mbit 4 M x 8-bit 2 1 13 9 32 Mbytes 4 64 Mbit 1 M x 16-bit 4 2 12 8 64 Mbytes 8 64 Mbit 2 M x 8-bit 4 2 12 9 64 Mbytes 4 128 Mbit 2 M x 16-bit 4 2 12 9 128 Mbytes 8 128 Mbit 4 M x 8-bit 4 2 12 10 2.4.4 SRAM Unit The IXP1200 Network Processor provides an SRAM Unit for very high bandwidth memory for storage of lookup tables and other data for the packet processing microengines. The SRAM Unit controls the SRAM (up to 8 Mbytes), BootROM (up to 8 Mbytes) for booting, and the SlowPort for peripheral device access. The I/O signal timing is determined by internal address decodes and configuration registers for the BootROM and SlowPort address regions. The SRAM Unit includes an 8 entry Push/Pop register list for fast queue operations, bit test, set and clear instructions for atomic bit operations, and an 8 entry CAM for Read Locks. The SRAM Unit accessed the SRAM via a 32-bit bus operating at one-half the IXP1200 Network Processor core frequency, typically 81 MHz, which provides a peak bandwidth of 334 Mbytes per second. The SRAM Unit supports both Pipelined Burst and Flowthru SRAM types. The bus is also used to attach BootROM and can be used to interface other peripheral devices such as custom interface logic or MAC management ports. The SRAM interface provides three separate timing domains for the three device types: SRAM, BootROM, and Peripheral (also referred to as SlowPort access). Figure 5 details the major components of the SRAM Unit. 13 Figure 5: SRAM Unit Block Diagram Service Priority (Arbitration) Machine & Registers SCLK SRAM 32 KB to 8 MB PipelinedDCD or Flowthru RD/WR/EN Signals SRAM Pin Interface Memory/ AMBA Data FIFO Addr[18:0] data AMBA Bus Interface Logic Data[31:0] Buffer BootROM 512 KB to 8 MB addr Peripheral Device (i.e., MAC CPU port) AMBA[31:0] (from Intel(R) StrongARM(R) * Core) AMBA Address Rd/Wr Queue Command Decoder & Address Generator Microengine Address & Command Queues (High Priority, Read, Readlock Fail and Order) Microengine Commands & Addresses Microengine Data * StrongARM is a registered trademark of ARM Limited. ** ARM architecture compatible A7014-02 The SRAM bus consists of 19 address bits, 32 data bits, 4 chip enable bits, 8 buffer and read/write control signals, a synchronous output clock (SCLK) running at one-half the IXP1200 Network Processor core frequency, and a synchronous input clock (SACLK). When using Flowthru SRAM types, it is recommended to route the SCLK signal from the SRAMs back to the SACLK input. Routing this trace identically to the DQ data signals will skew the SACLK slightly to track the return data trace propagation delay. When using Pipelined/DCD SRAMs, the SACLK input is not used and may be held inactive with a pulldown to GND to save power. Hardware Reference Manual for details on the prioritization and queues provided for servicing these requests. 2.4.4.1 SRAM Types Supported Pipeline Burst DCD (double cycle deselect) type: 150 MHz, tKQ=3.8 ns*, 3.3 V * may be recharacterized to relax specification to 133 MHz, tKQ=4.2 ns Flowthru type: 94 MHz, tKQmin= 9 ns cycle time, 3.3 V The SRAM Unit receives memory requests from seven sources: the StrongARM(R) Core and each of the six microengines. Refer to the IXP1200 Network Processor Table 3: 14 2.4.4.2 SRAM Configurations SRAM Configurations Total Memory # of Chips (Maximum of 8) Size of SRAM Device Organization 1 Mbytes 8 1 Mbit 32 K x 32-bit 2 Mbytes 8 2 Mbit 64 K x 32-bit 2 Mbytes 8 2 Mbit 128 K x 16-bit 4 Mbytes 8 4 Mbit 128 K x 32-bit 4 Mbytes 8 4 Mbit 256 K x 16-bit 8 Mbytes (maximum) 8 8 Mbit 256 K x 32-bit 2.4.4.3 BootROM Configurations Table 4: BootROM Configurations Total Memory # of Chips (Maximum of 8) Size of Boot ROM Device Organization 512 Kbytes (min) 2 2 Mbit 128 K x 16-bit 2 Mbytes 8 2 Mbit 128 K x 16-bit 4 Mbytes 8 4 Mbit 256 K x 16-bit 6 Mbytes 6 6 Mbit 512 K x 16-bit 8 Mbytes (maximum) 8 8 Mbit 512 K x 16-bit 2.4.4.4 SRAM Bus Access Behavior * The SRAM controller within the IXP1200 Network Processor will never initiate automatic bursting. Bursting is controlled by the requestor StrongARM(R) core or microengine) depending on the type and number of SRAM accesses needed. -- Unlike the StrongARM(R) Core, the microengine microinstruction allows you to perform bit operations within the instruction (Push, Pop, Bit Test and Set, CAM operations, Lock/Unlock, etc.). * Accesses are always Lword 32-bit cycles on the SRAM bus. 2.5 PCI Unit * The IXP1200 Network Processor always drives the address for each data cycle. No external address generation or address advance control to SRAM devices is required. The PCI Unit provides an industry standard 32-bit PCI bus to interface to PCI peripheral devices such as host processors and MAC devices. The PCI Unit supports operating speeds from 33 MHz up to 66 MHz, and is compliant with the PCI Local Bus Specification, Revision 2.1. This unit contains: * Arbitration logic to support up to three PCI bus masters, * Accesses from the StrongARM(R) Core: -- Byte, Word and Lword accesses generated from the StrongARM(R) instructions are supported. -- Bit operations are supported via StrongARM(R) Core accesses to the SRAM Alias Address Space to perform the same operations as a microengine can accomplish implicitly in a microinstruction (Push, Pop, Bit Test and Set, CAM operations, Lock/Unlock, etc.). -- Bit, Byte, and Word writes result in ReadModify-Write cycles. -- Declare memory-mapped I/O as non-cachable to prevent line fill burst cycles, and disable caching and write buffering to ensure I/O device coherency. -- For best performance, use Lword accesses to avoid R-M-W cycles on the SRAM bus that will occur with byte and word accesses. * Accesses from the microengines: -- The microcode SRAM instruction defines the number of 32-bit accesses to make, up to 8 Dwords with one microengine command. * PCI Intelligent I/O (I2O), * Two DMA channels * Four 24-bit timers Refer to the IXP1200 Network Processor Hardware Reference Manual for details on PCI bus behavior for Target and Initiator modes, configuration and register definitions. The PCI interface is specified to operate from 33 MHz up to 66 MHz. Above 33 MHz operation, two PCI devices are supported only, the IXP1200 Network Processor and a second PCI device. To increase the number of PCI devices supported or to add connectors to the bus at the higher PCI bus speeds, a PCI-to-PCI bridge device, such the Intel 21150, 21152, or 21153 is required. Both PCI Initiator and Target cycles are supported. As a target device, the IXP1200 Network Processor responds as a Medium Speed device asserting DEVSEL# two PCI_CLK cycles after FRAME# was asserted. -- Only Bit and Dword accesses are supported. -- Bit write accesses result in R-M-W cycles. 15 2.6 Device Reset The IXP1200 Network Processor can be reset by the following: * Hardware Reset via RESET_IN# pin * Software Reset by StrongARM(R) Core or by PCI device write to the RESET_CSR register * PCI Reset via the PCI_RST# pin * Watchdog Timer expiration Refer to the Hardware Reference Manual for complete details of the internal Reset function logic. 2.6.1 Hardware Initiated Reset The IXP1200 Network Processor provides the RESET_IN# pin so that an external device can reset the IXP1200 Network Processor. Asserting this pin will reset the internal functions as well generate an external reset via the RESET_OUT# pin. Upon power-up, RESET_IN# must remain asserted for 150 ms after VDD and VDDX are stable to properly reset the IXP1200 Network Processor and ensure that the PXTAL clock input and PLL Clock generator are stable. While RESET_IN# is asserted, the processor will perform idle cycles. When RESET_IN# is released, the StrongARM(R) processor will begin execution from address 0. If RESET_IN# is asserted while the StrongARM(R) Core is executing, the current instruction will terminate abnormally, and the on-chip caches, MMU, and write buffer will be disabled. 2.6.2 Software Initiated Reset The StrongARM(R) Core and a device on the PCI Bus can reset specific functions in the IXP1200 Network Processor by writing to the RESET_CSR PCI registers. In most cases, only the individual microengines are reset and the external RESET_OUT# pin will be asserted via this register. The ability to reset the other functions is provided for debugging. The SRAM Unit is always reset when the StrongARM(R) Core is reset. The StrongARM(R) Core and the SRAM unit are held in reset for 5000 system clock cycles to ensure a proper reset. The other functions that can be reset via the RESET_CSR PCI registers will be properly reset when consecutive writes are performed to assert and de-assert the reset. 16 2.6.3 PCI Initiated Reset The IXP1200 Network Processor can be reset by a device on the PCI bus when the IXP1200 Network Processor is not the PCI Central Function device (PCI_CFG[0] = 0) and PCI_RST# is an input. The entire IXP1200 Network Processor is reset during a PCI Initiated Reset. When the IXP1200 Network Processor is assigned as the PCI Central Function device (PCI_CFG[0] = 1), the IXP1200 Network Processor drives PCI_RST# as an output to the other devices on the PCI bus. 2.6.4 Watchdog Timer Initiated Reset The IXP1200 Network Processor provides a watchdog timer that can reset the StrongARM(R) Core. The StrongARM(R) Core should be programmed to reset the watchdog timer periodically to ensure that the timer does not expire. If the watchdog timer expires, it is assumed the StrongARM(R) Core has ceased executing instructions properly. The reset generated by the Watchdog Timer will reset each of the functions in the IXP1200 Network Processor. It does not generate an external reset by asserting the RESET_OUT# pin. SECTION 3 - SIGNAL DESCRIPTION 3.1 Pinout Diagram Figure 6: Pinout Diagram PORTCTL#[3:0] RESET_OUT# Processor Support FPS[2:0] RESET_IN# FCLK FDAT[63:0] FBE#[7:0] PXTAL CINT# Miscellaneous Test SCAN_EN SOP TCK_BYP EOP TSTCLK TXASIS/TXERR RXFAIL FAST_RX1 TCK TMS JTAG TDI TDO IXP1200 (432 Pins) TRST# IX Bus Interface FAST_RX2 RDYCTL#[4:0] RDYBUS[7:0] SOP32 SACLK EOP32 A[18:0] TK_OUT DQ[31:0] TK_IN CE#[3:0] GPIO[3:0] SCLK SOE# SRAM Interface SWE# General Purpose RXD TXD SLOW_WE# Serial Port LOW_EN# HIGH_EN# SLOW_RD# SP_CE# SLOW_EN# MADR[13:0] MDATA[63:0] PARITY SDRAM Interface CBE#[3:0] PAR FRAME# IRDY# TRDY# STOP# DEVSEL# RAS# IDSEL PERR# CAS# SERR# WE# PCI_IRQ# DQM PCI_RST# SDCLK VDD VDDX Power Supply AD[31:0] VDDP1 VSS VSSP1 VDD_REF PCI Interface PCI_CLK PCI_CFN[1:0] REQ#[0] GNT#[0] GNT#[1] REQ#[1] * StrongARM is a registered trademark of ARM Limited. A7007-02 17 3.2 Pin Type Legend Interface, FIFO Bus Interface, General Purpose, Serial Port, and PCI Interface. Table 5 defines the signal type abbreviations used in the Pin Description section. The IXP1200 Network Processor signals are categorized into one of several groups: Processor Support, Miscellaneous/Test, JTAG, SRAM Interface, SDRAM Table 5: Signal Type Abbreviations Signal Type Description I Standard input only. There are 2 types of inputs (I1,I2) for the IXP1200 Network Processor. Refer to Table 27 and Table 28 for more information. O Standard output only. There are 4 types of outputs (O1,O2,O3,O4) for the IXP1200 Network Processor. Refer to Table 27 and Table 28 for more information. TS Tri-state output. STS Sustained tri-state. Active low signal owned and driven by one and only one agent at a time. The agent that drives this pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving this signal any sooner than one clock after the previous owner tri-states it. A pullup is required to sustain the inactive state until another agent drives it, and it must be provided by the central resource (that is, on a PC board). P Power Supply. OD Standard open drain allows multiple devices to share as a wire-OR. A pullup is required to sustain the inactive state until another agent drives it, and it must be provided by the central resource. 3.3 Pin Description, Grouped by Function 3.3.1 Processor Support Pins Table 6: Processor Support Pins Processor Support Signal Names Pin # Type Total Pin Descriptions PXTAL B4 I1 1 Input connection for system oscillator. Typically 3.686 MHz. Drives internal PLL clock generator. CINT# Y28 I1 1 External interrupt input to StrongARM(R) Core. IXP1200 Network Processor System Reset Output. Asserted when: RESET_OUT# A5 O4 1 * RESET_IN# is asserted. * PCI arbiter function disabled (PCI_CFN[0]=0) and PCI_RST# is asserted. * A soft reset is initiated. RESET_IN# Totals: 18 C6 I1 1 4 IXP1200 Network Processor System Reset Input. If asserted, the IXP1200 Network Processor will perform a system reset and will assert RESET_OUT#. If PCI Central Function is enabled (PCI_CFN[0]=1), PCI_RST# output will also be asserted. 3.3.2 SRAM Interface Pins Table 7: SRAM Interface Pins (Sheet 1 of 2) SRAM Interface Signal Names Pin # Type Total Pin Descriptions O4 19 Address outputs I1/O4 32 32 Bidirectional data signals O4 4 SRAM bus chip enable outputs. A[18:0] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] A28 B28 D27 E28 D30 D31 E29 F28 E30 E31 F29 F30 F31 G29 H28 G30 G31 H29 J28 [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] H30 J30 J31 K29 L28 K30 K31 L29 M28 L30 L31 M29 N28 M30 M31 N29 N30 N31 P29 R28 P30 R29 R30 R31 T28 T29 T30 T31 U29 U28 V30 V29 [3] [2] [1] [0] A26 B26 C26 A27 DQ[31:0] CE#[3:0] 19 Table 7: SRAM Interface Pins (Sheet 2 of 2) SRAM Interface Signal Names Pin # Type Total SCLK W31 O3 1 SRAM Clock - Frequency is one half the speed of the core clock (1/2 * Fcore). Pin Descriptions SACLK B24 I1 1 SRAM clock input, used to compensate for skew in data path when using Flowthru SRAMs. Must be connected to SCLK when using Flowthru devices. Not used with Pipelined devices and should be pulled low. SOE# W30 O4 1 SRAM output enable. SWE# Y30 O4 1 SRAM write enable. SLOW_WE# W28 O4 1 Slow asynchronous interface write enable (Flash, ROM or MAC). LOW_EN# D26 O4 1 Low order SRAM bank enable and buffer direction select for slow interface. When used as the buffer direction select: 0 = write and 1 = read. HIGH_EN# C27 O4 1 High order SRAM bank enable. SLOW_EN# Y29 O4 1 Slow device enable: 0 = Slow device (BootROM or SlowPort), 1=SRAM. SP_CE# W29 O4 1 Slow asynchronous interface chip enable output. SLOW_RD# Y31 O4 1 Slow asynchronous interface read enable output. Totals: 20 65 3.3.3 SDRAM Interface Pins Table 8: SDRAM Interface Pins (Sheet 1 of 2) SDRAM Interface Signal Names Pin # Type Total Pin Descriptions O4 14 Multiplexed Row/Column address outputs. I1/O1 64 64 Bidirectional data signals. MADR[13:0] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] AD1 AC3 AC2 AC1 AB3 AA4 AB2 AB1 AA3 AA1 Y3 W4 Y2 Y1 MDATA[63:0] [63] [62] [61] [60] [59] [58] [57] [56] [55] [54] [53] [52] [51] [50] [49] [48] [47] [46] [45] [44] [43] [42] [41] [40] [39] [38] [37] [36] [35] [34] [33] [32] [31] [30] [29] [28] [27] [26] AH6 AJ5 AL4 AK4 AH5 AH2 AH1 AG3 AF4 AG2 AG1 AF3 AF2 AF1 AE3 AD4 AE2 AE1 U4 V2 U3 U2 U1 T4 T3 T2 T1 R3 R4 P2 P3 N1 N2 N3 M1 M2 N4 M3 21 Table 8: SDRAM Interface Pins (Sheet 2 of 2) SDRAM Interface Signal Names [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Type Total Pin Descriptions L1 L2 M4 L3 K1 K3 J1 J2 J3 H1 H2 J4 H3 G1 G2 H4 G3 F1 F2 F3 E1 E2 F4 E3 D1 D2 Row Address Select output. RAS# W2 O4 1 CAS# W3 O4 1 Column Address Select output. WE# W1 O4 1 Write Enable output. DQM V3 O4 1 Data Buffer Direction Control output. PARITY AK5 I1/O1 1 Bidirectional Data Parity bit. Pullup if not used. SDCLK AD2 O3 1 SDRAM Clock output. Frequency is one half the speed of the core clock (1/2 * Fcore). Totals: 22 Pin # 84 Precharge cycle indicated if asserted with WE#. 3.3.4 IX Bus Interface Pins Table 9: IX Bus Interface Pins (Sheet 1 of 4) IX Bus Signal Names FCLK Pin # AB30 Type I1 Total 1 IX Bus Clock input. All IX Bus transfers are synchronized to this clock. Typical operating frequency 33 MHz - 66 MHz. Port Control outputs. Used to select the transmit and/or receive mode for IX Bus devices, typically MAC devices. PORTCTL#[3:0] [3] [2] [1] [0] Pin Descriptions AC30 AC31 AB29 AA28 O1/TS 4 In 64-bit bidirectional IX Bus mode, this is a 4-bit bus used to select both transmit and receive modes. In 32-bit unidirectional IX Bus mode, bits [1:0] are used to select the receive port and bits [3:2] are used to select the transmit port. In a shared IX Bus system, these pins will be tri-stated when the current master yields the IX Bus. MAC Port Select outputs. In 64-bit bidirectional IX Bus mode, it is used to select one of eight MAC ports from a MAC device. FPS[2:0] [2] AC29 [1] AD31 [0] AD30 O4/TS 3 In 32-bit unidirectional IX Bus mode, it is used to select one of eight MAC receive ports from the selected MAC device (GPIO[3:1] used for transmit port select). See IX Bus control signal decode tables. In a shared IX Bus system, these pins will be tri-stated when the current master yields the IX Bus. FDAT[63:0] [63] [62] [61] [60] [59] [58] [57] [56] [55] [54] [53] [52] [51] [50] [49] [48] [47] [46] [45] [44] [43] [42] [41] [40] [39] [38] [37] [36] [35] [34] [33] [32] [31] AC28 AD29 AE31 AE30 AF31 AF30 AF29 AG31 AG30 AF28 AG29 AH31 AH30 AH27 AK28 AL28 AJ27 AH26 AK27 AL27 AJ26 AK26 AL26 AJ25 AH24 AK25 AL25 AJ24 AH23 AK24 AL24 AJ23 AK23 IX Data Bus. One 64 bit bus in bidirectional IX Bus mode. I2/O2/ 64 TS Two 32-bit buses in unidirectional IX Bus mode where bits [63:32] are used for Transmit Data output and [31:0] are used for Receive Data inputs. In a shared IX Bus system, these pins will be tri-stated when the current master yields the IX Bus. 23 Table 9: IX Bus Interface Pins (Sheet 2 of 4) IX Bus Signal Names Pin # [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] AL23 AJ22 AH21 AK22 AL22 AJ21 AH20 AK21 AL21 AJ20 AH19 AK20 AL20 AJ19 AK19 AL19 AJ18 AH17 AK18 AJ17 AK17 AL17 AH16 AJ16 AK16 AL16 AJ15 AH15 AK14 AJ14 AL13 [7] [6] [5] [4] [3] [2] [1] [0] AK13 AJ13 AL12 AK12 AH13 AJ12 AL11 AK11 Type Total FBE#[7:0] Pin Descriptions Bidirectional Byte Enables. One 8-bit bus in 64-bit bidirectional IX Bus mode. I2/O2/ 8 TS Two 4-bit buses in 32-bit unidirectional IX Bus mode where bits [7:4] are used for Transmit Byte Enables and [3:0] used for Receive Byte Enables. In a shared IX Bus system, these pins will be tri-stated when the current master yields the IX Bus. Transmit As Is/Transmit Error output. When asserted on the first data transfer of a transmit packet, indicates to the MAC not to pad or append CRC bytes to the packet, even if the ports were programmed to do so. TXASIS/TXERR AL10 O4/TS 1 When asserted on the final data transfer along with EOP, the MAC should transmit the packet with an MII error (if programmed) and a symbol error. In a shared IX Bus system, these pins will be tri-stated when the current master yields the IX Bus. RXFAIL AK10 I1/O1/ TS Receive Packet Failure. As Input, asserted by a MAC device if a packet was received with errors. Mimics the behavior of EOP to terminate an IX Bus cycle. 1 As Output, driven when no receive cycle in-progress. In a shared IX Bus system, these pins will be tri-stated when the current master yields the IX Bus. 24 FAST_RX1 AH11 I1 1 Ready Input from Fast MAC port 1 (i.e. Gigabit port). FAST_RX2 AJ10 I1 1 Ready Input from Fast MAC port 2 (i.e. Gigabit port). Table 9: IX Bus Interface Pins (Sheet 3 of 4) IX Bus Signal Names Pin # Type Total Pin Descriptions Bidirectional Ready Control signals. In 64-bit Bidirectional IX Bus Mode: * 1-2 MAC mode: Bits [3:0] are used to enable the transmit or receive FIFO Ready Flags and bit [4] is used as a flow control enable for MAC 2 (GPIO[0] is used as a flow control enable for MAC 1). * 3+ MAC mode: The transmit and receive FIFO Ready, the flow control, and inter-processor communication enables are decoded from all five bits. RDYCTL#[4:0] [4] [3] [2] [1] [0] AK6 AL6 AJ7 AH8 AK7 I1/O4/ 5 TS * In a shared IX Bus system the IXP1200 Network Processor Ready Bus Master drives this bus. IXP1200 Network Processor slave devices snoop these pins as inputs. In 32-bit Unidirectional Mode: * 1-2 MAC mode: Bits [3:0] are used to enable the transmit or receive FIFO Ready Flags and bit [4] is used as a flow control enable for MAC 1. GPIO[0] is used as a flow control enable for MAC 0. * 3+ MAC mode: Bits [3:0] are used to enable the FIFO Ready Flags, enable shared IX Bus communications, and enable flow control inputs. Bit [4] is used as an active low enable for an external decoder for the PORTCTL[1:0] signals. RDYBUS[7:0] [7] [6] [5] [4] [3] [2] [1] [0] AL9 AK9 AJ9 AL8 AK8 AH9 AJ8 AL7 Bidirectional Ready Bus data. I1/O4 8 * Inputs the Transmit and Receive Ready Flags from IX Bus devices. * Outputs flow control data to IX Bus devices. * Shared IX Bus I/O data bus. In a shared IX Bus system, the Ready Bus Master drives this bus and the Slave snoops. Start of Packet indication. SOP AH12 I1/O4/ 1 TS * Input in 32-bit unidirectional IX Bus mode. * Input/Output in 64-bit bidirectional IX Bus mode. * In a shared IX Bus system, this pin will be tri-stated when the current master yields the IX Bus. End of Packet indication. EOP AJ11 I1/O4/ 1 TS * Input in 32-bit unidirectional IX Bus mode. * Input/Output in 64-bit bidirectional IX Bus mode. * In a shared IX Bus system, this pin will be tri-stated when the current master yields the IX Bus. Transmit Start Of Packet indication. * Output in 32-bit unidirectional IX Bus modes. SOP32 AJ6 O4 1 * 64-bit bidirectional 3+ MAC mode, is IX Bus Request output indication. * 64-bit bidirectional 1-2 MAC mode, not used in and should be left unconnected. * In shared IX Bus mode, used as IX Bus Request output. 25 Table 9: IX Bus Interface Pins (Sheet 4 of 4) IX Bus Signal Names Pin # Type Total Pin Descriptions Transmit End Of Packet. * 32-bit unidirectional IX Bus modes, Transmit End Of Packet indication. EOP32 AL5 I1/O4 1 * 64-bit bidirectional IX Bus modes, single-chip operation, this input should be pulled high. * In shared IX Bus mode, as an input indicates IX Bus Request Pending from another device. Token Output. TK_OUT AA29 O1 1 Used to pass ownership of the IX Bus in a shared IX Bus system in 64-bit bidirectional IX Bus mode. In 32-bit unidirectional mode this bit is unused and should be left unconnected. Token Input. TK_IN AB31 I1 1 64-bit bidirectional IX Bus Mode: If asserted, this device has been given ownership of the IX Bus in a shared IX Bus system. During Reset, used to configure the device as Initial IX Bus Master. 1= device is Initial Master, 0= device is slave. In 32-bit unidirectional mode this input is not used and should be pulled high. Totals: 103 3.3.5 General Purpose I/Os Table 10: General Purpose I/Os General Purpose I/O Signal Names Pin # Type Total Pin Descriptions Bidirectional General Purpose pins. GPIO[3:1] [3] A25 [2] B25 [1] D24 I1/O4 3 Bidirectional IX Bus mode: Accessible by StrongARM(R) Core. Configurable as Input or Output. Unidirectional IX Bus mode: Dedicated to IX Bus Interface, used as an output for Transmit Port selects [2:0]. Bidirectional General Purpose I/O pin. 1-2 MAC mode (Uni or Bidirectional mode): Dedicated to the FBI unit. Is output for Flow Control indication to MAC 0. GPIO[0] C25 I1/O4 1 3+ MAC 64-bit Bidirectional IX Bus mode: Accessible to the StrongARM(R) Core. Configurable as Input or Output. 3+ MAC 32-bit Unidirectional IX Bus mode: Output dedicated to the FBI Unit. Active low enable for an external PORTCTL[3:2] decoder. Totals: 26 4 3.3.6 Serial Port (UART) Pins Table 11: Serial Port (UART) Pins Serial Port (UART) Signal Names Pin # Type Total RXD D23 I1 1 UART Receive data. TXD C24 O1 1 UART Transmit data. Totals: Pin Descriptions 2 3.3.7 PCI Interface Pins Table 12: PCI Interface Pins (Sheet 1 of 3) PCI Interface Signal Names Pin # Type Total Pin Descriptions AD[31:0] [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] B20 A20 C19 C18 B18 D17 C17 A16 D16 A15 B15 C15 B14 D15 C14 A13 A10 B10 D11 C10 A9 B9 C9 A8 D9 C8 A7 B7 D8 C7 A6 B6 [3] [2] [1] [0] B16 B13 C11 B8 32 Address/data. These signals are multiplexed address and data bus. The IXP1200 Network Processor receives addresses as target and drives addresses as master. It receives write data and drives read data as target. It drives write data and receives read data as master. I2/ O2/ TS 4 Command byte enables. These signals are multiplexed command and byte enable signals. The IXP1200 Network Processor receives commands as target and drives commands as master. It receives byte enables as target and drives byte enables as master. I2/ O2/ TS 1 Parity. This signal carries even parity for AD and CBE# pins. It has the same receive and drive characteristics as the address and data bus, except that it is one PCI cycle later. I2/ O2/ TS CBE#[3:0] PAR D12 27 Table 12: PCI Interface Pins (Sheet 2 of 3) PCI Interface Signal Names Pin # Type Total Pin Descriptions FRAME# C13 I2/ O2/ STS 1 FRAME# indicates the beginning and duration of an access. The IXP1200 Network Processor receives as target and drives as master. IRDY# A12 I2/ O2/ STS 1 Initiator ready. Indicates the master's ability to complete the current data phase of the transaction. The IXP1200 Network Processor receives as target and drives as master. TRDY# B12 I2/ O2/ STS 1 Target ready. Indicates the target's ability to complete the current data phase of the transaction. The IXP1200 Network Processor drives as target and receives as master. STOP# C12 I2/ O2/ STS 1 Stop. Indicates that the target is requesting the master to stop the current transaction. The IXP1200 Network Processor drives as target and receives as master. DEVSEL# D13 I2/ O2/ STS 1 Device Select. Indicates that the target has decoded its address as the target of the current access. The IXP1200 Network Processor drives as target and receives as initiator. IDSEL C16 I2 1 Initialization Device Select. Used as Chip Select during PCI Configuration Space read and write transactions. PERR# A11 I2/O2/ STS 1 Parity error. Used to report data parity errors. The IXP1200 Network Processor asserts this when it receives bad data parity as target of a write or master of a read. System Error. SERR# B11 I2/ O2/ OD 1 As an input, it can cause an interrupt to the StrongARM(R) Core if the IXP1200 Network Processor is selected for PCI Central Function support (PCI_CFN[0]=1). As an output it can be asserted by the IXP1200 Network Processor by writing the SERR bit in the PCI control register, or in response to a PCI address parity error when not providing PCI Central Function support (PCI_CFN[0]=0). PCI Interrupt Request. PCI_IRQ# A22 I2/O2/ OD 1 As output, used to interrupt the PCI Host Processor. It is asserted when there is a doorbell set or there are messages on the I2O outbound post list. This is usually connected to INTA# on the PCI bus. As Input, It is asserted when there is a doorbell set or there are messages on the I 2 O outbound post list. PCI Reset. PCI_RST# PCI_CLK 28 C21 D20 I2/ O2/ TS 1 I2 1 * When providing PCI Central Function support (PCI_CFN[0]=1), PCI _RST# is an output controlled by the StrongARM(R) Core. Used to reset the PCI Bus. * When not providing PCI Central Function (PCI_CFN[0]=0), PCI_RST# is an input, and when asserted resets the IXP1200 Network Processor StrongARM(R) Core, all registers, all transaction queues, and all PCI related state. PCI Clock input. Reference for PCI signals and internal operations. PCI clock is typically 33 or 66 MHz. Table 12: PCI Interface Pins (Sheet 3 of 3) PCI Interface Signal Names Pin # Type Total Pin Descriptions PCI Central Function select input. When PCI_CFN[0]=1, the IXP1200 Network Processor provides the PCI Central Function support and: * PCI_RST# is an output asserted by the PCI unit when initiated by the StrongARM(R) Core. PCI_CFN[0] A24 I2 1 * IXP1200 Network Processor provides bus parking during reset. * SERR# is an input, when asserted will generate an interrupt to the StrongARM(R) Core. When PCI_CFN[0]=0, PCI central function is disabled and: * PCI_RST# is an input asserted by the Host processor. * The IXP1200 Network Processor does not provide bus parking during reset. PCI Arbitration Enable, PCI_CFN[1] PCI_CFN[1] C23 I2 1 When PCI_CFN[1]=1, enables the internal PCI arbiter to perform bus arbitration. When PCI_CFN[1]=0, disables internal PCI bus arbiter. PCI Bus Master Grant 1. GNT#[0] B21 I2/O2 1 Internal PCI arbiter is enabled (PCI_CFN[1] = 1): Pin is an output to grant a PCI device 1 control of the PCI bus. (The IXP1200 Network Processor is PCI device 0 in this case) Internal PCI arbiter is disabled (PCI_CFN[1] = 0): Pin is an input that indicates that the IXP1200 Network Processor can assert FRAME# and become the bus master. If the IXP1200 Network Processor is idle when GNT#[0] is asserted, it parks the PCI bus. PCI Bus Master Request 1. REQ#[0] A21 I2/O2 1 Internal PCI arbiter is enabled (PCI_CFN[1] = 1): Pin is an input indicating an external PCI device is requesting use of the PCI bus. Internal PCI arbiter is disabled (PCI_CFN[1] = 0): Pin is an output indicating that the IXP1200 Network Processor is requesting use of the PCI bus. PCI Bus Master Grant 2. GNT#[1] C20 I2/O2 1 Internal PCI arbiter is enabled (PCI_CFN[1] = 1): Pin is an output to grant a PCI device 2 control of the PCI bus (The IXP1200 Network Processor is PCI device 0 in this case.) When Internal PCI arbiter is disabled (PCI_CNF[1]=0, GNT#[1] should be connected to GND through a pulldown resistor of 10 KOhms. PCI Bus Master Request 2. REQ#[1] D19 I2/O2 1 Internal PCI arbiter is enabled (PCI_CFN[1] = 0): This input indicates that PCI device 2 is requesting to take control of the PCI bus. When Internal PCI arbiter is disabled (PCI_CFN[1] = 0), REQ#[1] is undefined and should be tied to VDDX through a pullup resistor of 10 KOhms. Totals: 54 29 3.3.8 Power Supply Pins Table 13: Power Supply Pins Supply Signal Names Pin # VDD Type Total P 17 Pin Descriptions IXP1200 Network Processor Core supply (2 V). A19, B19, B27, H31, J29, K2, L4, Y4, AA2, AA30, AA31, AC4, AD3, AD28, AE29, AG4, AG28 Total VDD pins 17 VDDX P 40 IXP1200 Network Processor I/O supply (3.3 V). A1, A31,B2, B30, C3, C29, D4, D7, D10, D14, D18, D22, D25, D28, G4, G28, K4, K28, P4, P28, V4, V28, AB4, AB28, AE4, AE28, AH4, AH7, AH10, AH14, AH18, AH22, AH25, AH28, AJ3, AJ29, AK2, AK30, AL1, AL31 Total VDDX pins 40 VDD_REF E4 P 1 IXP1200 Network Processor 3.3 V reference - used to bias the ESD circuitry Can be tied directly to VDDX external to chip. VSSP1 A4 P 1 IXP1200 Network Processor PLL ground Can be tied directly to VSS external to chip. VDDP1 D5 P 1 IXP1200 Network Processor PLL supply (2 V) typical. Can be tied directly to VDD external to chip. Total VSS 3 P 48 IXP1200 Network Processor ground. A2, A3, A14, A17, A18, A29, A30, B1, B3, B17, B29, B31, C1, C2, C4, C28, C30, C31, D3, D29, P1, P31, R1, R2, U30, U31, V1, V31, AH3, AH29, AJ1, AJ2, AJ4, AJ28, AJ30, AJ31, AK1, AK3, AK15, AK29, AK31, AL2, AL3, AL14, AL15, AL18, AL29, AL30 30 Total VSS pins 48 Total Power Supply Pins 108 3.3.9 JTAG Interface Pins Table 14: JTAG Interface Pins JTAG Interface Pin Name Pin # Type Total TCK A23 I1 1 Test Interface reference clock. This clock times all the transfers on the JTAG test interface. TMS C22 I1 1 Test Interface mode select. Causes state transitions on the test access port (TAP) controller. TDI B22 I1 1 Test Interface data input. The serial input through which JTAG instructions and test data enter the JTAG interface. TDO D21 O1 1 Test Interface data output. The serial output through which test instruction and data from the test logic leave the IXP1200 Network Processor. TRST# B23 I1 1 Test Interface RESET. When asserted low, the TAP controller is asynchronously forced to enter a reset state, and disables the JTAG port. This pin must be driven or held low to achieve normal device operation. Totals: Pin Description 5 3.3.10 Miscellaneous Test Pins Table 15: Miscellaneous Test Pins Processor Support Signal Names Pin # Type Total SCAN_EN C5 I1 1 For test purposes only. Used to enable internal scan chains for chip testing. This pin should be connected to ground through a pulldown resistor. TCK_BYP D6 I1 1 For test purposes only. Bypass PPL for Test/debug. TSTCLK B5 I1 1 For test purposes only. Used as clock input when bypassing the internal PPL clock generator. For Normal operation, this pin should be connected to ground through a 10 KOhm pulldown resistor. Totals: Pin Descriptions 3 3.3.11 Pin Usage Summary Table 16: Pin Usage Summary Type Quantity Inputs 21 Outputs 68 Bidirectional 235 Total Signal 324 Power 108 Overall Totals: 432 31 3.4 Pin/Signal List Table 17: Pin Table in Pin Order (Sheet 1 of 4) Pin Number 32 Signal Name Pin Number Signal Name Pin Number C1 Signal Name A1 VDDX B1 VSS VSS A2 VSS B2 VDDX C2 VSS A3 VSS B3 VSS C3 VDDX A4 VSSP1 B4 PXTAL C4 VSS A5 RESET_OUT# B5 TSTCLK C5 SCAN_EN A6 AD[1] B6 AD[0] C6 RESET_IN# A7 AD[5] B7 AD[4] C7 AD[2] A8 AD[8] B8 CBE#[0] C8 AD[6] A9 AD[11] B9 AD[10] C9 AD[9] A10 AD[15] B10 AD[14] C10 AD[12] A11 PERR# B11 SERR# C11 CBE#[1] A12 IRDY# B12 TRDY# C12 STOP# A13 AD[16] B13 CBE#[2] C13 FRAME# A14 VSS B14 AD[19] C14 AD[17] A15 AD[22] B15 AD[21] C15 AD[20] A16 AD[24] B16 CBE#[3] C16 IDSEL A17 VSS B17 VSS C17 AD[25] A18 VSS B18 AD[27] C18 AD[28] A19 VDD B19 VDD C19 AD[29] A20 AD[30] B20 AD[31] C20 GNT#[1] A21 REQ#[0] B21 GNT#[0] C21 PCI_RST# A22 PCI_IRQ# B22 TDI C22 TMS A23 TCK B23 TRST# C23 PCI_CFN[1] A24 PCI_CFN[0] B24 SACLK C24 TXD A25 GPIO[3] B25 GPIO[2] C25 GPIO[0] A26 CE#[3] B26 CE#[2] C26 CE#[1] A27 CE#[0] B27 VDD C27 HIGH_EN# A28 A[18] B28 A[17] C28 VSS A29 VSS B29 VSS C29 VDDX A30 VSS B30 VDDX C30 VSS A31 VDDX B31 VSS C31 VSS D1 MDATA[1] E1 MDATA[5] J1 MDATA[19] D2 MDATA[0] E2 MDATA[4] J2 MDATA[18] D3 VSS E3 MDATA[2] J3 MDATA[17] D4 VDDX E4 VDD_REF J4 MDATA[14] D5 VDDP1 E28 A[15] J28 A[0] Table 17: Pin Table in Pin Order (Sheet 2 of 4) Pin Number Signal Name Pin Number Signal Name Pin Number Signal Name D6 TCK_BYP E29 A[12] J29 VDD D7 VDDX E30 A[10] J30 DQ[30] D8 AD[3] E31 A[9] J31 DQ[29] D9 AD[7] F1 MDATA[8] K1 MDATA[21] D10 VDDX F2 MDATA[7] K2 VDD D11 AD[13] F3 MDATA[6] K3 MDATA[20] D12 PAR F4 MDATA[3] K4 VDDX D13 DEVSEL# F28 A[11] K28 VDDX D14 VDDX F29 A[8] K29 DQ[28] D15 AD[18] F30 A[7] K30 DQ[26] D16 AD[23] F31 A[6] K31 DQ[25] D17 AD[26] G1 MDATA[12] L1 MDATA[25] D18 VDDX G2 MDATA[11] L2 MDATA[24] D19 REQ#[1] G3 MDATA[9] L3 MDATA[22] D20 PCI_CLK G4 VDDX L4 VDD D21 TDO G28 VDDX L28 DQ[27] D22 VDDX G29 A[5] L29 DQ[24] D23 RXD G30 A[3] L30 DQ[22] D24 GPIO[1] G31 A[2] L31 DQ[21] D25 VDDX H1 MDATA[16] M1 MDATA[29] D26 LOW_EN# H2 MDATA[15] M2 MDATA[28] D27 A[16] H3 MDATA[13] M3 MDATA[26] D28 VDDX H4 MDATA[10] M4 MDATA[23] D29 VSS H28 A[4] M28 DQ[23] D30 A[14] H29 A[1] M29 DQ[20] D31 A[13] H30 DQ[31] M30 DQ[18] H31 VDD M31 DQ[17] N1 MDATA[32] U1 MDATA[41] AA1 MADR[4] N2 MDATA[31] U2 MDATA[42] AA2 VDD N3 MDATA[30] U3 MDATA[43] AA3 MADR[5] N4 MDATA[27] U4 MDATA[45] AA4 MADR[8] N28 DQ[19] U28 DQ[2] AA28 PORTCTL#[0] N29 DQ[16] U29 DQ[3] AA29 TK_OUT N30 DQ[15] U30 VSS AA30 VDD N31 DQ[14] U31 VSS AA31 VDD P1 VSS V1 VSS AB1 MADR[6] P2 MDATA[34] V2 MDATA[44] AB2 MADR[7] P3 MDATA[33] V3 DQM AB3 MADR[9] 33 Table 17: Pin Table in Pin Order (Sheet 3 of 4) Pin Number 34 Signal Name Pin Number Signal Name Pin Number Signal Name P4 VDDX V4 VDDX AB4 VDDX P28 VDDX V28 VDDX AB28 VDDX P29 DQ[13] V29 DQ[0] AB29 PORTCTL#[1] P30 DQ[11] V30 DQ[1] AB30 FCLK P31 VSS V31 VSS AB31 TK_IN R1 VSS W1 WE# AC1 MADR[10] R2 VSS W2 RAS# AC2 MADR[11] R3 MDATA[36] W3 CAS# AC3 MADR[12] R4 MDATA[35] W4 MADR[2] AC4 VDD R28 DQ[12] W28 SLOW_WE# AC28 FDAT[63] R29 DQ[10] W29 SP_CE# AC29 FPS[2] R30 DQ[9] W30 SOE# AC30 PORTCTL#[3] R31 DQ[8] W31 SCLK AC31 PORTCTL#[2] T1 MDATA[37] Y1 MADR[0] AD1 MADR[13] T2 MDATA[38] Y2 MADR[1] AD2 SDCLK T3 MDATA[39] Y3 MADR[3] AD3 VDD T4 MDATA[40] Y4 VDD AD4 MDATA[48] T28 DQ[7] Y28 CINT# AD28 VDD T29 DQ[6] Y29 SLOW_EN# AD29 FDAT[62] T30 DQ[5] Y30 SWE# AD30 FPS[0] T31 DQ[4] Y31 SLOW_RD# AD31 FPS[1] AE1 MDATA[46] AH9 RDYBUS[2] AJ10 FAST_RX2 AE2 MDATA[47] AH10 VDDX AJ11 EOP AE3 MDATA[49] AH11 FAST_RX1 AJ12 FBE#[2] AE4 VDDX AH12 SOP AJ13 FBE#[6] AE28 VDDX AH13 FBE#[3] AJ14 FDAT[1] AE29 VDD AH14 VDDX AJ15 FDAT[4] AE30 FDAT[60] AH15 FDAT[3] AJ16 FDAT[7] AE31 FDAT[61] AH16 FDAT[8] AJ17 FDAT[11] AF1 MDATA[50] AH17 FDAT[13] AJ18 FDAT[14] AF2 MDATA[51] AH18 VDDX AJ19 FDAT[17] AF3 MDATA[52] AH19 FDAT[20] AJ20 FDAT[21] AF4 MDATA[55] AH20 FDAT[24] AJ21 FDAT[25] AF28 FDAT[54] AH21 FDAT[28] AJ22 FDAT[29] AF29 FDAT[57] AH22 VDDX AJ23 FDAT[32] AF30 FDAT[58] AH23 FDAT[35] AJ24 FDAT[36] AF31 FDAT[59] AH24 FDAT[39] AJ25 FDAT[40] AG1 MDATA[53] AH25 VDDX AJ26 FDAT[43] Table 17: Pin Table in Pin Order (Sheet 4 of 4) Pin Number Signal Name Pin Number Signal Name Pin Number Signal Name AG2 MDATA[54] AH26 FDAT[46] AJ27 FDAT[47] AG3 MDATA[56] AH27 FDAT[50] AJ28 VSS AG4 VDD AH28 VDDX AJ29 VDDX AG28 VDD AH29 VSS AJ30 VSS AG29 FDAT[53] AH30 FDAT[51] AJ31 VSS AG30 FDAT[55] AH31 FDAT[52] AK1 VSS AG31 FDAT[56] AJ1 VSS AK2 VDDX AH1 MDATA[57] AJ2 VSS AK3 VSS AH2 MDATA[58] AJ3 VDDX AK4 MDATA[60] AH3 VSS AJ4 VSS AK5 PARITY AH4 VDDX AJ5 MDATA[62] AK6 RDYCTL#[4] AH5 MDATA[59] AJ6 SOP32 AK7 RDYCTL#[0] AH6 MDATA[63] AJ7 RDYCTL#[2] AK8 RDYBUS[3] AH7 VDDX AJ8 RDYBUS[1] AK9 RDYBUS[6] AH8 RDYCTL#[1] AJ9 RDYBUS[5] AK10 RXFAIL AK11 FBE#[0] AL1 VDDX AL22 FDAT[26] AK12 FBE#[4] AL2 VSS AL23 FDAT[30] AK13 FBE#[7] AL3 VSS AL24 FDAT[33] AK14 FDAT[2] AL4 MDATA[61] AL25 FDAT[37] AK15 VSS AL5 EOP32 AL26 FDAT[41] AK16 FDAT[6] AL6 RDYCTL#[3] AL27 FDAT[44] AK17 FDAT[10] AL7 RDYBUS[0] AL28 FDAT[48] AK18 FDAT[12] AL8 RDYBUS[4] AL29 VSS AK19 FDAT[16] AL9 RDYBUS[7] AL30 VSS AK20 FDAT[19] AL10 TXASIS AL31 VDDX AK21 FDAT[23] AL11 FBE#[1] AK22 FDAT[27] AL12 FBE#[5] AK23 FDAT[31] AL13 FDAT[0] AK24 FDAT[34] AL14 VSS AK25 FDAT[38] AL15 VSS AK26 FDAT[42] AL16 FDAT[5] AK27 FDAT[45] AL17 FDAT[9] AK28 FDAT[49] AL18 VSS AK29 VSS AL19 FDAT[15] AK30 VDDX AL20 FDAT[18] AK31 VSS AL21 FDAT[22] 35 3.5 Signals Listed in Alphabetical Order Table 18: Pin Table in Alphabetical Order (Sheet 1 of 4) Signal Name 36 Pin Number Signal Name Pin Number Signal Name Pin Number A[0] J28 FDAT[42] AK26 RDYCTL#[4] AK6 A[1] H29 FDAT[43] AJ26 REQ#[0] A21 A[10] E30 FDAT[44] AL27 REQ#[1] D19 A[11] F28 FDAT[45] AK27 RESET_IN# C6 A[12] E29 FDAT[46] AH26 RESET_OUT# A5 A[13] D31 FDAT[47] AJ27 RXD D23 A[14] D30 FDAT[48] AL28 RXFAIL AK10 A[15] E28 FDAT[49] AK28 SACLK B24 A[16] D27 FDAT[5] AL16 SCAN_EN C5 A[17] B28 FDAT[50] AH27 SCLK W31 A[18] A28 FDAT[51] AH30 SDCLK AD2 A[2] G31 FDAT[52] AH31 SERR# B11 A[3] G30 FDAT[53] AG29 SLOW_EN# Y29 A[4] H28 FDAT[54] AF28 SLOW_RD# Y31 A[5] G29 FDAT[55] AG30 SLOW_WE# W28 A[6] F31 FDAT[56] AG31 SOE# W30 A[7] F30 FDAT[57] AF29 SOP AH12 A[8] F29 FDAT[58] AF30 SOP32 AJ6 A[9] E31 FDAT[59] AF31 SP_CE# W29 AD[0] B6 FDAT[6] AK16 STOP# C12 AD[1] A6 FDAT[60] AE30 SWE# Y30 AD[10] B9 FDAT[61] AE31 TCK A23 AD[11] A9 FDAT[62] AD29 TCK_BYP D6 AD[12] C10 FDAT[63] AC28 TDI B22 AD[13] D11 FDAT[7] AJ16 TDO D21 AD[14] B10 FDAT[8] AH16 TK_IN AB31 AD[15] A10 FDAT[9] AL17 TK_OUT AA29 AD[16] A13 FPS[0] AD30 TMS C22 AD[17] C14 FPS[1] AD31 TRDY# B12 AD[18] D15 FPS[2] AC29 TRST# B23 AD[19] B14 FRAME# C13 TSTCLK B5 AD[2] C7 GNT#[0] B21 TXASIS AL10 AD[20] C15 GNT#[1] C20 TXD C24 AD[21] B15 GPIO[0] C25 VDD A19 AD[22] A15 GPIO[1] D24 VDD B19 Table 18: Pin Table in Alphabetical Order (Sheet 2 of 4) Signal Name Pin Number Signal Name Pin Number Signal Name Pin Number AD[23] D16 GPIO[2] B25 VDD B27 AD[24] A16 GPIO[3] A25 VDD H31 AD[25] C17 HIGH_EN# C27 VDD J29 AD[26] D17 IDSEL C16 VDD K2 AD[27] B18 IRDY# A12 VDD L4 AD[28] C18 LOW_EN# D26 VDD Y4 AD[29] C19 MADR[0] Y1 VDD AA2 AD[3] D8 MADR[1] Y2 VDD AA30 AD[30] A20 MADR[10] AC1 VDD AA31 AD[31] B20 MADR[11] AC2 VDD AC4 AD[4] B7 MADR[12] AC3 VDD AD3 AD[5] A7 MADR[13] AD1 VDD AD28 AD[6] C8 MADR[2] W4 VDD AE29 AD[7] D9 MADR[3] Y3 VDD AG4 AD[8] A8 MADR[4] AA1 VDD AG28 AD[9] C9 MADR[5] AA3 VDD_REF E4 CAS# W3 MADR[6] AB1 VDDP1 D5 CBE#[0] B8 MADR[7] AB2 VDDX A1 CBE#[1] C11 MADR[8] AA4 VDDX A31 CBE#[2] B13 MADR[9] AB3 VDDX B2 CBE#[3] B16 MDATA[0] D2 VDDX B30 CE#[0] A27 MDATA[1] D1 VDDX C3 CE#[1] C26 MDATA[10] H4 VDDX C29 CE#[2] B26 MDATA[11] G2 VDDX D4 CE#[3] A26 MDATA[12] G1 VDDX D7 CINT# Y28 MDATA[13] H3 VDDX D10 DEVSEL# D13 MDATA[14] J4 VDDX D14 DQ[0] V29 MDATA[15] H2 VDDX D18 DQ[1] V30 MDATA[16] H1 VDDX D22 DQ[10] R29 MDATA[17] J3 VDDX D25 DQ[11] P30 MDATA[18] J2 VDDX D28 DQ[12] R28 MDATA[19] J1 VDDX G4 DQ[13] P29 MDATA[2] E3 VDDX G28 DQ[14] N31 MDATA[20] K3 VDDX K4 DQ[15] N30 MDATA[21] K1 VDDX K28 DQ[16] N29 MDATA[22] L3 VDDX P4 DQ[17] M31 MDATA[23] M4 VDDX P28 DQ[18] M30 MDATA[24] L2 VDDX V4 37 Table 18: Pin Table in Alphabetical Order (Sheet 3 of 4) Signal Name 38 Pin Number Signal Name Pin Number Signal Name Pin Number DQ[19] N28 MDATA[25] L1 VDDX V28 DQ[2] U28 MDATA[26] M3 VDDX AB4 DQ[20] M29 MDATA[27] N4 VDDX AB28 DQ[21] L31 MDATA[28] M2 VDDX AE4 DQ[22] L30 MDATA[29] M1 VDDX AE28 DQ[23] M28 MDATA[3] F4 VDDX AH4 DQ[24] L29 MDATA[30] N3 VDDX AH7 DQ[25] K31 MDATA[31] N2 VDDX AH10 DQ[26] K30 MDATA[32] N1 VDDX AH14 DQ[27] L28 MDATA[33] P3 VDDX AH18 DQ[28] K29 MDATA[34] P2 VDDX AH22 DQ[29] J31 MDATA[35] R4 VDDX AH25 DQ[3] U29 MDATA[36] R3 VDDX AH28 DQ[30] J30 MDATA[37] T1 VDDX AJ3 DQ[31] H30 MDATA[38] T2 VDDX AJ29 DQ[4] T31 MDATA[39] T3 VDDX AK2 DQ[5] T30 MDATA[4] E2 VDDX AK30 DQ[6] T29 MDATA[40] T4 VDDX AL1 DQ[7] T28 MDATA[41] U1 VDDX AL31 DQ[8] R31 MDATA[42] U2 VSS A2 DQ[9] R30 MDATA[43] U3 VSS A3 DQM V3 MDATA[44] V2 VSS A14 EOP AJ11 MDATA[45] U4 VSS A17 EOP32 AL5 MDATA[46] AE1 VSS A18 FAST_RX1 AH11 MDATA[47] AE2 VSS A29 FAST_RX2 AJ10 MDATA[48] AD4 VSS A30 FBE#[0] AK11 MDATA[49] AE3 VSS B1 FBE#[1] AL11 MDATA[5] E1 VSS B3 FBE#[2] AJ12 MDATA[50] AF1 VSS B17 FBE#[3] AH13 MDATA[51] AF2 VSS B29 FBE#[4] AK12 MDATA[52] AF3 VSS B31 FBE#[5] AL12 MDATA[53] AG1 VSS C1 FBE#[6] AJ13 MDATA[54] AG2 VSS C2 FBE#[7] AK13 MDATA[55] AF4 VSS C4 FCLK AB30 MDATA[56] AG3 VSS C28 FDAT[0] AL13 MDATA[57] AH1 VSS C30 FDAT[1] AJ14 MDATA[58] AH2 VSS C31 FDAT[10] AK17 MDATA[59] AH5 VSS D3 Table 18: Pin Table in Alphabetical Order (Sheet 4 of 4) Signal Name Pin Number Signal Name Pin Number Signal Name Pin Number FDAT[11] AJ17 MDATA[6] F3 VSS D29 FDAT[12] AK18 MDATA[60] AK4 VSS P1 FDAT[13] AH17 MDATA[61] AL4 VSS P31 FDAT[14] AJ18 MDATA[62] AJ5 VSS R1 FDAT[15] AL19 MDATA[63] AH6 VSS R2 FDAT[16] AK19 MDATA[7] F2 VSS U30 FDAT[17] AJ19 MDATA[8] F1 VSS U31 FDAT[18] AL20 MDATA[9] G3 VSS V1 FDAT[19] AK20 PAR D12 VSS V31 FDAT[2] AK14 PARITY AK5 VSS AH3 FDAT[20] AH19 PCI_CFN[0] A24 VSS AH29 FDAT[21] AJ20 PCI_CFN[1] C23 VSS AJ1 FDAT[22] AL21 PCI_CLK D20 VSS AJ2 FDAT[23] AK21 PCI_IRQ# A22 VSS AJ4 FDAT[24] AH20 PCI_RST# C21 VSS AJ28 FDAT[25] AJ21 PERR# A11 VSS AJ30 FDAT[26] AL22 PORTCTL#[0] AA28 VSS AJ31 FDAT[27] AK22 PORTCTL#[1] AB29 VSS AK1 FDAT[28] AH21 PORTCTL#[2] AC31 VSS AK3 FDAT[29] AJ22 PORTCTL#[3] AC30 VSS AK15 FDAT[3] AH15 PXTAL B4 VSS AK29 FDAT[30] AL23 RAS# W2 VSS AK31 FDAT[31] AK23 RDYBUS[0] AL7 VSS AL2 FDAT[32] AJ23 RDYBUS[1] AJ8 VSS AL3 FDAT[33] AL24 RDYBUS[2] AH9 VSS AL14 FDAT[34] AK24 RDYBUS[3] AK8 VSS AL15 FDAT[35] AH23 RDYBUS[4] AL8 VSS AL18 FDAT[36] AJ24 RDYBUS[5] AJ9 VSS AL29 FDAT[37] AL25 RDYBUS[6] AK9 VSS AL30 FDAT[38] AK25 RDYBUS[7] AL9 VSSP1 A4 FDAT[39] AH24 RDYCTL#[0] AK7 WE# W1 FDAT[4] AJ15 RDYCTL#[1] AH8 RDYCTL#[4] AK6 FDAT[40] AJ25 RDYCTL#[2] AJ7 FDAT[41] AL26 RDYCTL#[3] AL6 39 3.6 IX Bus Pins Function Listed by Operating Mode Figure 7: 64-Bit Bidirectional IX Bus, 1-2 MAC Mode 3.3V 3.3V Intel(R) StrongARM(R)* CINT IXP1200 SA-1200 CINT GPIO[3:1] GPIO[3:1] GPIO[0] GPIO[0] RDYBUS[7:0] RDYBUS[7:0] RDYCTL#[4:0] RDYCTL#[4:0] wireor wireor not used D Q e D FCLK e Q not used FCLK [0] [1] [0] [0] PORTCTL#[3:0] PORTCTL#[3:0] [1] [0] [2] FDAT[63:0] FPS[2:0] FBE[7:0] FDAT[63:0] FBE[7:0] SOP EOP SOP TxASIS EOP RxFAIL TxASIS RxFAIL SOP32 SOP32 EOP32 EOP32 MAC0 MAC0 RxSEL# TxSEL# TxSEL# FPS[2:0] [2] FPS[2:0] FDAT[63:0] FPS[2:0] FBE[7:0] FDAT[63:0] FBE[7:0] CINT[7:0] CINT[7:0] FLCTL[7:0] FLCTL[7:0] RxRDY[7:0] TxRDY[7:0] RxRDY[7:0] TxRDY[7:0] RxCTL# RxCTL# TxCTL# TxCTL# RxSEL# SOP EOP SOP TxASIS EOP RxFAIL TxASIS RxFAIL not used not used not used [4] [4] D Q e D Q e FCLK FCLK [2] [3] [2] [1] [3] [1] [3] [3] CINT[7:0] CINT[7:0] FLCTL[7:0] MAC1 MAC1 FLCTL[7:0] RxRDY[7:0] TxRDY[7:0] RxRDY[7:0] RxCTL# TxRDY[7:0] TxCTL# RxCTL# TxCTL# RxSEL# TxSEL# RxSEL# FPS[2:0] TxSEL# FDAT[63:0] FPS[2:0] FBE#[7:0] FDAT[63:0] FBE#[7:0] SOP EOP SOP TxASIS EOP RxFAIL TxASIS RxFAIL * StrongARM is a registered trademark of ARM Limited. A6995-02 A6995-01 40 Table 19: 64-Bit Bidirectional IX Bus, 1-2 MAC Mode Signal Description GPIO[3:1] Active High input/output assigned to StrongARM(R) not used for MAC interface. GPIO[0] Active Low, output Flow-control enable for MAC 0. RDYCTL#[3:0] Active Low, output, enables for tx or rx ready flags. RDYCTL#[4] Active Low, output, flow-control enable for MAC 1. RDYBUS[7:0] Active Low, input/output, tx or rx ready flags. PORTCTL#[3:0] Active Low, output, transmit and receive mode enables. FPS[2:0] Active High, output port select (transmit or receive). SOP Active High, input/output, Start of Packet indication. SOP_32 Output, not used, no connect. EOP Active High, input/output, End of Packet indication. EOP_32 Input/output, not used, terminate through 10 KOhms to Vdd. TK_IN Input, not used, terminate through 10 KOhms to Vdd. TK_OUT Output, not used, no connect. Active High, input/output. RXFAIL Input - Receive Error input. Output - driven high on non-receive IX Bus cycles. Active High, output. Asserted on first transfer: 1 -Transmit using CRC in Tx FIFO. TXASIS/TXERR 0 -Transmit using MAC generated CRC. Asserted with EOP: 1 - Force a transmit error. 0 - Do not force a transmit error. FBE[7:0] Active High, byte enables for FDAT [64:0]. FDAT[64:0] Active High, read and write data. FAST_RX1 Active High ready input from FastPort 0, pulldown 10 KOhms to GND if not used. FAST_RX2 Active High ready input from FastPort 1, pulldown 10 KOhms to GND if not used. 41 Figure 8: 64-Bit Bidirectional IX Bus, 3+ MAC Mode 3.3V 3.3V Intel(R) StrongARM(R)* SA-1200 IXP1200 CINT wireor CINT GPIO[3:1] not used GPIO[3:1] GPIO[0] RDYBUS[7:0] GPIO[0] RDYCTL#[4:0] RDYBUS[7:0] not used RDYCTL#[4:0] MAC0 not used 5 > 32 5 > 32 PORTCTL#[3:0] 4 > 16 PORTCTL#[3:0] FPS[2:0] FDAT[63:0] FPS[2:0] FBE#[7:0] FDAT[63:0] FBE#[7:0] SOP EOP SOP TxASIS EOP RxFAIL TxASIS SOP32 RxFAIL EOP32 SOP32 4 > 16 not used not used used not EOP32 not used wireor DQ e DQ FCLK [19] e [19] FCLK [31:0] [27] [23] [27] [31:0] FCLK [15:0] FCLK [1] [15:0] FCLK [0] [1] FCLK [23] MAC0 CINT[7:0] CINT[7:0] FLCTL[7:0] FLCTL[7:0] RxRDY[7:0] TxRDY[7:0] RxRDY[7:0] RxCTL# TxRDY[7:0] TxCTL# RxCTL# TxCTL# RxSEL# TxSEL# RxSEL# FPS[2:0] TxSEL# FDAT[63:0] FPS[2:0] FBE#[7:0] FDAT[63:0] FBE#[7:0] SOP EOP SOP TxASIS EOP RxFAIL TxASIS [0] RxFAIL MAC3 MAC3 CINT[7:0] [16] [16] FCLK FCLK [7] [6] [7] [6] [24] [20] [24] [20] D Q e D Q e CINT[7:0] FLCTL[7:0] FLCTL[7:0] RxRDY[7:0] TxRDY[7:0] RxRDY[7:0] RxCTL# TxRDY[7:0] TxCTL# RxCTL# TxCTL# RxSEL# TxSEL# RxSEL# FPS[2:0] TxSEL# FDAT[63:0] FPS[2:0] FBE#[7:0] FDAT[63:0] FBE#[7:0] SOP EOP SOP TxASIS EOP RxFAIL TxASIS RxFAIL * StrongARM is a registered trademark of ARM Limited. A6996-02 A6996-01 42 Table 20: 64-Bit Bidirectional IX Bus, 3+ MAC Mode (Shared IX Bus Operation Only in This Mode) (Sheet 1 of 2) Signal Description GPIO[3:1] Active High input/output assigned to StrongARM(R) not used for MAC interface. GPIO[0] Active High, output assigned to StrongARM(R) not used for MAC interface. RDYCTL#[4:0] RDYBUS[7:0] PORTCTL#[3:0] FPS[2:0] SOP Active Low, output 5 bits encoded for tx/rx ready flags, flow-control, and inter-chip communication in shared IX Bus mode. Shared IX Bus mode, Initial ReadyBus master drives RDYCTL#[4:0] and ReadyBus slave snoops. Active High, input/output. Active Low, output, 4 bits encoded for transmit and receive mode select. Shared IX Bus mode - Tri-stated when bus slave. Active High, output, port select (transmit or receive). Shared IX Bus mode - Tri-stated when bus slave. Active High, input/output, Start of Packet indication. Shared IX Bus mode - Tri-stated when bus slave. Active High, output. SOP_32 Singlechip mode - not used, no connect. Shared IX Bus mode - IX Bus Request. EOP Active High, input/output, End of Packet indication. Shared IX Bus mode - Tri-stated when bus slave. Active High, input/output. EOP_32 Singlechip mode - output, not used, no connect. Shared IX Bus mode - input, IX Bus Request pending. Input in shared IX Bus mode. Singlechip mode - pullup through 10 KOhms to Vdd. TK_IN Shared IX Bus mode - Token_Input, enables IX Bus ownership when low at reset pulldown through 10 KOhms to GND to set as IX Bus Slave, pullup through 10 KOhms to VDD to set as Initial IX Bus Master. Active High, output. TK_OUT Singlechip mode - output, not used, no connect. Shared IX Bus mode - Token_Output. When high, indicates this IXP1200 Network Processor owns IX Bus as master. Active High, input/output. RXFAIL Input - Receive Error input. Output - driven high on non-receive cycles. Shared IX Bus mode - Tri-stated when bus slave. Active High, output. Asserted on first transfer: 1 -Transmit using CRC in Tx FIFO. TXASIS/TXERR 0 -Transmit using MAC generated CRC. Asserted with EOP: 1 - Force a transmit error. 0 - Do not force a transmit error. Tri-stated in shared IX Bus mode when bus slave. FBE[7:0] Active High, byte enables for FDAT [64:0]. Tri-stated in shared IX Bus Mode when bus slave. 43 Table 20: 64-Bit Bidirectional IX Bus, 3+ MAC Mode (Shared IX Bus Operation Only in This Mode) (Sheet 2 of 2) Signal FDAT[64:0] Description Active High, read and write data. Tri-stated in shared IX Bus mode when bus slave. FAST_RX1 Active High ready input from FastPort 0, pulldown 10KOhms to GND if not used. FAST_RX2 Active High ready input from FastPort 1, pulldown 10KOhms to GND if not used. Shared IX Bus Operation Signals These signals are driven by the IXP1200 Network Processor IX Bus master, and are tri-stated on IXP1200 Network Processor IX Bus slave devices: PORTCTL#[3:0] FPS[2:0] FDAT[63:0] FBE#[7:0] TXASIS/TXERR RXFAIL SOP EOP 44 Figure 9: 32-Bit Unidirectional IX Bus, 1-2 MAC Mode 3.3V Intel(R) StrongARM(R)* IXP1200 SA-1200 wireor CINT [7:0] D Q e GPIO[0] FCLK RDYBUS[7:0] Receive PORTCTL#[1:0] FDAT [31:0] FBE#[3:0] FPS[2:0] RxFAIL SOP EOP Transmit PORTCTL#[3:2] FLCTL[7:0] RxRDY[7:0] TxRDY[7:0] RxCTL# TxCTL# RxSEL# RxFDAT#[31:0] RxFBE#[3:0] RxFPS[2:0] RxFail RxSOP RxEOP [0] [1] RDYCTL#[4:0] MAC0 CINT[7:0] [0] [2] TxSEL# TxFDAT[32:0] TxFBE#[7:4] TxFPS[2:0] TxASIS TxSOP TxEOP FDAT[63:32] FBE#[7:4] GPIO[3:1] TxASIS SOP32 EOP32 MAC1 [7:0] [4] FCLK D e Q [2] [3] [1] [3] CINT[7:0] FLCTL[7:0] RxRDY[7:0] TxRDY[7:0] RxCTL# TxCTL# FDAT[31:0] FBE_L[3:0] FPS[2:0] RxFAIL SOP EOP RxSEL# RxFDAT[31:0] RxFBE#[3:0] RxFPS[2:0] RxFail RxSOP RxEOP FDAT [63:32] FBE_L[7:4] GPIO[3:1] TxASIS TxSOP32 TxEOP32 TxSEL# TxFDAT[32:0] TxFBE#[7:4] TxFPS[2:0] TxASIS TxSOP TxEOP A6994-02 * StrongARM is a registered trademark of ARM Limited. A6994-01 45 Table 21: 32-Bit Unidirectional IX Bus, 1-2 MAC Mode Transmit Path Signals GPIO[3:1] PORTCTL#[3:2] Description Active high transmit port select. Active Low. Transmit device select. SOP32 Active High, output, transmit Start of Packet. EOP32 Active High, output, transmit End of Packet. Active High, output. Asserted on first transfer: 1 -Transmit using CRC in Tx FIFO. TXASIS/TXERR 0 -Transmit using MAC generated CRC. Asserted with EOP: 1 - Force a transmit error. 0 - Do not force a transmit error. FBE[7:4] Active High, output, byte enables for FDAT [63:31]. FDAT[63:31] Active High, output, 32-bit transmit data. Receive Path Signals PORTCTL#[1:0] FPS[2:0] Active Low, output. Receive device select. Active High, output. Receive port select. SOP Active High input, receive Start of Packet. EOP Active High input, receive End of Packet. RXFAIL Active High, input, Receive Error. FBE[3:0] Active High, output, byte enables for FDAT [31:0]. FDAT[31:0] Active High, input, 32-bit receive data. Control Signals Common to both Transmit/Receive Paths 46 GPIO[0] Active Low flow-control for MAC 0. RDYCTL#[4] Active Low flow-control for MAC 1. RDYCTL#[3:0] Active Low enables for tx or rx ready flags. TK_IN Input, pulldown for Initial Master initialization in this mode. TK_OUT Output, not used, no connect. FAST_RX1 Active High, input, FastPort Ready, pulldown if not used. FAST_RX2 Active High, input, FastPort Ready, pulldown if not used. Figure 10: 32-bit Unidirectional IX Bus, 3+ MAC Mode (3-4 MACs Supported) 3.3V 3.3V Intel(R) StrongARM(R)* IXP1200 SA-1200 wireor wireor CINT [0] CINT [0] RDYCTL#[3:0] RDYCTL#[3:0] D D e Q Q FCLK e [3] [3] 4 > 16 [15:0] 4 > 16 [15:0] decoder decoder FCLK FCLK FCLK Receive Receive Transmit Transmit RDYBUS[7:0] RDYBUS[7:0] RDYCTL#[4] RDYCTL#[4] PORTCTL#[1:0] PORTCTL#[1:0] FDAT [31:0] FDAT [31:0] FBE#[3:0] FBE#[3:0] FPS[2:0] FPS[2:0] RxFAIL SOP RxFAIL EOP SOP EOP GPIO[0] GPIO[0] PORTCTL#[3:2] PORTCTL#[3:2] FDAT[63:32] FBE#[7:4] FDAT[63:32] GPIO[3:1] FBE#[7:4] TxASIS GPIO[3:1] SOP32 TxASIS EOP32 SOP32 EOP32 3>8 decoder 3>8 decoder [11] [11] [7] [2:0] [2:0] [7] [0] [0] FCLK FCLK 3 > 8 [2:0] [0] decoder 3 > 8 [2:0] [0] decoder FCLK FCLK CINT[7:0] CINT[7:0] MAC0 MAC0 FLCTL[7:0] FLCTL[7:0] RxRDY[7:0] RxRDY[7:0] TxRDY[7:0] TxRDY[7:0] RxCTL# RxCTL# TxCTL# TxCTL# RxSEL# RxSEL# RxFDAT#[31:0] RxFDAT#[31:0] RxFBE#[3:0] RxFBE#[3:0] RxFPS[2:0] RxFPS[2:0] RxFail RxSOP RxFail RxSOP RxEOP RxEOP TxSEL# TxSEL# TxFDAT[32:0] TxFBE#[7:4] TxFDAT[32:0] TxFPS[2:0] TxFBE#[7:4] TxFPS[2:0] TxASIS TxSOP TxASIS TxEOP TxSOP TxEOP MAC3 D [0] e Q D [0] FCLK e Q FCLK [8] [8] [4] [4] [3] [3] FDAT [31:0] FBE_L[31:0] [3:0] FDAT FPS[2:0] FBE_L [3:0] RxFAIL FPS[2:0] RxFAIL EOP [3] [3] EOP FDAT [63:32] FBE_L [7:4] FDAT [63:32] GPIO[3:1] FBE_L [7:4] TxASIS GPIO[3:1] TxSOP32 TxASIS TxEOP32 TxSOP32 TxEOP32 * StrongARM is a registered trademark of ARM Limited. MAC3 CINT[7:0] CINT[7:0] FLCTL[7:0] FLCTL[7:0] RxRDY[7:0] TxRDY[7:0] RxRDY[7:0] TxRDY[7:0] RxCTL# TxCTL# RxCTL# TxCTL# RxSEL# RxFDAT[31:0] RxSEL# RxFBE#[3:0] RxFDAT[31:0] RxFPS[2:0] RxFBE#[3:0] RxFail RxFPS[2:0] RxSOP RxFail RxEOP RxSOP RxEOP TxSEL# TxFDAT[ TxSEL# 63:32] TxFBE#[7:4] 63:32] TxFDAT[ TxFPS[2:0] TxFBE#[7:4] TxASIS TxFPS[2:0] TxSOP TxASIS TxEOP TxSOP TxEOP A6993-01 A6993-02 Table 22: 32-bit Unidirectional IX Bus, 3+ MAC Mode Transmit Path Signals GPIO[3:1] GPIO[0] PORTCTL#[3:2] Description Active high transmit port select [2:0]. Active Low. Used with PortCTL#[3:2] for transmit device select via external 3-to-8 decoder. Active Low Used with GPIO[0] for transmit device select via external 3-to-8 decoder. 47 Table 22: 32-bit Unidirectional IX Bus, 3+ MAC Mode Transmit Path Signals Description SOP32 Active High output, transmit Start of Packet. EOP32 Active High output, transmit End of Packet. Active High, output. Asserted on first transfer: 1 -Transmit using CRC in Tx FIFO. TXASIS/TXERR 0 -Transmit using MAC generated CRC. Asserted with EOP: 1 - Force a transmit error. 0 - Do not force a transmit error. FBE[7:4] Active High, output, byte enables for FDAT [63:31]. FDAT[63:31] Active High, output, 32-bit transmit data. Receive Path Signals RDYCTL#[4] PORTCTL#[1:0] FPS[2:0] SOP Active Low. Used with PortCTL#[1:0] for transmit device select via external 3-to-8 decoder. Active Low, output, enable to external PORTCTL[1:0] decoder. Used with RDYCTL#[4] for receive device select via external 3-to-8 decoder. Active High, output. Receive port select. Active High input, receive Start of Packet. EOP Active High input, receive End of Packet. RXFAIL Active High, input, Receive Error. FBE[3:0] Active High, byte enables for FDAT [31:0]. FDAT[31:0] Active High, input, 32-bit receive data. Control Signals Common to both Transmit/Receive Paths 48 RDYCTL#[3:0] Active Low, 4 bits encoded for tx/rx ready flags, flow-control, and inter-chip communication. Used as selects to external 4-to-16 decoder. TK_IN Input, pulldown for Initial Master initialization in this mode. TK_OUT Output, not used, no connect. FAST_RX1 Active High, input, FastPort Ready, pulldown if not used. FAST_RX2 Active High, input, FastPort Ready, pulldown if not used. 3.7 IX Bus Decode Table Listed by Operating Mode Type Table 23: IX Bus Decode Table Listed by Operating Mode Type (Sheet 1 of 2) PIN NAME 64-bit Bidirectional 1-2 MAC mode 64-bit Bidirectional 3+ MAC mode 32-bit Unidirectional 1-2 MAC mode If RDYCTL<4> = 0 0000 MAC0 TxSEL XX00 MAC0 RxSEL 0001 MAC0 RxSEL PORTCTL#[3:0] 0010 MAC1 TxSEL 1110 MAC0 RxSel XX01 MAC1 RxSEL 0011 MAC1 RxSEL 1101 MAC1 RxSel XX10 MAC2 RxSEL 0100 MAC2 TxSEL 1011 MAC0 TxSel XX11 MAC3 RxSEL 1110 MAC0 RxSEL 0101 MAC2 RxSEL 0111 MAC1 TxSel If RDYCTL<4> = 1 1101 MAC1 RxSEL 0110 MAC3 TxSEL No Select 1011 MAC0 TxSEL 0111 MAC3 RxSEL 1010 MAC0 TxSel/ MAC0 RxSel 0111 MAC1 TxSEL 1000 MAC4 TxSEL If GPIO<0> = 1 1111 No Select 1001 MAC4 RxSEL 0110 MAC1 TxSel/ MAC0 RxSel 1001 MAC0 TxSel/ MAC1 RxSel 01XX MAC1 TxSEL 1010 MAC5 TxSEL 1011 MAC5 RxSEL 1100 MAC6 TxSEL FPS[2:0] 32-bit Unidirectional 3+ MAC mode 101 MAC1 TxSel/ MAC1 RxSel 00XX MAC0 TxSEL 10XX MAC2 TxSEL 11XX MAC3 TxSEL 1101 MAC6 RxSEL If GPIO<0> = 0 1110/1111 No Select No Select Rx/Tx Port Select Rx/Tx Port Select Rx Port Select Rx Port Select GPIO[3:1] Not used Not used Tx Port Select Tx Port Select GPIO[0] MAC0 Flw Ctl enable Not used MAC0 Flw Ctl enable PORTCTL#[3:2] Tx enable (see above) FDAT[63:32] Rx/Tx Data Rx/Tx Data Tx Data Tx Data FDAT[31:0] Rx/Tx Data Rx/Tx Data Rx Data Rx Data FBE#[7:4] Rx/Tx Byte Enables Rx/Tx Byte Enables Tx Byte Enables Tx Byte Enables FBE#[3:0] Rx/Tx Byte Enables Rx/Tx Byte Enables Rx Byte Enables Rx Byte Enables SOP Rx/Tx SOP Rx/Tx SOP Rx SOP Rx SOP EOP Rx/Tx EOP Rx/Tx EOP Rx EOP Rx EOP SOP32 Not used Not used Tx SOP Tx SOP 49 Table 23: IX Bus Decode Table Listed by Operating Mode Type (Sheet 2 of 2) PIN NAME 64-bit Bidirectional 1-2 MAC mode 64-bit Bidirectional 3+ MAC mode 32-bit Unidirectional 1-2 MAC mode 32-bit Unidirectional 3+ MAC mode EOP32 Not used Not used Tx EOP Tx EOP RDYCTL#[4] MAC1 Flw Ctl enable Ready Control (see below) MAC1 Flw Ctl enable PORTCTL#[1:0] Rx enable (see above) 11111 NOP 11110 GET 1 11101 SEND 1 11100 autopush 11011 MAC0 Rx 11010 MAC1 Rx 11001 MAC2 Rx 11000 MAC3 Rx x1111 NOP x1110 GET 1 10111 MAC0 Tx x1101 SEND 1 10110 MAC1 Tx x1100 autopush 10101 MAC2 Tx 10100 MAC3 Tx x1011 MAC0 Rx x1010 MAC1 Rx 10011 MAC0 Flw Ctl enable x1111 NOP x1110 MAC0 Rx RDYCTL#[4:0] x1101 MAC0 Tx x1011 MAC1 Rx x0111 MAC1 Tx 10010 MAC1 Flw Ctl enable x1111 NOP 10001 MAC2 Flw Ctl enable x1101 MAC0 Tx 10000 MAC3 Flw Ctl enable x0111 MAC1 Tx 01110 GET 2 01101 SEND 2 01011 MAC4 Rx 01010 MAC5 Rx 01001 MAC6 Rx 00111 MAC4 Tx 00110 MAC5 Tx 00101 MAC6 Tx 00011 MAC4 Flw Ctl enable 00010 MAC5 Flw Ctl enable 00001 MAC6 Flw Ctl enable 50 x1001 MAC2 Rx x1110 MAC0 Rx x1011 MAC1 Rx x1000 MAC3 Rx x0111 MAC0 Tx x0110 MAC1 Tx x0101 MAC2 Tx x0100 MAC3 Tx x0011 MAC0 Flw Ctl enable x0010 MAC1 Flw Ctl enable x0001 MAC2 Flw Ctl enable x0000 MAC3 Flw Ctl enable 3.8 Pin State During Reset TBD 3.9 Pullup/Pulldown and Unused Pin, Drive Guidelines For normal (i.e., non-test mode) operation, terminate signals as follows: * Pullup these signals to 3.3 V: TCK, TMS, TDI. * Pulldown these signals to Ground: SCAN_EN, TSTCLK, TCK_BYP, TRST#. Terminate unused signals as follows: * Pullup these signals to 3.3 V: PARITY, REQ#[1], GNT#[1], TK_IN, EOP32. * Pulldown these signals FAST_RX1, FAST_RX2. to Ground: SACLK, For shared IX Bus operation: Pullup PORTCTL#[3:0], FPS[2:0], and TXASIS Drive guidelines: TBD. 51 SECTION 4 - ELECTRICAL SPECIFICATIONS This chapter specifies the following electrical behavior of the IXP1200 Network Processor: * Absolute maximum ratings. * DC specifications. * AC timing specifications for the following signal interfaces: -- PXTAL Clock input. -- PCI Bus Interface. -- JTAG Interface. -- Serial Port signals. 4.1 Absolute Maximum Ratings The IXP1200 Network Processor is specified to operate at a maximum core frequency (Fcore) of 162 MHz at a junction temperature (Tj) not to exceed 100C. Table 24 lists the absolute maximum ratings for the IXP1200 Network Processor. These are stress ratings only; stressing the device beyond the absolute maximum ratings may cause permanent damage. Operating beyond the functional operating range (Table 25) is not recommended and extended exposure beyond the functional operating range may affect reliability. -- FIFO Bus Interface. -- ReadyBus Interface. -- TK_OUT/TK_IN signals. -- SRAM interface. -- SDRAM Interface. -- Reset signals. -- GPIO signals. Table 24: Absolute Maximum Ratings Parameter Junction temperature, Tj Minimum --- Maximum Comment 100C Maximum voltage applied to signal pins 3.6 V Supply voltage (core and PLL), VDD, VDDP1 2.1 V 2 V supply Supply voltage (I/O), VDDX, VDDREF --- 3.6 V 3.3 V supply Storage temperature range -55C 125C Vdelta 0.0 V 1.6 V The power specifications listed below are based on the following assumptions: * Core System Frequency (Fcore)= 162 MHz. * FIFO Bus Frequency (FCLK) = 66 MHz. * PCI Bus Frequency (PCI_CLK) = 66 MHz. Table 25: Functional Operating Range Parameter 52 Minimum Maximum Operating temperature range 0C 55C Supply voltage (core and PLL), VDD, VDDP1 1.9 V 2.1 V Supply voltage (I/O), VDDX, VDDREF 3.0 V Comment +/- 5% 3.6 V +/- 10% Maximum Power, 2 V supply 2.7 W (1.35 A) Maximum Power, 3.3 V supply 2.3 W (0.7 A) Total Power 5.0 W Table 26: Thermal Specifications Parameter Minimum Maximum Comment Junction Temperature, Tj - Thermal Conductance, ja, 400 LFM airflow 8.5C/W Four-layer board Thermal Conductance, ja, No airflow 12.5C/W Four-layer board 4.2 DC Specifications 100C The Type 1 pins are 3.3 V Low Voltage TTL compatible I/O buffers. There are three versions of the Type 1 driver that differ by the maximum available driver current. The IXP1200 Network Processor supports two fundamental I/O buffer Types: Type 1 and Type 2. The Pin Description section defines which pins use which I/O buffer type. The driver characteristics are described in the following sections. Please note that IXP1200 Network Processor input pins are not 5 volt tolerant. Devices driving the IXP1200 Network Processor must provide 3.3 V signal levels or use level shifting buffers to provide 3.3 V compatible levels, otherwise damage to the device will result. The Type 2 pins are 3.3 V PCI 2.1 compliant I/O buffers. 4.2.1 Type 1 Driver DC Specifications Table 27 refers to pin types: I1, O1, O3, O4. Table 27: I1, O1, O3 and O4 Pin Types Symbol Parameter Condition Minimum Maximum Vih Input High Voltage 2.0 V --- Vil Input Low Voltage --- 0.8 V Voh Output High Voltage 2.4 V - --- 0.4 V O1: Ioh = -tbd mA O3: Ioh = -tbd mA O4: Ioh = -tbd mA Load circuit 1 O1: Iol = +tbd mA O3: Iol = +tbd mA Vol Output Low Voltage Ii Input Leakage Current1 - - tbd A tbd A Cin Pin Capacitance - 5 pF 10 pF O4: Iol = +tbd mA Load circuit 2 Test Load 1 tbd Test Load 2 tbd 4.2.1.1 Type 2 Driver DC Specifications Table 28 refers to pin types: I2, O2. 53 Table 28: I2 and O2 Pin Types Symbol Parameter Condition Maximum Vih Input High Voltage 0.5 x VDDX VDD_REF + 0.5V Vil Input Low Voltage --- 0.3 x VDDX Voh Output High Voltage Ioh = -500 uA 0.9 x VDDX --- Vol Output Low Voltage Iol = 1500 uA --- 0.1 x VDDX Ii Input Leakage Current1 0 < Vin <VDDX -15 uA 15 uA Cin Pin Capacitance 5 pF 10 pf NOTE In Table 27 and Table 28, currents into the chip (chip sinking) are denoted as positive(+) current. Currents from the chip (chip sourcing) are denoted as negative(-) current. Input leakage currents include high-Z output leakage for all bidirectional buffers with tri-state outputs. NOTE The electrical specifications are preliminary and subject to change. 4.3 AC Specifications 4.3.1 Clock Timing Specifications The ac specifications consist of input requirements and output responses. The input requirements consist of setup and hold times, pulse widths, and high and low times. Output responses are delays from clock to signal. The ac specifications are defined separately for each clock domain within the IXP1200 Network Processor. For example, Figure 12 shows the ac parameter measurements for the PCI_CLK signal, and Table 30 and Table 31 specify parameter values for clock signal ac timing. See also Figure 13 for a further illustration of signal timing. Unless otherwise noted, all ac parameters are guaranteed when tested within the functional operating range of Table 25. 54 Minimum 4.3.2 PXTAL Clock Input Figure 11: PXTAL Clock Input 1/FPXTAL Thigh Vh Vptp Tlow Vl Tr Tf A6991-01 Table 29: PXTAL Clock Inputs Symbol Parameter Minimum Fpxtal Clock frequency 3.5795 Vptp Clock peak to peak Vhigh Vlow Unit MHz 0.4*VDDX --- V Clock high threshold 2.0 --- V Clock low threshold --- 0.8 V 1 4 V/ns Core rate1 frequency2 3.6864 Maximum --- Clock slew Fcore Typical 166 MHz 1. Not tested. Guaranteed by design. 2. Core frequency (Fcore) of 162 MHz when register PLL_CFG[4:0] = 00111. 4.3.3 PXTAL Clock Oscillator Specifications Frequency: Fpxtal 0.01% Stability: 100 ppm Voltage signal level: 3.3 V Rise/fall time: < 4 ns Duty cycle: 40%-60% 55 4.3.4 PCI 4.3.4.1 PCI Electrical Specification Conformance The IXP1200 Network Processor PCI pins conform to the basic set of PCI electrical specifications in the PCI Local Bus Specification, Revision 2.1. See that document for a complete description of the PCI I/O protocol and pin ac specifications. 4.3.4.2 PCI Clock Signal AC Parameter Measurements Figure 12: PCI Clock Signal AC Parameter Measurements Tcyc Thigh Vt1 Vt2 Vt3 Tlow Tr Tf A6992-01 Vt1 = 0.5*VDDX Vt2 = 0.4*VDDX Vt3 = 0.3*VDDX Table 30: 66 MHz PCI Clock Signal AC Parameters Symbol Tcyc Parameter Minimum PCI_CLK cycle time Maximum Unit 15 30 ns Thigh PCI_CLK high time 6 --- ns Tlow PCI_CLK low time 6 --- ns 1.5 4 V/ns PCI_CLK slew rate 1, 2 1. 0.2 VDDX to 0.6 VDDX. 2. Not tested. Guaranteed by design. Table 31: 33 MHz PCI Clock Signal AC Parameters Symbol Parameter Maximum Unit Tcyc PCI_CLK cycle time 30 ns Thigh PCI_CLK high time 11 --- ns Tlow PCI_CLK low time 11 --- ns 1 4 V/ns PCI_CLK slew rate 1. 0.2 VDDX to 0.6 VDDX. 2. Not tested. Guaranteed by design. 56 Minimum 12 Figure 13: PCI Bus Signals PCI_CLK Vtest Tval(max) Tval(min) Outputs Ton Toff Inputs Tsu Th Note: Vtest - 0.4 VDDX for 3.3 volt PCI signals A6988-01 4.3.4.3 PCI Bus Signals Timing Table 32: 33 MHZ PCI Signal Timing Symbol Parameter Minimum Maximum Unit Tval CLK to signal valid delay, bused signals 2 11 ns Tval (point-topoint) CLK to signal valid delay, point-topoint signals1 2 12 ns Ton Float to active delay 2 --- Toff Active to float delay --- 28 ns Tsu Input setup time to CLK, bused signals1 7 --- ns Tsu (point-topoint) Input setup time to CLK, point-topoint signals2 10 --- ns Th Input signal hold time from CLK 0 --- ns 1. Point-to-point signals are REQ#, GNT#. 2. Bused signals are AD, CBE#, PAR, PERR#, SERR#, FRAME#, IRDY#, TRDY#, DEVSEL#, STOP# Table 33: 66 MHz PCI Signal Timing (Sheet 1 of 2) Symbol Parameter Minimum Maximum Unit Tval CLK to signal valid delay, bused signals 2 6 ns Tval (point-topoint) CLK to signal valid delay, point-topoint signals1 2 6 ns Ton Float to active delay 2 --- Toff Active to float delay --- 14 ns 57 Table 33: 66 MHz PCI Signal Timing (Sheet 2 of 2) Symbol Parameter Minimum Maximum Unit Tsu Input setup time to CLK, bused signals2 3 --- ns Tsu (point-topoint) Input setup time to CLK, point-topoint signals1 5 --- ns Th Input signal hold time from CLK 0 --- ns 1. Point-to-point signals are REQ#, GNT#. 2. Bused signals are AD, CBE#, PAR, PERR#, SERR#, FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#. 4.3.5 Reset 4.3.5.1 Reset Timings Specification Table 34 shows the reset timing specifications for RESET_IN# and RESET_OUT#. Table 34: Reset Timings Specification TBD Symbol Parameter Minimum Maximum Unit Figure 14: RESET_IN# Timing Diagram VDD, VDDX RESET_IN# StrongARMTM and SRAM internal reset signals 150ms 5000 PXTAL cycles A6245-01 58 4.3.6 JTAG 4.3.7 IX Bus 4.3.6.1 JTAG Timing Specifications 4.3.7.1 FCLK Signal AC Parameter Measurements TBD Figure 15: FCLK Signal AC Parameter Measurements Tc Thigh Vh Vptp Tlow Vl Tr Tf A6987-01 Table 35: FCLK Signal AC Parameter Measurements Symbol Parameter Minimum Maximum Unit Freq Clock frequency 25 tbd 66.6 MHz Tc Cycle time 15 40 ns Thigh Clock high time 6 --- ns Tlow Clock low time 6 --- ns Vptp Clock peak to peak (0.2* VDDX to 0.6*VDDX) 0.4*VDDX --- V Vh Clock high threshold 0.5*VDDX --- V Vl Clock low threshold --- 0.3*VDDX V 1 4 V/ns Clock slew rate 1, 2 1. 0.2 *VDDX to 0.6 *VDDX. 2. Not tested. Guaranteed by design. 4.3.7.2 IX Bus Signals Timing Figure 16: IX Bus Signals Timing CLK Tval(max) Tval(min) Outputs Ton Toff Inputs Tsu Th A6989-02 59 Table 36: IX Bus Signals Timing Symbol Parameter Minimum Maximum Unit Tval Clock-to-signal valid delay (except RDYBUS signals) 2 6 ns Tvalrb Clock-to-valid delay1, RDYBUS 2 8 ns Tsu Input signal valid setup time before clock 3 --- ns Th Input signal hold time from clock 0 --- ns Ton Float-to-active delay from clock 1 --- ns Toff Active-to-float delay from clock --- 14 ns 1. RDYCTL#[4:0] and RDYBUS[7:0] driven for two cycles. 4.3.7.3 IX Bus Protocol The following timing diagrams show the IX Bus signal protocol for both 64-bit Bidirectional and 32-bit Unidirectional modes of operation. Figure 17: 64-Bit Bidirectional IX Bus Timing - Consecutive Receives with EOP on 1st Data Return, No Status Transfer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FCLK PORT_CTL# [3:0] No Sel MAC RxSEL A No Sel MAC RxSEL B No Sel MAC RxSEL C Rx_SELA# (from decoder) Rx_SELB# (from decoder) Rx_SELC# (from decoder) FPS[2:0] XXX FDAT[63:0] Port A Port B XXX Ra0 XXX XXX XXX XXX XXX Rb0 Rb1 Rb2 Rb3 Rb4 Rb5 Rb6 Rb7 Port C Rc0 Rc1 Rc2 Rc3 Rc4 EOP NOTES: Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A7004-01 60 Figure 18: 64-Bit Bidirectional IX Bus Timing - Consecutive Receive and Transmit with No EOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC TxSEL B MAC RxSEL C Port B Port C Rx_SELA# (from decoder) Tx_SELB# (from decoder) Rx_SELC# (from decoder) FPS[2:0] FDAT[63:0] Port A XXX Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 Ra7 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 XXX Rc0 Rc1 Rc2 Rc3 EOP NOTES: FDAT pattern over time based on EOP on 8th data return = Ra - Tb - - Rc - RaS - Td - - Re - - RbS - Tf - - Rg - - RcS Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A6997-01 61 Figure 19: 64-Bit Bidirectional IX Bus Timing - Consecutive Receive and Transmit with EOP on 8th Data Return 1 2 3 4 5 6 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 8 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC TxSEL B MAC RxSEL C No Sel RxA No Sel MAC TxSEL D Rx_SELA# (from decoder) Tx_SELB# (from decoder) Rx_SELC# (from decoder) Tx_SELD# (from decoder) FPS[2:0] FDAT[63:0] Port A Ra0 Ra1 Ra2 XXX Ra7 Port B Tb0 Tb1 Port C Tb7 XXX Rc0 Rc1 Rc2 XXX Port A XXX Rc7 RaS Port D Td0 Td1 Td2 Td3 EOP NOTES: FDAT pattern over time based on EOP on 8th data return = Ra - Tb - - Rc - RaS - Td - - Re - - RbS - Tf - - Rg - - RcS Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A6288-01 62 Figure 20: 64-Bit Bidirectional IX Bus Timing - Consecutive Receive and Transmit with EOP on 7th Data Return 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC TxSEL B MAC RxSEL C Port B Port C Rx_SELA# (from decoder) Tx_SELB# (from decoder) Rx_SELC# (from decoder) FPS[2:0] FDAT[63:0] Port A XXX Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 RaS Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 XXX Rc0 Rc1 Rc2 Rc3 EOP NOTES: Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A6283-01 63 Figure 21: 64-Bit Bidirectional IX Bus Timing - Consecutive Receive and Transmit with EOP on 6th Data Return 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC TxSEL B MAC TxSEL C Rx_SELA# (from decoder) Tx_SELB# (from decoder) Rx_SELC# (from decoder) FPS[2:0] FDAT[63:0] Port A XXX Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 RaS XXX Port B Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 XXX Port C Rc0 Rc1 Rc2 Rc3 EOP NOTES: Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A6289-02 64 Figure 22: 64-Bit Bidirectional IX Bus Timing - Consecutive Receive and Transmit with EOP on 5th Data Return 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC TxSEL B MAC RxSEL C Port B Port C Rx_SELA# (from decoder) Tx_SELB# (from decoder) Rx_SELC# (from decoder) FPS[2:0] FDAT[63:0] Port A XXX Ra0 Ra1 Ra2 Ra3 Ra4 RaS XXX XXX Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 XXX Rc0 Rc1 Rc2 Rc3 EOP NOTES: Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A7001-01 65 Figure 23: 64-Bit Bidirectional IX Bus Timing - Consecutive Receive and Transmit with EOP on 1st through 3rd Data Return (3rd Data Return Shown) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC RxSEL C MAC TxSEL B No Sel MAC TxSEL D Rx_SELA# (from decoder) Tx_SELB# (from decoder) Rx_SELC# (from decoder) Tx_SELD# (from decoder) FPS[2:0] FDAT[31:0] Port A XXX Ra0 Ra1 Ra2 RaS XXX XXX XXX Port B Tb0 EOP NOTES: Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = 66 Tb7 Port C Rc0 Rc1 Rc2 Rc3 XXX Port D Rc7 Td0 Td1 Td2 Td3 Figure 24: 64-Bit Bidirectional IX Bus Timing - Consecutive Receive and Transmit with EOP on 4th Data Return 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC TxSEL B MAC RxSEL C Port B Port C Rx_SELA# (from decoder) Tx_SELB# (from decoder) Rx_SELC# (from decoder) FPS[2:0] FDAT[63:0] Port A XXX Ra0 Ra1 Ra2 Ra3 RaS XXX XXX XXX Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 XXX Rc0 Rc1 Rc2 Rc3 EOP NOTES: Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A7002-01 67 Figure 25: 64-Bit Bidirectional IX Bus Timing - Consecutive Receives with No EOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC TxSEL B No Sel No Sel MAC RxSEL C Rx_SELA# (from decoder) Rx_SELB# (from decoder) Rx_SELC# (from decoder) FPS[2:0] FDAT[63:0] Port A XXX Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 Ra7 Port B XXX Rb0 Rb1 Rb2 Rb3 Rb4 Rb5 Rb6 Rb7 Port C Rc0 Rc1 Rc2 Rc3 Rc4 Rc5 EOP NOTES: FDAT pattern over time based on EOP on 8th data return = Ra - Rb - RaS - Rc - RbS - Rd - RcS Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A7003-01 68 Figure 26: 64-Bit Bidirectional IX Bus Timing - Consecutive Receives with EOP on 8th Data Return 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC RxSEL B No Sel No Sel A Sel MAC RxSEL C MAC No Sel No Sel B Sel RxSEL D Rx_SELA# (from decoder) Rx_SELB# (from decoder) Rx_SELC# (from decoder) Rx_SELD# (from decoder) FPS[2:0] FDAT[63:0] Port A Ra0 Ra1 Ra2 Ra3 XXX Port B Ra7 XXX Port XXX A Rb0 Rb1 Rb3 Rb3 Rb7 Port C RaS Rc0 Rc1 Rc2 Rc3 XXX Port XXX Port D B Rc7 RbS EOP NOTES: FDAT pattern over time based on EOP on 8th data return = Ra - Rb - RaS - Rc - RbS - Rd - RcS Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A6291-02 69 Figure 27: 64-Bit Bidirectional IX Bus Timing - Consecutive Receives with EOP on 7th Data Return 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC RxSEL B No Sel MAC RxSEL C Rx_SELA# (from decoder) Rx_SELB# (from decoder) Rx_SELC# (from decoder) FPS[2:0] FDAT[63:0] Port A XXX Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 RaS Port B XXX Rb0 Rb1 Rb2 Rb3 Rb4 Rb5 Rb6 RbS Port C Rc0 Rc1 Rc2 Rc3 Rc4 EOP A6918-01 70 Figure 28: 64-Bit Bidirectional IX Bus Timing - Consecutive Receives with EOP on 6th Data Return 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC RxSEL B No Sel MAC RxSEL C No Sel Rx_SELA# (from decoder) Rx_SELB# (from decoder) Rx_SELC# (from decoder) FPS[2:0] FDAT[63:0] Port A XXX Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 XXX Port B XXX Rb0 Rb1 Rb2 Rb3 Rb4 Rb5 Rb6 XXX Port C Rc0 Rc1 Rc2 Rc3 Rc4 Rc5 EOP NOTES: Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A6919-01 71 Figure 29: 64-Bit Bidirectional IX Bus Timing - Consecutive Transmits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] No Sel MAC RxSEL A No Sel MAC TxSEL B No Sel MAC RxSEL C Tx_SELA# (from decoder) Tx_SELB# (from decoder) Tx_SELC# (from decoder) FPS[2:0] XXX Port A XXX Port B Port C Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 XXX Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 XXX Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 FDAT[63:0] NOTES: Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A6286-01 Figure 30: 64-Bit Bidirectional IX Bus Timing - Consecutive Transmits with Prepend 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC TxSEL B No Sel MAC RxSEL C Tx_SELA# (from decoder) Tx_SELB# (from decoder) Tx_SELC# (from decoder) FPS[2:0] FDAT[63:0] Port A XXX Port B XXX Port C TaP Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 XXX TbP Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 XXX TcP Tc0 Tc1 Tc2 Tc3 Tc4 NOTES: Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A6287-01 72 Figure 31: 32-Bit Unidirectional IX Bus Timing - Consecutive Receives with No EOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC TxSEL B No Sel MAC RxSEL C No Sel MAC RxSEL D No Sel Rx_SELA# (from decoder) Rx_SELB# (from decoder) Rx_SELC# (from decoder) Rx_SELD# (from decoder) FPS[2:0] FDAT[31:0] Port A Port B XXX Ra0 Ra1 Ra2 Ra3 Ra 15 Port C XXX Rb0 Rb1 Rb2 Rb 15 Port D XXX Rc0 Rc1 Rc2 Rc 15 XXX Rd0 Rd1 Rd2 Rd 15 EOP NOTES: FDAT pattern over time based on EOP on 16th data return = Ra - Rb - RaS - Rc- RbS- Rd - RcS Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A6292-02 73 Figure 32: 32-Bit Unidirectional IX Bus Timing - Consecutive Receives with EOP on 16th Data Return 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC RxSEL B No Sel No Sel A Sel MAC RxSEL C MAC No Sel No Sel B Sel RxSEL D Rx_SELA# (from decoder) Rx_SELB# (from decoder) Rx_SELC# (from decoder) Rx_SELD# (from decoder) FPS[2:0] FDAT[63:0] Port A Ra0 Ra1 Ra2 Ra3 Port B XXX Ra 15 XXX Port XXX Rb0 Rb1 Rb3 Rb3 Port C A Rb 15 RaS Rc0 Rc1 Rc2 Rc3 XXX Port XXX Port B D Rc 15 RbS EOP NOTES: FDAT pattern over time based on EOP on 16th data return = Ra - Rb - RaS - Rc- RbS- Rd - RcS Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A6293-02 74 Figure 33: 32-Bit Unidirectional IX Bus Timing - Receive with EOP on 15th Data Return 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC RxSEL B No Sel MAC RxSEL C No Sel MAC RxSEL D Rx_SELA# (from decoder) Rx_SELB# (from decoder) Rx_SELC# (from decoder) Rx_SELD# (from decoder) FPS[2:0] FDAT[63:0] Port A Ra0 Ra1 Ra2 XXX Ra RaS 14 Port B Rb0 Rb1 Rb3 Rb3 XXX Rb 14 RbS Port C Rc0 Rc1 Rc2 Rc3 XXX Port D Rc 14 RcS Rc0 EOP NOTES: Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A6294-02 75 Figure 34: 32-Bit Unidirectional IX Bus Timing - Receive with EOP on 14th Data Return 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC RxSEL B No Sel MAC RxSEL C No Sel MAC RxSEL D Rx_SELA# (from decoder) Rx_SELB# (from decoder) Rx_SELC# (from decoder) Rx_SELD# (from decoder) FPS[2:0] FDAT[31:0] Port A Ra0 Ra1 XXX Ra XXX 13 RaS Port B Rb0 Rb1 Rb2 XXX Rb 13 RbS XXX Port C Rc0 Rc1 Rc2 XXX Port D Rc RcS XXX 13 Rc0 EOP NOTES: Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A6296-02 76 Figure 35: 32-Bit Unidirectional IX Bus Timing - Consecutive Receives with EOP on 1st Through 13th Data Return (13th Data Return Shown) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] MAC RxSEL A No Sel MAC RxSEL B No Sel MAC RxSEL C No Sel MAC RxSEL D Rx_SELA# (from decoder) Rx_SELB# (from decoder) Rx_SELC# (from decoder) Rx_SELD# (from decoder) FPS[2:0] FDAT[31:0] Port A Ra0 XXX Ra 12 RaS XXX XXX Port B Rb0 Rb1 XXX Rb RbS XXX XXX 12 Port C Rc0 Rc1 XXX Port D Rc 12 RcS XXX XXX Rc0 EOP NOTES: Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A6297-02 77 Figure 36: 32-Bit Unidirectional IX Bus Timing - Consecutive Transmits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] No Sel MAC RxSEL A No Sel MAC RxSEL B No Sel MAC RxSEL C Tx_SELA# (from decoder) Tx_SELB# (from decoder) Tx_SELC# (from decoder) FPS[2:0] Port A Ta 12 Ta0 Ta1 Ta2 FDAT[31:0] Port B XXX Ta 13 Ta 14 Ta 15 Tb0 Tb1 Tb2 Tb 12 Port C XXX Tb 13 Tb 14 Tb 15 Tc0 Tc1 Tc2 Tc 12 Tc 13 Tc 14 Tc 15 NOTES: Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A6298-01 Figure 37: 32-Bit Unidirectional IX Bus Timing - Consecutive Transmits with Prepend 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FCLK PORT_CTL# [3:0] No Sel MAC RxSEL A No Sel MAC RxSEL B MAC RxSEL C Tx_SELA# (from decoder) Tx_SELB# (from decoder) Tx_SELC# (from decoder) FPS[2:0] FDAT[31:0] XXX Port A TaP Ta0 Ta1 Ta2 Ta 12 Ta 13 Ta 14 Port B TbP Tb0 Tb1 Tb2 Tb 13 XXX Tb 14 Tb 15 Tb 15 Port C TcP Tc0 Tc1 Tc2 Tc 12 NOTES: Numbers do not refer to consecutive clock cycles. They are to be used only to reference the timing diagrams. Don't care = XXX Status = RaS, RbS,RcS Tri-state, undriven = All cycles not shown = A6299-01 78 4.3.7.4 RDYBus Figure 38: Consecutive Fetch Ready Flags, 1-2 MACs (with No External Registered Decoder) RDYBUS_TEMPLATE_CTL[10]=1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FCLK RDYCTL#[4:0] TRdyMAC1 NOP TRdyMAC2 NOP RRdyMAC1 NOP RRdyMAC2 NOP RDYBUS[7:0] TRdyMAC1 TRdyMAC2 RRdyMAC1 RRdyMAC2 A6925-01 Figure 39: Consecutive Fetch Ready Flags, 3+ MACs (with External Decoder) RDYBUS_TEMPLATE_CTL[10]=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FCLK RDYCTL#[4:0] RdyMAC1 NOP RdyMAC2 NOP RdyMAC3 NOP RdyMAC4 NOP Tx/Rx RDY(MAC1) (from decoder) Tx/Rx RDY(MAC2) (from decoder) Tx/Rx RDY(MAC3) (from decoder) Tx/Rx RDY(MAC4) (from decoder) RDYBUS[7:0] RdyMAC1 RdyMAC2 RdyMAC3 RdyMAC4 A6924-01 Figure 40: Fetch Ready Flags, Get/Send Commands, 1-2 MACs (with No External Registered Decoder) - RDYBUS_TEMPLATE_CTL[10]=1 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 8 FCLK RDYCTL# [4:0] RDYBUS[7:0] Rdy MAC1 NOP Rdy MAC1 Get Get Byte1 Get Byte2 NOP Get Byte3 Get Byte4 Send Send Byte1 Send Byte2 NOP Send Byte3 Send Byte4 A6923-01 79 Figure 41: Fetch Ready Flags, Get/Send Commands, 3+ MACs (with No External Registered Decoder) - RDYBUS_TEMPLATE_CTL[10]=0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 8 FCLK RDYCTL# [4:0] Rdy MAC1 NOP Get Send NOP NOP Tx/RxRDY(MAC1) (from decoder) Rdy MACa RDYBUS[7:0] Get Byte1 Get Byte2 Get Byte3 Get Byte4 Send Byte1 Send Byte2 Send Byte3 Send Byte4 A6922-01 Figure 42: Ready Bus Control Timing, Fetch Ready Flags - Flow Control - Fetch Ready Flags, 1-2 MACs (with No External Registered Decoder) - RDYBUS_TEMPLATE_CTL[10]=1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FCLK RDYCTL#[4:0] Rdy1 Flow Control NOP RDYBUS[7:0] Rdy1 Data Rdy2 Flow Control Mask NOP Rdy2 Data FLWCTL A6926-01 Figure 43: Ready Bus Control Timing, Fetch Ready Flags - Flow Control - Fetch Ready Flags, 1-2 MACs (with No External Registered Decoder) - RDYBUS_TEMPLATE_CTL[10]=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FCLK RDYCTL#[4:0] Rdy1 NOP Flow Cntl NOP Rdy2 NOP Rdy3 NOP Tx/Rx RDY1 (from decoder) FLWCTL# (from decoder) Tx/Rx RDY2 (from decoder) Tx/Rx RDY3 (from decoder) RDYBUS[7:0] Rdy1 Data Flow Control Mask Rdy2 Data A6927-01 80 4.3.7.5 TK_IN/TK_OUT The following timing diagrams show the transition from one IX Bus owner to another. Note that prior to giving up the bus, the PORTCTL[4:0] signals are driven high which will not select any ports. Then the signal is tri-stated and held up with weak pull-up resistors. Figure 44: IX Bus Ownership Passing Device 1 Releases Token 1 2 3 Device 2 Now Has Token 4 5 6 7 8 9 FCLK TK_OUT #1 (is TK_IN to #2 ) TK_OUT #2 FDAT[63:0] Data A PORTCTL#[7:0] FPS[2:0] TxASIS B C Notes: A = Driven by the IPX1200 Network Processor #1 if the transfer is a Tx, not driven if the transfer is a Rx. B = Driven high for one cycle by the IXP1200 #2 (no port is selected) then tristated. C = Weak external pull-up resistors will be required on PORTCTL#[7:0], FPS[2:0] and TxASIS. A7005-01 4.3.8 SRAM Interface 4.3.8.1 SRAM SCLK Signal AC Parameter Measurements Figure 45: SRAM SCLK Signal AC Parameter Measurements Tcyc Thigh Vt1 Vt2 Tlow Vt3 Tr Tf A6992-01 Vt1 = 0.5*VDDX Vt2 = 0.4*VDDX Vt3 = 0.3*VDDX 81 Table 37: SRAM SCLK Signal AC Parameter Measurements Symbol Parameter Minimum Maximum Unit Freq Clock frequency tbd 0.5*Fcore MHz Tc Cycle time 12 tbd ns Thigh Clock high time 5 --- ns Tlow Clock low time 5 --- ns Voh Output high voltage 2.4 --- V Vol Output low voltage --- 0.4 V 0.5 1 ns Tr, Tf SCLK rise/fall time 1 1. Not tested. Guaranteed by design. 4.3.8.2 SRAM Bus Signal Timing Figure 46: SRAM Bus Signal Timing CLK Tval(max) Tval(min) Outputs Ton Toff Inputs Tsu Th A6989-02 Table 38: SRAM Bus Signal Timing Symbol 82 Parameter Minimum Maximum Unit Tval Clock-to-signal valid delay 2 6 ns Tsu Input signal valid setup time before clock 3.5 (Flowthru SRAMs) 7.5 (Pipelined SRAMs) --- ns Th Input signal hold time from clock 1 --- ns Ton Float-to-active delay from clock 1 --- ns Toff Active-to-float delay from clock --- 10 ns 4.3.8.3 SRAM Bus - SRAM Signal Protocol and Timing Figure 47: Pipelined SRAM Read Burst of Eight SCLK SLOW_EN# SLOW_RD# SLOW_WR# HIGH_EN# LOW_EN# CE#<3:0> = 1110 CE#<3:0> A<18:0> A0 A1 A2 A3 A4 A5 D(A1) D(A2) D(A3) A6 A7 SWE# SOE# DQ<31:0> D(A0) D(A4) D(A5) D(A6) D(A7) A7022-02 Figure 48: Pipelined SRAM Write Burst of 8 DWords SCLK SLOW_EN# SLOW_RD# SLOW_WR# HIGH_EN# LOW_EN# CE#<3:0> = 1110 CE#<3:0> A<18:0> A0 A1 A2 A3 A4 A5 A6 A7 SWE# SOE# DQ<31:0> D(A0) D(A1) D(A2) D(A3) D(A4) D(A5) D(A6) D(A7) A7015-02 83 Figure 49: Pipelined SRAM Read Burst of Four From Bank 0 Followed by Write Burst of Four From Bank 8 SCLK SLOW_EN# SLOW_RD# SLOW_WR# HIGH_EN# LOW_EN# CE#<3:0> A<18:0> CE#<3:0> = 1110 A0 A1 A2 CE#<3:0> = 1110 A4 A3 A5 A6 A7 SWE# SOE# DQ<31:0> D(A0) D(A1) D(A2) D(A3) D(A4) D(A5) D(A6) D(A7) Idle State (see Note 1) Note 1: There is always a 1 clock clcyle idle state on the data bus when switching from read to write. A7016-02 84 Figure 50: Pipelined SRAM DWord Write Followed by 2 DWord Burst Read Followed by 4 DWord Burst Write SCLK SLOW_EN# SLOW_RD# SLOW_WR# HIGH_EN# LOW_EN# CE#<3:0> A<18:0> CE#<3:0> = 1110 A0 A1 CE#<3:0> = 1111 A3 A2 A4 A5 A6 SWE# SOE# DQ<31:0> D(A0) D(A1) D(A2) D(A3) D(A4) D(A5) D(A6) Idle State [note 1] Note 1: There is always a one clock cycle idle state on the data bus when switched from a read to write cycle. A7025-01 85 Figure 51: Flowthrough SRAM Read Burst of Eight SACLK SLOW_EN# SLOW_RD# SLOW_WR# HIGH_EN# LOW_EN# CE#<3:0> = 1110 CE#<3:0> A<18:0> A0 A1 A2 D(A0) D(A1) A3 A4 A5 A6 A7 SWE# SOE# DQ<31:0> D(A2) D(A3) D(A4) D(A5) D(A6) D(A7) A7021-02 4.3.8.4 SRAM Bus - BootROM and SlowPort Timings Timing for the BootROM and SlowPort areas are programmable through the SRAM configuration registers described in the IXP1200 Network Processor Programmer's Reference Manual. The designer should refer to this manual to understand restrictions in selecting timing values. Each timing illustration shows the appropriate register settings to generate the timing shown. 86 4.3.8.5 SRAM Bus - BootRom Signal Protocol and Timing Figure 52: BootROM Read SCLK Valid Address A<18:0> Valid DQ<31:0> SLOW_EN# SLOW_RD# SLOW_WE# LOW_EN# CH#<3:0> Valid CE Externally Generated Signal Boot ROM Chip select signal SLOW_EN# & CE#<3:0> Valid CE Cycle Count = 2 1 0 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 SLOW_EN# Deassert. (3) SLOW_RD# Deassert. (5) SLOW_RD# Assert. (9) SLOW_EN# Assert. (10) BootROM Cycle Count (11) Example for the following setting in SRAM registers SRAM_SLOW_CONFIG 31:16 15:8 7:0 RES 0x0B 0x0B SRAM SlowPort Cycle Count (Does not apply to BootROM) BootROM Cycle Count (11) Cycle time = Cycle Count + 1 (12 cycles) SRAM_BOOT_CONFIG 31:24 23:16 15:8 7:0 09 05 0A 03 SLOW__EN# Deassert. (3) SLOW__EN# Assert (10) SLOW_RD#/SLOW_WE# Deassert. (5) SLOW_RD#/SLOW_WE# Assert. (9) A7028-01 87 Figure 53: BootROM Write SCLK Valid Address A<18:0> DQ<31:0> Valid Data SLOW_EN# SLOW_RD# SLOW_WE# LOW_EN# CH#<3:0> Valid CE Externally Generated Signal BootROM Chip select signal SLOW_EN# & CE#<3:0> Valid CE Cycle Count = 2 1 0 11 10 9 8 7 6 5 SLOW_WE# Assert. (9) SLOW_EN# Assert. (10) BootROM Cycle Count (11) 4 3 2 1 0 11 10 9 SLOW_EN# Deassert. (3) SLOW_WE# Deassert. (5) Example for the following setting in SRAM registers SRAM_SLOW_CONFIG 31:16 15:8 7:0 RES 0x0B 0x0B SRAM SlowPort Cycle Count (Does not apply to BootROM) BootROM Cycle Count (11) Cyele time= Cycle Count + 1 (12 cycles) SRAM_BOOT_CONFIG 31:24 23:16 15:8 7:0 09 05 0A 03 SLOW_EN# Deassert. (3) SLOW_EN# Assert. (10) SLOW_RD#/SLOW_WE# Deassert. (5) SLOW_RD#/SLOW_WE# Assert. (9) A7029-01 88 Figure 54: Pipelined SRAM Two DWord Burst Read Followed by BootROM Write SCLK SLOW_EN# SLOW_RD# SLOW_WR# HIGH_EN# LOW_EN# CE#<3:0> A<18:0> CE#<3:0> = 1110 A1 CE#<3:0> = 1111 A2 A3 A3 D(A3) D(A3) SWE# SOE# DQ<31:0> D(A1) D(A1) D(A2) DQ<31:0> BootROM_CE#<3:0> D(A3) D(A3) BootROM_CE# = -(-SLOW_EN# & -CE#) A7023-01 89 4.3.8.6 SRAM Bus - Slow-Port Device Signal Protocol and Timing Figure 55: SRAM SlowPort Read SCLK Valid Address A<18:0> Valid DQ<31:0> SLOW_EN# SLOW_RD# SLOW_WE# LOW_EN# SP_CE# Externally Generated Signal SRAM SlowPort Chip select signal - SP_CE# & address Cycle Count = 2 Valid CE 1 0 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 SLOW_EN# Deassert. (3) SLOW_RD# Deassert. (5) SLOW_RD# Assert. (9) SP_CE#/SLOW_EN# Assert. (10) BootROM Cycle Count (11) Example for the following setting in SRAM registers SRAM_SLOW_CONFIG 31:16 15:8 7:0 RES 0x0B 0x0B SRAM Slow Port Cycle Count (11) Cycle time = Cycle Count + 1 (12 cycles) BootROM Cycle Count (Does not apply to SRAM SlowPort) SRAM_SLOWPORT_CONFIG 31:24 23:16 15:8 7:0 09 05 0A 03 SP_CE#/SLOW_EN# Deassert. (3) SP_CE#/SLOW_EN# Assert. (10) SLOW_RD#/SLOW_WE# Deassert. (5) SLOW_RD#/SLOW_WE# Assert. (9) A7026-01 90 Figure 56: SRAM SlowPort Write SCLK A<18:0> Valid Address DQ<31:0> Valid Data SLOW_EN# SLOW_RD# SLOW_WE# LOW_EN# SP_CE# Externally Generated Signal SRAM SlowPort Chip select signal - SP_CE# & address Cycle Count = 2 Valid CE 1 0 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 SLOW_EN# Deassert. (3) SLOW_RD# Deassert. (5) SLOW_WE# Assert. (9) SP_CE#/SLOW_EN# Assert. (10) BootROM Cycle Count (11) Example for the following setting in SRAM registers SRAM_SLOW_CONFIG 31:16 15:8 7:0 RES 0x0B 0x0B SRAM SlowPort Cycle Count (11) Cycle time = Cycle Count + 1 (12 cycles) BootROM Cycle Count (Does not apply to SRAM SlowPort) SRAM_SLOWPORT_CONFIG 31:24 23:16 15:8 7:0 09 05 0A 03 SP_CE#/SLOW_EN# Deassert. (3) SP_CE#/SLOW_EN# Assert. (10) SLOW_RD#/SLOW_WE# Deassert. (5) SLOW_RD#/SLOW_WE# Assert. (9) A7027-01 91 Figure 57: Pipelined SRAM 2 Dword Burst Read Followed By SlowPort Write SCLK SP_CE# SLOW_EN# SLOW_RD# SLOW_WR# HIGH_EN# LOW_EN# CE#<3:0> A<18:0> CE#<3:0> = 1110 A1 A2 A3 A3 D(A3) D(A3) SWE# SOE# DQ<31:0> Buffered DQ<31:0> D(A1) D(A2) D(A3) D(A3) BootROM_CE#<3:0> A7024-01 92 4.3.9 SDRAM Interface 4.3.9.1 SDCLK AC Parameter Measurements Figure 58: SDCLK AC Timing Diagram Tcyc Thigh Vt1 Vt2 Tlow Vt3 Tr Tf A6992-01 Vt1 = 0.5*VDDX Vt2 = 0.4*VDDX Vt3 = 0.3*VDDX Table 39: SDCLK AC Parameter Measurements Symbol Parameter Minimum Maximum Unit Freq Clock frequency tbd 0.5*Fcore MHz Tcyc Cycle time 12 tbd ns Th Clock high time 5 --- ns Tl Clock low time 5 --- ns Voh Output high voltage 2.4 --- V Vl Output low voltage --- 0.4 V 0.5 1 ns Tr, Tf SDCLK rise/fall time 1 1. Not tested. Guaranteed by design. 93 4.3.9.2 SDRAM Bus Signal Timing Figure 59: SDRAM Bus Signal Timing SDCLK Tval(max) Tval(min) MDAT (output) Ton Toff MDAT (input) Tsu control outputs (RAS#, CAS#, WE#, DQM, MADR) Th tCTL(max) tCTL(min) A6990-01 Table 40: SDRAM Bus Signal Timing Parameters Symbol 94 Parameter Minimum Maximum Unit Tval Clock-to-data output valid delay 1 4.5 ns Tsu Input data setup time before clock 0.5 * Tcyc --- ns Th Input data hold time from clock 1 --- ns Ton Float-to-active data delay from clock 1 --- ns Toff Data Active-to-float delay from clock --- 10 ns tCTL Clock to control output low valid delay 4 9 ns 4.3.9.3 SDRAM Signal Protocol Figure 60: SDRAM Initialization Sequence INIT_DLY tRP tRSC tRc SDCLK RAS# CAS# WE# MADR MDAT DQM Precharge all banks Mode Register Set Command (see note 2) Auto Refresh Auto Refresh (see note 1) Notes: 1. Number of total initialization phase refresh cycles programmed as INIT_RFRSH value in register SDRAM_MEMINIT. 2. Burst length and CAS latency values programmed as BURSTL value in register SDRAM_MEMCTL0 emitted in this cycle. 3. INIT_DLY, tRSC values programmed into register SDRAM_MEMINIT. 4. tRP, tRC values programmed into register SDRAM_MEMCTL1 5. tRSC is minimum SDRAM programmable register value. In actual use, refresh cycles will not occur immediately after tRSC cycles due to SDRAM unit internal pipeline delays. A7009-01 95 Figure 61: SDRAM Read Cycle tRASmin tDQZ tRCD SDCLK RAS# tRP CAS# WE# MADR MDAT DQM Read command Activate command Precharge command (terminates access) DQM remains high until next read or write command Notes: 1. Parameters tRWT, tDPL, tDQZ, tRC, tRRD, tRCD, tRASmin, and tRP programmed into register SDRAM_MEMCTL1 2. CAS Latency value (CASL) = 3 programmed in SDRAM_MEMCTL0 A7012-01 Figure 62: SDRAM Write Cycle tRASmin tDPL tRCD SDCLK RAS# tRP CAS# WE# MADR MDAT DQM Activate command Write command Precharge command (terminates access) DQM remains high until next read or write command Notes: 1. Parameters tRWT, tDPL, tDQZ, tRC, tRRD, tRCD, tRASmin, and tRP programmed into register SDRAM_MEMCTL1 2. CAS Latency value (CASL) = 3 programmed in SDRAM_MEMCTL0 A7011-01 96 Figure 63: SDRAM Read-Modify-Write Cycle tRASmin tRCD tDPL tDQZ tRWT SDCLK RAS# CAS# WE# MADR MDAT DQM Activate command Read command DQM remains high Write during modify command Precharge command DQM remains high until next read or write command Notes: 1. Parameters tRWT, tDPL, tDQZ, tRC, tRRD, tRCD, tRASmin, and tRP programmed into register SDRAM_MEMCTL1 2. CAS Latency value (CASL) = 3 programmed in SDRAM_MEMCTL0 A7010-01 4.4 Asynchronous Signal Timing Descriptions RESET_IN must remain asserted for 150 ms after VDD and VDDX are stable to properly reset the IXP1200 Network Processor. RESET_OUT is asserted for all types of reset (hard, watchdog, and software) and appears on the pin asynchronously to all clocks. TRST# TBD. GPIO<3:0> are read and written under software control. When writing a value to these pins, the pins transition approximately 20 ns after the write is performed. When reading these pins, the signal is first synchronized to the internal clock and must be valid for at least 20 ns before it is visible to a processor read. TXD, RXD are asynchronous relative to any device outside the IXP1200 Network Processor. 97 SECTION 5 - MECHANICAL SPECIFICATIONS 5.1 Package Dimensions The IXP1200 Network Processor is contained in a 432BGA package, as shown in the following illustrations. Figure 64: IXP1200 Network Processor Part Marking (TBD) Figure 65: 432-BGA Package - Bottom View D D1 b0 A1 Ball Corner 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0.30 A C A S A S A B C D E F G H J K L M N P R T U V W X S A E1 E AA AB AC AD AE AF AG AH AJ AK AL e S e A A7063-01 98 Figure 66: IXP1200 Network Processor Side View A A2 bbb C ccc aaa -C- Seating Plane A1 A7064-01 Figure 67: IXP1200 Network Processor A-A Section View P d ddd A7043-01 5.2 IXP1200 Network Processor Package Dimensions (mm) Table 41: IXP1200 Network Processor Package Dimensions (mm) Symbol Definition Minimum Nominal Maximum A Overall thickness 1.41 1.54 1.67 A1 Ball height 0.56 0.63 0.70 A2 Body thickness 0.85 0.91 0.97 D Body size 39.90 40.00 40.10 D1 Ball footprint 38.00 38.10 38.20 E Body size 39.90 40.00 40.10 E1 Ball footprint 38.00 38.10 38.20 b Ball diameter 0.60 0.75 0.90 aaa Coplanarity -- -- 0.15 bbb Parallel -- -- 0.15 ccc Top flatness -- -- 0.20 ddd [8] Seating plane clearance 0.15 0.33 0.50 P Encapsulation height 0.20 0.30 0.35 S Solder ball placement -- -- 0.00 M, N Ball matrix -- 31 x 31 -- M1[7] Number of rows deep -- 4 -- 99 Table 41: IXP1200 Network Processor Package Dimensions (mm) - continued Symbol Definition Minimum Nominal Maximum d Minimum distance, encap to balls -- 0.6 -- e Ball pitch -- 1.27 -- NOTES: 1. All dimensions and tolerances conform to ANSI Y1.45M-1982. 2. Dimension "b" is measured at the maximum solder ball diameter parallel to primary datum "c". 3. Primary datum "c" and seating plane are defined by the spherical crowns of the solder balls. 4. Pin A1 I.D. marked by ink. 5. Shape at corner, single form. 6. All dimensions are in millimeters. 7. Number of rows in from edge to center. 8. Height from ball seating plane to plane of encapsulant. 9. S is measured with respect to -A- and -B- and defines the position of the center solder ball in the outer row. When there is an odd number of solder balls in the outer row, S=0.000; when there is an even number of solder balls in the outer row, the value S=e/2. S can be either 0.000 or e/2 for each variation. 10.The dimension from the outer edge of the resin dam to the edge of the innermost row of the solder ball pads is to be a minimum of 0.50 mm. 100 5.3 Package Pin Layout with Power and Ground Figure 68: IXP1200 Network Processor Package Pin Layout with Power and Ground 1 A B A C DB C E D F E G F H G J H K J L K M L N M P N R P T R U T V U W V Y W AA Y AB AA AC AB AD AC AE AD AF AE AG AF AH AG AJ AH AK AJ AL AK AL 1 2 2 3 4 3 4 5 5 6 6 7 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Intel(R) StrongARM(R)* IXP1200 Ball Ball Grid Grid SA-1200 TopView View Top VDDX (I/O Supply) - 3.3 V VDD (Core Supply) - 2.0 V VDDX (I/O Supply) - 3.3 V VDDP1 (PLL Supply) - 2V VDD (Core Supply) - 2.0 V VSS VDDP1 (PLL Supply) - 2V VSSP1 VSS VDD_REF (Refernce Supply) - 3.3V VSSP1 VDD_REF (Refernce Supply) - 3.3V * StrongARM is a registered trademark of ARM LImited. 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Additional patents pending. 5,008,637; 5,028,888; 5,057,794; 5,059,924; 5,068,628; 5,077,529; 5,084,866; 5,148,427; 5,153,875; 5,157,690; 5,159,291; 5,162,746; 5,166,635; 5,181,228; 5,204,880; 5,249,183; 5,257,286; 5,267,269; 5,267,746; 5,461,661; 5,493,243; 5,534,863; 5,574,726; 5,581,585; 5,608,341; 5,671,249; 5,666,129; 5,701,099