10
2.3 IX Bus Interface Unit
and IX Bus
The IX Bus Interface Unit is respon sible f or servicing fast
peripherals, such as MAC-layer devices, on the IX Bus
(FIFO Bus). This includes moving data to and from the
IXP1200 Network Processor Receive and T rans mit FIFOs.
The IX Bus provides a 4.2 Gb/s interface to peripheral
devices. The IX Bus was specifically designed to provide
a simple and efficient interface. The IX Bus can be
configured as either a 64-bit, bidirectional bus or as two
32-bit, unidirectional buses operating at up to 66 MHz.
The IX Bus Interface Unit contains the Transmit and
Receive FIFO elements, chip-level Control Status
Registers (CSRs), a 4 Kbyte Scratchpad RA M, and a Hash
Unit for generating 48- and 64-bit hash keys.
The IX Bus consists of 64 data pins, 23 control pins, and a
clock input pin with a typical operating frequency of
66 MHz. A sideband control bus operating in parallel to
the IX Bus, called the ReadyBus, consists of eight
additional data pins and five control pins.
The ReadyB us i s sy nchr ono us t o t he I X Bu s cl o ck, but it’s
operation is controlled by a programmable hardware
sequencer. ReadyBus cycles are separate and distinct from
IX Bus cycles. Up to twelve sequencer commands are
loaded at chip initialization time, and run in a continuous
loop. The commands can consist of sampling FIFO status
for the IX Bus d evices, sen ding Flow Co ntrol m essages to
MAC devices, and reads/writes to other IXP12 00 Network
Processor devices as required by the application design.
Refer to the IXP1200 Network Processor Hardware
Reference Manual f or specific details on using the
ReadyBus.
2.3.1 IX Bu s Access Behavior
There are two basic modes of IX Bus operation. This is a
configuration option only and is not intended to be used
“on the fly” to switch bet ween mo des.
•64-Bit Bidirectional Mode
The entire 64-bit data path FDAT[63:0] is used for
reads, or writes to IX Bus devices. The IXP1200
Network Processor will always drive and receive all
64-bits of the IX Bu s in this mode. Valid bytes are
indicated on FBE[7:0] driven by the IXP1200
Network Processor du ring writes, and by the tar get IX
Bus resource on reads.
•32-bit Unidirectiona l Mode
The IX Bus is split into independent 32-bit Transmit
and 32-bit Receive data paths . T rans mit data is driven
on FDAT[63:32] and Receive data is input on
FDAT[31:0]. In this mod e, the Transmit path is
always driven, and the Receive path is always an
input. Valid bytes ar e identif ied for the Transmit path
by FBE[7:4] signals. Valid bytes are identified for the
Receive path by FBE[3:0].
Each basic mode has two additional modes depending on
the number of IX Bus devices and ports being used. 1-2
MAC mode for a one or t wo devices, and 3+ MAC mode
when using three to seven devices. Bus timing, and the
functions of the IX Bus signals are slightly different in
each mode. These functional definitions per IX Bus mode
are listed in Section 3.6 and Section 3.7.
In addition, a shared IX Bus mode is supported in 64-bit
Bidirectional mode. Refer to the list at the bottom of Table
20 for the signals that the IX Bus masters must drive and
IX Bus slaves must tri-state.
The IX Bus, and Level OneTM devices using the IX Bus
such as the IXF440 Octal Fast Ethernet Media Access
Controller and the IXF1002 Dual Port Gigabit Ethernet
Media Access Controller observe a pipelined bus pro tocol.
When cycles are ended early on receive cycles, the
pipeline continues to cause several extra bus cycles
depending on when th e EOP sign al was as s erted. Data is a
“don't c are” for these trailing bus cycles, except in the case
of a status transfer where the IX Bus burst includes a
possible status transfer if the device were pr ogrammed to
support it.
The tables below show the number of total IX Bus data
cycles that will occur for a burst with EOP ass er ted at
specific clocks for 64 bit and 32 bit IX Bus modes. In each
case, the tables show IX Bus cycles with and without the
optional status transfer cycle. Refer to the IX Bus Protocol
Timing diagrams (Figure 17 through Figure 37) when
interpreting these tables.
Table 1: 64-bit IX Bus Receive Rem ainder Cycles, No Status Transfer
EOP signaled on this
cycle: 12345678
# of bus cycles in burst: 56788888
# of Don’t Care cycles: 44443210