© 2011 Microchip Technology Inc. DS80526B-page 1
dsPIC33EPXXX(GP/MC/MU)806/810/814
and PIC24EPXXX(GP/GU)810/814
The dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 family devices that you
have received conform functionally to the current
Device Data Sheet (DS70616F), except for the
anomalies described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the dsPIC33EPXXX(GP/MC/
MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
silicon.
Data Sheet clarifications and corrections start on page
13, following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s
programmers, debuggers and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 3 or
PICkit™ 3:
1. Using the appropriate interface, connect the device
to the MPLAB ICD 3 programmer/debugger or
PICkit 3.
2. From the main menu in MPLAB IDE, select
Configure>Select Device, and then select the
target part number in the dialog box.
3. Select the MPLAB hardware tool
(Debugger>Select Tool).
4. Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the devel-
opment tool used, the part number and Device
Revision ID value appear in the Output window.
The Device and Revision ID values for the various
dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 silicon revisions are
shown in Table 1.
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon
revision (B1).
Note: If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
TABLE 1: SILICON DEVREV VALUES
Part Number Device ID(1) Revision ID for Silicon Revision(2)
B1
dsPIC33EP256MU806 0x1861
0x4002
dsPIC33EP256MU810 0x1862
dsPIC33EP256MU814 0x1863
PIC24EP256GU810 0x1826
PIC24EP256GU814 0x1827
dsPIC33EP512MU810 0x1872
dsPIC33EP512MU814 0x1873
dsPIC33EP512GP806 0x187D
dsPIC33EP512MC806 0x1879
Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
2: Refer to the “dsPIC33E/PIC24E Flash Programming Specification” (DS70619) for detailed information on
Device and Revision IDs for your specific device.
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/
GU)810/814 Family Silicon Errata and Data Sheet Clarification
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS80526B-page 2 © 2011 Microchip Technology Inc.
PIC24EP512GU810 0x1836
0x4002PIC24EP512GU814 0x1837
PIC24EP512GP806 0x183D
TABLE 1: SILICON DEVREV VALUES (CONTINUED)
Part Number Device ID(1) Revision ID for Silicon Revision(2)
B1
Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
2: Refer to the “dsPIC33E/PIC24E Flash Programming Specification” (DS70619) for detailed information on
Device and Revision IDs for your specific device.
© 2011 Microchip Technology Inc. DS80526B-page 3
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
TABLE 2: SILICON ISSUE SUMMARY
Module Feature Item
Number Issue Summary
Affected
Revisions(1)
B1
I/O
Multiplexer
Open Drain
Feature
1. The open drain control signal from GPIO, PORTA bit 3, is
inadvertently controlling the data output of bit 15 of PORTC.
X
CPU DSP DO
Instruction
2. The assembly language DO instruction does not function
correctly with nested loops when the inner loop count is zero
(one iteration).
X
CPU div.sd
Instruction
3. When using the div.sd instruction, the overflow bit is not
getting set when an overflow occurs.
X
PPS Virtual Remap 4. Virtual pin remapping does not work correctly. X
SPI Frame Sync
Pulse
5. Frame sync pulse not generated in Master mode when
FRMPOL = 0.
X
SPI Frame Sync
Pulse
6. When in SPI Slave mode, with the frame sync pulse set as an
input, FRMDLY must be set to ‘0’.
X
PWM Dead Time
Compensation
7. The duty cycle is not correct when using dead time and the
programmed duty cycle is close to 0% or 100%.
X
PWM Dead Time
Compensation
8. Dead Time Compensation is not enabled for Center Aligned
PWM Mode.
X
Power
System
BOR 9. BOR must always be enabled. X
Reserved — 10. ——
ECAN™ CANCKS 11. The function of the CANCKS bit is reversed. X
ECAN ERRIF 12. The ERRIF status bit does not get set when a CAN error
condition occurs.
X
USB LS through
Hub
13. The USB bus might not be returned to the J-state following an
acknowledgement packet when running low-speed through a
hub.
X
USB UIDLE
Interrupt
14. UIDLE interrupts cease if the UIDLE interrupt flag is cleared. X
DMA CAN 15. Possible loss of interrupts when DMA is used with CAN. X
UART TX Interrupt 16. A TX Interrupt may occur before the data transmission is
complete.
X
UART UTXBRK 17. When a Read-Modify-Write operation is performed to set or
clear any bit(s) in the UxSTA register while hardware is
clearing the UTXBRK bit, the UTXBRK bit may remain set.
X
UART UARTEN 18. The transmitter write pointer does not get cleared when the
UART is disabled (UARTEN = 0), it requires TXEN to be set in
order to clear the write pointer.
X
I2C™ I2CxCON 19. When a Read-Modify-Write operation is performed to set or
clear any bit(s) in the I2CxCON register while hardware is
clearing the ACKEN bit, the ACKEN bit may remain set.
X
ADC DONE bit 20. The ADC Conversion Status bit, DONE (ADxCON1<0>), does
not indicate completion of conversion when External Interrupt is
selected as the ADC trigger source (ADxCON1<SSRC> = 1).
X
PMP —21. On the dsPIC33EPXXXGU814 or PIC2EPXXXMU814
devices, the PMCS1/PMA14 and PMCS2/PMA15 pin
functionality is duplicated on the RJ14/15 pins in addition to
the expected RK11/RK12 pins.
X
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS80526B-page 4 © 2011 Microchip Technology Inc.
Flash
Memory
ICSP™ 22. If either the General or Auxiliary Segment is protected, neither
segment can be read.
X
Flash
Memory
Programming 23. Stall mechanism may not function properly when erasing or
programming Flash memory while executing code from the
same Flash segment.
X
Power
System
Flash
Regulator
24. The RCON<VREGSF> bit always reads as ‘0’. X
PWM Dead Time 25. When operating in Edge-Aligned Complimentary mode the
dead time could become zero.
X
QEI Index Counter 26. The QEI Index Counter does not count correctly in Quadrature
Detector mode.
X
QEI Modulo Mode 27. Modulo mode functionality is incorrect when the Count Polarity
bit is set.
X
CPU DO Loop 28. PSV access, including table reads or writes, in the last
instruction of a DO loop are not allowed.
X
PWM Master Time
Base Mode
29. In Master Time Base mode, writing to the period register and
any other timing parameter of the PWM module will cause the
update of the other timing parameter to take effect one PWM
cycle after the period update is effective.
X
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature Item
Number Issue Summary
Affected
Revisions(1)
B1
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
© 2011 Microchip Technology Inc. DS80526B-page 5
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
Silicon Errata Issues
1. Module: I/O Multiplexer
The open drain control signal from GPIO PORTA,
bit 3, is inadvertently controlling the data output of
bit 15 of PORTC.
Work around
There is no work around. If bit 15 of PORTC is
being used as an output (FOSC<OSCIOFNC> = 0
and TRISC<15> = 0), the open drain capability for
bit 3 of PORTA cannot be enabled and used as an
open drain output (ODCA<3> ≠ 1).
This issue only applies when the OSC2 pin
function is set for general purpose digital I/O
(FOSC<ISCIOFNC> = 0) and the device is using
the FRC or EC Primary Oscillator modes.
Affected Silicon Revisions
2. Module: CPU
The assembly language DO instruction does not
function correctly with nested loops when the inner
loop count is zero (one iteration).
Work arou nd
With nested DO loops where an inner loop can
have a single iteration (DCOUNT = 0), one of the
following precautions must be taken for proper
operation:
1. Insert a NOP immediately after the DO
instruction, which can contain a loop count
of zero, and insert two NOP instructions
immediately following the DO instruction of
the next outer loop, as shown in Example 1.
2. Alternatively, the code can test for a count
of zero and branch over the DO instruction
for all nested loops. In this case, insertion of
NOP instructions is not required.
This issue does not apply if there are no nesting of
DO loops or if all of the inner loop counts are always
greater than zero. When a nested DO loop has a
count of zero, only the immediate next outer loop
will be affected.
Affected Silicon Revisions
EXAMPLE 1:
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B1).
B1
X
Note: This silicon issue applies only to the
dsPIC33EPXXXGP/MC/MU806/810/814
devices.
B1
X
do w0, out_lp ; w0 contains the count for the outer loop
nop ; 2 NOPs are added for the work around
nop ;
… ; user code
do w1, in_lp ; w1 contains count for the inner loop
nop ; A Single NOP is the required work around for the inner loop
… ; user code
in_lp: ; end of inside loop
…
out_lp: ; end of outside loop
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS80526B-page 6 © 2011 Microchip Technology Inc.
3. Module: CPU
When using the Signed 32-by-16-bit Division
instruction, div.sd, the overflow bit does not
always get set when an overflow occurs.
Work around
Test for and handle overflow conditions outside of
the div.sd instruction.
Affected Silicon Revisions
4. Module: PPS
Virtual pin remapping does not work.
Work around
Virtual remapping applies to comparator outputs
and the QEI Home and Index functions:
1. Comparator outputs can be connected to a
peripheral input by mapping both the com-
parator output and the peripheral input to an
unused physical pin using the peripheral
pin select feature.
The following example assumes that there is
no connection to the RP127/RG15 pin on the
device. The following statements connect
Comparator Output 1 to Input Capture IC1
using RP127.
RPINR7bits.IC1R = 127;
/*assign Input Capture 1 to RP127*/
RPOR15bits.RP127R = 0b011000;
/*assign RP127 to Comparator Output 1*/
2. The FCLCONx register can be used to map
comparator outputs to PWM fault inputs
without the use of virtual remapping.
The following statement will connect
Comparator 1 output to Fault Control Signal
Source for PWM 1.
FCLCON1bits.FLTSRC = 8;
/* value of 0b01000 selects Comp. 1 */
3. FHOMEx and FINDXx are not accessible,
making the digital filter in the QEI module
unusable for any other peripheral besides
the QEI. There is no work around.
Affected Silicon Revisions
5. Module: SPI
When using the frame sync pulse output feature
(SPIxCON2<FRMEN> = 1) in Master Mode
(SPIxCON2<SPIFSD> = 0), the frame sync pulse
is not being generated with an active low pulse
(SPIxCON2<FRMPOL> = 0).
Work aro und
The SS pin is used as the frame sync pulse when
the frame sync pulse output feature is used.
Mapping the SSx input function and output
function to the same pad using the PPS feature
resolves this issue.
The following code example assigns SPI1 SS
input and SPI1 SS output to RP118.
RPINR21bits.SS1R = 118;
/* assign the SPI1 Slave Select Input to
RP118 */
RPOR13bits.RP118R = 0b000111;
/* assign peripheral output function SPI1
to RP118 */
Affected Silicon Revisions
6. Module: SPI
When in SPI Slave mode (SPIxCON1<MSTEN> =
0) and using the frame sync pulse output feature
(SPIxCON2<FRMEN> = 1) in Slave Mode
(SPIxCON2<SPIFSD> = 0), the Frame Sync
Pulse Edge Select bit must be set to ‘0’
(SPIxCON2 <FRMDLY> = 0)
Work aro und
There is no work around. The Frame Sync Pulse
Edge Select bit cannot be set to produce a Frame
sync pulse that coincides with the first bit clock.
Affected Silicon Revisions
B1
X
B1
X
B1
X
B1
X
© 2011 Microchip Technology Inc. DS80526B-page 7
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
7. Module: PWM
When dead time compensation is enabled
(PWMCONx<DTC> = 11) in Edge-Aligned mode
(PWMCONx<CAM> = 0), the setting of the
DTCP<1:0> bits (PWMCONx<7:6>) and the
external signal DTCMPx, determine whether the
DTRx register is added to or subtracted from the
duty cycle specified by the PDCx or MDC
registers.
When DTR is being subtracted from the duty cycle,
the resulting duty cycle will be 0% if the
programmed duty cycle, minus two times the DTR
value, is less than ‘0’.
Duty Cycle = 0% when (PDCx – 2 DTR)
< 0 if MDCS = 0 (PWMCONx<8>)
or
(MDC – 2 DTR) < 0 if MDCS = 1
(PWMCONx<8>)
When DTR is being added to the duty cycle, the
resulting duty cycle will be 100% if the
programmed duty cycle, plus two times the DTR
register, is greater than the period.
Duty Cycle = 100% when (PDCx + 2 DTR)
≥ Period if MDCS = 0 (PWMCONx<8>)
or
(MDC + 2 DTR) ≥ Period if MDCS = 1
(PWMCONx<8>)
The period is specified by the PTPER, STPER or
PHASEx registers, depending on the ITB
(PWMCON<9>) and MTBS (PWMCONx<3>) bit
settings.
Work around
If using dead time compensation, do not use duty
cycle values that are less than two times the DTR
value or that are greater than or equal to the period
less two times the DTR value.
Affected Silicon Revisions
8. Module: PWM
When dead time compensation is enabled
(PWMCONx<DTC> = 11) in Center-Aligned mode
(PWMCONx<CAM> = 1), the dead time, as
specified in the ALTDTRx register, is not being
applied to the PWMxH output. The leading and
trailing edges of the PWMxL output are extended
by one-half the value of the ALTDTRx register, but
the PWMxH leading and trailing edges are
unaffected.
Work arou nd
Using the values from Section 14. “High-Speed
PWM” (DS70645), adjust the PWM parameters as
follows:
• Subtract one-half of the ALTDTR dead time
from PDCx
• Use twice the value for ALTDTR. For example:
- Frequency of 60 kHz, duty cycle of 50%
- Desired dead time of 833 ns and dead time
compensation of 833 ns
Using the specified values from Section 14.
“High-Speed PWM” (DS70645):
• PHASEx = 1000
• PDCx = 500
• ALTDTR = 833 ns/8.33 ns = 100
• DTR = (833 ns/8.33 ns)/2 = 50
Applying the work around:
• ALTDTR = 2 * 100 = 200
• PDCx = PDCx – 25 = 475
Affected Silicon Revisions
9. Module: Power System
For this version of silicon, the Brown-out Reset
(BOR) must always be enabled.
Work arou nd
Do not disable the BOR by setting BOREN = 0
(FPOR<3>) or by setting SBOREN = 0
(RCON<13>).
Affected Silicon Revisions
Note: The dead time values, as specified in the
ALTDTRx register, are not part of the
equations shown above, and are still
applied when the duty cycle is not forced
to 0% or 100%.
B1
X
B1
X
B1
X
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS80526B-page 8 © 2011 Microchip Technology Inc.
10. Module: Reserved
11. Module: ECAN™
The CANCKS (CiCTRL1<11>) function is
reversed.
Work around
Set CiCTRL1<CANCKS> = 0 to obtain an FCAN
equal to twice FCY or CiCTRL1<CANCKS> = 1 to
obtain an FCAN equal to FCY. This bit must be set
to ‘1’ for compatibility with the dsPIC33F or
PIC24H. At reset it is set to ‘0’.
Affected Silicon Revisions
12. Module: ECAN
The ERRIF status flag (CiINTF<5>) does not get
set when a CAN error condition occurs, and as a
result, an interrupt is not generated even if
enabled.
Work around
Use the Invalid Message Interrupt (IVRIF) to
inspect the individual error condition status flags
TXBO, TXBP, RXBP, TXWAR, RXWAR and
EWARN (CiINTF<13:8>) to determine if an error
condition has occurred.
Affected Silicon Revisions
13. Module: USB
While operating in Host mode and attached to a
low-speed device through a full-speed USB hub,
the host may persistently drive the bus to an SE0
state (both D+/D- as ‘0’), which would be
interpreted as a bus Reset condition by the hub; or
the host may persistently drive the bus to a J state,
which would make the hub detach condition
undetectable by the host.
Work aro und
Connect low-speed devices directly to the Host
USB port and not through a USB hub.
Affected Silicon Revisions
14. Module: USB
In the case where the bus has been idle for > 3 ms,
and the UIDLE interrupt flag is set, if software
clears the interrupt flag, and the bus remains idle,
the UIDLE interrupt flag will not be set again.
Work aro und
Software can leave the UIDLE bit set until it has
received some indication of bus resumption.
(Resume, Reset, SOF, or Error).
Affected Silicon Revisions
B1
X
B1
X
B1
X
Note: Resume and Reset are the only interrupts
that should occur following UIDLE
assertion. If, at any point in time, the
UIDLE bit is set, it should be okay to
suspend the USB module (as long as this
code is protected by the GUARD and/or
ACTPEND logic). Note that this will
require software to clear the UIDLE
interrupt enable bit to exit the USB ISR (if
using interrupt driven code).
B1
X
© 2011 Microchip Technology Inc. DS80526B-page 9
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
15. Module: DMA
When the DMA is set up for CAN receive,
interrupts can sometimes be lost if the DMA is held
in an “OFF” state by the system arbiter. If a CAN
receive interrupt occurs while the DMA is waiting
for a grant for the previous CAN transaction, this
current interrupt will be dropped.
Work arounds
There are two possible work arounds for this issue:
1. Use Dual Port RAM (If available) for target
DMA memory; the DMA cannot be held
“OFF” when accessing the back side of
DPRAM. Only channels set up for CAN
receive would need to use DPRAM; all
other peripherals can use any RAM.
2. Elevate the system priority of DMA by writ-
ing a 0x20 to the MSTRPR (Master Priority)
SFR register (address 0x0058). This will
also prevent the DMA from being held
“OFF”.
Affected Silicon Revisions
16. Module: UART
When using UTXISEL = 01 (Interrupt when last
character is shifted out of the Transmit Shift
Register), and the final character is being shifted
out through the Transmit Shift Register, the TX
interrupt may occur before the final bit is shifted
out.
Work arou nd
If it is critical that the interrupt processing occurs
only when all transmit operations are complete,
after which the following work around can be
implemented:
Hold off the interrupt routine processing by adding
a loop at the beginning of the routine that polls the
transmit shift register empty bit, as shown in
Example 2.
Affected Silicon Revisions
EXAMPLE 2:
B1
X
B1
X
// in UART2 initialization code
...
U2STAbits.UTXISEL0 = 1; // Set to generate TX interrupt when all
U2STAbits.UTXISEL1 = 0; // transmit operations are complete.
...
U2TXInterrupt(void)
{
while(U2STAbits.TRMT==0); // wait for the transmit buffer to be empty
... // process interrupt
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS80526B-page 10 © 2011 Microchip Technology Inc.
17. Module: UART
When a Read-Modify-Write operation is performed
to set or clear any bit(s) in the UxSTA register while
hardware is clearing the UTXBRK bit (UxSTA<11>),
the UTXBRK bit may remain set. BSET and BCLR
are examples of Read-Modify-Write instructions.
Work around
Wait for the UTXBRK bit to get cleared by
hardware, before performing a Read-Modify-Write
operation on the UxSTA register.
Affected Silicon Revisions
18. Module: UART
The transmitter write pointer does not get cleared
when the UART module is disabled
(UARTEN = 0), and it requires the TXEN bit to be
set in order to clear the write pointer.
Work around
Do not load data into the TX FIFO (register) before
setting the TXEN bit.
Affected Silicon Revisions
19. Module: I2C™
When a Read-Modify-Write operation is performed
to set or clear any bit(s) in the I2CxCON register
while hardware is clearing the ACKEN bit
(I2CxCON<4>), the ACKEN bit may remain set.
BSET and BCLR are examples of Read-Modify-Write
instructions.
Work around
Wait for the ACKEN bit to get cleared by hardware
before performing a Read-Modify-Write operation
on the I2CxCON register.
Affected Silicon Revisions
20. Module: ADC
The ADC Conversion Status bit, DONE
(ADxCON1<0>), does not indicate completion of
conversion when External Interrupt is selected as
the ADC trigger source (ADxCON1<SSRC> = 1).
Work aro und
Use ADC interrupt or poll ADxIF (in the IFSx
registers) bit to determine the completion of
conversion.
Affected Silicon Revisions
21. Module: PMP
When PTEN14 = 1 (PMAEN<14>), the PMA<14> or
PMCS1 functionality is present on the PMCS1/RK11
(pin 94) and RJ14 (pin 21).
When PTEN15 = 1 (PMAEN<15>), the PMA<15> or
PMCS2 functionality is present on the PMCS2/
RK12 (pin 93) and RJ15 (pin 22).
Work aro und
None.
Affected Silicon Revisions
22. Module: Flash Memory
If code or write protection is enabled on either the
General Segment or Auxiliary Segment, neither
segment can be read by the programmer. Code or
write protection is enabled for the General Segment
when the GSS (FGS<1>) or GWRP (FGS<0>) bits
are ‘0’. Code or write protection is enabled for the
Auxiliary Segment when the APL (FAS<1>) or
AWRP (FAS<0>) bits are ‘0’.
Work aro und
None.
Affected Silicon Revisions
B1
X
B1
X
B1
X
B1
X
Note: This silicon issue applies only to
dsPIC33EPXXXMU814 and
PIC24EPXXXMC814 devices.
B1
X
Note: This silicon issue applies only to In-
Circuit Serial Programming™
(ICSP™) mode.
B1
X
© 2011 Microchip Technology Inc. DS80526B-page 11
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
23. Module: Flash Memory
The processor stalls while performing Run-Time
Self-Programming (RTSP) erase and write
operations on the same Flash segment (General or
Auxiliary) from which code is being executed. The
stall mechanism does not always function properly
and can cause unexpected behavior.
Work arounds
Two options are available to avoid this issue:
1. If you are required to execute code, includ-
ing an Interrupt Service Routine (ISR), from
the same segment (either General or Auxil-
iary) that you are performing RTSP opera-
tions on, you must disable interrupts until
the erase or programming operation is
complete (see Example 3).
2. If possible, structure your project such that
RTSP operations are performed on a seg-
ment from which no code is being executed.
For example, place all of your executable
code in the General Segment and all repro-
grammable data in the Auxiliary Segment or
vice versa. This solution has the added
advantage that no CPU stalls occur since
the programming operation is not being
performed on the same segment that is
executing the code.
EXAMPLE 3:
Affected Silicon Revisions
24. Module: Power System
The VREGSF bit functions as documented, but will
always read as ‘0’. Because of the Read-Modify-
Write process, any BSET or BCLR instruction of the
RCON register will also write a ‘0’ to the VREGSF
bit.
Work arou nd
If the VREGSF bit is intended to be set to a ‘1’, the
user must also write a ‘1’ to the VREGSF bit when
setting or clearing any other bit in the RCON
register.
Affected Silicon Revisions
25. Module: PWM
When operating in Edge-Aligned Complimentary
mode, if the duty cycle (PDCx) becomes less than
the alternate dead time (ALTDTRx), the dead time
on the PWMs will become zero.
Work arou nd
Ensure that the duty cycle (PDCx) always meets
the following condition: PDCx > (ALTDTRx - 1)
Affected Silicon Revisions
26. Module: QEI
In Quadrature Encoder mode (QEIxCON<CMM> =
00), the index counter registers (INDXxCNTH and
INDXxCNTL) cannot be relied upon to increment
when the last known direction was positive and an
index pulse occurs. The index register can
decrement even if the last known direction was
positive. This does not apply to external clock or
internal timer QEI modes.
Work arou nd
The Index Event can be used to implement a
software counter. The direction could be
determined by comparing the current POSxCNT
value to that of the previous Index Event.
Affected Silicon Revisions
B1
X
; Load write latches if programming
…
; Setup NVMCON register to erase or program
as required
…
; Disable interrupts
PUSH SR
MOV #0x00E0, W0
IOR SR
; Write the KEY sequence
MOV #0x55, W0
MOV W0, NVMKEY
MOV #0xAA, W0
MOV W0, NVMKEY
; Start the programming sequence
BSET NVMCON, #15
; Insert two NOPs after programming
NOP
NOP
; Wait for operation to complete
prog_wait:
BTSC NVMCON, #15
BRA prog_wait
; Re-enable interrupts,
POP SR
B1
X
B1
X
B1
X
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS80526B-page 12 © 2011 Microchip Technology Inc.
27. Module: QEI
When Modulo Count mode (Mode 6) is selected for
the position counter (QEIxCON<PIMOD> = 110)
and the counter direction is set to negative
(QEIxCON<CNTPOL> = 1), the functions of the
QEIxLEC and QEIxGEC registers are reversed.
Work around
When using Modulo Count mode in conjunction
with a negative count direction (polarity) use the
QEIxLEC register as the upper count limit and the
QEIxGEC register as the lower count limit.
Affected Silicon Revisions
28. Module: CPU
Table write (TBLWTL, TBLWTH) instructions cannot
be the first or last instruction of a DO loop.
Work around
None.
Affected Silicon Revisions
29. Module: PWM
The PWM module can operate with variable
period, duty cycle, dead-time, and phase values.
The master period and other timing parameters
can be updated in the same PWM cycle. With
immediate updates disabled, the new values
should take effect at the start of the next PWM
cycle.
As a result of this issue, the updated master period
takes effect on the next PWM cycle, while the
update of the additional timing parameter is
delayed by one PWM cycle. The parameters
affected by this erratum are as follows:
Master period registers – update effective on the
next PWM cycle:
• PTPER – if PWMCONx<MTBS> = 0
• STPER – if PWMCONx<MTBS> = 1
Additional PWM timing parameters – update
effective one PWM cycle after master period
update:
• Duty cycle – PDCx, SDCx, and MDC registers
• Phase – PHASEx or SPHASEx registers
• Dead-time – DTRx and ALTDTRx registers
and dead-time compensation signals
• Clearing of current-limit and Fault conditions,
and application of external period reset signal
Work aro und
If the application requires the master period and
other parameters to be updated at the same time,
enable both immediate updates:
• PTCON<EIPU> = 1 – to enable immediate
period updates
• PWMCONx<IUE> = 1 – to enable immediate
updates of additional parameters listed above
Enabling immediate updates will allow updates to
the master period and the other parameters to take
effect immediately after writing to the respective
registers.
Affected Silicon Revisions
B1
X
Note: This silicon issue applies only to
dsPIC33EPXXXGP/MC/MU806/810/
814 devices.
B1
X
B1
X
© 2011 Microchip Technology Inc. DS80526B-page 13
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS70616F):
None to report at this time.
Note: Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS80526B-page 14 © 2011 Microchip Technology Inc.
APPENDIX A: REVISION HISTORY
Rev A Document (6/2011)
Initial release of this document; issued for revision B1
silicon.
Includes silicon issues 1 (I/O Multiplexer), 2-3 (CPU), 4
(PPS), 5-6 (SPI), 7-8 (PWM), 9 (Power System), 10
(Reserved), 11-12 (ECAN™), 13-14 (USB), 15 (DMA)
16-18 (UART), and 19 (I2C™).
Rev B Document (11/2011)
Updated issues 2 (CPU), 7 (PWM), 8 (PWM),
12 (ECAN™), and 14(USB).
Added issues 20 (ADC), 21 (PMP), 22 (Flash Memory),
23 (Flash Memory), 24 (Power System), 25 (PWM),
26 (QEI), 27 (QEI), 28 (CPU), and 29 (PWM).
© 2011 Microchip Technology Inc. DS80526B-page 15
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-818-5
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:200 9 certif ication for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and
analog product s. In addition, Microchip ’s quality system for the desig n
and manufacture of development systems is ISO 9001:2000 certified.
DS80526B-page 16 © 2011 Microchip Technology Inc.
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