1/27
L6208
September 2003
■
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V
■5.6A OUTPUT PEAK CURRENT (2.8A RMS)
■RDS(ON) 0.3Ω TY P. VAL U E @ Tj = 25° C
■OPERA TING FREQUENCY UP T O 100KHz
■NON DISSIPATIVE OVERCURRENT
PROTECTION
■DUAL INDEPENDENT CONSTANT tOFF PW M
CURRENT CONTROLLE RS
■FAST/SLOW DECAY MO D E SEL E CTION
■FAST DECAY QUASI-SYNCHRO NOUS
RECTIFICATION
■DECODING LOGIC FOR STE PPER MOTOR
FULL AND HALF STEP DRIVE
■CROSS CONDUCTION PROTECTION
■THERMAL SHUTDOWN
■UNDER VOLTAG E LOCKOUT
■
INTEGRATED FAST FREE WHEELING DIODES
TYPICAL APPLICATIONS
■BIPOLAR STEPPER MOTOR
DESCRIPTION
The L6208 is a DM OS Fully Integrated Stepper Motor
Driver with non-dissipative Overcurrent Protection,
realized in MultiPower-BCD technology, which com-
bines isolated DMOS Power Transistors with CMO S
and bipolar circuits on the same chip. The device in-
cludes all the circuitry needed to drive a two-phase
bipolar stepper motor including: a dual DMOS Full
Bridge, t he constan t off tim e PWM Current C ontroller
that performs the chopping regulati on and the Phase
Sequence Generator, that generates the stepping
sequence. Available in PowerDIP24 (20+2+2),
PowerSO36 and SO24 (20+2+2) packages, the
L6208 features a non-dissipative overcurrent protec-
tion on the high side Power MOSFETs and thermal
shutdown.
BLOCK DIAGRAM
GATE
LOGIC
STEPPING
SEQUENCE
GENERATION
OVER
CURRENT
DETECTION
OVER
CURRENT
DETECTION
GATE
LOGIC
VCP
VBOOT
EN
CONTROL
CW/CCW
VREF
A
V
BOOT
5V10V
VS
A
VS
B
OUT1
A
OUT2
A
OUT1
B
OUT2
B
SENSE
A
CHARGE
PUMP
VOLTAGE
REGULATOR
ONE SHOT
MONOSTABLE MASKING
TIME
THERMAL
PROTECTION
V
BOOT
V
BOOT
OCD
B
OCD
A
10V 10V
BRIDGE A
SENSE
COMPARATOR
BRIDGE B
D01IN1225
RC
A
+
-
SENSE
B
VREF
B
RC
B
HALF/FULL
CLOCK
RESET
PWM
ORDERING NUMBERS:
L6208N (PowerDIP24)
L6208PD (PowerSO36)
L6208D (SO24)
PowerDIP24
(20+2+2) PowerSO36 SO24
(20+2+2)
DMOS DRIV ER FOR BIPOLAR STEPPER MOTOR
L6208
2/27
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Test conditions Value Unit
VSSupply Voltage
V
SA
=
VSB =
VS60 V
VOD Differential Voltage between
VS
A
, OUT1
A
, OUT2
A
, SEN SE
A
and
VSB, OUT1B, OUT2B, SENS EB
V
SA
=
VSB =
VS = 60V;
V
SENSEA
= V
SENSEB = GND 60 V
VBOOT Bootstrap Peak Voltage
V
SA
=
VSB =
VSVS + 10 V
VIN,VEN Input and Enable Voltage Range -0.3 to +7 V
VREFA,
VREFB Voltage Range at pins VREFA
and VREFB -0.3 to +7 V
VRCA, VRCB Voltage Range at pins RCA and
RCB-0.3 to +7 V
VSENSEA,
VSENSEB Voltage Range at pins SENSEA
and SENSEB -1 to +4 V
IS(peak) Pulsed Supply Current (for each
VS pin), internally limited by the
overcurrent protection
V
SA
=
VSB =
VS;
tPULSE < 1ms 7.1 A
ISRMS Supply Current (for each
VS pin)
V
SA
=
VSB =
VS2.8 A
Tstg, TOP Storage and Operating
Temperature Range -40 to 150 °C
Symbol Parameter Test Conditions MIN MAX Unit
VSSupply Voltage
V
SA
=
VSB =
VS852V
V
OD Differential Voltage Between
VS
A
, OUT1
A
, OUT2
A
, SEN SE
A
and
VSB, OUT1B, OUT2B, SENS EB
V
SA
=
VSB =
VS;
V
SENSEA
= V
SENSEB 52 V
VREFA,
VREFB Voltage Range at pins VREFA
and VREFB -0.1 5 V
VSENSEA,
VSENSEB Voltage Range at pins SENSEA
and SENSEB(pulsed tW < trr)
(DC) -6
-1 6
1V
V
IOUT RMS Output Current 2.8 A
TjOperating Junction Temperature -25 +125 °C
fsw Switching Frequency 100 KHz
3/27
L6208
THE RMAL DA TA
PIN CONNECTIONS (Top View)
(5) The slug is internally connected to pins 1, 18,19 and 36 (GND pins).
Symbol Description PowerDIP24 SO24 PowerSO36 Unit
Rth-j-pins Maximum Thermal Resistance Junction-Pins 18 14 - °C/W
Rth-j-case Maximum Thermal Resistance Junction-Case - - 1 °C/W
Rth-j-amb1 Maximum Thermal Resistance Junction-Ambient (1)
(1) Mounted on a m ul ti-layer FR4 PCB with a di ss i pating copper surface on the bot tom side of 6cm2 (with a thickness of 35µm).
43 51 - °C/W
Rth-j-amb1 Maximum Thermal Resistance Junction-Ambient (2)
(2) Mounted on a m ul ti-layer FR4 PCB with a di ss i pating copper surface on the top side of 6cm2 (with a thicknes s of 35µm).
--35°C/W
Rth-j-amb1 Maximum Thermal Resistance Junction-Ambient (3)
(3) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35µm), 16 via holes
and a ground l ayer.
--15°C/W
Rth-j-amb2 Maximum Thermal Resistance Junction-Ambient (4)
(4) Mounted on a m ul ti-layer FR4 PCB without any heat s i nking surf ace on th e board.
58 77 62 °C/W
GND
GND
OUT1B
RCB
SENSEB
HALF/FULL
VREFB
1
3
2
4
5
6
7
8
9
CONTROL
VBOOT
EN
OUT2B
VSB
GND
GND19
18
17
16
15
13
14
D99IN1083
10
11
12
24
23
22
21
20
CLOCK
CW/CCW
SENSEA
RCA
OUT1AVSA
OUT2A
VCP
RESET
VREFA
GND
N.C.
N.C.
VSA
RCA
OUT1A
N.C.
N.C.
N.C. N.C.
N.C.
OUT1B
RCB
N.C.
VSB
N.C.
N.C.
GND
18
16
17
15
6
5
4
3
2
21
22
31
32
33
35
34
36
20
1
19
GND GND
D99IN1084
CLOCK
SENSEA
CW/CCW
SENSEB
HALF/FULL
VREFB
9
8
7
28
29
30
VREFACONTROL
10 27
OUT2A
RESET
VCP
EN
OUT2B
VBOOT
14
12
11
23
25
26
N.C. N.C.
13 24
PowerDIP24/SO24 PowerSO 36 (5)
L6208
4/27
PIN DESCRIPTION
PACKAGE
Name Type Function
SO24/
PowerDIP24
PowerSO36
PIN # PIN #
1 10 CLOCK Logic Input Step Clock input. The state machine makes one step on
each rising edge.
2 11 CW/CCW Logic Input Selects the direction of the rotation. HIGH logic level sets
clockwise direction, whereas LOW logic level sets
counterclockwise direction.
If not used, it has to be connected to GND or +5V.
3 12 SENSEAPower Supply Bridge A Source Pin. This pin must be connected to Po wer
Ground through a sensing power resistor.
413RC
ARC Pin RC Network Pin. A parallel RC network connected
between this pin and ground sets the Current Controller
OFF-Time of the Bridge A.
5 15 OUT1APower Output Bridge A Output 1.
6, 7,
18, 19 1, 18,
19, 36 GND GND Ground terminals. In PowerDIP24 and SO24 packages,
these pins are also used for heat dissipation toward the
PCB. On PowerSO36 package the slug is connected to
these pins.
8 22 OUT1BPower Output Bridge B Output 1.
924RC
BRC Pin RC Network Pin. A parallel RC network connected
between this pin and ground sets the Current Controller
OFF-Time of the Bridge B.
10 25 SENSEBP ower Supply Bridge B Source Pin. This pin must be connected to Po wer
Ground through a sensing power resistor.
11 26 VREFBAnalog Input Bridge B Current Controller Reference Voltage.
Do not leave this pin open or connected to GND.
12 27 HALF/FULL Logic Input Step Mode Selector. HIGH logic level sets HALF STEP
Mode, LOW logic level sets FULL STEP Mode.
If not used, it has to be connected to GND or +5V.
13 28 CONTROL Logic Input Deca y Mode Selector. HIGH logic level sets SLOW DECA Y
Mode. LOW logic level sets FAST DECAY Mode.
If not used, it has to be connected to GND or +5V.
14 29 EN Logic Input (6) Chip Enable. LOW logic level switches OFF all Power
MOSFETs of both Bridge A and Bridge B. This pin is also
connected to the collector of the Overcurrent and Thermal
Protection to implement over current protection.
If not used, it has to be connected to +5V through a
resistor.
15 30 VBOOT Supply
Voltage Bootstrap Voltage needed for driving the upper Power
MOSFETs of both Bridge A and Bridge B.
16 32 OUT2BPower Output Bridge B Output 2.
17 33 VSBPower Supply Bridge B Power Supply Voltage. It must be connected to
the Supply Voltage together with pin VSA
20 4 VSAPower Supply Bridge A Power Supply Voltage. It must be connected to
the Supply Voltage together with pin VSB
5/27
L6208
(6) Also connected at the output drain of the Over current and Thermal protection MOSFET. Therefore, it has to be driven putting in series
a resistor with a value in the range of 2.2KΩ - 180KΩ, r ecommended 100KΩ.
PACKAGE
Name Type Function
SO24/
PowerDIP24
PowerSO36
PIN # PIN #
21 5 OUT2APower Output Bridge A Output 2.
22 7 VCP Output Charge Pump Oscillator Output.
23 8 RESET Logic Input Reset Pin. LOW logic level restores the
Home
State
(State 1) on the Phase Sequence Generator State
Machine.
If not used, it has to be connected to +5V.
24 9 VREFAAnalog Input Bridge A Current Controller Reference Voltage.
Do not leave this pin open or connected to GND.
ELECTRICAL CHARACTERISTICS
(Tamb = 25°C, Vs = 48V, unless otherwise specified)
Symbol Parameter Test Conditions Min Typ Max Unit
VSth(ON) Turn-on Threshold 6.6 7 7.4 V
VSth(OFF) Turn-off Threshold 5.6 6 6.4 V
ISQuiescent Supply Current All Bridges OFF;
Tj = -25°C to 125°C (7) 510mA
T
j(OFF) Thermal Shutdown Temperature 165 °C
Output DMOS Tra nsist ors
RDS(ON) High-Side Switch ON Resistance Tj = 25 °C 0.34 0.4 Ω
Tj =125 °C (7) 0.53 0.59 Ω
Low-Side Switch ON Resistance Tj = 25 °C 0.28 0.34 Ω
Tj =125 °C (7) 0.47 0.53 Ω
IDSS Leakage Current EN = Low; OUT = VS2mA
EN = Low; OUT = GND -0.15 mA
Source Drain Diodes
VSD Forward ON Voltage ISD = 2.8A, EN = LOW 1.15 1.3 V
trr Reverse Recove r y Time If = 2.8A 300 ns
tfr Forward Recovery Time 200 ns
Logic Inputs (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW)
VIL Low level logic input voltage -0.3 0.8 V
VIH High level logic input voltage 2 7 V
PIN DESCRIPTION
(continued)
L6208
6/27
IIL Low Level Logic Input Current GND Logic Input Voltage -10 µA
IIH High Level Logic Input Current 7V Logic Input Voltage 10 µA
Vth(ON) Turn-on Input Threshold 1.8 2.0 V
Vth(OFF) Turn-off Input Threshold 0.8 1.3 V
Vth(HYS) Input Threshold Hysteresis 0.25 0.5 V
Switching Characteristics
tD(ON)EN
Enable to Output Turn-on Dela y
Time
(8)
ILOAD =2.8A, Resistive Load 100 250 400 ns
tD(OFF)EN Enable to Output Turn-off Delay
Time (8) ILOAD =2.8A, Resistive Load 300 550 800 ns
tRISE Output Rise Time (8) ILOAD =2.8A, Resistive Load 40 250 ns
tFALL Output Fall Time (8) ILOAD =2.8A, Resistive Load 40 250 ns
tDCLK Clock to Output Delay Time (9) ILOAD =2.8A, Resistive Load 2 µs
tCLK(min)L Minimum Clock Time (10) 1µs
t
CLK(min)
HMinimum Clock Time (10) 1µs
f
CLK Clock Frequency 100 KHz
tS(MIN) Minimum Set-up Time (11) 1µs
t
H(MIN) Minimum Hold Time (11) 1µs
t
R(MIN) Minimum Reset Time (11) 1µs
t
RCLK(MIN
)Minimum Reset to Clock Delay
Time (11) 1µs
t
DT Dead Time Protection 0.5 1 µs
fCP Charge Pump Frequency Tj = -25°C to 125°C (7) 0.6 1 MHz
PWM Comparator and Monostable
I
RCA,
I
RCB
Source Current at pins RC
A
and
RC
B
VRCA = VRCB = 2.5V 3.5 5.5 mA
Voffset Offset Voltage on Sense
Comparator VREFA, VREFB = 0.5V ±5 mV
tPROP Turn OFF Propagation Delay (12) 500 ns
tBLANK Internal Blanking Time on
SENSE pins 1µs
t
ON(MIN) Minimum On Time 1.5 2 µs
ELECTRICAL CHARACTERISTICS (continued)
(Tamb = 25°C, Vs = 48V, unless otherwise specified)
Symbol Parameter Test Conditions Min Typ Max Unit
7/27
L6208
(7) Tested at 25°C in a restricted range and guaranteed by characterization.
(8) See Fig. 1.
(9) See Fig. 2.
(10) See Fig. 3.
(11) See Fig. 4.
(12) Measure d applyin g a voltage of 1V to pi n S EN SE and a voltage drop from 2V to 0V to pin VR E F .
(13) See Fig. 5.
Figure 1. Switching Characteristi c Definition
tOFF PWM Recirculation Time ROFF = 20KΩ; COFF = 1nF
13
µs
ROFF = 100KΩ; COFF = 1nF
61
µs
IBIAS Input Bias Current at pins VREF A
and VREFB 10 µA
Over Current Protection
ISOVER Input Supply Overcurrent
Protection Threshold Tj = -25°C to 125°C (7) 4 5.6 7.1 A
ROPDR Open Drain ON Resistance I = 4mA 40 60 Ω
tOCD(ON) OCD Turn-on Delay Time (13) I = 4mA; CEN < 100pF 200 ns
tOCD(OFF) OCD Turn-off Delay Time (13) I = 4mA; CEN < 100pF 100 ns
ELECTRICAL CHARACTERISTICS (continued)
(Tamb = 25°C, Vs = 48V, unless otherwise specified)
Symbol Parameter Test Conditions Min Typ Max Unit
V
th(ON)
V
th(OFF)
90%
10%
EN
I
OUT
t
t
t
FALL
t
D(OFF)EN
t
RISE
t
D(ON)EN
D01IN1316
L6208
8/27
Figu re 2. Clo ck t o Ou tp ut D el a y Time
Figure 3. Minimum Timing Definiti on; Clock Input
Figure 4. Minimum Timing Definiti on; Logic Inputs
CLOCK
IOUT
t
t
tDCLK
Vth(ON)
D01IN1317
CLOCK
t
CLK(MIN)H
t
CLK(MIN)L
V
th(OFF)
V
th(ON)
D01IN1318
V
th(OFF)
CLOCK
RESET
t
S(MIN)
t
H(MIN)
t
R(MIN)
t
RCLK(MIN)
LOGIC INPUTS
D01IN1319
V
th(OFF)
V
th(ON)
V
th(ON)
9/27
L6208
Figu re 5. Overcurre nt D et ect i on Tim i ng Defi ni tio n
CIRCUI T DESCRIPTION
POWER STAGES and CHARGE PUMP
The L6208 integrates two independent Power MOS Full Bridges. Each Power MOS has an R
DS(ON)
= 0.3
Ω
(typ-
ical val ue @ 25°C), with intr insic fast freewheeling di ode. Switching patter ns are generated by the P WM Cur rent
Controller and the P hase Sequence Generator (see below). Cross conduction protection is achieved using a
dead time (t
DT
= 1
µ
s typical value) between the sw itch off and s witch on of tw o Power MOSFETSs in one leg of
a bridge.
Pins V S
A
and VS
B
MUST be connected together to the supply voltage V
S
. The device operates with a supply
voltage in the range from 8V to 52V. It has to be noticed that the R
DS(ON)
inc r eases of some percents when the
supply voltage is in the range from 8V to 12V (see Fig. 34 and 35).
Using N-Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above the
power suppl y volt age. The bootstrapped supply voltage V
BOOT
is obtained thr ough an internal Oscillator and few
external components to realize a charge pump circuit as shown in Figure 6. The oscillator output (VCP) is a
squar e wave at 600KHz (typic al) wi th 10V amplitud e. Rec ommended va lues/part number s for the c harge pump
circuit are shown in Table 1.
Table 1. Charge Pump E xternal Components Values
CBOOT 220nF
CP10nF
RP100Ω
D1 1N4148
D2 1N4148
ISOVER
90%
10%
IOUT
VEN
tOCD(OFF)
tOCD(ON)
D02IN1399
ON
OFF
BRIDGE
L6208
10/27
Figu re 6. Charge Pum p Circ u it
LOGIC INPUTS
Pins CONTROL, HALF/FULL, CLOCK, RESET and CW/CCW are TTL/CMOS and uC compatible logic inputs.
The internal structure is shown in Fig. 7. Typical value for turn-on and turn-off thresholds are respectively
V
th(ON)
= 1.8V and V
th(OFF)
= 1.3V.
Pin EN (Enable) has identical input structure with the exception that the drain of the Overcurrent and thermal
protec tion M OSFET is al so c onnected to this pin. Due to this connectio n some care needs to be taken in driv ing
this pin. The EN input may be driven in one of two configur ations as show n in Fig. 8 or 9. If driven by an open
drain ( collector) structure, a pull-up resistor R
EN
and a capacitor C
EN
are connected as shown in Fig. 8. If the
driver is a standard Push-Pull structure the resistor R
EN
and the capacitor C
EN
are connected as shown in Fig.
9. The resistor R
EN
should be chosen in the range from 2.2K
Ω
to 180K
Ω
. Recommended values for R
EN
and
C
EN
ar e respectively 100K
Ω
and 5.6nF. More information on selecting the values is found in the Overcurrent
Protection section.
Figu re 7. Lo gi c Inp uts I nte rn al S truc ture
Figu re 8. EN Pin Open Col lec to r Dri v in g
Figu re 9. E N Pi n Pu s h-P ull Drivi ng
D2 CBOOT
D1
RP
CP
VS
VSA
VCP VBOOT VSB
D01IN1328
5V
D01IN1329
ESD
PROTECTION
5V
5V
OPEN
COLLECTOR
OUTPUT
R
EN
C
EN
EN
D01IN133
0
ESD
PROTECTION
5V
PUSH-PULL
OUTPUT
R
EN
C
EN
EN
D01IN1331
ESD
PROTECTION
11/27
L6208
PWM CURRENT CONTROL
The L6208 includes a constant off time PWM current controller for each of the two bridges. The current control
circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected be-
tween the source of the two lower power MOS transistors and ground, as shown in Figure 10. As the current in
the motor builds up the voltage across the sense resistor increases proportionally. When the voltage drop
acro ss the sense res istor becomes greater than the vol tage at the re feren ce i nput (V REF
A
or VREF
B
) the sense
comparator triggers the monostable switching the bridge off. The pow er MOS remain off for the time set by the
monostable and the motor current recirculates as defined by the selected decay mode, described in the next
section. W hen the monostable times out the bridge w ill again turn on. Sinc e the inter nal dead time, us ed to pre-
vent cr os s conduction in the bridge, delays the turn on of the pow er MOS, the effective off time is the sum of the
monostable time plus the dead time.
Figure 10. PWM Current Controller Simplified Schematic
Figure 11 shows the typical operating waveforms of the output current, the voltage drop across the sensing re-
sistor , the RC pin vol tage and the status of the bridge. More d etails regarding the S ynchr onous Rectificati on and
the output stage configuration are included in the next section.
Immediately after the Power MOS turns on, a high peak current flows through the sensing resistor due to the
rever se recovery of the freewheeling diodes. The L6208 provides a 1
µ
s Blanking Time t
BLANK
that inhibits the
comparator output so that this current spike cannot prematurely re-trigger the monostable.
DRIVERS
+
DEAD TIME
S
Q
RDRIVERS
+
DEAD TIME
2H 1H
2L 1L
OUT2A(or B)
SENSEA(or B)
RSENSE
D01IN1332
RCA(or B)
ROFF
COFF
VREFA(or B)
IOUT
OUT1A(or B)
+
+
-
-
1µs
5mA
BLANKER
SENSE
COMPARATOR
COMPARATOR
OUTPUT
MONOSTABLE
SET
2.5V
5V
FROM THE
LOW-SIDE
GATE DRIVERS
2 PHASE
STEPPER MOTOR
BLANKING TIME
MONOSTABLE
VSA (or B)
TO GATE LOGIC
(0) (1)
L6208
12/27
Figure 11. Output Current Regulation Waveforms
Figur e 12 shows the magnitude of the Off Time t
OFF
versus C
OFF
and R
OFF
values. It can be approximately
calculated from the equations:
t
RCFALL
= 0.6 · R
OFF
· C
OFF
t
OFF
= t
RCFALL
+ t
DT
= 0.6 · R
OFF
· C
OFF
+ t
DT
where R
OFF
and C
OFF
are the external component values and t
DT
is the internally generated Dead Time with:
20K
Ω
≤
R
OFF
≤
100K
Ω
0.47nF
≤
C
OFF
≤
100nF
t
DT
= 1µs (typical value)
Therefore:
t
OFF(MIN)
= 6.6µs
t
OFF(MAX)
= 6ms
These values allow a sufficient range of t
OFF
to implement the drive circuit for most motors.
The capacitor value chosen for C
OFF
also affects the Rise Time t
RCRISE
of the voltage at the pin RCOFF. The
Rise Time t
RCRISE
will only be an issue if the capacitor is not completely charged before the next time the
monostable is triggered. Therefore, the on time t
ON
, which depends by motors and supply parameters, has to
be bigger than t
RCRISE
for allowing a good current regulation by the PWM stage. Furthermore, the on time t
ON
can not be smaller than the minimum on time t
ON(MIN)
.
OFF BCDDA
t
ON
t
OFF
t
OFF
BC
ON
2.5V
0
Fast Decay
Fast Decay
Slow Decay Slow Decay
1µs t
BLANK
t
RCRISE
1µs t
DT
1µs t
DT
t
RCRISE
t
RCFALL
t
RCFALL
SYNCHRONOUS OR QUASI
SYNCHRONOUS RECTIFICATION
1µs t
BLANK
5V
V
RC
V
SENSE
V
REF
I
OUT
V
REF
R
SENSE
D01IN1334
13/27
L6208
t
RCRISE
= 600 · C
OFF
Figure 13 shows the lower limit for the on time t
ON
for having a good PWM current regulation capac ity. It has to
be said that t
ON
is always bigger than t
ON(MIN)
because the device imposes this condition, but it can be smaller
than t
RCRISE
- t
DT
. In this last case the device continues to work but the off time t
OFF
is not more constant.
So, small C
OFF
value gives more flexibility for the applications (allows smaller on time and, therefore, higher
switching frequency), but, the smaller is the value for C
OFF
, the more influential will be the noises on the circuit
performance.
Figure 12. tOFF ver sus COFF and ROFF
Figure 13. Area where tON can vary maintaining the PWM regulation.
tON tON MIN()
>1.5µs (typ. value)=
tON tRCRISE tDT
–>
0.1 1 10 100
1
10
100
1.103
1.104
Coff [nF]
toff [µs]
Roff = 100kΩ
Roff = 47kΩ
Roff = 20kΩ
0.1 1 10 100
1
10
100
Coff [nF]
ton(min) [µs]
1.5µs (typ. value)
L6208
14/27
DECAY MODES
The CONTROL input is used to select the behavior of the bridge during the off time. When the CONTROL pin
is low, the Fast Decay mode is selected and both transistors in the bridge are switched off during the off time.
When the CON TROL pin is high, th e S low De cay mode i s s elected and onl y th e low s ide tr ansistor of the bridge
is switched off during the off time.
Figure 14 shows the operation of the bridge in the Fast Decay mode. At the start of the off time, both of the
power MOS are switched off and the current recirculates thr ough the two opposite free wheeling diodes. The
current decays with a high di/dt since the voltage across the coil is essentially the power supply voltage. After
the dead time, the lower power MOS in parallel with the conducting diode is tur ned on in synchronous recti fica-
tion mode. In applications where the motor current is low it is possible that the current can decay completely to
zero during the off time. At this point if both of the power MOS were operating in the synchronous rectification
mode it would then be possible for the current to build in the opposite direction. To prevent this only the lower
power MOS is operated in synchronous rectification mode. This operation is called Quasi-Synchronous Recti-
fication Mode. When the monostable times out, the power MOS are turned on again after s ome dela y s et by the
dead time to prevent cross conduction.
Figu re 15 s hows the operation of the bridge i n the Sl ow De cay mode. At the start of the off ti me, the lower power
MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage acr oss
the coil is low, the current decays slowly. After the dead time the upper power MOS is operated in the s ynchro-
nous rectification mode. When the monostable times out, the lower power MOS is turned on again after some
delay set by the dead time to prevent cross conduction.
Figure 14. Fast Decay Mode Output Stage Configurations
Figure 15. Slow Decay Mo de Output Stage Config urations
STEPPING SEQUENCE GENERATION
The p hase sequence generator is a state machine that provides the phase and enable inputs for the two bri dges
to dr ive a stepper motor in e ither full step or half step. Tw o full step m odes are possibl e, the N ormal Drive Mode
where both phases ar e energized each st ep and the Wave Dri ve Mode where only one phase is energized at a
A) ON TIME B) 1µs DEAD TIME C) QUASI-SYNCHRONOUS
RECTIFICATION D) 1µs SLOW DECAY
D01IN1335
A) ON TIME B) 1µs DEAD TIME C) SYNCHRONOUS
RECTIFICATION D) 1µs DEAD TIME
D01IN1336
15/27
L6208
time. The drive mode is selected by the HALF/FULL input and the current state of the sequence generator as
descr ibed below. A rising edge of the CLOC K input advances th e state machi ne to the next state. The dir ect ion
of rotation is set by the CW/CCW input. The RESET input resets the state machine to state.
HALF STEP MODE
A HIGH logic level on the HALF/FULL input selects Half Step Mode. Figure 16 shows the motor current wave-
forms and the state diagram for the Phase Sequencer Generator. At Start-Up or after a RESET the Phase Se-
quen cer is at state 1. After each clock pulse the state change s follow ing the sequence 1,2,3,4,5,6,7,8,… if CW/
CCW is high (Clockwise movement) or 1,8,7,6,5,4,3,2,… if CW/CCW is low (Counterclockwise movement).
NORMAL DRIVE MODE (Full-step two-phase-on)
A LOW level on the HALF/FULL i nput selects the Full Step mode. When the low level is applied when the state
machine is at an ODD numbered state the Normal Drive Mode is selec ted. Figure Fig. 17 shows the motor cur-
rent waveform state diagram for the state machine of the Phase Sequencer Generator. The Normal Drive Mode
can easily be selected by holding the HALF/FULL input low and applying a RESET. AT start -up or after a RE-
SET the State Machine is in state1. While the HALF/FULL input is kept low, state changes following the se-
quen ce 1,3,5,7,… if CW/CCW is hi gh (C lockwise movement) or 1,7,5,3,… if CW/CCW is low (Counter clockwise
movement).
WAVE DRIVE MODE (Full-step one-phase-on)
A LOW level on the pin HALF/FULL input selects the Full Step mode. When the low level is applied when the
st ate mach ine is at a n EVEN numbered s tate the Wa ve Drive Mode is selected. Figure 18 shows the motor cur-
rent waveform and the state diagram for the state machine of the Phase Sequence Generator. To enter the
Wave Drive Mode the state machine must be in an EV EN numbered s tate. The most direct method to select the
Wave Drive Mode is to fir st apply a RESET, then while keeping the HALF/FU LL input high apply one pulse to
the clock input then take the HALF/FULL input low. This sequence first forces the state machine to sate 1. The
clock pulse, with the HALF/FULL input high advances the state machine from state 1 to either state 2 or 8 de-
pending on the C W/CCW input. Starting from this point, after each clock pulse (rising edge) will advance the
state machi ne follow ing the s equence 2,4,6,8, … if CW/CCW is high (Clockwis e movement) o r 8, 6,4,2,… if CW/
CCW is low (Counterclockwise movement).
Figure 16. Half Step Mode
Figu re 17 . Normal Dri ve Mo de
3
2
4 5
1
D01IN1320
2345678
6
187
I
OUTA
IOUTB
CLOCK
Start Up or Reset
2
4
1
D01IN1322
3571357
6
8
I
OUTA
IOUTB
CLOCK
35
17
Start Up or Reset
L6208
16/27
Figure 18. Wave Drive Mode
NON-DISSIPATIVE OVERCURRENT PROTECTION
The L6208 integrates an Overcurrent Detection Circuit (OCD). This circuit provides protection against a short
cir cuit to gr ound or between two phases of the br idge. With this internal over current detection, the external cur -
rent sense resistor normally used and its associated power dissipation are eliminated. Figure 19 shows a sim-
plified schematic of the overcurrent detection circuit.
To implement the over current detection, a sens ing element that deli vers a small but preci se fraction of the out-
put current is implemented with each high side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference cur-
rent I
REF
. W hen the output c urrent r eaches the detec tion thresh old (t ypi cally 5.6A ) the OCD com parator signal s
a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off threshold (1.3V typ-
ical) by an internal open drain MO S with a pull dow n capa bility of 4mA. By usi ng an exter nal R-C on the EN pin,
the off time before recovering normal oper ation can be easily pr ogrammed by means of the acc urate thr esholds
of the logic inputs.
Figure 19. Overcu rrent Pro tection Simplified Schematic
2
4
2
D01IN1321
4682468
6
8
I
OUTA
IOUTB
CLOCK
35
17
Start Up or Reset
+
OVER TEMPERATURE
IREF
(I1A+I2A) / n
I1A / n
POWER SENSE
1 cell
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
HIGH SIDE DMOSs OF
THE BRIDGE A
OUT1A OUT2A
VSA
I1A I2A
I2A / n
FROM THE
BRIDGE B
OCD
COMPARATOR
OCD
COMPARATOR
TO GATE
LOGIC
INTERNAL
OPEN-DRAIN
RDS(ON)
40Ω TYP.
CEN.
REN.EN
V
DD
µC or LOGIC
D01IN1337
17/27
L6208
Figure 20 shows the Overcurrent Detection operation. The Disable Time t
DISABLE
before recovering normal oper-
ation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by
C
EN
and R
EN
values and its magnitude is reported in Figure 21. The Delay Time t
DELAY
before turning off the
bridge when an overcurrent has been detected depends only by C
EN
value. Its magnitude is reported in Figure 22.
C
EN
is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C
EN
should be c hosen as big as possi ble acc or ding to the maximum tolerable D elay Time and th e R
EN
value should
be chosen according to the desired Disable Time.
The res istor R
EN
should be chosen in the range from 2.2K
Ω
to 180K
Ω
. Recom mended val ues for R
EN
and C
EN
are respectively 100K
Ω
and 5.6nF that allow obtaining 200
µ
s Disable Time.
Figure 20. Overcur rent Protecti on Waveforms
ISOVER
IOUT
Vth(ON)
Vth(OFF) VEN(LOW)
VDD
tOCD(ON) tD(ON)EN
tEN(FALL) tEN(RISE)
tDISABLE
tDELAY
tOCD(OFF)
tD(OFF)EN
VEN
BRIDGE
ON
OFF
OCD
ON
OFF
D02IN1400
L6208
18/27
Figure 21. tDISABLE versu s C EN and REN (VDD = 5V ).
Figure 22. tDELAY versus CEN (VDD = 5V ).
THERMAL PROTECTION
In addition to the Ovecurrent Protection, the L6208 integrates a Thermal Protection for preventing the device
destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible
element integrated in the die. The device switch-off when the junction temperature reaches 165°C (typ. value)
with 15°C hysteresis (typ. value).
110100
1
10
100
1.103
CEN [nF]
tDISABLE [µs]
REN = 220 kΩREN = 100 kΩREN = 47 kΩ
REN = 33 kΩ
REN = 10 kΩ
110100
1
10
100
1.103
CEN [nF]
tDISABLE [µs]
REN = 220 kΩREN = 100 kΩREN = 47 kΩ
REN = 33 kΩ
REN = 10 kΩ
1 10 100
0.1
1
10
Cen [n F]
tdelay [µs]
19/27
L6208
APPLICATION INFORMATION
A typical Bipolar Stepper Motor Driver application using L6208 is shown in Fig. 23. T ypical component values
for the application are shown in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should
be placed between the pow er pins (VS
A
and V S
B
) and ground near the L6208 to improve the high frequency
filtering on the power supply and reduce high frequency transients generated by the switching. The capacitor
connected fr om the EN input to ground sets the shut dow n time when an over cur rent is detected (see Overcur-
rent Protection). The tw o current sensing inputs (SENSE
A
and SENSE
B
) should be connected to the sensing
resistors with a trace length as short as possible in the layout. The sense resistors should be non-inductive re-
sistors to minimize the di/dt transients across the resistor. To increase noise immunity, unused logic pins (except
EN) are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin description). It is recom-
mended to keep Power Ground and Signal Ground separated on P CB .
Table 2. Component Valu es for Typ ical Application
Figure 23. Typical Appli cation
C1100µF D11N4148
C2100nF D21N4148
CA1nF RA39KΩ
CB1nF RB39KΩ
CBOOT 220nF REN 100KΩ
CP10nF RP100Ω
CEN 5.6nF RSENSEA 0.3Ω
CREF 68nF RSENSEB 0.3Ω
M
OUT1
A
VREF
A
VREF
B
CLOCK
1
5
21
18
19
8
16
OUT2
A
GND
GND
GND
GND
RC
A
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
V
S
8-52V
DC
24VS
B
VCP
VBOOT
C
P
C
BOOT
R
P
D
2
D
1
C
1
C
2
SENSE
A
R
SENSEA
20
CW/CCW
CLOCK
CW/CCW2
6
7
11
RESET
EN
C
EN
R
EN
RESET
ENABLE
V
REF
= 0-1V
23
HALF/FULL HALF/FULL12
CONTROL FAST/SLOW DECAY13
14
4
17
3
15
22
SENSE
B
R
SENSEB
C
A
R
A
10
C
REF
RC
B
9
C
B
R
B
D01IN1341
L6208
20/27
Output Current Capability and IC Power Dissipation
In Fig. 24, 25, 26 and 27 ar e shown the approxim ate relation between the output current and the IC power dis-
sipation using PWM current control driving a two-phase stepper motor, for different driving sequences:
– HALF STE P mode (Fig. 24) in which alternately one phase / two phases are energized.
– NORMAL DRIVE (FULL-STEP TWO PHASE ON) mode (Fig. 25) in which two phases are en ergized
during each step.
– WAVE DRIVE (FUL L-STEP ONE PHASE ON) mod e (Fig. 26) in which only one pha se is energized at
each step.
– MICROSTEPPING mode (Fig. 27), in which the current follows a sine-wave profile, provided through
the Vref pins.
For a given output curr ent and driving seque nce the power diss ipated by the IC can be easily evaluated, in order
to establish which package should be used and how large must be the on-board copper dissipating area to guar-
antee a safe operating junction temperature (125°C maximum).
Figure 24. IC Po wer Dissipation versus Output Current in HALF STEP Mo de.
Figure 25. I C Power Dissi pation versus Output Current in NORMAL Mode (full step two phase on) .
No PWM
fSW = 30 kHz (slow decay)
Test Condit ion s:
Supply Voltage = 24V
IA
IB
IOUT
IOUT
0 0.5 1 1.5 2 2.5 3
0
2
4
6
8
10
PD [W]
IOUT [A]
HALF STEP
No PWM
fSW = 30 kHz (slow decay)
Test Conditions:
Supply Voltage = 24 V
IA
IB
IOUT
IOUT
00.511.522.53
0
2
4
6
8
10
PD [W]
IOUT [A]
NORMAL DRIVE
21/27
L6208
Figure 26. IC Power Dissipation versus Outp ut Current in WAVE Mo de (full step one phase on).
Figure 27. IC Power Dissipation versus Output Current in MICROSTEPPING Mode.
Thermal Management
In most applications the power dissipation in the IC is the main factor that sets the maximum current that can
be delivered by the devic e in a safe operating condi tion. Therefore, it has to be taken i nto account ver y carefully.
Besi des the available space on the P CB , the right package s hould be chosen c onsidering the power dissi pation.
Heat sinking can be achieved using copper on the PCB with proper area and thickness. Figures 28, 29 and 30
show the Junction-to-A mbient Thermal Resistance values for the PowerSO36, PowerDIP24 and SO 24 pa ckag-
es.
For instance, using a PowerSO package with copper slug soldered on a 1.5mm copper thickness FR4 board
with 6cm
2
dissipating footp rint (copper thick ness of 35µm), the R
th(j-amb)
is about 35°C /W. Fig. 31 shows mount-
ing methods for this pack age. Using a multi-layer board wi th vias to a ground plane, thermal impeda nce can be
reduced dow n to 15°C/W.
No PWM
fSW = 30 kHz (slow decay)
Test Conditions:
Supply Voltage = 24V
IA
IB
IOUT
IOUT
WAVE DRIVE
0 0.5 1 1.5 2 2.5 3
0
2
4
6
8
10
PD [W]
IOUT [A]
fSW = 50 kHz (slow decay)
fSW = 30 kHz (slow decay)
IA
IB
IOUT
IOUT
MICROSTEPPING
0 0.5 1 1.5 2 2.5 3
0
2
4
6
8
10
PD [W]
IOUT [A]
Test Conditions:
Supply Voltage = 24V
L6208
22/27
Figure 28. PowerSO36 Junction-Ambient Thermal Resistance versus On-Board Copper Area.
Figure 29. Pow erDIP2 4 Junction -Ambient Th erm al Resis tance vers us On -Board Copp er Area.
Figure 30. SO24 Junction-Ambient Thermal Resistance versus On-Board Copper Area.
Figure 31. Mou nting the PowerS O Pa ckag e.
13
18
23
28
33
38
43
12345678910111213
Without Ground Layer
With Ground Layer
With Ground Layer+16 via
Holes
sq . cm
ºC / W
On-Board Copper Area
39
40
41
42
43
44
45
46
47
48
49
1 2 3 4 5 6 7 8 9 101112
Copper Area is on Bottom
Side
Copper Are a is on To p Side
sq. cm
ºC / W On-Board Copper Area
48
50
52
54
56
58
60
62
64
66
68
123456789101112
Copper Area is on Top Side
sq. cm
ºC / W On-Board Copper Area
Sl ug soldered
to PCB with
dissipati ng area
Sl ug soldered
t o PCB with
dissipating area
plus ground layer
Slug soldered t o PCB with
dissipa t ing area plus ground lay e r
contacted through via ho les
23/27
L6208
Figure 32. Typical Quie scen t Curren t vs.
Sup ply Voltage
Figure 33. Normalized Ty pi cal Quiescent
Current vs. Switching Frequen cy
Figure 34. Typical Low-Side RDS(ON) vs. Supply
Voltage
Figu re 35 . Ty pi ca l Hi gh-Side R D S (ON ) vs .
Sup ply Voltage
Figu re 36. Normaliz ed R DS(ON) vs.Junction
Temperatu re (typi cal value)
Figure 37. Typical Drain-Source Diode Forward
ON Characteristic
4.6
4.8
5.0
5.2
5.4
5.6
0 102030405060
Iq [m A ]
VS [V ]
fsw = 1k Hz Tj = 25°C
Tj = 85°C
Tj = 125°C
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
0 20406080100
Iq / (Iq @ 1 kHz)
fSW [kHz]
0.276
0.280
0.284
0.288
0.292
0.296
0.300
0 5 10 15 20 25 30
RDS(ON) [Ω]
VS [V]
Tj = 25°C
0.336
0.340
0.344
0.348
0.352
0.356
0.360
0.364
0.368
0.372
0.376
0.380
0 5 10 15 20 25 30
RDS(ON) [Ω]
VS [V ]
Tj = 25°C
0.8
1.0
1.2
1.4
1.6
1.8
0 20406080100120140
R
DS(ON)
/ (R DS(ON) @ 25 °C)
Tj [°C]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
700 800 900 1000 1100 1200 1300
ISD [A]
VSD [mV]
Tj = 25°C
L6208
24/27
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 3.60 0.141
a1 0.10 0.30 0.004 0.012
a2 3.30 0.130
a3 0 0.10 0 0.004
b 0.22 0.38 0.008 0.015
c 0.23 0.32 0.009 0.012
D (1) 15.80 16.00 0.622 0.630
D1 9.40 9.80 0.370 0.385
E 13.90 14.50 0.547 0.570
e 0.65 0.0256
e3 11.05 0.435
E1 (1) 10.90 11.10 0.429 0.437
E2 2.90 0.114
E3 5.80 6.20 0.228 0.244
E4 2.90 3.20 0.114 0.126
G 0 0.10 0 0.004
H 15.50 15.90 0.610 0.626
h 1.10 0.043
L 0.80 1.10 0.031 0.043
N10°(max.)
S8°(max.)
(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".
PowerSO36
e
a2 A
Ea1
PSO36MEC
DETAIL A
D
118
1936
E1
E2
h x 45˚
DETAIL A
lead
slug
a3
S
Gage Plane 0.35
L
DETAIL B
DETAIL B
(COPLANARITY)
GC
- C -
SEATING PLANE
e3
c
NN
⊕
M
0.12 AB
b
B
A
H
E3
D1
BOTTOM VIEW
OUTLINE AND
MECHANICAL DATA
25/27
L6208
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.320 0.170
A1 0.380 0.015
A2 3.300 0.130
B 0.410 0.460 0.510 0.016 0.018 0.020
B1 1.400 1.520 1.650 0.055 0.060 0.065
c 0.200 0.250 0.300 0.008 0.010 0.012
D 31.62 31.75 31.88 1.245 1.250 1.255
E 7.620 8.260 0.300 0.325
e 2.54 0.100
E1 6.350 6.600 6.860 0.250 0.260 0.270
e1 7.620 0.300
L 3.180 3.430 0.125 0.135
M 0˚ min, 15˚ max.
Powerdip 24
A1
B eB1
D
13
12
24
1
L
A
e1
A2
c
E1
SDIP24L
M
OUTLINE AND
MECHANICAL DAT A
Information furnishe d is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the c onsequences
of use of such information nor for any inf ringement of patents or other rights of third parties which may result from its use. No lic ense is granted
by i m pl icati on or otherwise under any patent or patent right s of ST M icroe l ectronics. Sp ecification s mentioned in this p ublicat i on are subject
to change without notice. This publication supersedes and replaces all i nformation previously supplied. STMicroelectronics produ ct s are not
authorized for use as critical comp onents in life support dev i ces or systems without express wri tten ap proval of ST M i croel ectronics.
Th e ST logo is a registered tra dem ark of STM icroe l ectronics.
All o ther nam es are the property of th eir resp ective owners
© 200 3 STMicr oelectronics - A l l r i ghts reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belg i um - Brazil - Canada - China - Czech Republic - F i nland - France - Germany - Hong Kon g - India - Israel - It aly - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
26/27
L6208
OUTLINE AN D
M E CHANICAL DA T A
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B 0.33 0.51 0.013 0.200
C 0.23 0.32 0.009 0.013
D
(1)
15.20 15.60 0.598 0.614
E 7.40 7.60 0.291 0.299
e 1.27 0.050
H 10.0 10.65 0.394 0.419
h 0.25 0;75 0.010 0.030
L 0.40 1.27 0.016 0.050
k 0˚ (min.), 8˚ (max.)
ddd 0.10 0.004
(1) “D” di m ens i on does not i nclu de mold f l ash, prot u s ions or gate
bur rs . Mo ld f las h, p rotus ion s o r gat e bur rs shall not exce ed
0.15mm per side.
SO24
0070769 C
Weight: 0.60gr
Information furnishe d is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the c onsequences
of use of such information nor for any inf ringement of patents or other rights of third parties which may result from its use. No lic ense is granted
by i m pl icati on or otherwise under any patent or patent right s of ST M icroe l ectronics. Sp ecification s mentioned in this p ublicat i on are subject
to change without notice. This publication supersedes and replaces all i nformation previously supplied. STMicroelectronics produ ct s are not
authorized for use as critical comp onents in life support dev i ces or systems without express wri tten ap proval of ST M i croel ectronics.
Th e ST logo is a registered tra dem ark of STM icroe l ectronics.
All o ther nam es are the property of th eir resp ective owners
© 200 3 STMicr oelectronics - A l l r i ghts reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belg i um - Brazil - Canada - China - Czech Republic - F i nland - France - Germany - Hong Kon g - India - Israel - It aly - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
27/27
L6208
