74LCX16374MTD_NL - Fairchild Semiconductor

Februa ry 199 4

Revised May 2005

74LCX16374 Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Ou tputs

74LCX16374

Low Voltage 16-Bit D-Type Flip-Flop

with 5V Tolerant Inputs and Outputs

General Descript ion

The LCX16374 contains sixteen non-inverting D-type

flip-flops with 3-STATE outputs and is int ended for bus ori-

ented applications. The device is byte controlled. A buff-

ered clock (CP) and Output Enable (OE) are common to

each byte and can be shorted together for full 16-bit opera-

tion.

The LCX16374 is designed for low voltage (2.5V or 3.3V)

VCC applications with capability of interfacing to a 5V signal

environment.

The LCX16374 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintaining

CMOS low power dissipation.

Features

■5V tolerant inputs and outputs

■2.3V–3.6V VCC specifications provided

■6.2 ns tPD max (VCC

3.3V), 20

A ICC max

■Power down high impedance inputs and outputs

■Supports live insertion/withdrawal (Note 1)

■

24 mA output drive (VCC

3.0V)

■Latch-up per for man c e exce eds 500 mA

■ESD performa nce :

Human body model

2000V

Machine model

200V

■Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Note 1: To ensure the high-impedance state during power up or down, OE

should be tied to VCC through a p ull-up re sistor: the minim um value or the

resistor is determined by the current-sourcing capability of the driver.

Ordering Code:

Note 2: Ordering code “G” indicates Trays.

Note 3: Devices al so av ailable in Tape and Reel. Specify by appendi ng t he suffix lette r “X” to th e ordering co de.

Logic Symbol

Order Number Package Number Package Description

74LCX16374G

(Note 2)( Note 3) BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

74LCX16374MEA

(Note 3) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LCX16374MTD

(Note 3) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

■Uses proprietary noise /E MI reduct ion c ircui tr y

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74LCX16374

Connection Diagrams

Pin Assignment for SSOP and TSSOP

Pin Assignment for FBGA

(Top Thr u View)

Pin Descriptions

FBGA Pin Assignments

Truth Tables

HIGH Voltage Level

LOW Voltage Le ve l

Immaterial

High Impedance

Previ ous O0 before HIGH-to- LOW of CP

Pin Names Description

OEnOutput Enable Input (Active LOW)

CPnClock Pulse Input

I0–I15 Inputs

O0–O15 Outputs

NC No Connect

123456

AO0NC OE1CP1NC I0

BO2O1NC NC I1I2

CO4O3VCC VCC I3I4

DO6O5GND GND I5I6

EO8O7GND GND I7I8

FO10 O9GND GND I9I10

GO12 O11 VCC VCC I11 I12

HO14 O13 NC NC I13 I14

JO15 NC OE2CP2NC I15

Inputs Outputs

CP1OE1I0–I7O0–O7



LH H



LL L

LL X O

XH X Z

Inputs Outputs

CP2OE2I8–I15 O8–O15



LH H



LL L

LL X O

XH X Z

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74LCX16374

Functional Description

The LC X16374 con si sts of sixtee n e dge -tr iggered f lip -flops

with individual D-type inputs and 3-STATE true outputs.

The device is byte controlled with each byte functioning

identically, but independent of the other. The control pins

can be shorted together to obtain full 16-bit operation. Each

byte has a buffered clock and buffered Output Enable com-

mon to all fli p-flops within that by te. The description whic h

follows applies to each byte. Each flip-flop will store the

state of their individual D inputs that meet the setup and

hold time requirements on the LOW-to-HIGH Clock (CPn)

transition. With the Output Enable (OEn) LOW, the con-

tents of the flip-flops are available at the outputs. When

OEn is HIG H, the outputs go to the high imped ance state.

Operation of the OEn input does not affect the s tate of the

flip-flops.

Logic Diagrams

Byte 1 (0:7)

Byte 2 (8:15)

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delay s .

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74LCX16374

Absolute Maximum Ratings(Note 4)

Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated

at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-

mend ed Operating Co nditions ” tab le w ill define th e c onditions fo r ac t ual devi c e operation.

Note 5: IO Absolute Maximum Rating must be observed.

Recommended Operating Conditions (Note 6)

Note 6: Unused inputs mu st be held HI GH or LOW. They ma y not fl oat .

DC Electrical Characteristics

Symbol Parameter Value Conditions Units

VCC Supply Voltage



0.5 to



7.0 V

VIDC Input Voltage



0.5 to



7.0 V

VODC Output Voltage



0.5 to



7.0 3-STATE V



0.5 to VCC



0.5 Output in HIGH or LOW State (Note 5)

IIK DC Input Diode Current



50 VI



GND mA

IOK DC Output Diode Current



50 VO



GND mA



50 VO

VCC

IODC Output Source/Sink Current

50 mA

ICC DC Supply Current per Supply Pin

100 mA

IGND DC Ground Current per Ground Pin

100 mA

TSTG Storage Temperature



65 to



150

Symbol Parameter Min Max Units

VCC Supply Voltage Operati ng 2.0 3.6 V

Data Retention 1.5 3.6

VIInput Voltage 0 5.5 V

VOOutput Voltage HIGH or LOW State 0 VCC V

3-STATE 0 5.5

IOH/IOL Output Current VCC

3.0V



3.6V

24 mAVCC

2.7V



3.0V

VCC

2.3V



2.7V

TAFree-Air Operating Temperature



40 85

V Input Edge Rate, VIN

0.8V – 2.0V, VCC

3.0V 0 10 ns/V

Symbol Parameter Conditions VCC TA



C to



CUnits

(V) Min Max

VIH HIGH Level Input Voltage 2.3



2.7 1.7 V

2.7



3.6 2.0

VIL LOW Level Input Voltage 2.3



2.7 0.7 V

2.7



3.6 0.8

VOH HIGH Level Output Voltage IOH



100

A2.3



3.6 VCC



0.2

IOH



8 mA 2.3 1.8

IOH



12 mA 2.7 2.2

IOH



18 mA 3.0 2.4

IOH



24 mA 3.0 2.2

VOL LOW Level Output Voltage IOL

100

A2.3



3.6 0.2

IOL

8 mA 2.3 0.6

IOL

12 mA 2.7 0.4

IOL

16 mA 3.0 0.4

IOL

24 mA 3.0 0.55

IIInput Leakage Current 0

5.5V 2.3



3.6

5.0

IOZ 3-STATE Output Leakage 0

5.5V 2.3



3.6

5.0

VIH or VIL

IOFF Power-Off Leakage Current VI or VO

5.5V 0 10

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74LCX16374

DC Electrical Characteristics (Continued)

Note 7: Outputs disabled or 3-STATE only.

AC Electrical Characteristics

Note 8: Skew is defined as the absolute value of the differences between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (t OSLH). Parameter guaranteed by design.

Dynamic Switching Characteristics

Capacitance

Symbol Parameter Conditions VCC TA



C to



CUnits

(V) Min Max

ICC Quiescent Supply Current VI

VCC or GND 2.3



3.6 20

3.6V

VI, VO

5.5V (Note 7) 2.3



3.6

ICC Increase in ICC per Input VIH

VCC



0.6V 2.3



3.6 500

Symbol Parameter





C, RL

500

Units

VCC

3.3V

0.3V VCC

2.7V VCC

2.5V

0.2V

50 pF CL

30 pF

Min Max Min Max Min Max

fMAX Maximum Clock Frequency 170 MHz

tPHL Propagation Delay 1.5 6.2 1.5 6.5 1.5 7.4 ns

tPLH CP to On1.5 6.2 1.5 6.5 1.5 7.4

tPZL Output Enable time 1.5 6.1 1.5 6.3 1.5 7.9 ns

tPZH 1.5 6.1 1.5 6.3 1.5 7.9

tPLZ Output Disable Time 1.5 6.0 1.5 6.2 1.5 7.2 ns

tPHZ 1.5 6.0 1.5 6.2 1.5 7.2

tSSetup Time 2.5 2.5 3.0 ns

tHHold Time 1.5 1.5 2.0 ns

tWPulse Width 3.0 3.0 3.5 ns

tOSHL Output to Output Skew (Note 8) 1.0 ns

tOSLH 1.0

Symbol Parameter Conditions VCC TA

CUnits

(V) Typical

VOLP Quiet Output Dynamic Peak VOL CL

50 pF, VIH

3.3V, VIL

0V 3.3 0.8 V

30 pF, VIH

2.5V, VIL

0V 2.5 0.6

VOLV Quiet Output Dynamic Valley VOL CL

50 pF, VIH

3.3V, VIL

0V 3.3



0.8 V

30 pF, VIH

2.5V, VIL

0V 2.5 0.6

Symbol Parameter Conditions Typical Units

CIN Input Capacitance VCC

Open, VI

0V or VCC 7pF

COUT Output Capacitance VCC

3.3V, VI

0V or VCC 8pF

CPD Power Dissipation Capacitance VCC

3.3V, VI

0V or VCC, f

10 MHz 20 pF

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74LCX16374

AC LOADING and WAVEFORMS Generic for LCX Family

FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)

Waveform for Inverting and Non-Inverting Functions

Propagation Delay. Pulse Width and trec Waveforms

3-STATE Output Low Enable and

Disable Times for Logic

3-STATE Output High Enable and

Disable Times for Logic

Setup Time, Hold Time and Recovery Time for Logic

trise and tfall

FIGURE 2. Waveforms

(Input Characteristics; f = 1MHz, tr = tf = 3ns)

Test Switch

tPLH, tPHL Open

tPZL, tPLZ 6V at VCC

3.3

0.3V, and 2.7V

VCC x 2 at VCC

2.5

0.2V

tPZH, tPHZ GND

Symbol VCC

3.3V

0.3V 2.7V 2.5V

0.2V

Vmi 1.5V 1.5V VCC/2

Vmo 1.5V 1.5V VCC/2

VxVOL



0.3V VOL



0.3V VOL



0.15V

VyVOH



0.3V VOH



0.3V VOH



0.15V

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74LCX16374

Schematic Diagram Ge neric f or LCX Family

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74LCX16374

Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Packag e Num b er BGA5 4A

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74LCX16374

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

Package Number MS48A

www.fairchildsemi.com 10

74LCX16374 Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Output s

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD48

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a lif e supp ort

device or system whose failure to perform can be rea-

sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.