APEX20K - Altera Corporation

Alt er a Cor pora t ion 1

APEX 20K

Programmable Logic

Device Family

Febr u ar y 2002, ver. 4.3 Data Sheet

DS-APEX20K-4.3

Features... ■Industry’s first programmable logic device (PLD) incorporating

system-on-a-programmable-chip (SOPC) integration

–MultiCore

TM architecture integrating look-up table (LUT) logic,

product-term logic, and embedded memory

– LUT logic used for regi ster-in ten sive fun ctions

– Embedded system block (ESB) used to implement memory

functions, including first-in first-out (FIFO) buffers, dual-port

RAM, and content-addressable memory (CAM)

– ESB implementation of product-term logic used for

combinatorial-intensive functions

■High density

– 30,000 to 1.5 million typical gates (see Tables 1 and 2)

– Up to 51,840 logic elements (LEs)

– Up to 442,368 RAM bits that can be used without reducing

available logic

– Up to 3,456 product-term-based macrocells

Table 1. APEX 20K Device Fea t ures Not e (1)

Feature EP20K30E EP20K60E EP20K100 EP20K100E EP20K160E EP20K200 EP20K200E

Maximum

system

gates

113,000 162,000 263,000 263,000 404,000 526,000 526,000

Typical

gates 30,000 60,000 100,000 100,000 160,000 200,000 200,000

LEs 1,200 2,560 4,160 4,160 6,400 8,320 8,320

ESBs 12 16 26 26 40 52 52

Maximum

RA M b i ts 24,576 32,768 53,248 53,248 81,920 106,496 106,496

Maximum

macrocells 192 256 416 416 640 832 832

Maximum

us er I/O

pins

128 196 252 246 316 382 376

2Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Note to ta bles:

(1) The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to

57,000 add itional gates.

...and More

Features

■Designed for low-power operation

– 1.8-V and 2.5-V supply voltage (see Table 3)

– MultiVoltTM I/O in te rfa ce su ppor t to inter face w i th 1.8 - V, 2 .5-V,

3.3-V, and 5.0-V devices (see Table 3)

– ESB offering programmable power-saving mode

Notes:

(1) Certain APEX 20K devices are 5.0-V tolerant. See “MultiVolt I/O Interface” on page

46 for details.

(2) APE X 20KE devices c an be 5.0- V tolerant by u s ing an ex t ernal resisto r .

Table 2. APEX 20K Device Fea t ures Note (1)

Feature EP20K300E EP20K400 EP20K400E EP20K600E EP20K1000E EP20K1500E

Maximum

system gates 728,000 1,052,000 1,052,000 1,537,000 1,772,000 2,392,000

Typical gates 300,000 400 ,00 0 400, 000 600,0 00 1,000,000 1,500,000

LEs 11,520 16,640 16,640 24,320 38,400 51,840

ESBs 72 104 104 152 160 216

Maximum

RA M b i ts 147,456 212,992 212,992 311,296 327,680 442,368

Maximum

macrocells 1,152 1,664 1,664 2,432 2,560 3,456

Max imum us er

I/O pins 408 502 488 588 708 808

Tabl e 3. APE X 20K Supply Vol t ages

Feature Device

EP20K100

EP20K200

EP20K400

EP20K30E

EP20K60E

EP20K100E

EP20K160E

EP20K200E

EP20K300E

EP20K400E

EP20K600E

EP20K1000E

EP20K1500E

Internal supply voltage (VCCINT) 2.5 V 1.8 V

MultiVolt I/O interface voltage

leve ls (VCCIO)2.5 V, 3.3 V, 5.0 V (1) 1.8 V, 2.5 V, 3.3 V,

5.0 V (2)

Altera Corporation 3

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

■Flexible clock management circuitry with up to four phase-locked

loops (PLLs)

– Built-in low-skew clock tree

– Up to eight global clock signals

– ClockLockTM feature reducing clock delay and skew

– ClockBoostTM fe ature providing clock multiplication and

division

– ClockShiftTM programmable clock phase and delay shifting

■Powerful I/O features

– Compliant with peripheral component interconnect Special

Interest Group (PCI SIG) PCI Local Bus Specification,

Revision 2.2 for 3.3- V o pera tion at 3 3 or 66 MHz and 32 o r 6 4 bit s

– Sup port for high-speed external memorie s, incl u di ng DDR

SDRAM and Z B T SRAM (ZB T is a trademark of Integra ted

Device Technology, Inc.)

– Bidirectio nal I/O performance (tCO + tSU) up to 250 MHz

– LVDS performance up to 840 Mbits per channel

– Direct con nection from I/O pins to local in te rconne ct pr oviding

fast tCO and tSU times for complex logic

– MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,

3.3-V, and 5.0-V devices (see Table 3)

– P rogrammab le clamp to VCCIO

– Individual tri-state output enable control for each pin

– Programmable output slew-rate control to reduce switching

noise

– Support for advanced I/O standards, including low-voltage

differential signalin g (LV DS) , LVPECL, PCI-X, AGP , CTT, stub-

series terminated logic (SSTL-3 and SSTL-2), Gunning

transceiver logic plus (GTL+), and high-speed terminated logic

(HSTL Class I)

– Pull-up on I/O pins before and during configura tion

■Ad vanced interco nnect str ucture

– Four-level hierarchical FastTrack® Interconnect stru cture

providing fast, predictable interconnect delays

– Dedicated carry chain that implements arithmetic functions such

as fast adders, counters, and comparators (automatically used by

software tools and megafunctions)

– Dedicated cascade chain that implements high-speed,

high-fan-i n logic fu nctions (automa tically used by software t ools

and megafunctions)

– Interleaved local interconnect allows one LE to drive 29 other

LEs through the fast local interconnect

■Advanced packaging options

– Availa ble in a variety of packages with 144 to 1,020 pins (see

Tables 4 through 7)

– FineLine BGATM packages maximize board space efficiency

■Advanced software support

– Software design support and automatic place-and-route

provided by the Altera® QuartusTM II d e velopment sy stem for

4Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Windows-based PCs, Sun SPARCstations, and HP 9000

Series 700/800 workstations

–Altera MegaCore

® functions and Altera Megafunction Partners

Program (AMPPSM) megafunctions

–NativeLink

TM integration with popular synthesis, simulation,

and timing analysis tools

– Quartus II SignalTapTM embedded logic analyzer simplifies

in-system design evaluation by giving access to internal nodes

during device operation

– Supports popular revision-control software packages including

PVCS, Revision Control System (RCS), and Source Code Control

System (SCCS )

Table 4. APEX 20K QFP, BGA & PGA Package Options & I/O Count Notes (1), (2)

Device 144-Pin

TQFP 208-Pin

PQFP

RQFP

240-Pin

PQFP

RQFP

356- P i n BG A 652-P i n BG A 655 -Pi n PG A

EP20K30E 92 125

EP20K60E 92 148 151 196

EP20K100 101 159 189 252

EP20K100E 92 151 183 246

EP20K160E 88 143 175 271

EP20K200 144 174 277

EP20K200E 136 168 271 376

EP20K300E 152 408

EP20K400 502 502

EP20K400E 488

EP20K600E 488

EP20K1000E 488

EP20K1500E 488

Altera Corporation 5

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Notes to tables:

(1) I/O counts include dedicated input and clock pins.

(2) APEX 20K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat

pack (RQ FP ), 1.2 7-mm pitc h b all -g ri d array (BG A), 1.00-mm pi tch Fi n eLin e BGA, and pi n- grid ar r ay (PGA)

packages.

(3) This device uses a thermally enhanced package, which is taller than the regular package. Consult the Altera Device

Package Information Data Sheet for detailed package size infor mation.

Table 5. APEX 20K FineLi ne BGA Packag e Options & I/O Count Notes (1), (2)

Device 144 Pin 324 Pin 484 Pin 672 Pin 1,020 Pin

EP20K30E 93 128

EP20K60E 93 196

EP20K100 252

EP20K100E 93 246

EP20K160E 316

EP20K200 382

EP20K200E 376 376

EP20K300E 408

EP20K400 502 (3)

EP20K400E 488 (3)

EP20K600E 508 (3) 588

EP20K1000E 508 (3) 708

EP20K1500E 808

Table 6. APEX 20K QFP, BGA & PGA Package Si zes

Feature 144-Pin TQFP 208-Pin QFP 240-Pin QFP 356 -Pi n BG A 6 52-Pi n BGA 655- Pin PGA

Pitch (mm) 0. 50 0.50 0. 50 1.27 1.27 –

Area (mm2) 484 924 1,218 1,225 2,025 3,906

Length × Width

(mm × mm) 22 × 22 30.4 × 30.4 34.9 × 34.9 35 × 35 45 × 45 62. 5 × 62.5

Table 7. APEX 20K FineLi ne BGA Pa ckag e Sizes

Feature 144 Pin 324 Pin 484 Pin 672 Pin 1,020 Pin

Pitch (mm) 1.00 1.00 1.00 1. 00 1.00

Area (mm2) 169 361 529 729 1,089

Length × Width (mm × mm) 13 × 13 19 × 19 23 × 23 27 × 27 33 × 33

6Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

General

Description

APEXTM 20K devices are the first PLDs designed with the MultiCore

architecture, which combines the strengths of LUT-based and product-

term-based devices with an enhanced memory structure. LUT-based logic

provides optimized performance and efficiency for data-path, register-

intensive, mathematical, or digital signal processing (DSP) designs.

Product-term-based logic is optimized for complex combinatorial paths,

such as complex state machines. LUT- and product-term-based logic

combined with memory functions and a wide variety of MegaCore and

AMPP function s make the APE X 20K device a rchitecture un iquely suit ed

for system-on-a-programmable-chip designs. Applications historically

requiring a combination of LUT-, product-term-, and memory-based

de vices can now be inte g rated in to one AP EX 20K de vice.

APEX 20K E dev ic es are a superset of APEX 20K devices and include

additional features such as advanced I/O standard support, CAM,

additional global clocks, and enhanced ClockLock clock circuitry. In

addition, APEX 20KE devices extend the APEX 20K family to 1.5 million

gates. APEX 20KE devices are denoted w i th an “E” suffi x i n the device

name (e.g., the EP20K1000E device is an APEX 20KE device). Table 8

compares the features included in APEX 20K and APEX 20KE devices.

Altera Corporation 7

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Tab l e 8. Comp ar i s on of APE X 20K & AP EX 20K E Featur e s

Feature APEX 20K Devi ces APEX 20KE Dev i ce s

MultiCore system integration Full suppo rt Full support

SignalTa p logic analy s is Full s upport Full suppo rt

32/64-B it, 33-M H z PCI Full com pliance in -1, -2 speed

grades F ull c om pliance in -1, -2 speed gr ades

32/64-Bit, 66-MHz PCI - Full compliance in -1 speed grade

MultiVolt I/O 2.5-V or 3.3-V VCCIO

VCCIO selected for device

Certain devices are 5. 0-V tolerant

1.8-V , 2.5-V, or 3. 3-V VCCIO

VCCIO selected block-by-block

5.0-V tolerant with use of external resistor

ClockLo ck su pport Clock delay reduc t ion

2× and 4× clock mul ti p lication Clock delay reduction

m/(n × v) or m/(n × k) clock multiplication

Drive C loc kL ock out put of f-chip

External clock feedback

ClockShift

LVDS support

Up to four PLLs

Clock Shif t , cloc k pha se adjus tment

Dedicate d clo ck and input pins Six Eight

I/O standard s upport 2.5-V, 3.3-V, 5.0-V I/O

3.3-V PCI

Low- vo lta ge co mp lem ent ary

metal-oxide semiconduct or

(LVCMOS)

Low- vo lta ge tra ns istor-to-tra ns istor

logic (LVTTL)

1.8-V , 2.5-V, 3. 3-V, 5.0 -V I/O

2.5-V I/O

3.3-V PCI and PC I -X

3.3-V Advanced Graphics Port (AGP)

Center t ap te rm inat ed (C T T)

GTL+

LVCMOS

LVTTL

True- LVD S and LVPECL data pins

(in EP20K300E and larger devices)

LVDS and LVPECL clock pins (in all BGA

and Fin eLine BGA devic es )

LVDS and LVPECL dat a pins up to

156 Mbps (in -1 speed grade devices)

HSTL Class I

PCI-X

SSTL -2 C las s I and II

SSTL -3 C las s I and II

Memory support Dual-port RAM

FIFO

RAM

ROM

CAM

Dual- port RA M

FIFO

RAM

ROM

8Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Al l APEX 20 K devices are reconfig urable and are 100% tested prior to

shipment. As a result, test vectors do not have to be generated for fault

coverage purposes. Instead, the designer can focus on simulation and

design verification. In addition , the designe r do es not need to manage

inventories of different application-specific integrated circuit (ASIC)

designs; APEX 20K devices can be configured on the board for the specific

function alit y required.

APEX 20K devic es are conf igur ed at system pow er-up with da ta stored in

an Altera serial configuration device or provided by a system controller.

Altera offers in-system programmability (ISP)-capable EPC1, EPC2, and

EPC16 configuratio n de v ices, which configure APEX 20K devices via a

serial data stream. Moreover, APEX 20K devices contain an optimized

interface that permits microprocessors to configure APEX 20K devices

serially or in parallel, and synchronously or asynchronously. The interface

also enables microprocessors to treat APEX 20K devices as memory and

configure the device by writing to a virtual memory location, making

reconfiguration easy.

After an APEX 20K device has been configured, it can be reconfigured

in-circuit by resetti ng the de vice and loadin g new data. Real-time changes

can be made during system operation, enabling innovative reconfigurable

computing applications.

APEX 20K devices are supported by the Altera Quartus II development

system, a single, integrated package that offers HDL and schematic design

entry, compilation and logic synthesis, full simulation and worst-case

timing analysis, SignalTap logic analysis, and device configuration. The

Qu artus II software runs on Win dows- b ased PCs, Sun S PARCstations,

and HP 900 0 S eri e s 700 / 80 0 wor k sta ti ons.

The Qua rtus II softwa re provi des Nat iveLin k inte rface s to othe r indust ry-

standard PC- and UNIX workstation-based EDA tools. For example,

designers can invoke the Quartus II software from within third-party

design tools. Furthe r, the Quart us I I soft wa re con tai ns b uilt -in op timiz ed

synthesis libraries; synthesis tools can use these libraries to optimize

desig ns fo r APEX 20K devices. For example, the Synops ys Design

Compiler library, supplied with the Quartus II development system,

includ es Desig nWar e fun ctions optimi ze d for the APEX 20K archi tecture .

Altera Corporation 9

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Functional

Description

APEX 20K devices incorporate LUT-based logic, product-term-based

logic, and memory into one device. Signal interconnections within

APEX 20K devices (as well as to and from device pins) are provided by the

FastTrack Interconnect—a series of fast, continuous row and column

channels that run the entire length and width of the device.

Each I/O pin is fed by an I/O element (IOE) located at the end of each row

and column of the FastTrack Interconnect. Each IOE contains a

bid ir e cti o nal I /O bu f fer an d a re gister t hat can be used as ei t her an input

or output register to feed input, output, or bidirectional signals. When

used with a dedicated clock pin, these registers provide exceptional

performance. IOEs provide a variety of features, such as 3.3-V, 64-bit,

66-MHz PCI compliance; JTAG BST support; slew-rate control; and

tri-state buffers. APEX 20KE devices offer enhanced I/O support,

including sup port for 1.8-V I/O, 2.5-V I/O , LVCMOS, LVTTL, LVPECL,

3.3-V PCI, PCI-X, LVDS, GTL+, SSTL-2, SSTL-3, HSTL, CTT, and 3.3-V

AGP I/O standards.

The ESB can implement a variety of memory functions, including CAM,

RAM, dual-port RAM, ROM, and FIFO functions. Embedding th e

memory direc tly into the die improve s performanc e and reduces die area

compared to distributed-RAM implementations. Moreover, the

abundance of cascadable ESBs ensures th at the APEX 20K device can

implement multiple wide memory blocks for high-density designs. The

ESB’ s high sp eed ensu res it can im plemen t smal l memory b locks wi thout

any speed penalty . The abundance of ESBs e nsures that de signers ca n

create as many different-sized memory blocks as the system requires.

Figure 1 shows an overview of the APEX 20K device.

Figure 1. A PEX 20K Device B l ock D iagr am

LUT

Memory

IOE

IOE IOE

IOE

IOE IOE

LUT

Memory

IOE

Product Term

LUT

Memory

IOE

Product Term

Product Term Product Term

Product Term

FastTrack

Interconnect

Clock Management Circuitry

IOEs support

PCI, GTL+,

SSTL-3, LVDS,

and other

standards.

ClockLock

Four-input LUT

for data path and

DSP functions.

Product-term

integration for

high-speed

control logic and

state machines. Flexible integration

of embedded

memory, including

CAM, RAM,

ROM, FIFO, and

other memory

functions.

10 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

APEX 20K devices provide two dedicated clock pins and four de di cated

input pin s that drive regis ter control input s. These signals ensu re efficie nt

distribution of high-speed, low-skew control signals. These signals use

dedicated routing channels to provide short delays and low skews. Four

of the de dicated inputs d rive four global s ignals. These four global signals

can also be driven by interna l logic, providing an ideal solution for a clock

divider or internally generated asynchronous clear signals with high

fan-out. The dedicated clock pins featured on the APEX 20K devices can

also feed logic. The devices also feature ClockLock and ClockBoost clock

management circuitry. APEX 20KE devices provide two additional

dedic at ed clock pins, for a total of four dedicated clock pins.

MegaL AB St ru ctur e

APEX 20K devices are con st ru cted from a series of MegaLABTM

structures. Each MegaLAB structure contains a group of logic array blocks

(LABs), one ESB, and a MegaLA B i nterconnec t, which routes signals

within the Mega LAB structu re. The EP20K3 0E device has 10 LABs,

EP20K60E through EP20K600E devices have 16 LABs, and the

EP20K100 0E and EP20K15 00 E devices have 2 4 LA Bs. Signals are ro uted

between MegaLAB structures and I/O pins via the FastTrack

Interconnect. In addition, edge LABs can be driven by I/O pins through

the local interconnect. Figure 2 shows the MegaLAB structure.

Figure 2. MegaLAB Structure

ESB

MegaLAB Interconnect

Local

Interconnect

To Adjacent

LAB or IOEs

LABs

LE1

LE2

LE3

LE4

LE5

LE6

LE7

LE8

LE9

LE10

LE1

LE2

LE3

LE4

LE5

LE6

LE7

LE8

LE9

LE10

LE1

LE2

LE3

LE4

LE5

LE6

LE7

LE8

LE9

LE10

Altera Corporation 11

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Logic Array Bloc k

Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains,

LAB control signals, and the local interconnect. The local interconnect

transfers si gnals between LEs in the same or adjacent LABs, IOEs, or ESBs.

The Quartus II Compiler places associated logic within an LAB or adjacent

LABs, allowing the use of a fast local interconnect for high performance.

Figure 3 shows the APEX 20K LAB.

APEX 20K devices use an interleaved LAB structure. This structure allows

each LE to dr ive two local int ercon nec t are as. Thi s featur e minimize s use

of the MegaLAB and FastTrack interconnect, providing higher

performance and flexibility. Each LE can drive 29 other LEs through the

fast local interconnect.

Figure 3. LAB Structure

To/From

Adjacent LAB,

ESB, or IOEs

To/From

Adjacent LAB,

ESB, or IOEs

The 10 LEs in the LAB are driven by

two local interconnect areas. These LEs

can drive two local interconnect areas.

Local Interconnect

LEs drive local

MegaLAB, row,

and column

interconnects.

Column

Interconnect

Row

Interconnect

MegaLAB Interconnect

12 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Each LAB contains dedicated logic for driving control signals to its LEs

and ESBs. The control signals include clock, clock enable, asynchronous

clear, asynchronous preset, asynchronous load, synchronous clear, and

synchronous load signals. A maximum of six control signals can be used

at a ti me. Althou gh synchron ous load an d clear sig nals are g enerally us ed

when implementing counters, they can also be used with other functions.

Each LAB can use two clocks and two clock enable signals. Each LAB’s

clock and c lock e na ble s ig nals a re linked (e.g. , a ny L E in a partic ula r LAB

using CLK1 w ill also use CLKENA1). LEs w ith th e s ame cloc k bu t diffe rent

clock enable sig nals e ither u se both cloc k signal s in one LAB or are pla ced

into separate LABs.

If both the rising and falling edges of a c lock are used in a LAB, both LAB -

wide clock signals are used.

The LAB-wide control signals can be generated from the LAB local

interconnect, global signals, and dedicated clock pins. The inherent low

skew of the FastTrack Interconnect enables it to be used for clock

distribution. Figure 4 shows the LAB control signal generation circuit.

Figure 4. LAB Co nt rol Signal Generat i on

Notes:

(1) APEX 20KE devices have four dedicated clocks.

(2) The LABCLR1 and LABCLR2 signals also control asynchron ous load and asy n chronous preset for LEs within the

LAB.

(3) The SYNCCLR sign a l c an be generate d by the local inter c o nnec t o r glo bal si gn a ls.

SYNCCLR

or LABCLK2

(3)

SYNCLOAD

or LABCLKENA2

LABCLK1

LABCLKENA1

LABCLR2

(2)

LABCLR1

(2)

Dedicated

Clocks

Global

Signals

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

2 or 4

(1)

Altera Corporation 13

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Logic Element

The L E, the smalles t unit of lo gic in the APEX 20K archite cture, is c ompact

and provides efficient logic usage. Each LE contains a four-input LUT,

whic h is a fu ncti on g en erat or th at can quickly i mple ment an y function of

four variables. In addition, each LE contains a programmable register and

carry and cascade chains. Each LE drives the local interconnect, MegaLAB

inte r conn ect , and FastT r ac k Inte r conn ec t ro utin g structure s. Se e Figure 5.

Figure 5. AP EX 20K Logi c Element

Each LE’s programmable register can be configured for D, T, JK, or SR

operation. The register’s clock and clear control signals can be driven by

global signals, general-purpose I/O pins, or any internal logic. For

combinatorial functions, the register is bypassed and the output of the

LUT drives the outputs of the LE.

labclk1

labclk2

labclr1

labclr2

Carry-In

Clock &

Clock Enable

Select

Carry-Out

Look-Up

Table

(LUT)

Carry

Chain Cascade

Chain

Cascade-In

Cascade-Out

To F

astTrack Interconnect,

MegaLAB Interconnect,

or Local Interconnect

To F

astTrack Interconnect,

MegaLAB Interconnect,

or Local Interconnect

Programmable

PRN

CLRN

ENA

Packed

Chip-Wide

Reset

labclkena1

labclkena2

Synchronous

Load & Clear

Logic

LAB-wide

Synchronous

Load

LAB-wide

Synchronous

Clear

Asynchronous

Clear/Preset/

Load Logic

data1

data2

data3

data4

14 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Each LE has two outputs that drive the local, MegaLAB, or FastTrack

Inter conn ect r outin g s tr uct ur e. Ea ch output can be dri ven indep ende ntly

by the LUT’s o r reg ister’s o utput. For exampl e, the LUT can d r ive o ne

output while the register drives the other output. This feature, called

regist er p acking, improve s device utiliz ation because t he reg ist er a nd t he

LUT can be used for unrelated functions. The LE can also drive out

registered and unregistered versions of the LUT output.

The APEX 20K architecture provides two types of dedica ted high-speed

data paths that connect adjacent LEs without using local interconnect

paths: carry chains and cascade chains. A carry chain supports high-speed

ar ithm eti c functions such as counters an d add ers, while a cas cade chain

implements wide-input functions such as equality comparators with

minimu m delay . Car ry an d casc ade chain s connect LEs 1 throug h 10 in an

LAB and all LABs in the same M egaLAB structure.

Carry Chain

The carry chain provides a very fast carry-forward function between LEs.

The carry-in signal from a lower-order bit drives forward into the higher-

order bit via the carry chain, and feeds into both the LUT and the next

portio n of th e car ry ch ain . Th is fe ature al lows the APE X 20K archite ctu r e

to implement high-speed counters, adders, and comparators of arbitrary

width. Carry chain logic can be created automatically by the Quartus II

software Compiler during design processing, or manually by the designer

during design entry. Parameterized functions such as library of

parameterized modules (LPM) and DesignWare functions automatically

take advantage of carry chains for the appropriate functions.

The Quartus II software Compiler creates carry chains longer than ten LEs

by linking LABs together automatically. For enhanced fitting, a long carry

chain skips alternate LABs in a MegaLAB structure. A carry chain longer

th an one LAB s k ips ei ther fro m an ev en-numbered LAB to th e next even -

number ed LAB, o r fro m an odd-numbered LAB to the next odd-

numbered LAB. For example, the last LE of the first LAB in the upper-left

MegaLAB structure carries to the fi rst LE o f the t hird LAB in the

Mega LAB structur e.

Figure 6 shows how an n-bit full adder can be implemented in n + 1 LEs

with the carry chain. On e portion of t he LUT generat es the sum of two bits

using the input signals and the carry-in signal; the sum is routed to the

output of the LE. The register can be bypassed for simple adders or used

for accumulator functions. Another portion of the LUT and the carry chain

logic genera te s the carry -out sig nal , which is rou te d direct ly to the carry -

in signal of the next-higher-order bit. The final carry-out signal is routed

to an LE, where it is driven onto the local, MegaLAB, or FastTrack

Interc o nnect rou ting structures.

Altera Corporation 15

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Figure 6. APEX 20K Carr y Chain

LUT

Carry Chain

LE1

Carry Chain

LE2

Carry Chain

LEn

Carry Chain

Carry-Out

LEn + 1

Carry-In

LUT

16 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Cascade Chain

With the cascade chain, the APEX 20K architecture can implement

functions with a very wide fan-in. Adjacent LUTs can compute portions

of a function in parallel; the cascade chain serially connects the

intermedia te va lues. The casca de chai n can u se a lo gical AND or logical OR

(via De Morgan’s inversion) to connect the outputs of adjacent LEs. Each

additional LE provides four more inputs to the effective width of a

function, with a short cascade delay. Cascade chain logic can be created

automatica lly b y the Quartus II softw a re Com piler dur ing design

processing, or manually by the designer during design entry.

Ca sca d e ch ains longer than ten LEs ar e implemented automatically b y

linking LABs together. For enhanced fitting, a long cascade chain skips

alter na te LA Bs in a Meg aL A B st r uct ur e. A cascad e chain longer th an one

LAB skips either from an even-numbered LAB to the next even-numbered

LAB, or from an odd-numbered LAB to the next odd-numbered LAB. For

exam p l e, the las t LE o f the fir st LAB in the upper-l e f t Meg a LA B s tr u c t ur e

carrie s to the first LE of th e third LAB in the MegaLAB str ucture. Figure 7

shows how the cascade function can connect adjacent LEs to form

functions with a wide fan-in.

Figu re 7. APE X 20K Cascade Chain

LE1

LUT

LE2

LUT

d[3..0]

d[7..4]

d[(4

n –

1)..(4

n –

4)]

d[3..0]

d[7..4]

LE1

LE2

LUT

AND Cascade Chain OR Cascade Chain

d[(4

n –

1)..(4

n –

4)]

Altera Corporation 17

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

LE Operat ing M ode s

The APEX 20 K LE can operate in one of the following three modes:

■Normal mode

■Arithmet ic mode

■Counter mod e

Each mode uses LE resources differently. In each mode, seven available

inputs to the LE—the four data inputs from the LAB local interconnect,

the feedback from the programmable register, and the carry-in and

cas cade-in fro m the previous L E—are directed to differe nt destinations to

implement the desired log i c function. LAB-wide signals pro vide clock,

asynchronous clear, asynchronous preset, asynchronous load,

synchronous clear, synchronous load, and clock enable control for the

The Quartus II software, in conjunction with parameterized functions

such as LPM and De sig nWar e functions, automatically chooses the

appropriate mode for common functio ns such as co unt ers , adders, and

multipliers. If required, the designer can also create special-purpose

functions that specify which LE operating mode to use for optimal

performance. Figure 8 shows the LE operating modes.

18 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Figure 8. APEX 20K LE Operating Modes

Notes:

(1) LEs in normal mode support register packing.

(2) There are two LAB-wide clock enables per LAB.

(3 ) When usin g t h e carry - in in n o r mal mod e, th e packed reg is t er fe at ure is un a v aila ble.

(4) A register feedback multiplexer is available on LE1 of each LAB.

(5) The DATA1 and DATA2 input signals can supply counter enable, up or down control, or register feedback signals for

LEs other than the second LE in an LAB.

(6) The LAB-wide synchronous clear and LAB wide synchronous load affect all registers in an LAB.

PRN

CLRN

4-Input

LUT

Carry-In

(3)

Cascade-Out

Cascade-In LE-Out

Normal Mode

(1)

PRN

CLRN

Cascade-Out

Cascade-In

3-Input

LUT

Carry-In

3-Input

LUT

Carry-Out

Arithmetic Mode

Counter Mode

data1

(5)

data2

(5)

PRN

CLRN

Carry-In

LUT

3-Input

LUT

Carry-Out

data3 (data)

Cascade-Out

Cascade-In

LAB-Wide

Synchronous

Load

(6)

LAB-Wide

Synchronous

Clear

(6)

(4)

LE-Out

ENA

LAB-Wide

Clock Enable

(2)

ENA

LAB-Wide

Clock Enable

(2)

ENA

LAB-Wide

Clock Enable

(2)

data1

data2

data1

data2

data3

data4

Altera Corporation 19

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Normal Mode

The normal mod e is suitable for general log ic application s, combinatoria l

functions, or wide decoding functions that can take advantage of a

cascade chain. In normal mode, four data inputs from the LAB local

interconnect and the carry-in are inputs to a four-input LUT. The

Quartus II software Compiler automatically selects the carry-in or the

DATA3 signal as one of the inputs to the LUT. The LUT output can be

com bi ned wit h the casc ad e -in sig nal to form a cas cade cha in thr oug h the

cascade-out signal. LEs in normal mode support packed registers.

Arithmetic Mode

The arith metic mode is ideal for imple menting adders , accumulator s, and

compa rators. An L E in arithme tic mode use s two 3-inpu t LUTs. One LUT

computes a three-input function; the other generates a carry output. As

shown in Figure 8, the first LUT uses the carry-in signal and two data

inputs from the LAB local interconnect to generate a combinatorial or

registered output. For example, when implementing an adder, this output

is the sum of thr e e sig na ls: DATA1, DATA2, and ca rr y-in. The se cond L UT

uses the same three signals to generate a carry-out signal, thereby creating

a c ar r y cha i n. The arith m etic mode also suppo r ts sim ul t aneous us e o f the

cascade chain. LEs in arithmetic mode can drive out registered and

unregistered versions of the LUT output.

The Quar tus I I software imp leme nts p ara meteri zed fu ncti ons th at use the

arithmetic mode automatically where appropriate; the designer does not

need to specify how the carry chain will be used.

Counter Mode

The counter mode offers clock enable, counter enable, synchronous

up/down contr ol, synchr onous cl ear, and s ynchrono us lo ad options . The

counter enable and synchronous up/down control signals are generated

from the da ta in puts o f the LAB lo cal int erconne ct. T he s ynchrono us cle ar

and synchronous load options are LAB-wide signals that affect all

registers i n the LAB. Conseq u en tly, if any of the LEs in an LAB use the

counter mode, other LEs in that LAB must be used as part of the same

counter or be used for a combinatorial function. The Quartus II software

automatically places any registers that are not used by the counter into

other LABs.

20 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

The counter mode uses two three-input LUTs: one generates the counter

data, and the other generates the fast carry bit. A 2-to-1 multiplexer

provides synchronous loading, and another AND gate provide s

synchronous clearing. If the cascade function is used by an LE in counter

mode, the synchronous clear or load overrides any signal carried on the

cascade chain. The synchronous clear overrides the synchronous load.

LEs in arithmetic mode can drive out registered and unregistered versions

of the LUT output.

Clear & Preset Logic Control

Logic fo r the reg ist er’ s clear and pres et sign als is contr oll ed by LAB-w ide

signals. The LE directly supports an asynchronous clear function. The

Quartus II software Compiler can use a NOT-gate push - back te chnique to

emulate an asynchronous preset. Moreover, the Quartus II software

Compiler can use a programmable NOT-gate push-back technique to

emulate simultaneous preset and clear or asynchronous load. However,

this technique uses three additional LEs per register. All emulation is

performed automatically when the design is compiled. Registers that

emulate simultaneous preset and load will enter an unknown state upon

power-up or when the chip-wide reset is asserted.

In addit ion to th e two cle ar and pre set modes, A PEX 20K devices provid e

a chip-wide reset pin (DEV_CLRn) that resets all registers in the device.

Use of this pin is controlled through an option in the Quartus II software

that is set before compilation. The chip-wide reset overrides all other

contr ol signals. Reg ist er s us ing an a synchronous pres et are preset when

the chip-wide reset is asserted; this effect results from the inversion

technique used to implement the asynchro nous preset.

FastTrack Interconnect

In the APEX 20K architecture, connections between LEs, ES Bs, and I/O

pins are provided by the FastTrack Interconnect. The FastTrack

Interconnect is a series of continuous horizontal and vertical routing

channels that traverse the device. This global routing structure provides

predictable performance, even in complex designs. In contrast, the

segmented routing in FPGAs requires switch matrices to connect a

variable number of routing paths, increasing the delays between logic

resources and reducing p erformance.

The FastTrack Interconnect consists of row and column interconnect

channels that span the entire device. The row interconnect routes signals

throughout a row of MegaLAB structures; the column interconnect routes

signals throughout a column of MegaLAB structures. When using the row

and column interconnect, an LE, IOE, or ESB can drive any other LE, IOE,

or ESB in a device. See Figure 9.

Altera Corporation 21

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Figure 9. AP EX 20K Interconnec t Stru ctur e

A row line can be driven direc tly by LEs, IOEs, o r ESBs in that row.

Furth er, a column lin e can dr ive a row line, al lowing an LE, IOE, or ESB t o

drive elements in a different row via the column and row interconnect.

The row interconnect drives the MegaLAB interconnect to drive LEs,

IOEs, or ESBs i n a pa rticular MegaLAB stru cture.

A colu mn line can be directl y driven by LEs , IOEs, or ESB s in tha t column.

A column line on a device’s left or right edge can also be driven by row

IOEs. T he column line is used to route sig nals from one row to anoth er. A

column line can drive a row line; it can also drive the MegaLAB

interconnect directly, allowing faster connections between rows.

Figure 10 shows how the FastTrack Interconnect uses the local

intercon ne ct to drive LEs withi n MegaLAB s tructures .

MegaLAB MegaLAB MegaLAB MegaLAB I/O

I/O I/OI/OI/O

I/O

MegaLAB MegaLAB MegaLAB MegaLAB I/O

I/O I/OI/OI/O

Column

Interconnec

Column

Interconnect

Row

Interconnect

22 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Figure 10. FastTrack Connection to Local Interconnect

I/O

MegaLAB

Column

Row

MegaLAB

Interconnect

Row & Column

Interconnect Drives

MegaLAB Interconnect

MegaLAB

Interconnect Drives

Local Interconnect

Row

Column

Altera Corporation 23

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Figure 11 shows the intersection of a row and column interconnect, and

how these forms of interconnects and LEs drive each other.

Figure 11. Driving the FastTrack Interconnect

APE X 20KE devic es incl ude an e nhance d int erconne ct str ucture for f aste r

rou ting of input signals with high fan-out. Col umn I/O pi ns can drive the

FastRow interconnect, which routes signals directly into the local

inte rconnect with out having t o drive thr ough the MegaLAB in terc onnect .

FastRow lines traverse two MegaLAB structures. Also, these pins can

drive the local interconnect directly for fast setup times. On EP20K300E

and larger devices, the FastRow interconnect drives the two MegaLABs in

the top left corner, the two MegaLABs in the top right corner, the two

MegaLABS in the bottom left corner, a nd the two MegaLABs in the

bottom right corner. On EP20K200E and smaller devices, FastRow

inte rconnect driv es the two Mega LABs on th e top and the t wo MegaLABs

on the bottom of the device. On all devices, the FastRow interconnect

drives all local interconnect in the appropriate MegaLABs except the

inte rconnect areas on the fa r left a nd far r ight of the Me gaLAB. Pi ns usin g

the FastRow interconnect achieve a faster set-up time, as the signal does

not need to use a MegaLab interconnect line to reach the destination LE.

Figure 12 shows the FastRow interconnect.

Row Interconnect

MegaLAB Interconnect

Column

Interconnec

Local

Interconnect

24 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Figure 12. APEX 20KE FastRow Interconnect

Table 9 summarizes h ow vari ous elements of the APEX 20K ar chitectu r e

drive each other.

IOE IOE IOE IOE

FastRow Interconnect

Drives Local Interconnect

in Two MegaLAB Structures

MegaLAB MegaLAB

Local

Interconnect

Select Vertical I/O Pins

Drive Local Interconnec

and FastRow

Interconnect

FastRow

Interconnect

LEs

LABs

Altera Corporation 25

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Note:

(1) This connection is supported in APEX 20KE devices only.

Product-Term Logic

The product-term portion of the MultiCore architecture is implemented

with the ESB . The ESB can be configure d to act as a bloc k of macroc ells on

an ESB-by-ESB basis. Each ESB is fed by 32 inputs from the adjacent local

interconnect; therefore, it can be driven by the MegaLAB interconnect or

the adjacent LAB. Als o, ni ne ESB macro ce l l s feed ba ck int o the ESB

through the local interconnect for higher performance. Dedicated clock

pins, global signals, and additional inputs from the local interconnect

drive the ESB control signals .

In product-term mode, each ESB contains 16 macrocells. Each macrocell

consists of two product terms and a programmable register. Figure 13

shows the ESB in product-term mode.

Table 9. APEX 20K Routing Scheme

Source Destination

Row

I/O Pin Column

I/O Pin LE ESB Local

Interconnect MegaLAB

Interconnect Row

FastTrack

Interconnect

Column

FastTrack

Interconnect

FastRow

Interconnect

Row I/O Pin vvvv

Column I/O

(1)

LE vvvv

ESB vvvv

Local

Interconnect

vvvv

MegaLAB

Interconnect

Row

FastTrack

Interconnect

v v

Column

FastTrack

Interconnect

FastRow

Interconnect

(1)

26 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Figur e 13. Pr oduc t -Term Logic in ESB

Note:

(1) APEX 20KE devices have four dedicated clocks.

Macrocells

APEX 20K macrocells can be confi gured individua lly for either s equential

or combinatorial logic operation. The macrocell consists of three

function al block s: the logi c arr ay, t he p roduct-t erm se lect mat rix, and th e

programmable register.

Combinatorial logic is implemented in the product terms. The product-

term sele ct matrix alloc ates the se pro du ct t erms for use as eith er pr ima ry

logic inputs (to the OR and XOR gates) to implement combinatorial

functions, or as parallel expanders to be used to increase the logic

available to another macrocell. One product term can be inverted; the

Quartus II software uses this feature to perform DeMorgan’s inversion for

more efficient implementation of wide OR functions. The Quartus II

soft ware Com pil er can us e a NOT-gate push-back technique to emulate an

asyn chro nous preset. Figure 14 shows the APEX 20K macrocell.

Global Signals

Dedicated Clocks

Macrocell

Inputs (1-16)

CLK[1..0]

ENA[1..0]

CLRN[1..0]

From

Adjacent

LAB

MegaLAB Interconnect

To Row

and Column

Interconnect

216

4 2 or 4

(1)

Local

Interconnect

Altera Corporation 27

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Figure 14. APEX 20K Macr ocell

For registered functions, e ach macrocell register can be programmed

individually to implement D, T, JK, or SR operation with programmable

clock control. The register can be bypassed for combinatorial operation.

During design entry, the designer specifies the desired register type; the

Quartus II software then selects the most efficient register operation for

each registered function to optimize resource utilization. The Quartus II

softw are or oth er s ynt he sis tools ca n a lso select the mo st effic ien t reg is ter

operation automatically when synthesizing HDL designs.

Each programmable register can be c locked by one of two ESB-wide

clocks. The ESB-wide clocks can be generated from device dedicated clock

pins, global signals, or local interconnect. Each clock also has an

associated clock enable, generated from the local interconnect. The clock

and clock enable signals a re related for a particular ESB; any macrocell

using a clock also uses the associated clock enable.

If both the rising and falling edges of a clock are used in an ESB, both

ESB-wide clock sign als are used.

Clock/

Enable

Select

Product-

Term

Select

Matrix

Parallel Logic

Expanders

(From Other

Macrocells)

ESB-Wide

Clears ESB-Wide

Clock Enables ESB-Wide

Clocks

32 Signals

from Local

Interconnect

Clear

Select

ESB

Output

Programmable

222

ENA

CLRN

28 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

The programmable register also supports an asynchronous clear function.

Within the ESB, two asynchronous clears are generated from global

signals and the local interconnect. Each macrocell can either choose

between the two asynchronous clear signals or choose to not be cleared.

Either of the two cl ear signals can be invert ed within the ESB. Figure 15

shows the ESB control log ic when implementing product-terms.

Figure 15. ESB Product-Term Mode Control Logic

Note:

(1) APEX 20KE devices have four dedicated clocks.

Parallel Expanders

Parallel expanders are unused product terms that can be allocated to a

neighboring macrocell to implement fast, complex logic functions.

Paralle l expan ders allo w up to 32 prod uct ter ms to fee d the macroce ll OR

logic directly, with two product terms provided by the macrocell and 30

parallel expanders provided by the neighboring macrocells in the ESB.

The Quartus II software Compile r can allocate up to 15 sets of up to two

paralle l expand ers per set to the macrocel ls automatica lly. Each se t of two

parallel expanders incurs a small, incremental timing delay. Figure 16

shows the APEX 20K parallel expanders.

CLK2 CLKENA2 CLK1 CLKENA1 CLR2 CLR1

Dedicated

Clocks

Global

Signals

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

2 or 4

(1)

Altera Corporation 29

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Figure 16. APEX 20K Parallel Expanders

Embedded

System Block

The ESB can implement various types of memory blocks, including

dual-port RAM, ROM, FIFO , an d CAM blocks. The ESB includes input

and output registers; the input registers synchronize writes, and the

output registers can pipeline designs to improve system performance. The

ESB offers a dual-port mode, which sup p or ts simul taneous reads and

writes at two different clock frequencies. Figure 17 shows the ESB block

diagram.

Figur e 17. ESB Block Diagra m

32 Signals from

Local Interconnect To Next

Macrocell

From

Macrocell

Product-

Term

Select

Matrix

Product-

Term

Select

Matrix

Macrocell

Product-

Term Logic

Macrocell

Product-

Term Logic

Parallel

Expander Switch

Parallel

Expander Switch

wraddress[]

data[]

wren

inclock

inclocken

inaclr

rdaddress[]

q[]

rden

outclock

outclocken

outaclr

30 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

ESBs can implement synchronous RAM, which is easier to use than

asynchronous RAM. A circuit using asynchronous RAM must generate

the RAM write enable (WE) signal, while ensuring that its data and address

signals meet setup and hold time specifications relative to the WE signal.

In contrast, the ESB’s synchronous RAM generates its own WE signal and

is self-timed w ith resp ec t to the g lob al clock . Cir c uits usin g t he ESB ’s se lf-

timed RAM must only mee t the set up and hold time specifica tion s of the

global clock.

ESB in puts are driv en by the adjac ent local interconne ct, which in turn c an

be driven by the MegaLAB or FastTrack Interconnect. Because the ESB can

be driven by the local interconn ect, an adjacent LE can drive it direct ly for

fast memory acce ss. ESB outpu ts dri v e t he Meg aLA B and FastTrack

Inter conn ect. In addi tion , ten ESB outputs , nine of which are uniq ue

output lines, drive the local interconnect for fast connection to adjacent

LEs or for fast feedback product-term logic.

When im plem enting m e m ory, each ESB can be config ured i n any of th e

following sizes: 128 ×16, 256 ×8, 512 ×4, 1,0 24 ×2, or 2,04 8 ×1. By

combining multiple ESBs, the Quartus II software implements larger

memory blocks automatically. For example, two 128 ×16 RA M blocks can

be combined to form a 128 ×32 RAM block, a nd two 512 ×4 RAM blocks

can be combined to form a 512 ×8 RAM block. Memory performance does

not degrade for memory bl o cks up to 2,048 words deep. Each ESB can

implement a 2,048-word-deep memory; the ESBs are used in parallel,

eliminating the need for any external control logic and its associated

delays.

To cr eate a hi gh-s peed me mory blo ck th at is mo re th an 2, 048 w ord s de ep,

ESBs drive tri-state lines. Each tri-state line connects all ESBs in a column

of MegaLAB structures, an d dri ves the MegaLAB interconnect and row

and column FastTrack Interconnect throughout the column. Each ESB

incorporat es a programmab le decoder to activate the tri-sta te driver

appr opriatel y. For instance , to im plemen t 8,192- word-de ep memor y, four

ESBs are used. Eleven address lines drive the ESB memory, and two more

drive the tri-state decoder. Depending on which 2,048-word memory

page is selected, the appropriate ESB driver is turned on, driving the

output to the tri-state line. The Quartus II software automatically

combines ESBs with tri-state lines to form deeper memory blocks. The

interna l tri-state cont rol logic is design ed to avoid inter nal conte ntion and

floating lines. See Figure 18.

Altera Corporation 31

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Figure 18. D eep Memo ry Block Implement ed wi th Multiple ESBs

The ESB implements two forms of dual-port memory: read/write clock

mode and input/o utput clock mode. The ES B ca n also be used for

bidirectional, dual-port memory applications in which two ports read or

write simultaneously. To implement this type of dual-port memory, two

or four ESBs are used to support two simultaneous reads or writes. This

functionality is shown in Figure 19.

Figure 19. APEX 20K ESB Implementing Dual-Port RAM

ESB

to System Logic

Address Decoder

Port A Port B

address_a[] address_b[]

data_a[] data_b[]

we_a we_b

clkena_a clkena_b

Clock A Clock B

32 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Read/W rite Cloc k Mo de

The read/write clock mode contains two clocks. One clock controls all

registers associated with writing: data input, WE, and wr ite addr ess . The

other clock controls all registers associated with reading: read enable

(RE), read address, and data output. The ESB also supports clock enable

and asynchronous clea r sig nals; these signals also control the read and

write regis ters inde pendently. Rea d/write cloc k mode is commonly used

for applications where reads and writes occur at different system

frequencies. Figure 20 shows the ESB in read/write clock mode.

Figure 20. ESB in Read/Write Clock Mode Note (1)

Notes:

(1) All re gister s can b e clea re d a synchro no usly b y ESB l o cal int erconn ect signa ls, gl obal signals, or the chi p-w ide re set .

(2) APEX 20KE devices have four dedicated clocks.

Dedicated Clocks

2 or 4 4

ENA Q

ENA

ENA Q

ENA

data[ ]

rdaddress[ ]

wraddress[ ]

RAM/ROM

128 × 16

256 × 8

512 × 4

1,024 × 2

2,048 × 1

Data In

Read Address

Write Address

Read Enable

Write Enable

Data Out

outclocken

inclocken

inclock

outclock

ENA Q

Write

Pulse

Generator

rden

wren

Dedicated Inputs &

Global Signals

To MegaLAB,

FastTrack &

Local

Interconnect

(2)

Altera Corporation 33

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Input/Output Clock Mode

The input /output clock mode contains tw o clocks. One clock controls all

registers for i npu ts i nto the ESB: data input, WE, RE, read addres s, an d

write address. The othe r clock cont rols the ESB data outp ut regist ers. The

ESB also supports clock enable and asynchronous clear signals; these

signals also control the reading and writing of registers independently.

Input/output clock mode is commonly used for applications where the

reads and writes occur at the same system frequency, but require different

clock enable signals for the input and output registers. Figure 21 shows

the ESB in input/output clock mode.

Figure 21. ESB in I nput/Output Cloc k Mo de Notes (1) , (2)

Notes:

(1) All registers can be cleared asynchronously by ESB l ocal interconnect sign als, global signals, or the ch ip-wide re set.

(2) APEX 20KE devices have four dedicated clocks.

Dedicated Clocks

2 or 4 4

ENA Q

ENA

ENA Q

ENA

data[ ]

rdaddress[ ]

wraddress[ ]

RAM/ROM

128 × 16

256 × 8

512 × 4

1,024 × 2

2,048 × 1

Data In

Read Address

Write Address

Read Enable

Write Enable

Data Out

outclken

inclken

inclock

outclock

ENA Q

Write

Pulse

Generator

rden

wren

Dedicated Inputs &

Global Signals

to MegaLAB,

FastTrack &

Local

Interconnect

(2)

34 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Sing le- P or t Mode

The APEX 20K ESB also supports a single-port mode, which is used when

si multaneous reads and wr ite s are not r equ ired. S ee Figure 22.

Figure 22. ESB i n Single-Port Mode Note (1)

Notes:

(1) All re gister s ca n b e asynchronously cleared b y ESB l o ca l interconn ect signa ls, gl obal si gnals, or the chip-wide re set .

(2) APEX 20KE devices have four dedicated clocks.

Content-Addressable Memory

In APEX 20KE devices, the ESB ca n implement CAM. CAM can be

thought of as the inverse of RAM. When read, RAM outputs the data for

a given address. Co nversely, CAM outpu ts an address for a gi v en dat a

wo r d . For example, if the data FA12 is stored in address 14, the CAM

outputs 14 when FA12 is driven into it.

CAM is used for high-speed search operations. When searching for data

within a RAM block, the search is performed serially. Thus, finding a

particul ar data word can ta ke man y cycles. CAM searc hes all add resses in

paralle l and out puts t he addres s storing a pa rticular w ord. Whe n a match

is found, a match flag is set high. Figure 23 shows the CAM bl ock

diagram.

Dedicated Clocks

2 or 4 4

ENA Q

ENA

ENA Q

ENA

data[ ]

address[ ]

RAM/ROM

128 × 16

256 × 8

512 × 4

1,024 × 2

2,048 × 1

Data In

Address

Write Enable

Data Out

outclken

inclken

inclock

outclock

Write

Pulse

Generator

wren

Dedicated Inputs &

Global Signals

to MegaLAB,

FastTrack &

Local

Interconnect

(2)

Altera Corporation 35

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Figure 23. APEX 20KE CAM Bloc k D iagram

CAM ca n b e used in an y a ppl ica tion r e qui ri ng h ig h-spe ed s ea rche s, s uch

as networking, communications, data compression, and cache

management.

The APEX 20KE on-chip CAM provid es faste r system perf ormanc e tha n

trad itional discre te CAM. Inte grating CAM an d logic into th e APEX 20KE

device eliminates off-chip and on-chip delays, improving system

performance.

When in CAM mode, the ESB implements 32-word, 32-bit CAM. Wider or

deeper CAM can be implemented by combining multiple CAMs with

some ancillary logic implemented in LEs. The Quartus II software

combines ESBs an d LEs automati cal ly to c rea te larger CAMs.

CAM supports writing “don’t care” bits into words of the memory. The

“don’t-care” bit can be used as a mask for CAM comparisons; any bit set

to “don’t-care” has no effect on matches.

The output of the CAM can be encoded or unencoded. When encoded, the

ESB ou tputs a n encode d addres s of the data’s loca tion. F or instan ce, if t he

data is loc ated in addre ss 12, the ESB output is 12. When unen coded, the

ESB uses its 16 outputs to show the location of the data over two clock

cyc les. In this case, if the data is locat ed in address 12, the 12 th output line

goe s high . When using unenco ded output s, two clock cycle s are requir ed

to read the output because a 16-bit output bus is used to show the status

of 32 words.

The enc oded output is bet ter suited for designs that ens ure duplicate d ata

is not written int o the CAM. If d uplicate da ta is writte n into two locatio ns,

the CAM’s output will be incorrect. If the CAM may contain duplicate

data, the unencoded output is a better solution; CAM with unencoded

outputs can distinguish multiple data locations.

CAM can be pre-loaded with data during configuration, or it can be

written during system operation. In most cases, two clock cycles are

required to write each word into CAM. When “don’t-care” bits are used,

a third clock cycle is required.

wraddress[]

data[]

wren

inclock

inclocken

inaclr

data_address[]

match

outclock

outclocken

outaclr

36 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

fFor more information on APEX 20KE devices and CAM, see Application

Note 119 (Implementing High-Speed Search Applications with APEX CAM).

Drivi ng Si gnals to the ESB

ESBs provide flexib le option s for d riving cont r ol sig nals. D iffere nt c lock s

can be used for the ESB inputs and outputs. Registers can be inserted

independently on the data input, data output, read address, write

address, WE, a nd RE s ign als . The g lobal sig nals an d the l oca l inte r con nect

can driv e the WE and RE signa ls. The glo bal sig na ls, d edicated cloc k pin s,

and local interconnect can drive the ESB clock signals. Because the LEs

drive th e local intercon nect, the LEs can co ntrol the WE and RE signals an d

the ESB clock, clock enable, and asynchronous clear signals. Figure 24

shows the ESB control signal generation logic.

Figu r e 24 . ESB Co nt rol Sign al Ge ne r at i on

Note:

(1) APEX 20KE devices have four dedicated clocks.

An ESB is fed by the local interconnect, which is driven by adjacent LEs

(for high-sp eed conn ection to the ESB) or the MegaLAB intercon nect. The

ESB can drive the local, MegaLAB, or FastTrack Interconnect routing

structure to drive LEs and IOEs in the same MegaLAB structure or

anywhere in the device.

RDEN WREN INCLOCK

INCLKENA

OUTCLOCK

OUTCLKENA

Dedicated

Clocks

Global

Signals

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

2 or 4

Local

Interconnect

Local

Interconnect INCLR OUTCLR

(1)

Altera Corporation 37

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Imple menting Lo gic in ROM

In addition to implementing logic with product terms, the ESB can

implement logic functions when it is programmed with a read-only

patt er n duri ng configuration, creating a larg e LUT. Wi th LUTs ,

combinat orial functions a re implemented by looking up th e results, rat her

than by compu ting the m. This impl ementa tion of combinator ial fun ctions

can be faster than using algorithms implemented in general logic, a

performance advantage that is further enhanced by the fast access times of

ESBs. The large capa city of ESBs enables desig ners to imple ment compl ex

functions in one logic level without the routing delays associated with

linked LEs o r di stri buted RAM blo cks. Parame terized funct ions such as

LPM functions ca n take advantage of the ESB automatically. Further, the

Quartus II software can implement portions of a design with ESBs where

appropriate.

Programmable Speed/Power Control

APEX 20K ESBs offer a high-speed mode that supports very fast operation

on an ESB-by-ESB basis. When high speed is not required, this feature can

be turned off to reduce the ESB’s power dissipation by up to 50%. ESBs

that run at low power incur a nominal timing delay adder. This

Turbo BitTM option is available for ESBs that implement product-term

logic or memor y function s. An ESB t hat is not used wi ll be p owered d own

so that it does not consume DC current.

Designers can program each ESB in the APEX 20K device for either

high-s peed or low-pow er operation . As a result, s peed-criti cal paths in t he

design can run at high speed, while the remaining paths operate at

reduced power.

I/O Structure The APEX 20K IOE contains a bidirectiona l I/O buffer and a regis ter that

can be used either as an input register for external data requiring fast setup

times, or as an output register for data requiring fast clock-to-output

performance. IOEs can be used as input, output, or bidirectional pins. For

fast bidirect ional I/O timin g, LE re gisters using l ocal r outing c an impr ove

setup times and OE timing. The Quartus II software Compiler uses the

programmable inversion option to invert signals from the row and column

interconnect automatically where appropriate. Because the APEX 20K IOE

offers one output enable per pin, the Quartus II software Compiler can

emulate ope n-drain ope ration efficiently .

The APEX 20K IOE includes programmable delays that can be activated to

ensure zero hold times, minimum clock-to-output times, input IOE

regis ter-t o-core regist er tra nsfe rs, or c ore-t o-output I OE reg ister trans fers.

A path in which a pin directly drives a register may require the delay to

ensure zero hol d time, wherea s a path in which a pin d riv es a regi ster

through combinatorial logic may not require the delay.

38 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Table 10 describes the APEX 20K programmable delays and their logic

options in the Quartus II software.

The Quartus II software Compiler can program these delays

automatically to minimize setup time while providing a zero hold time.

Figure 25 shows how fast bidirectional I/Os are implemented in

APEX 20K devices.

The register in the APEX 20K IOE can be programmed to power-up high

or low after configuration is complete. If it is programmed to power-up

low, an asynchronous clear can control the register. If it is programmed to

power-up high, the register cannot be asynchronously cleared or preset.

This feature is useful for cases where the APEX 20K device controls an

active-low input or another device; it prevents inadvertent activation of

the input upon power-up.

Table 10. APE X 20K Progra mmable Delay Ch ains

Programmable Delays Quar tus II Logic Optio n

Inp ut pin to core delay Decrease inpu t del ay to int ernal cells

Inp ut pin to inpu t reg ister delay Decreas e input delay to input register

Cor e to ou tpu t reg ister delay Decreas e input delay to out put regis t er

Output register tCO delay Increas e delay to output pin

Altera Corporation 39

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Figure 25. APEX 20K Bidirectiona l I /O Regi st ers Note (1)

Note:

(1) The output enable and input registers are LE registers in the LAB adjacent to th e bidirectional pin.

VCC

OE[7..0]

CLK[1..0]

ENA[5..0]

CLRn[1..0]

Peripheral Control

Bus

CLRN

ENA

VCC

2 Dedicated

Clock Inputs

Chip-Wide

Output Enable

CLK[3..2]

VCC

Chip-Wide

Reset

Input Pin to

Core Delay

Slew-Rate

Control

VCCIO

Optional

PCI Clamp

Output Register

t Delay

Core to Output

Input Pin to Input

CLRN

ENA

VCC

Chip-Wide

Reset

Input Register

Output Register

CLRN

ENA

Chip-Wide Reset

VCC

OE Register

VCC

4 Dedicated

Inputs

Row, Column,

or Local Interconnect

Open-Drain

Output

40 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

APEX 20KE devices include an enhanced IOE, which drives the FastRow

interconnect. The FastRow interconnect connects a column I/O pin

directly to the LAB local interconnect within two MegaLAB structures.

This feature provides fast setup times for pins that drive high fan-outs

with c omplex logic, such as PCI des igns. For fast bidirect ional I/O timi ng,

LE registers using local routing can improve setup times and OE timing.

The APEX 20KE IOE also includes direct support for open-drain

operation, giving faster clock-to-output for open-drain signals. Some

programmable delays in the APEX 20KE IOE offer multiple levels of delay

to fine-tune setup and hold time requirements. The Quartus II software

Compile r can set the se delays aut omaticall y to minimiz e setup time while

providing a zero hold time.

Table 11 describes the APEX 20KE programmable delays and their logic

options in the Quartus II software.

The register in the APEX 20KE IOE can be programmed to power-up high

or low after configuration is complete. If it is programmed to power-up

low, an asynchronous clear can control the register. If it is programmed to

power-up high, an asynchronous preset can control the register. Figure 26

shows how fast bidirectional I/O pins are implemented in APEX 20KE

devices. This feature is useful for cases where the APEX 20KE device

controls an active-low input or another device; it prevents inadvertent

activation of the input upon power-up.

Table 11. APEX 20KE Programmable Delay Chains

Programmable Delays Quartus II Logic Option

Inp ut Pin to Core D elay Decreas e input delay to inte rnal c ells

Inp ut Pin to Input Re gis ter Dela y Decreas e input delay to input regis te rs

Cor e to Ou tpu t Regis t er D elay Decreas e input delay to outp ut regis te r

Output Register tCO Del ay Increase delay to ou tpu t pin

Clock Enable Delay Increase clock enable delay

Altera Corporation 41

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Figure 26. APEX 20KE Bidirectional I/O Registers Notes (1 ), (2)

Notes:

(1) This programmable delay has four settings: off and three levels of delay.

(2) The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin.

VCC

OE[7..0]

CLK[1..0]

ENA[5..0]

CLRn[1..0]

Peripheral Control

Bus

CLRN/

PRN

ENA

VCC

4 Dedicated

Clock Inputs

Chip-Wide

Output Enable

CLK[3..0]

VCC

Chip-Wide

Reset

Input Pin to

Core Delay

(1)

Slew-Rate

Control

Open-Drain

Output

VCCIO

Optional

PCI Clamp

Output Register

t Delay

Core to Output

Input Pin to Input

CLRN

ENA

VCC

Chip-Wide

Reset

Input Register

Output Register

CLRN

ENA

Chip-Wide Reset

VCC

OE Register

VCC

4 Dedicated

Inputs

Row, Column, FastRow,

or Local Interconnect

Clock Enable

Delay

)

Input Pin to

Core Delay

(1)

Input Pin to

Core Delay

(1)

42 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Each IOE drives a row, column, MegaLAB, or local interconnect when

used as an input or bidirectional pin. A row IOE can drive a local,

MegaLAB, row, and column interconnect; a column IOE can drive the

column inte rconn ec t. Figure 27 shows how a row IOE connects to the

interconnect.

Figure 27. Row IOE Connec t ion to the Interconnec t

Row Interconnect MegaLAB Interconnect

Any LE can drive a

pin through the row,

column, and MegaLAB

interconnect.

An LE can drive a pin through the

local interconnect for faster

clock-to-output times.

IOE

Each IOE can drive local,

MegaLAB, row, and column

interconnect. Each IOE data

and OE signal is driven by

the local interconnect.

LAB

Altera Corporation 43

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Figure 28 shows how a column IOE connects to th e interconnect.

Figure 28. Colu mn IOE Connec tion to the Interc on ne ct

Dedicated Fast I/O Pins

APEX 20KE devices inco rporate an enhan cement to s uppo rt bidir ectional

pins with high internal fanout such as PCI control signals. These pins are

calle d Dedicated Fa st I/O pins (FAST1, FAST2, FAST3, and FAST4) and

replace dedicated inputs. These pins can be used for fast clock, clear, or

high fanout logic signal distribution. They also can drive out. The

Dedicated Fast I/O pin data output and tri-state control are driven by

local interconnect from the adjacent MegaLAB for high speed.

Row Interconnect

Column Interconnec

Each IOE can drive column interconnect. In APEX 20KE devices,

IOEs can also drive FastRow interconnect. Each IOE data

and OE signal is driven by local interconnect.

Any LE or ESB can drive

a column pin through a

row, column, and MegaLAB

interconnect.

IOE IOE

LAB

An LE or ESB can drive a

pin through a local

interconnect for faster

clock-to-output times.

MegaLAB Interconnect

44 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Advanced I/O Standard Support

APEX 20KE IOEs support the following I/O standards: LVTTL,

LVCMOS, 1.8-V I/O, 2.5-V I/O, 3.3-V PCI, PCI-X, 3.3-V AGP, LVDS,

LVPECL, GTL+, CTT, HS TL Class I, S ST L-3 Class I and II, a nd SS TL-2

Class I and II.

fFor more informat i o n on I/O standards sup ported by AP EX 20KE

device s, se e Application Note 117 (Using Selectable I/O Standards in Altera

Devices).

The APEX 20KE device contains eight I/O banks. In QFP packages, the

banks ar e link ed to fo rm four I /O bank s. T he I/O b an ks dire ct ly s uppor t

all standards except LVDS and LVPECL. All I/O banks can support LVDS

and LVPECL with the addition of external resistors. In addition, one block

within a bank contains circuitry to support high-speed True-LVDS and

LVPECL inpu ts, and anothe r bl o ck within a parti cular bank supports

high-speed True-LVDS and LV PECL outputs. The LV DS bl o ck s support

all of the I /O sta ndards. E ac h I/O b ank ha s its own VCCIO pins. A s i ng le

device can support 1.8-V, 2.5-V, and 3.3-V interfaces; each bank can

support a different standard independently. Each bank can also use a

separate VREF level so that each bank can support any of the terminated

sta ndard s (suc h as SSTL -3) indep en dent ly. Within a bank, any one of the

terminated sta ndards can be suppo rted. EP20K3 00 E and larger

APEX 20KE devices su pport the LVDS interface for data pins (smal l er

devices support LVDS clock pins, but not data pins). All EP20K300E and

lar ger devices supp ort the LV DS interf ace for d ata pins up t o 155 Mbit pe r

channel; EP20K400E devices an d larger with an X-suffix on the ordering

code add a serializer/deserializer circuit and PLL for higher-speed

support.

Each bank can support multiple standards with the same VCCIO for

outpu t pins. Each bank can support on e voltage-r eferenced I/O st andar d,

but it can suppor t multip le I/O stand ards wit h the same VCCIO voltage

level. Fo r exampl e, when VCCIO is 3.3 V, a bank can support LVTTL,

LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.

When the LVDS banks are not use d as L VDS I /O ba nk s, the y su ppor t all

of the other I/O standards. Figure 29 shows the arrangement of the

APEX 20KE I/O banks.

Altera Corporation 45

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Figure 29. APEX 20KE I/O Banks

Notes:

(1) For more information on placing I/O pins in LVDS blocks, refer to the “Guidelines

for Using LVDS Blocks” section in Application Note 120 (Using LVDS in APEX 20KE

Devices).

(2) If the LVDS input and output blocks are not used for LVDS, they can support all of

the I/O st an d ard s an d can be use d as inpu t, ou tpu t , or bidi r ect ional pins wi th

VCCIO set to 3.3 V, 2.5 V, or 1.8 V.

Power Sequencing & Hot Socketin g

Because APEX 20K and APE X 20KE devices can be used in a mixed-

volta ge environ ment, t hey have been design ed specifica lly t o tolera te any

possible power-up sequence. Therefore, the VCCIO and VCCINT power

supplies may be powered in any order.

Signals can be driven into APEX 2 0K devices before and during power-up

without damaging the device. In addition, APEX 20K devices do not drive

out during power-up. Once operating conditions are reached and the

device is configured, APEX 20K and APEX 20KE de v ices operate as

spec ifi ed by th e user.

Under hot socketing cond itio ns, APE X 20 KE de vices will not sustai n any

dam age, but the I/O pins will drive out.

LVDS/LVPEC

Input

Block (2)

(1)

LVDS/LVPECL

Output

Block (2)

(1)

Regular I/O Blocks Support

■

LVTTL

■

LVCMOS

■

2.5 V

■

1.8 V

■

3.3 V PCI

■

LVPECL

■

HSTL Class I

■

GTL+

■

SSTL-2 Class I and II

■

SSTL-3 Class I and II

■

CTT

■

AGP

Individual

Power Bus

I/O Bank 8

I/O Bank 1 I/O Bank 2

I/O Bank 3

I/O Bank 4

I/O Bank 5I/O Bank 6

I/O Bank 7

46 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

MultiVolt I/O

Interface

The APEX device architecture supports the MultiVolt I/O interface

feature, which allows APEX devices in all packages to interface with

systems of d ifferent supply voltages. The de vices have one s et of VCC pins

for internal operation and i nput buffers (VCCINT), and another set for I/O

output driv ers ( VCCIO).

The A PE X 20K VCCINT pins must always be connected to a 2.5 V power

supply . With a 2.5- V VCCINT level, input pi ns are 2.5-V and 3.3-V to lerant.

Certain devices, identi fied by a “V” suffix following the speed grade in the

ordering code (e.g., EP20K400BC652-1V), are 5.0-V tolerant. The VCCIO

pins c an b e connected to either a 2.5-V or 3 .3-V p o we r s upply, depending

on the output requirements. When VCCIO pins are connected to a 2.5-V

power su pply, the outpu t levels are compa tible with 2.5-V s ystems . When

the VCCIO pins are conn ected to a 3.3 -V power sup ply, the output high is

3.3 V and is compatible with 3.3-V or 5.0-V systems.

Table 12 summarizes 5.0-V tolerant APEX 20K MultiVolt I/O support.

Notes:

(1) The PCI clamping diod e m ust be disabled to drive an input wit h vol t age s hi gher

than VCCIO.

(2) APE X 20K devic e s with a “V” suffix are 5.0-V to l era n t .

(3) W hen VCCIO = 3.3 V , an A PEX 20K dev ice can drive a 2. 5-V devi c e with 3. 3-V

to lerant inpu t s.

Open-drain output pins on 5.0-V tolerant APEX 20K devices (with a pull-

up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that

require a VIH of 3.5 V. Whe n the pin is inact ive, the trace will be pulled up

to 5.0 V by the resisto r. The open-dra in pin will only drive low or tri-stat e;

it will never driv e hig h. The rise time is dep endent on the va lue of the pu ll-

up resistor and load impedance. The IOL current specification should be

considered when selecting a pull-up resistor.

Table 12 . 5.0-V Tolerant APEX 20K Mult iVolt I/O Sup po r t

VCCIO (V ) Input Signal s (V) Output Si gnals (V)

2.5 3.3 5.0 2.5 3.3 5.0

2.5 vv(1) v(1), (2) v

3.3 vvv(1), (2) v(3) vv

Altera Corporation 47

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

APEX 20KE devic es also suppo rt the MultiVolt I/O interface feature. The

APEX 2 0 KE VCCINT pins must always be connected to a 1.8-V power

supply. With a 1. 8-V VCCINT level, input pins are 1.8-V, 2.5- V, and 3.3-V

tole rant. The VCCIO pins can be connected to eithe r a 1.8 -V, 2.5-V , or 3.3- V

power supply, depending on the I/O standard requirements. When the

VCCIO pins are connected to a 1.8-V power supply, the output levels are

compatible with 1.8-V systems. When VCCIO pins are connected to a 2.5-V

powe r supply, the output leve ls are c ompatible w ith 2.5-V sy stems. Wh en

VCCIO pins are connected to a 3.3-V power supply, the output high is

3.3 V and com p atible with 3.3-V or 5.0-V syste ms . An APE X 20 KE de vice

is 5.0-V tolerant with the addition of a resistor.

Table 13 summarizes APEX 20KE MultiVolt I/O support.

Notes:

(1) T h e P C I c lampin g d iode mu s t be dis abled t o drive an in put with v o ltages h ig h er than VCCIO, except for the 5.0-V

inp ut c a se.

(2) An APEX 20KE device can be made 5.0-V tolerant with the addition of an external resistor. You also need a PCI

clamp and series resistor.

(3) When VCCIO = 3.3 V, an AP E X 20K E d evice can dri v e a 2. 5-V de vice with 3.3-V toler an t inpu t s.

ClockLock &

ClockBoost

Features

APEX 20K devices support the ClockLock and ClockBoost clock

mana gement feat ures, whi ch are imple ment ed with PLLs. Th e ClockLock

circuitry uses a synchronizing PLL that reduces the clock delay and skew

within a device. This reduction minimizes clock-to-output and setup

times while maintain ing zero hold time s. The ClockBoost circu itry, which

provides a clock multiplier, allows the designer to enhance device area

efficiency by sharing resources within the device. The ClockBoost

circuit ry allows the des igner to distribute a low-sp eed cloc k and multiply

that clock on-device. APEX 2 0K devices include a high-speed clock tree;

unlike ASICs, the user does not have to design and optimize the clock tree.

The ClockLock and ClockBoost features work in conjunction with the

APEX 20K device’s high-speed clock to provide significant improvements

in system performance and band-width. Devices with an X-suffix on the

ordering code include the ClockLock circuit.

The ClockLock and ClockBoost features in APEX 20K devices are enabled

thr oug h the Quar tus II sof t war e . Exte r na l devices are not req uir ed to use

these features.

Table 13. APEX 20KE MultiVolt I/O Support

VCCIO (V ) Inp ut Signals (V) Out put Si gnals (V)

1.8 2.5 3.3 5.0 1.8 2.5 3.3 5.0

1.8 vv (1) v(1) v

2.5 vv(1) v

3.3 vvv (2) v (2) vv

48 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

For designs that require both a multiplied and non-multip lied clock, the

clock tr ace on the bo ard can b e connected to CLK2p. Table 14 shows the

combi nations supported by the Cl ock Lock a nd Cloc kBoos t circu i try . The

CLK2p pin can feed both the ClockLock and ClockBoost circuitry in the

APEX 20K device. However, when both circuits are used, the other clock

pin (CLK1p) cannot be used.

APEX 20KE ClockLock Feature

APEX 20KE devices include an enhanced ClockLock feature set. These

devices include up to four PLLs, which can be used independently. Two

PLLs are designed for either general-purpose use or LVDS use (on devices

that support LVDS I/O pins). The remaining two PLLs are designed for

general-purpose use. The EP20K200E and smaller devices have two PLLs;

the EP20K300E and larger device s have four PLLs.

The following sections describe some of the features offered by the

APEX 20KE PLLs.

External PLL Feedba ck

The ClockLock circuit’s output can be driven off-chip to clock other

device s in the syst em; furth er, the feed back loop of the PL L can be rout ed

off-chip . This feature allows the designer to exercis e fine cont rol over the

I/O i nterfac e between the APE X 20KE dev ice and an other high-sp eed

device, such as SDRAM.

Clock Multiplication

Th e APEX 20KE ClockBoost circui t can m ultiply or divi de clo cks b y a

programmable number. The clock can be multiplied by m/(n × k) or

m/(n × v), where m and k range fr om 2 to 16 0, an d n and v range from 1 t o

16. Clock multiplication and division can be used for time-domain

multiplexi ng and other fu nctions, which can reduce des i gn LE

requirements.

Table 14. Multiplication Factor Combi nations

Clock 1 Clock 2

×1×1

×1, ×2×2

×1, ×2, ×4×4

Altera Corporation 49

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Clock Phase & Delay Adju stm en t

The APEX 20KE ClockShift feat ure allows the clock phase and delay to be

adjusted. The clock phase can be adjusted by 90° steps. The clock delay

can be adjusted to increase or decrease the clock delay by an arbitrary

amount, up to one clock period.

LVDS Support

Two PLLs are designed to support the LVDS interface. When using LVDS,

the I /O clock run s a t a slow er r a te tha n the data tra nsf e r r ate . T hu s, PL Ls

are used to multiply the I/O clock internally to capture the LVDS data. For

example, an I/O clock may run at 105 MHz to support 840 megabits per

second (Mbps) LVDS data transfer. In this example, the PLL multiplies the

incom in g clock by eight to su ppor t the hig h- sp ee d data tr ans f er. Y ou can

use PLLs in EP20K4 00 E and larger devices for high-speed LVDS

interfacing.

Lock Signals

The APEX 20KE ClockLock circuitry supports individual LOCK signals.

The LOCK signal drives high when the ClockLock circuit has locked onto

the inp ut c lock . Th e LOCK signals are opt iona l for ea ch ClockLock circu it;

whe n not used, the y are I/O pins .

ClockL ock & C lock Boost Timing Pa rameters

For the ClockLock and ClockBoost circuitry to function properly, the

incoming clock must meet certain requirements. If these specifications are

not met, the circuitry may not lock onto the incoming clock, which

generates an erroneous clock within the device. The clock generated by

the ClockLock and ClockBoost circuitry must also meet certain

specifications. If the incoming clock meets these requirements during

config urat ion, the APEX 20K Clock Lock and Clock Boost cir cui tr y will

lock ont o th e clock d urin g config ura tion . T he circuit will be r e ady for us e

immediately after configuration. In APEX 20KE devices, the clock input

standard is programmable, so the PLL cannot respond to the clock until

the device is configured. The PLL locks onto the input clock as soon as

config urat ion is comple te . Figure 30 shows the incoming and generated

clock specifications.

1For more information on ClockLock and ClockBoost circuitry,

see Appl icatio n Note 11 5: Using t h e Cl oc kLock and C l ockB oos t PLL

Features in APEX Devices.

50 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Figure 30. Specifications for the Incoming & Generated Clocks

The t I parameter refer s to the nominal input clock period; the tO paramet er refe rs to the

nomina l output clock per iod.

Table 15 summarizes the APEX 20K ClockLock and ClockBoost

parameters for -1 speed-grade devices.

Tabl e 1 5. APE X 20K Cl ockLock & ClockB oo st Parameters f or -1 Speed- G rade

Devices (Part 1 of 2)

Symbol Parameter Min Max Unit

fOUT Output frequency 25 180 MHz

fCLK1 (1) Input clo ck fre quency (Cloc kB oos t

clock multiplication factor equals 1) 25 180

(1) MHz

fCLK2 Input clock fre quency (Cloc kB oos t

clock multiplication factor equals 2) 16 90 MHz

fCLK4 Input clock fre quency (Cloc kB oos t

clock multiplication factor equals 4) 10 48 MHz

tOUTDUTY Duty cycle for

ClockLock/ClockBoost-generated

clock

40 60 %

fCLKDEV I nput dev iat ion f rom use r

specification in the Quartus II

soft wa r e (Cl o ckB o os t cl oc k

multiplic at ion f ac to r equals 1) (2)

25,000

(3) PPM

tRInput rise time 5 ns

tFInput fal l time 5 ns

Input

Clock

ClockLock

Generated

Clock

CLK1

CLK2

CLK4

INDUTY

I+

CLKDEV

INCLKSTB

JITTER

OUTDUTY

Altera Corporation 51

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Notes:

(1) The PLL input frequency range for the EP20K100-1X device for 1x multiplication is

25 MHz to 175 M Hz.

(2) All input clock specifications must be met. The PLL may not lock onto an incoming

clock if the clock specifications are not met, cr eating an erro neous clock within the

device.

(3) During dev ice conf igurati on, the Clo ckLock and Clo ckBoost circui try is conf igured

fir s t . If the in c o ming clo c k is supp lied d ur ing c o n f iguratio n , t h e C lockL o c k an d

Clo c kBoo s t c ir c uitr y locks d ur ing c onfig u ratio n , becau se t he lock time is les s t han

the configuration time.

(4) The jitter specific ation is measu red under lo n g-ter m obse rv ation .

(5) If the input clock stability is 100 ps, tJITTER is 250 ps.

tLOCK Time required for

ClockLock/ClockBoost to acquire

lock(4)

10 µs

tSKEW Sk ew delay bet w een related

ClockLock/ClockBoost-generated

clocks

500 ps

tJITTER Jitter on Cloc k Loc k /Cloc k Boost-

generat ed c loc k (5) 200 ps

tINCLKSTB Input clo ck stability (measured

between adjacent clocks) 50 ps

Tabl e 1 5. APE X 20K Cl ockLock & ClockB oo st Parameters f or -1 Speed- G rade

Devices (Part 2 of 2)

Symbol Parameter Min Max Unit

52 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Table 16 summari z es the APEX 20K Cl ock Lo ck and Clock Bo o st

parameters for -2 speed grade devices.

Notes:

(1) To implement the ClockLock and ClockBoost circuitry with the Quartus II

software, designers must specify the input frequency . The Quar tus II software

tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. The

fCLKDEV parameter specifies how much the incoming clock can differ from the

spec ifi ed fr eq uenc y dur in g d evice op er at ion. Sim ulati on does not reflec t t hi s

parameter.

(2) Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock

period.

(3) During device config uration , the Cl ockLo ck and Cl ockBoost circ uitry i s conf igured

before the rest of the device. If the incoming clock is supplied during configuration,

the ClockLock and ClockBoost circuitry locks during configuration because the

tLOCK value is less than the time required for configuration.

(4) The tJITTER spec ific at ion is me a sured under lo n g-ter m obs er v ation.

Tabl e 1 6. APE X 20K Clo ckL ock & Cloc kBoost P ar a me te r s f o r - 2 S pee d Grade

Devices

Symbol Parameter Min Max Unit

fOUT Output frequency 25 170 MHz

fCLK1 Input clock frequency (ClockBoost

clock multiplication factor equals 1) 25 170 MHz

fCLK2 Input clock frequency (ClockBoost

clock multiplication factor equals 2) 16 80 MHz

fCLK4 Input clock frequency (ClockBoost

clock multiplication factor equals 4) 10 34 MHz

tOUTDUTY Duty cycle for ClockLock/ClockBoost-

generated clock 40 60 %

fCLKDEV Input deviation from user specification

in the Quartus II software (ClockBoost

clock multiplication factor equals one)

(1)

25,000

(2) PPM

tRInput rise time 5ns

tFInput fall time 5ns

tLOCK Time required for ClockLock/

ClockBoost to acquire lock

(3)

10 µs

tSKEW Skew delay between related

ClockLock/ ClockBoost-generated

clock

500 500 ps

tJITTER Jitter on ClockLock/ ClockBoost-

generated clock (4) 200 ps

tINCLKSTB Input clock stability (measured between

adjacent clocks) 50 ps

Altera Corporation 53

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Tables 17 and 18 summarize the ClockLock and ClockBoost parameters

for APEX 20KE device s.

Table 17. APEX 20KE ClockLock & ClockBoost Parameters Note (1)

Symbol Parameter Condition Min Typ Max Unit

tRInput rise time 5ns

tFInput fall time 5ns

tINDUTY Input duty cycle 40 60 %

tINJITTER Input jitter peak-to-peak 2% of input

period peak-to-

peak

tOUTJITTER Jitter on ClockLock or ClockBoost-

generated clock 0.35% of

output period RMS

tOUTDUTY Duty cycle for ClockLock or

ClockBoost-generated clock 45 55 %

tLOCK (2),

(3) Time required for ClockLock or

ClockBoost to acquire lock 40 µs

54 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Notes to table s:

(1) All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications

are not met, creating an erroneous clock within the device.

(2) Th e maxim um lock time is 40 µs or 2000 in pu t cl ock cycles, wh ich ever occur s first .

(3) Before configuration, the PLL circuits are disable and powered down. During configuration, the PLLs are still

disabled. The PLLs begin to lock once the device is in the user mode. If the clock enable feature is used, lock begins

once th e CLKLK_ENA pin goes high in user mode.

(4) Th e P L L VCO opera tin g r an ge is 200 MHz ð fVCO ð 840 MH z for L VDS mode .

Table 18. APEX 20KE Clock Input & Output Parameters Note (1)

Symbol Parameter I/O Standard -1X Speed Grade -2X Speed Grade Units

Min Max Min Max

fVCO (4) Voltage controlled oscillator

operating range 200 500 200 500 MHz

fCLOCK0 Clock0 PLL output frequency

for internal use 1.5 335 1.5 200 MHz

fCLOCK1 Clock1 PLL output frequency

for internal use 20 335 20 200 MHz

fCLOCK0_EXT Output clock frequency for

external clock0 output 3.3-V LVTTL 1.5 245 1.5 226 MHz

2.5-V LVTTL 1.5 234 1.5 221 MHz

1.8-V LVTTL 1.5 223 1.5 216 MHz

GTL+ 1.5 205 1.5 193 MHz

SSTL-2 Class I 1.5 158 1.5 157 MHz

SSTL-2 Class II 1.5 142 1.5 142 MH z

SSTL-3 Class I 1.5 166 1.5 162 MHz

SSTL-3 Class II 1.5 149 1.5 146 MH z

LVDS 1.5 420 1.5 350 MHz

fCLOCK1_EXT Output clock frequency for

external clock1 output 3.3-V LVTTL 20 245 20 226 MHz

2.5-V LVTTL 20 234 20 221 MHz

1.8-V LVTTL 20 223 20 216 MHz

GTL+ 20 205 20 193 MHz

SSTL-2 Class I 20 158 20 157 MHz

SSTL-2 Class II 20 142 20 142 MHz

SSTL-3 Class I 20 166 20 162 MHz

SSTL-3 Class II 20 149 20 146 MHz

LVDS 20 420 20 350 MHz

fIN Input clock frequency 3.3-V LVTTL 1.5 290 1.5 257 MHz

2.5-V LVTTL 1.5 281 1.5 250 MHz

1.8-V LVTTL 1.5 272 1.5 243 MHz

GTL+ 1.5 303 1.5 261 MHz

SSTL-2 Class I 1.5 291 1.5 253 MHz

SSTL-2 Class II 1.5 291 1.5 253 MH z

SSTL-3 Class I 1.5 300 1.5 260 MHz

SSTL-3 Class II 1.5 300 1.5 260 MH z

LVDS 1.5 420 1.5 350 MHz

Altera Corporation 55

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

SignalTap

Embedded

Logic Analyzer

APE X 20K devices include device enhancem ents t o suppor t the SignalTap

embedded logic analyzer. By including this circuitry, the APEX 20K

device provide s the abil ity to monitor design ope ration over a period of

time through the IEEE Std. 1149.1 (JTAG) circuitry; a designer can analyze

internal logic at speed without bringing internal signals to the I/O pins.

This feature is particularly important for advanced packages such as

FineLine BGA packages because adding a connection to a pin during the

debugging process can be difficult after a board is designed and

manufactured.

IEEE Std.

1149.1 (JTAG)

Boundary-Scan

Support

All APEX 20K devices pr ovide JTAG BST circuit ry that complie s with the

IEEE Std. 1149.1-1990 speci f i cation. JTAG bo undary-scan te st i ng can be

perfor med before or after config urat ion, bu t not during config urat ion.

APEX 20K devices can also use the JTAG port for configuration with the

Quar tus II so ftwa re or wi th h ardware using e ither Jam F iles (.jam) or Jam

Byte-Code Files (.jbc). Fin all y, APEX 20K devices use the JTA G port to

monitor the logic operation of the device with the SignalTap embedded

logic analyzer. APEX 20K devices support the JTAG instructions shown in

Table 19. Alt ho ugh EP20K1500E d evices suppor t the JTAG BYPASS and

Sign alT ap inst r uct ions, they do not support bou nd ary - sca n te st ing or the

use of the JTAG port for configuration.

Note:

(1) Th e E P 20K 1500E device suppo r ts the JT AG BYPAS S in str uct i on and t h e Sig n alTap instru cti on s.

Table 19. APEX 20K JTAG Instructions

JTAG In stru ction Descrip tion

SAMP LE/ PR ELOAD Allows a snapshot of si gnals at the device pins to be captur ed and exami ned during

normal device operation, and permits an initial data pattern to be output at the device

pins. Also used by the SignalTap em bedded log ic an aly ze r.

EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a

test patte rn at the out put pins and capt uring test resu lts at the inp ut pins.

BYPASS

(1) Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST

data to pass s ynchronou sly th rough selected devices to adjac ent dev ic es during

normal device operation.

USERCODE Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,

allowing the USERCODE to be serially shifted out of TDO.

IDCO DE Selects the IDCODE registe r and plac es it be tween TDI and TDO, allowing the

IDCODE t o be se rially sh ifted out of TDO.

ICR Instructions Used when configuring an APEX 20K device via the JTAG port with a MasterBlasterTM

or ByteBlasterMVTM download cable, or when using a Jam File or Jam Byte-Code File

via an embedded proces s or.

SignalT ap I ns tru ctions

(1) Monitors internal device operation with the SignalTap embedded logic analyzer.

56 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

The A PEX 20K device ins truc tion regist er len gth is 1 0 bits. The APE X 20K

device USERCODE register length is 32 bits. Tables 20 and 21 show the

boundary-scan register length and device IDCODE i n for m ati o n for

APEX 20K devices.

Note:

(1) This device does not support JTAG boundary scan testing.

Table 20. APEX 20K Boundary-Scan Register Lengt h

Device Boundary-Scan Register Length

EP20K30E 420

EP20K60E 624

EP20K100 786

EP20K100E 774

EP20K160E 984

EP20K200 1,176

EP20K200E 1,164

EP20K300E 1,266

EP20K400 1,536

EP20K400E 1,506

EP20K600E 1,806

EP20K1000E 2,190

EP20K1500E 1 (1)

Altera Corporation 57

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Notes:

(1) The m os t si gn ific ant bit (MSB) is o n th e left .

(2) Th e ID CODE ’ s least sig n ifi c an t bit (L SB) is alwa ys 1.

Figure 31 shows the timing requirements for the JTAG signals.

Figure 31. APEX 2 0K JTAG Wavefo r ms

Table 21. 32-Bit APEX 20K Device IDCODE

Devic e IDCODE (32 Bits ) (1)

Version

(4 Bits) Part Number (16 Bits) Manufacturer

Identity (11 Bits) 1 (1 Bit)

(2)

EP20K30E 0000 1000 0000 0011 0000 000 0110 1110 1

EP20K60E 0000 1000 0000 0110 0000 000 0110 1110 1

EP20K100 0000 0000 0100 0001 0110 000 0110 1110 1

EP20K100E 0000 1000 0001 0000 0000 000 0110 1110 1

EP20K160E 0000 1000 0001 0110 0000 000 0110 1110 1

EP20K200 0000 0000 1000 0011 0010 000 0110 1110 1

EP20K200E 0000 1000 0010 0000 0000 000 0110 1110 1

EP20K300E 0000 1000 0011 0000 0000 000 0110 1110 1

EP20K400 0000 0001 0110 0110 0100 000 0110 1110 1

EP20K400E 0000 1000 0100 0000 0000 000 0110 1110 1

EP20K600E 0000 1000 0110 0000 0000 000 0110 1110 1

EP20K1000E 0000 1001 0000 0000 0000 000 0110 1110 1

TDO

TCK

tJPZX tJPCO

tJPH

tJPXZ

tJCP tJPSU

tJCL

tJCH

TDI

TMS

Signal

to Be

Captured

Signal

to Be

Driven

tJSZX

tJSSU tJSH

tJSCO tJSXZ

58 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Table 22 shows the JTAG timing parameters and values for APEX 20K

devices.

fFor more information, see the following documents:

■Appl ication Note 39 (IEEE Std . 1149.1 (JTAG) Bounda r y-Scan Testin g in

Altera Devices)

■Jam Pr og ramming & Test La nguage Specific ation

Generic Testing Each APEX 20K device is functionally tested. Complete testing of each

configurable static random access memory (SRAM) bit and all logic

functionality ensures 100% yield. AC test measurements for APEX 20K

devices are made under conditions equivalent to those shown in

Figure 32. Multiple test patterns can be used to configure devices during

all stages of the production flow.

Table 22 . APEX 20K JTAG Timing Par ame t ers & Values

Symbol Parameter Min Max Unit

tJCP TCK clock period 100 ns

tJCH TCK clock high time 50 ns

tJCL TCK clock low time 50 ns

tJPSU JTAG port setup time 20 ns

tJPH JTAG port hold time 45 ns

tJPCO JTAG port clock to output 25 ns

tJPZX JTAG port high impedance to valid output 25 ns

tJPXZ JTAG port valid output to high impedance 25 ns

tJSSU Capture r egister setup time 20 ns

tJSH Capture r egister hold time 45 ns

tJSCO Update register clock to output 35 ns

tJSZX Update register high imp edance to valid output 35 ns

tJSXZ Update register valid output to high impedance 35 ns

Altera Corporation 59

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Figure 32. APEX 20K AC Test Co nditions

Operating

Conditions

Tables 23 through 26 provid e i nformat ion on absol ute maximum r ating s,

recommended operating conditions, DC operating conditions, and

capacitance for 2.5-V APEX 20K devices.

System

C1 (includes

JIG capacitance)

Device input

rise and fall

times < 3 ns

Device

Output to Test

Power supply transients can affect AC

measurements. Simultaneous transitions of

multi ple outputs should be avoided for

accurate measurement. Threshold tests

must not be performed und er AC conditi ons.

Large-amplitude, fast-ground-current

transients normally occur as the device

outputs discharge the load capacitances.

When these transients flow through the

parasitic inductance between the device

groun d pin and the tes t system ground,

significant reductions in observable noise

immunity can result.

Table 23. APEX 20K Device Abs olute Maxi mu m Ratings Note (1)

Symbol Parameter Conditions Min Max Unit

VCCINT Supply voltage With respect to ground (2) –0.5 3.6 V

VCCIO –0.5 4.6 V

VIDC input voltage –0.5 4.6 V

IOUT DC output current, per pin –25 25 mA

TSTG Storage temperature No bias –65 150 ° C

TAMB Ambient temperature Under bias –65 135 ° C

TJJunction temperature PQFP, RQFP, TQFP, and BGA packa ges,

under bias 135 ° C

Ceramic PGA packages, under bias 150 ° C

60 Altera  Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Table 24. APEX 20K Device Recommended Operating Conditions 
Symbol Parameter Conditions Min Max Unit
VCCINT Supply voltage for internal logic and 
input buffers (3), (4) 2.375 
(2.375) 2.625 
(2.625) V
VCCIO Supply voltage for output buffers, 3.3-V 
operation (3), (4) 3.00 ( 3.00) 3.60 (3.60) V
Supply voltage for output buffers, 2.5- V 
operation (3), (4) 2.375 
(2.375) 2.625 
(2.625) V
VIInput v o lta g e (2), (5) –0.5 4.1 V
VOOutput voltage 0V
CCIO V
TJJunction temperature For commercial use 0 85 ° C
For industrial use –40 100 ° C
tRInput ris e  time (10% to 90%) 40 ns
tFInput fall time ( 90 % to 10 %) 40 ns
Table 25. APEX 20K Devi ce DC O perating Condi t ions  (Part  1 of 2) Notes (6), (7)
Symbol Parameter Conditions Min Typ Max Unit
VIH High-level LVTTL, LVCMOS, or 
3.3-V PCI input voltage 1.7, 0.5 ×VCCIO 
(8) 4.1 V
VIL Low-level LVTTL, LVCM OS, or 
3.3-V PCI input voltage –0.5 0.8, 0.3 ×VCCIO 
(8) V
VOH 3.3-V high-level LVTTL output 
voltage IOH = –12 mA DC, 
VCCIO =3.00 V (9) 2.4 V
3.3-V high-level LVCMOS output 
voltage IOH = –0.1 mA DC, 
VCCIO =3.00 V (9) VCCIO –0.2 V
3.3-V high-level PCI output voltage IOH = –0.5 mA DC, 
VCCIO = 3.00 to 3.60 V (9) 0.9 ×VCCIO V
2.5-V high-level output voltage IOH = –0.1 mA DC, 
VCCIO =2.30 V (9) 2.1 V
IOH = –1 mA DC, 
VCCIO =2.30 V (9) 2.0 V
IOH = –2 mA DC, 
VCCIO =2.30 V (9) 1.7 V

Altera  Corporation  61
APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet
VOL 3.3-V low-level LVTTL output 
voltage IOL = 12 mA DC, 
VCCIO =3.00 V (10) 0.4 V
3.3-V low-level LVCM OS  output 
voltage IOL = 0.1 mA DC, 
VCCIO =3.00 V (10) 0.2 V
3.3-V low-level PCI output voltage IOL = 1.5 mA DC, 
VCCIO = 3.00 to 3.60 V 
(10)
0.1 ×VCCIO V
2.5-V low-level output voltage IOL = 0.1 mA DC, 
VCCIO =2.30 V (10) 0.2 V
IOL = 1 mA DC, 
VCCIO =2.30 V (10) 0.4 V
IOL = 2 mA DC, 
VCCIO =2.30 V (10) 0.7 V
IIInput pin leakage current VI = 4.1 to –0.5 V (11) –10 10 µA
IOZ Tri-stated I/O pin leakage current VO = 4.1 to –0.5 V (11) –10 10 µA
ICC0 VCC supply current (standby) 
(All ESBs in power-dow n m ode) VI = ground, no load, no 
toggling inputs, -1 speed 
grade
10 mA
VI = ground, no load, no 
toggling inputs,
-2, -3 speed grades
5mA
RCONF Value  of I/O pin pull-up resistor 
before and during configuration VCCIO =3.0 V (12) 20 50 k¾
VCCIO = 2.37 5 V (12) 30 80 k¾
Table 26. APEX 20K Device Capacitance Note (13)
Symbol Parameter Conditions Min Max Unit
CIN Input capacitance VIN = 0 V, f = 1.0 MHz 8 pF
CINCLK Input capacitance on dedicated 
clock pin VIN = 0 V, f = 1.0 MHz 12 pF
COUT Output capacitance VOUT = 0 V, f = 1.0 MHz 8 pF
Table 25. APEX 20K Devi ce DC O perating Condi t ions  (Part  2 of 2) Notes (6), (7)
Symbol Parameter Conditions Min Typ Max Unit

62 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Notes to tables:

(1) See th e Operating Requirements for Altera Devices Data Sheet.

(2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 4.6 V for

input curren ts less th an 100 mA an d pe riods sh or ter than 20 ns.

(3) Numbers in parenthes es are for industri al-t e mperatur e-ra nge devices.

(4) Max i mum VCC rise time is 100 ms, and VCC must rise mo notonically.

(5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are

powered.

(6 ) T ypical values are fo r TA = 25° C, VCCINT = 2.5 V, and VCCIO = 2.5 V or 3.3 V.

(7) These values are specified under the APEX 20K device recommended operating conditions, shown in Table 24 on

page 60.

(8) Th e AP EX 2 0K i npu t b uff er s are comp a tib le wi th 2. 5- V and 3. 3-V (L VTT L an d LVCMO S) sig n als . A dd it io na lly , the

input buffers are 3.3-V PCI compliant when VCCIO and VCCINT meet the relationship shown in Figure 33 on page 68.

(9) The IOH parameter refers to high-level TTL, PCI, or CMOS output current.

(10) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. Thi s parameter applies to open-drain pins

as well as outpu t pins.

(11) This v alue is specifi ed for n ormal de v ice operation . Th e v alue ma y v ar y durin g p ower-up.

(12) Pin pull-u p resist an c e valu es will be lo we r if an external sourc e d rives the p in hi gher t h an V CCIO.

(13 ) Cap a c it an ce is samp le-te st e d only.

Tables 27 through 30 provide infor ma tion on abs olut e maximu m ratin gs,

recommended operating conditions, DC operating conditions, a nd

capacitance for 5.0-V tolerant APEX 20K devices. These devices are

identifie d by a “V” suffix following the spe ed gra de in the ordering code

(e.g., EP20K400 BC652-1V).

Table 27. APEX 20K 5 .0-V Tol erant Device Absolute M aximum Rati ngs No te (1)

Symbol Parameter Conditions Min Max Unit

VCCINT Supply voltage With respect to ground (2) –0.5 3.6 V

VCCIO –0.5 4.6 V

VIDC input voltage –2.0 5.75 V

IOUT DC output current, per pin –25 25 mA

TSTG Storage temperature No bias –65 150 ° C

TAMB Ambient temperature Under bias –65 135 ° C

TJJunction temperature PQFP , RQFP, TQF P, and BGA packages,

under bias 135 ° C

Ceramic PGA packages, under bias 150 ° C

Altera  Corporation  63
APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Table 28. APEX 20K 5.0-V Tolerant Device Recommended Operating Conditions
Symbol Parameter Conditions Min Max Unit
VCCINT Supply voltage for internal logic 
and input buffers (3), (4) 2.375 
(2.375) 2.625 
(2.625) V
VCCIO Supply voltage for output buffers, 
3.3-V operation (3), (4) 3.00 (3.00) 3.60 (3.60) V
Supply voltage for output buffers, 
2.5-V operation (3), (4) 2.375 
(2.375) 2.625 
(2.625) V
VIInput voltage (2), (5) –0.5 5.75 V
VOOutput voltage 0V
CCIO V
TJJunction temperature For commercial use 0 85 ° C
For industrial use 40 100 ° C
tRInput rise  time 40 ns
tFInput fall time 40 ns
Table 29. APEX 20K 5.0-V Tolerant Device DC Operating Conditions  (Part 1 of 2) Notes (6), (7)
Symbol Parameter Conditions Min Typ Max Unit
VIH High-level input voltage 1.7, 0.5 ×VCCIO 
(8) 5.75 V
VIL Low-level input voltage –0.5 0.8, 0.3 ×VCCIO 
(8) V
VOH 3.3-V high-level TTL output 
voltage IOH = –8 mA DC, 
VCCIO = 3.00 V (9) 2.4 V
3.3-V high-level CMOS output 
voltage IOH = –0.1 mA DC, 
VCCIO = 3.00 V (9) VCCIO –0.2 V
3.3-V high-level PCI output voltage IOH = –0.5 mA DC, 
VCCIO = 3.00 to 3.60 V (9) 0.9 ×VCCIO V
2.5-V high-level output vo ltage IOH = –0.1 mA DC, 
VCCIO = 2.30 V (9) 2.1 V
IOH = –1 mA DC, 
VCCIO = 2.30 V (9) 2.0 V
IOH = –2 mA DC, 
VCCIO = 2.30 V (9) 1.7 V

64 Altera  Corporation
APEX 20K Programmable Logic Device Family Data Sheet
VOL 3.3-V low-level TTL output voltage IOL = 12 mA DC, 
VCCIO =3.00 V (10) 0.45 V
3.3-V low-level CMOS output 
voltage IOL = 0.1 mA DC, 
VCCIO =3.00 V (10) 0.2 V
3.3-V low-level PCI output voltage IOL = 1.5 mA DC, 
VCCIO = 3.00 to 3.60 V 
(10)
0.1 ×VCCIO V
2.5-V low-level output voltage IOL = 0.1 mA DC, 
VCCIO =2.30 V (10) 0.2 V
IOL = 1 mA DC, 
VCCIO =2.30 V (10) 0.4 V
IOL = 2 mA DC, 
VCCIO =2.30 V (10) 0.7 V
IIInput pin leakage current VI = 5.75 to –0.5 V –10 10 µA
IOZ Tri-stated I/O pin leakage current VO = 5.75 to –0.5 V –10 10 µA
ICC0 VCC supply current (standby) 
(All ESBs in power-dow n m ode) VI = ground, no load, no 
toggling inputs, -1 speed 
grade (11)
10 mA
VI = ground, no load, no 
toggling inputs,
-2, -3 speed grades (11)
5mA
RCONF Value  of I/O pin pull-up resistor 
before and during configuration VCCIO =3.0 V (12) 20 50 k¾
VCCIO = 2.37 5 V (12) 30 80 k¾
Table 30. APEX 20K 5 .0-V Tol erant  Device Capacitance Note (13)
Symbol Parameter Conditions Min Max Unit
CIN Input capacitance VIN = 0 V, f = 1.0 MHz 8 pF
CINCLK Input capacitance on dedicated 
clock pin VIN = 0 V, f = 1.0 MHz 12 pF
COUT Output capacitance VOUT = 0 V, f = 1.0 MHz 8 pF
Table 29. APEX 20K 5 .0-V Tolera nt De vice DC Operating Condi t ions  (Part  2 of 2) Notes (6), (7)
Symbol Parameter Conditions Min Typ Max Unit

Altera Corporation 65

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Notes to table s:

(1) See the Opera t i ng Re qui reme nt s f or Al t era Devic es Data Sheet.

(2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.75 V for

input currents less than 100 mA and periods shorter than 20 ns.

(3) Numbers in parentheses are for industrial-temperature-range devices.

(4) Maximum VCC rise time is 100 ms, an d VCC m ust rise monotonically.

(5) All pins, including dedicated inputs, clock I/O, and JTAG pins, may be driven before VCCINT and VCCIO are

powered.

(6) Typical values are for TA= 25 ° C, VCCINT = 2.5 V, and VCCIO = 2.5 or 3.3 V.

(7) These values are specified in the APEX 20K device recommended operating conditions, shown in Table 26 on

page 62.

(8) The APEX 20K input buffers are compatible with 2.5-V and 3.3-V (LVTTL and LVCMOS) signals. Additionally, the

input buffers are 3.3-V PCI compliant when VCCIO and VCCINT me et the rela tion ship sh own in Fig ure 33 on pag e 68.

(9) Th e IOH parameter refers to high-level TTL, PCI or CMOS output current.

(10) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applie s to open-drain pins

as well as output pins.

(11) This value is specified for normal device operation. The value may vary during power-up.

(12) Pin pull -up re sistan ce values wil l be lower if an exter n al sour ce d rives t he pin h ighe r than VCCIO.

(13) Capacitance is sample-tested only.

Tables 31 through 34 provid e i nformat ion on absol ute maximum r ating s,

recommended operating conditions, DC operating conditions, and

capacitance for 1.8-V APEX 20KE devices.

Table 31. APEX 20KE Device Absolute Maximum Ratings Note (1)

Symbol Parameter Conditions Min Max Unit

VCCINT Supply voltage With respect to ground (2) –0.5 2.5 V

VCCIO –0.5 4.6 V

VIDC input voltage –0.5 4.6 V

IOUT DC output current, per pin –25 25 mA

TSTG Storage temperature No bias –65 150 ° C

TAMB Ambient temperature Under bias –65 135 ° C

TJJunction temperature PQFP, RQFP, TQFP, and BGA packa ges,

under bias 135 ° C

Ceramic PGA packages, under bias 150 ° C

66 Altera  Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Table 32. APEX 20KE D evice Re commen ded Operating Conditions 
Symbol Parameter Conditions Min Max Unit
VCCINT Supply voltage for internal logic and 
input buffers (3), (4) 1.71 (1.71) 1.89 (1.89) V
VCCIO Supply voltage for output buffers, 3.3-V 
operation (3), (4) 3.00 (3.00) 3.60 (3.60) V
Supply voltage for output buffers, 2.5-V 
operation (3), (4) 2.375 
(2.375) 2.625 
(2.625) V
Supply voltage for output buffers, 1.8-V 
operation (3), (4) 1.71 (1.71) 1.89 (1.89) V
VIInput voltage (5), (6) –0.5 4.1 V
VOOutput voltage 0V
CCIO V
TJJunction temperature For commercial use 0 85 ° C
For industrial use –40 100 ° C
tRInput rise time 40 ns
tFInput fall time 40 ns

Altera  Corporation  67
APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Table 33. APEX 20KE Devi ce DC Operat i ng Condi t ions  Notes (7), (8), (9)
Symbol Parameter Conditions Min Typ Max Unit
VIH High-level LVTTL, CMOS, or 3.3-V 
PC I input voltag e 1.7, 0.5 ×VCCIO 
(10) 4.1 V
VIL Low-level LVTTL, CMOS, or 3.3-V 
PC I input voltag e –0.5 0.8, 0.3 ×VCCIO 
(10) V
VOH 3.3-V high-level LVTTL output 
voltage IOH = –12 mA DC, 
VCCIO = 3.00 V (11) 2.4 V
3.3-V high-level LVCMOS output 
voltage IOH = –0.1 mA DC, 
VCCIO = 3.00 V (11) VCCIO –0.2 V
3.3-V high-level PCI output voltage IOH = –0.5 mA DC, 
VCCIO = 3.00 to 3.60 V 
(11) 
0.9 ×VCCIO V
2.5-V high-level output vo ltage IOH = –0.1 mA DC, 
VCCIO = 2.30 V (11) 2.1 V
IOH = –1 mA DC, 
VCCIO = 2.30 V (11) 2.0 V
IOH = –2 mA DC, 
VCCIO = 2.30 V (11) 1.7 V
VOL 3.3-V low-level LVTTL output 
voltage IOL = 12 mA DC, 
VCCIO = 3.00 V (12) 0.4 V
3.3-V low-level LVCMO S output 
voltage IOL = 0.1 mA DC, 
VCCIO = 3.00 V (12) 0.2 V
3.3-V low-level PCI output voltage IOL = 1.5 mA DC, 
VCCIO = 3.00 to 3.60 V 
(12)
0.1 ×VCCIO V
2.5-V low-level output voltage IOL = 0.1 mA DC, 
VCCIO = 2.30 V (12) 0.2 V
IOL = 1 mA DC, 
VCCIO = 2.30 V (12) 0.4 V
IOL = 2 mA DC, 
VCCIO = 2.30 V (12) 0.7 V
IIInput pin leakage current VI = 4.1 to –0.5 V (13) –10 10 µA
IOZ Tri-stated I/O pin leakage current VO = 4.1 to –0.5 V (13) –10 10 µA
ICC0 VCC supply current (standby) 
(All ESBs in power-down mode) VI = gr ound, no load, no 
toggling inputs, -1 speed 
grade
10 mA
VI = ground, no load, no 
toggling inputs,
-2, -3 speed grades
5mA
RCONF Value of I/O pin pull-up resistor 
before and dur ing  co nfig uration VCCIO = 3.0 V (14) 20 50 k¾
VCCIO = 2.375 V (14) 30 80 k¾
VCCIO = 1.71 V (14) 60 150 k¾

68 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

1For DC Operating Specifications on APEX 20KE I/O standards,

please refer to Application Note 117 (Using Selectable I/O Standards

in Altera Devices).

Notes to tables:

(1) See the Operating Requirements for Altera Devices Data Sheet.

(2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.75 V for

input curren ts less th an 100 mA an d pe riods sh or ter than 20 ns.

(3) Numbers in parenthes es are for industri al-t e mperatur e-ra nge devices.

(4) Max i mum VCC rise time is 100 ms, and VCC must rise mo notonically.

(5) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 4.6 V for

input curren ts less th an 100 mA an d pe riods sh or ter than 20 ns.

(6) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are

powered.

(7 ) T ypical values are fo r TA = 25° C, VCCINT = 1.8 V, and VCCIO = 1.8 V, 2.5 V or 3.3 V.

(8) These values are speci f ied u nder the APEX 20KE devic e re commended operati ng condi tions, show n in Table 28 on

page 63.

(9) Refer to A ppl ica tion No te 11 7 (U sin g Se l ec ta ble I/O S ta nd a rds in Alte r a De vi ce s) for th e V IH, VIL, V OH, V OL, an d II

parameters when VCCIO = 1.8 V.

(10) The APEX 20K E in pu t bu ffer s ar e c om patible wi th 1. 8-V , 2.5- V an d 3. 3-V (L VTTL and LVCMO S) sig n als.

Additionally, the input buffers are 3.3-V PCI compliant. Input buffers also meet specifications for GTL+, CTT, AGP,

SSTL- 2, SS T L-3, an d HST L .

(11) The I OH parameter refers to high-level TTL, PCI, or CMOS output current.

(12) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. Thi s parameter applies to open-drain pins

as well as outpu t pins.

(13) This v alue is specifi ed for n ormal de v ice operation . Th e v alue ma y v ar y durin g p ower-up.

(14) Pin pull-u p resist an c e valu es will be lo we r if an external sourc e d rives the p in hi gher t h an V CCIO.

(15 ) Cap a c it an ce is samp le-te st e d only.

Figure 33 shows the relationship between VCCIO and VCCINT for 3.3-V PCI

compl ian ce on AP EX 20K devices .

Table 34. APEX 20KE Device Capacitance Note (15)

Symbol Parameter Conditions Min Max Unit

CIN Input capacitance VIN = 0 V, f = 1.0 MHz 8 pF

CINCLK Input capacitance on dedicated

clock pin VIN = 0 V, f = 1.0 MHz 12 pF

COUT Output capacitance VOUT = 0 V, f = 1.0 MHz 8 pF

Altera Corporation 69

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Figure 33. Relationship between VCCIO & VCCINT for 3.3-V PCI Compliance

Figure 34 shows the typical output drive characteristics of APEX 20K

devices with 3.3-V and 2.5-V VCCIO. The out put driver is compatib le with

the 3.3-V PCI Local Bus Specification, Revision 2.2 (when VCCIO pin s are

con nec ted to 3.3 V). 5-V tolerant APEX 20K devices in the -1 spee d grad e

are 5-V PCI compliant over all operating conditions.

Figure 34. O utput Drive Charac t eristics of APEX 20K Device Note (1)

Note:

(1) These are transient (AC) currents.

3.0 3.1 3.3

VCCIO

3.6

2.3

2.5

2.7

VCCINT (V)

(V)

PCI-Compliant Region

VO Output Voltage (V)

IOL

IOH IOH

VCCINT = 2.5

VCCIO = 2.5

Room Temperature

VCCINT = 2.5

VCCIO = 3.3

Room Temperature

123

VO Output Voltage (V)

123

90 IOL

Typical I

Output

Current (mA)

Typical I

Output

Current (mA)

70 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Figure 35 shows the output drive characteristics of APEX 20KE devices.

Figure 35. Output Drive Characteristics of APEX 20KE Devices Note (1)

Note:

(1) The se ar e tr an sie nt (A C) curren ts.

Vo Output Voltage (V)

IOL

IOH

Vo Output Voltage (V)

IOL

IOH

0.5 1 1.5 22.5

Typical IO

Output

Current (mA)

0.5 1 1.5 22.5 3

Vo Output Voltage (V)

VCCINT = 1.8 V

VCCIO = 3.3 V

Room Temperature

IOH

IOL

Typical IO

Output

Current (mA)

100

110

120

0.5 1 1.5 2.0

VCCINT = 1.8 V

VCCIO = 2.5V

Room Temperature

VCCINT = 1.8V

VCCIO = 1.8V

Room Temperature

Typical IO

Output

Current (mA)

Altera Corporation 71

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

T i mi ng Model The high-performance FastTrack and MegaLAB interconnect routing

resour c es en sur e pred ic ta ble perf orm an ce, accur a te simulation, and

accurate timing anal ysis. This predictable performance contrasts with that

of FPGAs, which use a segmen ted connection sch eme and therefore have

unpredictable performance.

All specifications are always representative of worst-case supply voltage

and junction temperature conditions. All output-pin-timing specifications

are reported for maxi mum dri ver stre ng th.

Figure 36 shows the fMAX timing model for APEX 20K devices.

Figure 36. APEX 20K fMAX T imi ng Mode l

Figure 37 shows the fMAX timing model for APEX 20KE devi ces. These

parameters can be used to estimate fMAX for multiple levels of logic.

Quartus II software timing analysis should be used for more accurate

timing information.

LUT

ttt

tttt

ESBRC

ESBWC

ESBWESU

ESBDATASU

ESBADDRSU

ESBDATACO1

ESBDATACO2

ESBDD

PTERMSU

PTERMCO

F1—4

F5—20

F20+

ESB

Routing Delay

72 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Altera Corporation 73

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Figure 37. APEX 20KE fMAX Timing Model

LUT

–

F20+

Routing Delay

ESBARC

ESBSRC

ESBSWDSU

ESBDATASU

ESBWADDRSU

ESBRADDRSU

ESBDATACO1

ESBDATACO2

ESBDD

ESBWDH

ESBRASU

ESBRAH

ESBWESU

ESBWEH

PTERMSU

PTERMCO

ESB

ESBSRASU

ESBWDSU

ESBWASU

ESBSWC

ESBAWC

74 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Figures 38 and 39 show the asynchronous and synchronous timing

waveforms, respectively, for the ESB macroparameters in Table 35.

Figu re 38. ESB As ync hr o no us Timing W ave f or ms

ESB Asynchronous Write

ESB Asynchronous Read

d0 d3

ESBARC

a1 a2 a3

d2d1

Rdaddress

Data-Out

din1 dout2

ESBDD

a1 a2

din1

din0

ESBWCCOMB

ESBWASU

ESBWAH

ESBWDH

ESBWDSU

ESBWP

din0

Data-In

Wraddress

Data-Out

Altera Corporation 75

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Figure 39. ESB Synchronous Timing Waveforms

Figure 40 shows the ti ming m odel for b idirectional I/O pin timing .

CLK

ESB Synchronous Read

ESBDATASU

ESBARC

ESBDATACO2

a1 a2 a3

ESBDATAH

CLK

dout0 din1 din2 din3 din2

ESBWESU

ESBSWC

ESBWEH

ESBDATACO1

a1 a2 a3 a2

din3

din2

din1

ESBDATAH

ESBDATASU

ESB Synchronous Write (ESB Output Registers Used)

dout1

Rdaddress

Data-Out

Wraddress

Data-Out

Data-In

76 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Figure 40. Synchronous Bidirectional Pin External Timing

Notes:

(1) The output enable and input registers are LE registers in the LAB adjacent to a

bidirectional row pin. The output enable register is set with “Output Enable

Rou tin g = Si gnal-Pin” option in the Qu ar tus II softwar e.

(2) The LAB adjacent input registe r is set with “Decrease Input De lay to Internal Cells=

Off”. This maintains a zero hold time for lab adjacent registers while giving a fast,

position independent setup time. A faster setup time with zero hol d time is possible

by setting “Decrease Input Delay to Internal Cells= ON” and moving the input

oc c urs with the min imum s etup time, varies with d ev ic e den sit y an d speed g ra d e.

Table 35 describes the fMAX timing parameters shown in Figure 36.

PRN

CLRN

PRN

CLRN

(1)

IOE Register

Bidirectional Pin

Dedicated

Clock

PRN

CLRN

(1)

XZBIDIR

ZXBIDIR

OUTCOBIDIR

INSUBIDIR

INHBIDIR

OE Register

Output IOE Register

Input Register

(2)

Table 35 . APEX 20K f MAX Timing Parameters (Part 1 of 2)

Symbol Parameter

tSU LE regis t er se tu p time bef ore clock

tHLE regis t er hold time after clock

tCO LE regis t er cl oc k-to-output delay

tLUT LUT del ay for dat a-in

tESBRC ESB Asy nc hronous read c ycle t im e

tESBWC E SB Asynchronous write cycle time

tESBWESU E SB W E s etu p time bef ore clock wh en us ing input register

tESBDATASU E SB data setup time before clock w hen us ing input regis te r

tESBADDRSU E SB address setup t ime bef ore cl oc k when us ing input regis te rs

tESBDATACO1 E SB c loc k- to -out put delay w hen us ing output reg isters

tESBDATACO2 E SB c loc k- to -out put delay w itho ut outp ut regis ter s

Altera Corporation 77

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Tables 36 and 37 describe APEX 20K external timing parameters.

Note to tables:

(1) These timing parameters are sample-tested only.

tESBDD ES B dat a-in t o dat a-out delay for RAM mode

tPD ESB macrocell input to non-registered output

tPTERMSU ESB macrocell register setup time before clock

tPTERMCO ESB macrocell register clock-to-output delay

tF1-4 Fanout delay using local interconnect

tF5-20 Fanout delay using MegaLab Interconnect

tF20+ Fanout delay using FastTrack Interconnect

tCH Minimum cl ock high time from clock pin

tCL Minimum clock low time from clock pin

tCLRP LE clear pulse width

tPREP LE preset pul se width

tESBCH Cloc k hig h time

tESBCL Clock low time

tESBWP Writ e puls e w idth

tESBRP Read pulse width

Table 35. APEX 20K fMAX Timing Paramete rs (Part 2 of 2)

Symbol Parameter

Table 36. APEX 20K External Timing Parameters Note (1)

Symb ol Clo ck Pa r ame t er Con di t i ons

tINSU Setup time with globa l clock at IOE register

tINH Hold time w ith global c loc k at IOE regis t er

tOUTCO Clock-to-output delay wit h global clock at IOE register

Table 37. APEX 20K External Bidirectional Timing Parameters No te (1)

Symbol Parameter Condition

tINSUBIDIR S et up time f or bidirectional pins with global cloc k at same-row or same-

column LE register

tINHBIDIR Hold time for bidirectional pins with global clock at same-row or same-

column LE register

tOUTCOBIDIR Cloc k -t o-output del ay for bidir ec tio nal pins wi th glo bal c loc k at IOE

tXZBIDIR S yn ch ronous IOE output buffer dis able delay C1 = 35 pF

tZXBIDIR S yn ch ronous IOE output buffer enable delay, slow s lew rate = off C1 = 35 pF

78 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Table 38 through 41 show APEX 20KE LE, ESB, rou tin g, an d fu nctional

timing microparameters for the fMAX timing model.

Table 38. APEX 20KE LE Timing Microparameters

Symbol Parameter

tSU LE register s et up time before clo ck

tHLE register hold time afte r clock

tCO LE register c loc k- to- out put delay

tLUT LUT delay for data-in to data-o ut

Table 39. APEX 20KE ESB Timin g Mic ropar am et ers

Symbol Parameter

tESBARC ESB Asynchronous read cycle time

tESBSRC ESB Synchronous read cycle time

tESBAWC ESB Asynchronous write cycle time

tESBSWC ESB Synchronous write cycle time

tESBWASU ESB write addr es s setu p time w it h res pec t to WE

tESBWAH ESB write addr es s hold time w ith resp ec t to WE

tESBWDSU ESB data setup tim e with resp e ct to WE

tESBWDH E S B da ta hold ti me with r e spe ct t o WE

tESBRASU ESB read addr es s setu p time w it h res pec t to RE

tESBRAH ESB read addr es s hold time w ith resp ec t to RE

tESBWESU ESB WE setup time before clo ck wh en us ing input register

tESBWEH ESB WE hold time af te r clock wh en us ing input register

tESBDATASU ESB data setup time before clock when using input register

tESBWADDRSU ESB write address setu p time before clo ck wh en us ing input

registers

tESBRADDRSU ESB read address setu p time before clo ck wh en us ing input

registers

tESBDATACO1 ESB clock -to -out put delay when using output regis ter s

tESBDATACO2 ESB clock-to-output delay without output registers

tESBDD ESB data-in to data-out delay for RAM mode

tPD ESB Macrocell input to non-registered output

tPTERMSU ESB Macrocell register setup time before clock

tPTERMCO ESB Macrocell register clock-to-output delay

Altera Corporation 79

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Note to Table:

(1) These parameters are worst-case values for typical applications. Post-compilation

timing simulation and timing analysis are requi re d to de ter mine actual worst-ca se

performance.

Tables 42 and 43 describe the APEX 20KE ex te rnal timing parame ters.

Table 40. APEX 20KE Routing Timing Microparameters Note (1)

Symbol Parameter

tF1-4 Fanout delay using Local Interconnect

tF5-20 Fanout delay esti m at e us ing M egaLab Inte rco nnec t

tF20+ Fanout delay estim at e us ing F astT rac k Interc onnect

Table 41. APEX 20K E Functional Timing Mi croparame t ers

Symbol Parameter

TCH Minimum c loc k hig h time f rom clock pin

TCL Minimum clock low time from clock pin

TCLRP LE clear Pulse Width

TPREP LE preset pulse width

TESBCH Clock high time for ESB

TESBCL Clock low time for ESB

TESBWP Write puls e w idt h

TESBRP Read pulse width

Table 42. APEX 20KE External Timing Parameters Note (1)

Symb ol Clo ck Pa r ame t er Con di t i ons

tINSU Setup time with globa l clock at IOE input register

tINH Hold time w ith global c loc k at IOE input regis t er

tOUTCO Clock-to-output de lay with global clock at IOE out put register C1 = 35 pF

tINSUPLL S et up time with PLL cloc k at IO E input regis t er

tINHPLL Hold time with PLL clock at IOE input register

tOUTCOPLL Clock-to-output de lay with PLL c loc k at IOE out put regis t er C1 = 35 pF

80 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Note to ta bles:

(1) These timing parameters are sample-tested only.

Table 43 . APE X 20KE Externa l Bi dir ectional Timing Par am et ers Note (1)

Symbol Parameter Condition

tINSUBIDIR Setup time for bidirec t ional pins with global clock at LAB adjac ent Input

tINHBIDIR H old t im e for bid irec ti onal pins with global c loc k at LAB adjac ent Inp ut

tOUTCOBIDIR Clock-to-output delay for bidirectional pins with global clock at IOE output

tXZBIDIR Sy nc hronous Out put Enable Regis te r to output buffer dis able delay C1 = 35 pF

tZXBIDIR Sy nc hronous Out put Enable Regis te r out put buffer enable de lay C1 = 35 pF

tINSUBIDIRPLL Setup time for bidirectional pins with PLL clock at LAB adjacent Input

tINHBIDIRPLL Hold t im e for bid irec ti onal pins with PLL cl oc k at LAB adjacent Inpu t

tOUTCOBIDIRPLL Clock- to -out put delay fo r bidirec t ional pins with PLL c loc k at IOE out put

tXZBIDIRPLL Sync hronous Out put Enable Register to output buff er dis able delay with

PLL C1 = 35 pF

tZXBIDIRPLL Synchronous Output Enable Register output buffer enable delay with PLL C1 = 35 pF

Altera Corporation 81

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Tables 44 through 46 show the fMAX timing parameters for EP20K100,

EP20K200, and EP2 0K4 00 APEX 2 0K de v ices.

Table 44. EP20K100 fMAX Timing Parameters

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade

Min Max Min Max Min Max

tSU 0.5 0.6 0.8

tH0.7 0.8 1.0

tCO 0.3 0.4 0.5

tLUT 0.8 1.0 1.3

tESBRC 1.7 2.1 2.4

tESBWC 5.7 6.9 8.1

tESBWESU 3.3 3.9 4.6

tESBDATASU 2.2 2.7 3.1

tESBADDRSU 2.4 2.9 3.3

tESBDATACO1 1.3 1.6 1.8

tESBDATACO2 2.6 3.1 3.6

tESBDD 2.5 3.3 3.6

tPD 2.5 3.0 3.6

tPTERMSU 2.3 2.6 3.2

tPTERMCO 1.5 1.8 2.1

tF1-4 0.5 0.6 0.7

tF5-20 1.6 1.7 1.8

tF20+ 2.2 2.2 2.3

tCH 2.0 2.5 3.0

tCL 2.0 2.5 3.0

tCLRP 0.3 0.4 0.4

tPREP 0.5 0.5 0.5

tESBCH 2.0 2.5 3.0

tESBCL 2.0 2.5 3.0

tESBWP 1.6 1.9 2.2

tESBRP 1.0 1.3 1.4

82 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Table 45. EP2 0K200 f MAX Timing Para me te rs

Sym bol -1 Speed Grade -2 Sp eed Gr ade -3 Speed Gr ade

Min Max Min Max Min Max

tSU 0.5 0.6 0.8

tH0.7 0.8 1.0

tCO 0.3 0.4 0.5

tLUT 0.8 1.0 1.3

tESBRC 1.7 2.1 2.4

tESBWC 5.7 6.9 8.1

tESBWESU 3.3 3.9 4.6

tESBDATASU 2.2 2.7 3.1

tESBADDRSU 2.4 2.9 3.3

tESBDATACO1 1.3 1.6 1.8

tESBDATACO2 2.6 3.1 3.6

tESBDD 2.5 3.3 3.6

tPD 2.5 3.0 3.6

tPTERMSU 2.3 2.7 3.2

tPTERMCO 1.5 1.8 2.1

tF1-4 0.5 0.6 0.7

tF5-20 1.6 1.7 1.8

tF20+ 2.2 2.2 2.3

tCH 2.0 2.5 3.0

tCL 2.0 2.5 3.0

tCLRP 0.3 0.4 0.4

tPREP 0.4 0.5 0.5

tESBCH 2.0 2.5 3.0

tESBCL 2.0 2.5 3.0

tESBWP 1.6 1.9 2.2

tESBRP 1.0 1.3 1.4

Altera Corporation 83

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Tables 47 through 52 show the I/O exte r nal and ex ternal bi d ir e ctional

timing paramete r values for EP2 0K100, EP20K200, and EP20 K400

APEX 20K devices.

Table 46. EP20K400 fMAX Timing Parameters

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade

Min Max Min Max Min Max

tSU 0.1 0.3 0.6

tH0.5 0.8 0.9

tCO 0.1 0.4 0.6

tLUT 1.0 1.2 1.4

tESBRC 1.7 2.1 2.4

tESBWC 5.7 6.9 8.1

tESBWESU 3.3 3.9 4.6

tESBDATASU 2.2 2.7 3.1

tESBADDRSU 2.4 2.9 3.3

tESBDATACO1 1.3 1.6 1.8

tESBDATACO2 2.5 3.1 3.6

tESBDD 2.5 3.3 3.6

tPD 2.5 3.1 3.6

tPTERMSU 1.7 2.1 2.4

tPTERMCO 1.0 1.2 1.4

tF1-4 0.4 0.5 0.6

tF5-20 2.6 2.8 2.9

tF20+ 3.7 3.8 3.9

tCH 2.0 2.5 3.0

tCL 2.0 2.5 3.0

tCLRP 0.5 0.6 0.8

tPREP 0.5 0.5 0.5

tESBCH 2.0 2.5 3.0

tESBCL 2.0 2.5 3.0

tESBWP 1.5 1.9 2.2

tESBRP 1.0 1.2 1.4

84 Altera  Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Table 47 . EP2 0K100 External Tim i ng Parameter s
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tINSU (1) 2.32.8 3.2ns
tINH (1) 0.00.0 0.0ns
tOUTCO (1) 2.0 4.5 2.0 4.9 2.0 6.6 ns
tINSU (2) 1.1 1.2 – ns
tINH (2) 0.0 0.0 – ns
tOUTCO (2) 0.5 2.7 0.5 3.1 – 4.8 ns
Table 48 . EP20K100 E xternal Bidirectional Timi ng Pa rameters 
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tINSUBIDIR (1) 2.3 2.8 3.2 ns
tINHBIDIR (1) 0.0 0.0 0.0 ns
tOUTCOBIDIR (1) 2.0 4.5 2.0 4.9 2.0 6.6 ns
tXZBIDIR (1) 5.0 5.9 6.9 ns
tZXBIDIR (1) 5.0 5.9 6.9 ns
tINSUBIDIR (2) 1.0 1.2 – ns
tINHBIDIR (2) 0.0 0.0 – ns
tOUTCOBIDIR (2) 0.5 2.7 0.5 3.1 – – ns
tXZBIDIR (2) 4.3 5.0 – ns
tZXBIDIR (2) 4.3 5.0 – ns
Table 49 . EP2 0K200 External Tim i ng Parameter s
Symbol -1 Speed Grade -2 Sp eed Gr ade -3 Speed Grade Unit
Min Max Min Max Min Max
tINSU (1) 1.9 2.3 2.6 ns
tINH (1) 0.0 0.0 0.0 ns
tOUTCO (1) 2.0 4.6 2.0 5.6 2.0 6.8 ns
tINSU (2) 1.1 1.2 – ns
tINH (2) 0.0 0.0 – ns
tOUTCO (2) 0.5 2.7 0.5 3.1 – – ns

Altera  Corporation  85
APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Table 50. EP20K200 External Bidirectional Timing Parameters
Sym bol - 1 Sp eed Gr ade -2 Spee d G rade -3  Speed  G rade Unit
Min Max Min Max Min Max
tINSUBIDIR (1) 1.9 2.3 2.6 ns
tINHBIDIR (1) 0.0 0.0 0.0 ns
tOUTCOBIDIR (1) 2.0 4.6 2.0 5.6 2.0 6.8 ns
tXZBIDIR (1) 5.0 5.9 6.9 ns
tZXBIDIR (1) 5.0 5.9 6.9 ns
tINSUBIDIR (2) 1.1 1.2 – ns
tINHBIDIR (2) 0.0 0.0 – ns
tOUTCOBIDIR (2) 0.5 2.7 0.5 3.1 – – ns
tXZBIDIR (2) 4.3 5.0 – ns
tZXBIDIR (2) 4.3 5.0 – ns
Table 51. EP20K400 External Timing Parameters
Symbol -1 Speed G rade -2 Spee d Grade -3 Speed Gr ade Unit
Min Max Min Max Min Max
tINSU (1) 1.4 1.8 2.0 ns
tINH (1) 0.0 0.0 0.0 ns
tOUTCO (1) 2.0 4.9 2.0 6.1 2.0 7.0 ns
tINSU (2) 0.4 1.0 – ns
tINH (2) 0.0 0.0 – ns
tOUTCO (2) 0.5 3.1 0.5 4.1 – – ns

86 Altera  Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Notes to tables:
(1) This para met er is measured withou t using  Clock L ock or Clock B oo st circu its.
(2) This para met e r  is mea sured u s ing  Clock Loc k or Clo ckBoost circuits.
Tables 53 through 58 describe fMAX LE Timing Microparameters, fMAX 
ESB Timin g Mi croparam et ers, fMAX Routing Delays, Minimum Pulse 
Width Timing Parameters, External Timing Parameters, and External 
Bidirectional Timin g Para meters for EP20K3 0E AP EX 20 KE devi ces.
Table 52 . EP20K400 E xternal Bidirectional Timi ng Pa rameters
Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit
Min Max Min Max Min Max
tINSUBIDIR (1) 1.4 1.8 2.0 ns
tINHBIDIR (1) 0.0 0.0 0.0 ns
tOUTCOBIDIR (1) 2.0 4.9 2.0 6.1 2.0 7.0 ns
tXZBIDIR (1) 7.3 8.9 10.3 ns
tZXBIDIR (1) 7.3 8.9 10.3 ns
tINSUBIDIR (2) 0.5 1.0 – ns
tINHBIDIR (2) 0.0 0.0 – ns
tOUTCOBIDIR (2) 0.5 3.1 0.5 4.1 – – ns
tXZBIDIR (2) 6.2 7.6 – ns
tZXBIDIR (2) 6.2 7.6 – ns
Table 53. EP2 0K30E f MAX LE Timing Microparameters 
Symbol -1 -2  -3 Unit
Min Max Min Max Min Max
tSU 0.01 0.02 0.02 ns
tH0.11 0.16 0.23 ns
tCO 0.32 0.45 0.67 ns
tLUT 0.85 1.20 1.77 ns

Altera Corporation 87

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Table 54. EP20K30E fMAX ESB Timing Mi croparamet ers

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tESBARC 2.03 2.86 4.24 ns

tESBSRC 2.58 3.49 5.02 ns

tESBAWC 3.88 5.45 8.08 ns

tESBSWC 4.08 5.35 7.48 ns

tESBWASU 1.77 2.49 3.68 ns

tESBWAH 0.00 0.00 0.00 ns

tESBWDSU 1.95 2.74 4.05 ns

tESBWDH 0.00 0.00 0.00 ns

tESBRASU 1.96 2.75 4.07 ns

tESBRAH 0.00 0.00 0.00 ns

tESBWESU 1.80 2.73 4.28 ns

tESBWEH 0.00 0.00 0.00 ns

tESBDATASU 0.07 0.48 1.17 ns

tESBWADDRSU 0.30 0.80 1.64 ns

tESBRADDRSU 0.37 0.90 1.78 ns

tESBDATACO1 1.11 1.32 1.67 ns

tESBDATACO2 2.65 3.73 5.53 ns

tESBDD 3.88 5.45 8.08 ns

tPD 1.91 2.69 3.98 ns

tPTERMSU 1.04 1.71 2.82 ns

tPTERMCO 1.13 1.34 1.69 ns

Table 55. EP20K30E fMAX Rou ting Delays

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tF1-4 0.24 0.27 0.31 ns

tF5-20 1.03 1.14 1.30 ns

tF20+ 1.42 1.54 1.77 ns

88 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Table 56. EP20K30E Minimum Pulse Width Timing Parameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tCH 0.55 0.78 1.15 ns

tCL 0.55 0.78 1.15 ns

tCLRP 0.22 0.31 0.46 ns

tPREP 0.22 0.31 0.46 ns

tESBCH 0.55 0.78 1.15 ns

tESBCL 0.55 0.78 1.15 ns

tESBWP 1.43 2.01 2.97 ns

tESBRP 1.15 1.62 2.39 ns

Table 57. EP20K30E External Timing Parameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tINSU 2.02 2.13 2.24 ns

tINH 0.00 0.00 0.00 ns

tOUTCO 2.00 4.88 2.00 5.36 2.00 5.88 ns

tINSUPLL 2.11 2.23 - ns

tINHPLL 0.00 0.00 - ns

tOUTCOPLL 0.50 2.60 0.50 2.88 - - ns

Table 58. EP20K30E External Bidirectional Timing Parameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tINSUBIDIR 1.85 1.77 1.54 ns

tINHBIDIR 0.00 0.00 0.00 ns

tOUTCOBIDIR 2.00 4.88 2.00 5.36 2.00 5.88 ns

tXZBIDIR 7.48 8.46 9.83 ns

tZXBIDIR 7.48 8.46 9.83 ns

tINSUBIDIRPLL 4.12 4.24 - ns

tINHBIDIRPLL 0.00 0.00 - ns

tOUTCOBIDIRPLL 0.50 2.60 0.50 2.88 - - ns

tXZBIDIRPLL 5.21 5.99 - ns

tZXBIDIRPLL 5.21 5.99 - ns

Altera Corporation 89

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Tables 59 through 64 describe fMAX LE Timing Microparameters, fMAX

ESB Timing Microparameters, fMAX Routing Delays, Minimum Pulse

Width Timing Para met ers, Exte rna l Ti mi ng Parameters, and External

Bidirecti ona l Tim ing Pa rame ters for EP20K60E APEX 20KE devices.

Table 59. EP20K60E fMAX LE Timin g Microparamet ers

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tSU 0.17 0.15 0.16 ns

tH0.32 0.33 0.39 ns

tCO 0.29 0.40 0.60 ns

tLUT 0.77 1.07 1.59 ns

Table 60. EP20K60E fMAX ESB Timing Mi croparamet ers

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tESBARC 1.83 2.57 3.79 ns

tESBSRC 2.46 3.26 4.61 ns

tESBAWC 3.50 4.90 7.23 ns

tESBSWC 3.77 4.90 6.79 ns

tESBWASU 1.59 2.23 3.29 ns

tESBWAH 0.00 0.00 0.00 ns

tESBWDSU 1.75 2.46 3.62 ns

tESBWDH 0.00 0.00 0.00 ns

tESBRASU 1.76 2.47 3.64 ns

tESBRAH 0.00 0.00 0.00 ns

tESBWESU 1.68 2.49 3.87 ns

tESBWEH 0.00 0.00 0.00 ns

tESBDATASU 0.08 0.43 1.04 ns

tESBWADDRSU 0.29 0.72 1.46 ns

tESBRADDRSU 0.36 0.81 1.58 ns

tESBDATACO1 1.06 1.24 1.55 ns

tESBDATACO2 2.39 3.35 4.94 ns

tESBDD 3.50 4.90 7.23 ns

tPD 1.72 2.41 3.56 ns

tPTERMSU 0.99 1.56 2.55 ns

tPTERMCO 1.07 1.26 1.08 ns

90 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Table 61. EP2 0K60E f MAX Routing Delays

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tF1-4 0.24 0.26 0.30 ns

tF5-20 1.45 1.58 1.79 ns

tF20+ 1.96 2.14 2.45 ns

Table 62. EP20K60E Minimum Pulse Width Timing Parameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tCH 2.00 2.50 2.75 ns

tCL 2.00 2.50 2.75 ns

tCLRP 0.20 0.28 0.41 ns

tPREP 0.20 0.28 0.41 ns

tESBCH 2.00 2.50 2.75 ns

tESBCL 2.00 2.50 2.75 ns

tESBWP 1.29 1.80 2.66 ns

tESBRP 1.04 1.45 2.14 ns

Table 63 . EP2 0K60E External Tim i ng Parameter s

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tINSU 2.03 2.12 2.23 ns

tINH 0.00 0.00 0.00 ns

tOUTCO 2.00 4.84 2.00 5.31 2.00 5.81 ns

tINSUPLL 1.12 1.15 - ns

tINHPLL 0.00 0.00 - ns

tOUTCOPLL 0.50 3.37 0.50 3.69 - - ns

Altera Corporation 91

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Tables 65 through 70 describe fMAX LE Timing Microparameters,

fMAX ES B Ti ming Mic ropa ram eter s, fMAX Routing Dela ys, Minimum

Pulse Width Timing P arameters, Ex te rn al Ti mi ng Paramete rs, and

External Bidirectional Timi ng Paramete rs for EP20K100E

APEX 20KE devices.

Table 64. EP20K60E External Bidirectional Timing Parameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tINSUBIDIR 2.77 2.91 3.11 ns

tINHBIDIR 0.00 0.00 0.00 ns

tOUTCOBIDIR 2.00 4.84 2.00 5.31 2.00 5.81 ns

tXZBIDIR 6.47 7.44 8.65 ns

tZXBIDIR 6.47 7.44 8.65 ns

tINSUBIDIRPLL 3.44 3.24 - ns

tINHBIDIRPLL 0.00 0.00 - ns

tOUTCOBIDIRPLL 0.50 3.37 0.50 3.69 - - ns

tXZBIDIRPLL 5.00 5.82 - ns

tZXBIDIRPLL 5.00 5.82 - ns

Table 65. EP20K100E fMAX LE Timing Microparameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tSU 0.25 0.25 0.25 ns

tH0.25 0.25 0.25 ns

tCO 0.28 0.28 0.34 ns

tLUT 0.80 0.95 1.13 ns

92 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Table 66. EP2 0K100E fMAX ESB Timing Mi cropa rameter s

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tESBARC 1.61 1.84 1.97 ns

tESBSRC 2.57 2.97 3.20 ns

tESBAWC 0.52 4.09 4.39 ns

tESBSWC 3.17 3.78 4.09 ns

tESBWASU 0.56 6.41 0.63 ns

tESBWAH 0.48 0.54 0.55 ns

tESBWDSU 0.71 0.80 0.81 ns

tESBWDH .048 0.54 0.55 ns

tESBRASU 1.57 1.75 1.87 ns

tESBRAH 0.00 0.00 0.20 ns

tESBWESU 1.54 1.72 1.80 ns

tESBWEH 0.00 0.00 0.00 ns

tESBDATASU -0.16 -0.20 -0.20 ns

tESBWADDRSU 0.12 0.08 0.13 ns

tESBRADDRSU 0.17 0.15 0.19 ns

tESBDATACO1 1.20 1.39 1.52 ns

tESBDATACO2 2.54 2.99 3.22 ns

tESBDD 3.06 3.56 3.85 ns

tPD 1.73 2.02 2.20 ns

tPTERMSU 1.11 1.26 1.38 ns

tPTERMCO 1.19 1.40 1.08 ns

Table 67. EP2 0K100E fMAX Routing Dela ys

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tF1-4 0.24 0.27 0.29 ns

tF5-20 1.04 1.26 1.52 ns

tF20+ 1.12 1.36 1.86 ns

Altera Corporation 93

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Table 68. EP20K100E Minimum Pulse Width Timing Parameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tCH 2.00 2.00 2.00 ns

tCL 2.00 2.00 2.00 ns

tCLRP 0.20 0.20 0.20 ns

tPREP 0.20 0.20 0.20 ns

tESBCH 2.00 2.00 2.00 ns

tESBCL 2.00 2.00 2.00 ns

tESBWP 1.29 1.53 1.66 ns

tESBRP 1.11 1.29 1.41 ns

Table 69. EP20K100E External Timing Parameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tINSU 2.23 2.32 2.43 ns

tINH 0.00 0.00 0.00 ns

tOUTCO 2.00 4.86 2.00 5.35 2.00 5.84 ns

tINSUPLL 1.58 1.66 - ns

tINHPLL 0.00 0.00 - ns

tOUTCOPLL 0.50 2.96 0.50 3.29 - - ns

Table 70. EP20K100E External Bidirectional Timing Parameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tINSUBIDIR 2.74 2.96 3.19 ns

tINHBIDIR 0.00 0.00 0.00 ns

tOUTCOBIDIR 2.00 4.86 2.00 5.35 2.00 5.84 ns

tXZBIDIR 5.00 5.48 5.89 ns

tZXBIDIR 5.00 5.48 5.89 ns

tINSUBIDIRPLL 4.64 5.03 - ns

tINHBIDIRPLL 0.00 0.00 - ns

tOUTCOBIDIRPLL 0.50 2.96 0.50 3.29 - - ns

tXZBIDIRPLL 3.10 3.42 - ns

tZXBIDIRPLL 3.10 3.42 - ns

94 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Tables 71 through 76 describe fMAX LE Timing Microparameters, fMAX

ESB Timin g Mi croparam et ers, fMAX Routing Delays, Minimum Pulse

Width Timing Parameters, External Timing Parameters, and External

Bidirectional Timin g Para meters for EP20K1 60 E APEX 2 0KE devices.

Table 71. EP2 0K160E fMAX LE Timing Mi croparam et ers

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tSU 0.22 0.24 0.26 ns

tH0.22 0.24 0.26 ns

tCO 0.25 0.31 0.35 ns

tLUT 0.69 0.88 1.12 ns

Table 72. EP2 0K160E fMAX ESB Timing Mi cropa rameter s

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tESBARC 1.65 2.02 2.11 ns

tESBSRC 2.21 2.70 3.11 ns

tESBAWC 3.04 3.79 4.42 ns

tESBSWC 2.81 3.56 4.10 ns

tESBWASU 0.54 0.66 0.73 ns

tESBWAH 0.36 0.45 0.47 ns

tESBWDSU 0.68 0.81 0.94 ns

tESBWDH 0.36 0.45 0.47 ns

tESBRASU 1.58 1.87 2.06 ns

tESBRAH 0.00 0.00 0.01 ns

tESBWESU 1.41 1.71 2.00 ns

tESBWEH 0.00 0.00 0.00 ns

tESBDATASU -0.02 -0.03 0.09 ns

tESBWADDRSU 0.14 0.17 0.35 ns

tESBRADDRSU 0.21 0.27 0.43 ns

tESBDATACO1 1.04 1.30 1.46 ns

tESBDATACO2 2.15 2.70 3.16 ns

tESBDD 2.69 3.35 3.97 ns

tPD 1.55 1.93 2.29 ns

tPTERMSU 1.01 1.23 1.52 ns

tPTERMCO 1.06 1.32 1.04 ns

Altera Corporation 95

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Table 73. EP20K160E fMAX R out i n g De lays

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tF1-4 0.25 0.26 0.28 ns

tF5-20 1.00 1.18 1.35 ns

tF20+ 1.95 2.19 2.30 ns

Table 74. EP20K160E Minimum Pulse Width Timing Parameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tCH 1.34 1.43 1.55 ns

tCL 1.34 1.43 1.55 ns

tCLRP 0.18 0.19 0.21 ns

tPREP 0.18 0.19 0.21 ns

tESBCH 1.34 1.43 1.55 ns

tESBCL 1.34 1.43 1.55 ns

tESBWP 1.15 1.45 1.73 ns

tESBRP 0.93 1.15 1.38 ns

Table 75. EP20K160E External Timing Parameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tINSU 2.23 2.34 2.47 ns

tINH 0.00 0.00 0.00 ns

tOUTCO 2.00 5.07 2.00 5.59 2.00 6.13 ns

tINSUPLL 2.12 2.07 - ns

tINHPLL 0.00 0.00 - ns

tOUTCOPLL 0.50 3.00 0.50 3.35 - - ns

96 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Tables 77 through 82 describe fMAX LE Timing Microparameters, fMAX

ESB Timin g Mi croparam et ers, fMAX Routing Delays, Minimum Pulse

Width Timing Parameters, External Timing Parameters, and External

Bidirectional Timin g Para meters for EP20K2 00 E APEX 2 0KE devices.

Table 76. EP2 0K160E External Bidirection al Timing Paramete rs

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tINSUBIDIR 2.86 3.24 3.54 ns

tINHBIDIR 0.00 0.00 0.00 ns

tOUTCOBIDIR 2.00 5.07 2.00 5.59 2.00 6.13 ns

tXZBIDIR 7.43 8.23 8.58 ns

tZXBIDIR 7.43 8.23 8.58 ns

tINSUBIDIRPLL 4.93 5.48 - ns

tINHBIDIRPLL 0.00 0.00 - ns

tOUTCOBIDIRPLL 0.50 3.00 0.50 3.35 - - ns

tXZBIDIRPLL 5.36 5.99 - ns

tZXBIDIRPLL 5.36 5.99 - ns

Table 77. EP2 0K200E fMAX LE Timing Mi croparam et ers

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tSU 0.23 0.24 0.26 ns

tH0.23 0.24 0.26 ns

tCO 0.26 0.31 0.36 ns

tLUT 0.70 0.90 1.14 ns

Altera Corporation 97

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Table 78. EP20K200E fMAX ES B Ti mi ng Mic r op ar am et e r s

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tESBARC 1.68 2.06 2.24 ns

tESBSRC 2.27 2.77 3.18 ns

tESBAWC 3.10 3.86 4.50 ns

tESBSWC 2.90 3.67 4.21 ns

tESBWASU 0.55 0.67 0.74 ns

tESBWAH 0.36 0.46 0.48 ns

tESBWDSU 0.69 0.83 0.95 ns

tESBWDH 0.36 0.46 0.48 ns

tESBRASU 1.61 1.90 2.09 ns

tESBRAH 0.00 0.00 0.01 ns

tESBWESU 1.42 1.71 2.01 ns

tESBWEH 0.00 0.00 0.00 ns

tESBDATASU -0.06 -0.07 0.05 ns

tESBWADDRSU 0.11 0.13 0.31 ns

tESBRADDRSU 0.18 0.23 0.39 ns

tESBDATACO1 1.09 1.35 1.51 ns

tESBDATACO2 2.19 2.75 3.22 ns

tESBDD 2.75 3.41 4.03 ns

tPD 1.58 1.97 2.33 ns

tPTERMSU 1.00 1.22 1.51 ns

tPTERMCO 1.10 1.37 1.09 ns

Table 79. EP20K200E fMAX R out i n g De lays

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tF1-4 0.25 0.27 0.29 ns

tF5-20 1.02 1.20 1.41 ns

tF20+ 1.99 2.23 2.53 ns

98 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Table 80. EP20K200E Minimum Pulse Width Ti ming Paramete rs

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tCH 1.36 2.44 2.65 ns

tCL 1.36 2.44 2.65 ns

tCLRP 0.18 0.19 0.21 ns

tPREP 0.18 0.19 0.21 ns

tESBCH 1.36 2.44 2.65 ns

tESBCL 1.36 2.44 2.65 ns

tESBWP 1.18 1.48 1.76 ns

tESBRP 0.95 1.17 1.41 ns

Table 81. EP20K200E Ext ernal Timing P arameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tINSU 2.24 2.35 2.47 ns

tINH 0.00 0.00 0.00 ns

tOUTCO 2.00 5.12 2.00 5.62 2.00 6.11 ns

tINSUPLL 2.13 2.07 - ns

tINHPLL 0.00 0.00 - ns

tOUTCOPLL 0.50 3.01 0.50 3.36 - - ns

Altera Corporation 99

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Tables 83 through 88 describe fMAX LE Timing Microparameters, fMAX

ESB Timing Microparameters, fMAX Routing Delays, Minimum Pulse

Width Timing Para met ers, Exte rna l Ti mi ng Parameters, and External

Bidirecti ona l Tim ing Pa rameters for EP20K 30 0E APEX 20KE devices.

Table 82. EP20K200E External Bidirectional Timing Parameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tINSUBIDIR 2.81 3.19 3.54 ns

tINHBIDIR 0.00 0.00 0.00 ns

tOUTCOBIDIR 2.00 5.12 2.00 5.62 2.00 6.11 ns

tXZBIDIR 7.51 8.32 8.67 ns

tZXBIDIR 7.51 8.32 8.67 ns

tINSUBIDIRPLL 3.30 3.64 - ns

tINHBIDIRPLL 0.00 0.00 - ns

tOUTCOBIDIRPLL 0.50 3.01 0.50 3.36 - - ns

tXZBIDIRPLL 5.40 6.05 - ns

tZXBIDIRPLL 5.40 6.05 - ns

Table 83. EP20K300E fMAX LE Timing Microparameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tSU 0.16 0.17 0.18 ns

tH0.31 0.33 0.38 ns

tCO 0.28 0.38 0.51 ns

tLUT 0.79 1.07 1.43 ns

100 Altera Corp ora t ion

APEX 20K Programmable Logic Device Family Data Sheet

Table 84. EP2 0K300E fMAX ESB Timing Mi cropa rameter s

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tESBARC 1.79 2.44 3.25 ns

tESBSRC 2.40 3.12 4.01 ns

tESBAWC 3.41 4.65 6.20 ns

tESBSWC 3.68 4.68 5.93 ns

tESBWASU 1.55 2.12 2.83 ns

tESBWAH 0.00 0.00 0.00 ns

tESBWDSU 1.71 2.33 3.11 ns

tESBWDH 0.00 0.00 0.00 ns

tESBRASU 1.72 2.34 3.13 ns

tESBRAH 0.00 0.00 0.00 ns

tESBWESU 1.63 2.36 3.28 ns

tESBWEH 0.00 0.00 0.00 ns

tESBDATASU 0.07 0.39 0.80 ns

tESBWADDRSU 0.27 0.67 1.17 ns

tESBRADDRSU 0.34 0.75 1.28 ns

tESBDATACO1 1.03 1.20 1.40 ns

tESBDATACO2 2.33 3.18 4.24 ns

tESBDD 3.41 4.65 6.20 ns

tPD 1.68 2.29 3.06 ns

tPTERMSU 0.96 1.48 2.14 ns

tPTERMCO 1.05 1.22 1.42 ns

Table 85. EP2 0K300E fMAX Routing Dela ys

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tF1-4 0.22 0.24 0.26 ns

tF5-20 1.33 1.43 1.58 ns

tF20+ 3.63 3.93 4.35 ns

Altera Corporation 101

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Table 86. EP20K300E Minimum Pulse Width Timing Parameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tCH 1.25 1.43 1.67 ns

tCL 1.25 1.43 1.67 ns

tCLRP 0.19 0.26 0.35 ns

tPREP 0.19 0.26 0.35 ns

tESBCH 1.25 1.43 1.67 ns

tESBCL 1.25 1.43 1.67 ns

tESBWP 1.25 1.71 2.28 ns

tESBRP 1.01 1.38 1.84 ns

Table 87. EP20K300E External Timing Parameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tINSU 2.31 2.44 2.57 ns

tINH 0.00 0.00 0.00 ns

tOUTCO 2.00 5.29 2.00 5.82 2.00 6.24 ns

tINSUPLL 1.76 1.85 - ns

tINHPLL 0.00 0.00 - ns

tOUTCOPLL 0.50 2.65 0.50 2.95 - - ns

Table 88. EP20K300E External Bidirectional Timing Parameters

Symbol -1 -2 -3 Unit

Min Max Min Max Min Max

tINSUBIDIR 2.77 2.85 3.11 ns

tINHBIDIR 0.00 0.00 0.00 ns

tOUTCOBIDIR 2.00 5.29 2.00 5.82 2.00 6.24 ns

tXZBIDIR 7.59 8.30 9.09 ns

tZXBIDIR 7.59 8.30 9.09 ns

tINSUBIDIRPLL 2.50 2.76 - ns

tINHBIDIRPLL 0.00 0.00 - ns

tOUTCOBIDIRPLL 0.50 2.65 0.50 2.95 - - ns

tXZBIDIRPLL 5.00 5.43 - ns

tZXBIDIRPLL 5.00 5.43 - ns

102 Altera Corp ora t ion

APEX 20K Programmable Logic Device Family Data Sheet

Tables 89 through 94 describe fMAX LE Timing Microparameters, fMAX

ESB Timin g Mi croparam et ers, fMAX Routing Delays, Minimum Pulse

Width Timing Parameters, External Timing Parameters, and External

Bidirectional Timin g Para meters for EP20K4 00 E APEX 2 0KE devices.

Table 89. EP2 0K400E fMAX LE Timing Mi croparam et ers

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tSU 0.23 0.23 0.23 ns

tH0.23 0.23 0.23 ns

tCO 0.25 0.29 0.32 ns

tLUT 0.70 0.83 1.01 ns

Table 90. EP2 0K400E fMAX ESB Timing Mi cropa rameter s

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tESBARC 1.67 1.91 1.99 ns

tESBSRC 2.30 2.66 2.93 ns

tESBAWC 3.09 3.58 3.99 ns

tESBSWC 3.01 3.65 4.05 ns

tESBWASU 0.54 0.63 0.65 ns

tESBWAH 0.36 0.43 0.42 ns

tESBWDSU 0.69 0.77 0.84 ns

tESBWDH 0.36 0.43 0.42 ns

tESBRASU 1.61 1.77 1.86 ns

tESBRAH 0.00 0.00 0.01 ns

tESBWESU 1.35 1.47 1.61 ns

tESBWEH 0.00 0.00 0.00 ns

tESBDATASU -0.18 -0.30 -0.27 ns

tESBWADDRSU -0.02 -0.11 -0.03 ns

tESBRADDRSU 0.06 -0.01 -0.05 ns

tESBDATACO1 1.16 1.40 1.54 ns

tESBDATACO2 2.18 2.55 2.85 ns

tESBDD 2.73 3.17 3.58 ns

tPD 1.57 1.83 2.07 ns

tPTERMSU 0.92 0.99 1.18 ns

tPTERMCO 1.18 1.43 1.17 ns

Altera Corporation 103

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Table 91. EP20K400E fMAX R out i n g De lays

Symbol -1 Speed G rade -2 Spee d Grade -3 Speed Gr ade Unit

Min Max Min Max Min Max

tF1-4 0.25 0.25 0.26 ns

tF5-20 1.01 1.12 1.25 ns

tF20+ 3.71 3.92 4.17 ns

Table 92. EP20K400E Minimum Pulse Width Timing Parameters

Symbol -1 Speed G rade -2 Spee d Grade -3 Speed Gr ade Unit

Min Max Min Max Min Max

tCH 1.36 2.22 2.35 ns

tCL 1.36 2.26 2.35 ns

tCLRP 0.18 0.18 0.19 ns

tPREP 0.18 0.18 0.19 ns

tESBCH 1.36 2.26 2.35 ns

tESBCL 1.36 2.26 2.35 ns

tESBWP 1.17 1.38 1.56 ns

tESBRP 0.94 1.09 1.25 ns

Table 93. EP20K400E External Timing Parameters

Symbol -1 Speed G rade -2 Spee d Grade -3 Speed Gr ade Unit

Min Max Min Max Min Max

tINSU 2.51 2.64 2.77 ns

tINH 0.00 0.00 0.00 ns

tOUTCO 2.00 5.25 2.00 5.79 2.00 6.32 ns

tINSUPLL 3.221 3.38 - ns

tINHPLL 0.00 0.00 - ns

tOUTCOPLL 0.50 2.25 0.50 2.45 - - ns

104 Altera Corp ora t ion

APEX 20K Programmable Logic Device Family Data Sheet

Tables 96 through 100 describe fMAX LE Timing Microparameters, fMAX

ESB Timin g Mi croparam et ers, fMAX Routing Delays, Minimum Pulse

Width Timing Parameters, External Timing Parameters, and External

Bidirectional Timin g Para meters for EP20K6 00 E APEX 2 0KE devices.

Table 94. EP2 0K400E External Bidirection al Timing Paramete rs

Symbol -1 Speed G rade -2 Speed G rade -3 Speed Grad e Uni t

Min Max Min Max Min Max

tINSUBIDIR 2.93 3.23 3.44 ns

tINHBIDIR 0.00 0.00 0.00 ns

tOUTCOBIDIR 2.00 5.25 2.00 5.79 2.00 6.32 ns

tXZBIDIR 5.95 6.77 7.12 ns

tZXBIDIR 5.95 6.77 7.12 ns

tINSUBIDIRPLL 4.31 4.76 - ns

tINHBIDIRPLL 0.00 0.00 - ns

tOUTCOBIDIRPLL 0.50 2.25 0.50 2.45 - - ns

tXZBIDIRPLL 2.94 3.43 - ns

tZXBIDIRPLL 2.94 3.43 - ns

Table 95. EP2 0K600E fMAX LE Timing Mi croparam et ers

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tSU 0.16 0.16 0.17 ns

tH0.29 0.33 0.37 ns

tCO 0.65 0.38 0.49 ns

tLUT 0.70 1.00 1.30 ns

Altera Corporation 105

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Table 96. EP20K600E fMAX ES B Ti mi ng Mic r op ar am et e r s

Symbol -1 Speed Grade -2 S peed G rade -3 Speed Grade Unit

Min Max Min Max Min Max

tESBARC 1.67 2.39 3.11 ns

tESBSRC 2.27 3.07 3.86 ns

tESBAWC 3.19 4.56 5.93 ns

tESBSWC 3.51 4.62 5.72 ns

tESBWASU 1.46 2.08 2.70 ns

tESBWAH 0.00 0.00 0.00 ns

tESBWDSU 1.60 2.29 2.97 ns

tESBWDH 0.00 0.00 0.00 ns

tESBRASU 1.61 2.30 2.99 ns

tESBRAH 0.00 0.00 0.00 ns

tESBWESU 1.49 2.30 3.11 ns

tESBWEH 0.00 0.00 0.00 ns

tESBDATASU -0.01 0.35 0.71 ns

tESBWADDRSU 0.19 0.62 1.06 ns

tESBRADDRSU 0.25 0.71 1.17 ns

tESBDATACO1 1.01 1.19 1.37 ns

tESBDATACO2 2.18 3.12 4.05 ns

tESBDD 3.19 4.56 5.93 ns

tPD 1.57 2.25 2.92 ns

tPTERMSU 0.85 1.43 2.01 ns

tPTERMCO 1.03 1.21 1.39 ns

Table 97. EP20K600E fMAX R out i n g De lays

Symbol -1 Speed G rade -2 Spee d Grade -3 Speed Gr ade Unit

Min Max Min Max Min Max

tF1-4 0.22 0.25 0.26 ns

tF5-20 1.26 1.39 1.52 ns

tF20+ 3.51 3.88 4.26 ns

106 Altera Corp ora t ion

APEX 20K Programmable Logic Device Family Data Sheet

Table 98. EP20K600E Minimum Pulse Width Ti ming Paramete rs

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tCH 2.00 2.50 2.75 ns

tCL 2.00 2.50 2.75 ns

tCLRP 0.18 0.26 0.34 ns

tPREP 0.18 0.26 0.34 ns

tESBCH 2.00 2.50 2.75 ns

tESBCL 2.00 2.50 2.75 ns

tESBWP 1.17 1.68 2.18 ns

tESBRP 0.95 1.35 1.76 ns

Table 99. EP20K600E Ext ernal Timing P arameters

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tINSU 2.74 2.74 2.87 ns

tINH 0.00 0.00 0.00 ns

tOUTCO 2.00 5.51 2.00 6.06 2.00 6.61 ns

tINSUPLL 1.86 1.96 - ns

tINHPLL 0.00 0.00 - ns

tOUTCOPLL 0.50 2.62 0.50 2.91 - - ns

Table 100. EP20 K600E External Bidirectiona l Ti ming Parameters

Symbol -1 Speed G rade -2 Speed G rade -3 Speed Grad e Uni t

Min Max Min Max Min Max

tINSUBIDIR 0.64 0.98 1.08 ns

tINHBIDIR 0.00 0.00 0.00 ns

tOUTCOBIDIR 2.00 5.51 2.00 6.06 2.00 6.61 ns

tXZBIDIR 6.10 6.74 7.10 ns

tZXBIDIR 6.10 6.74 7.10 ns

tINSUBIDIRPLL 2.26 2.68 - ns

tINHBIDIRPLL 0.00 0.00 - ns

tOUTCOBIDIRPLL 0.50 2.62 0.50 2.91 - - ns

tXZBIDIRPLL 3.21 3.59 - ns

tZXBIDIRPLL 3.21 3.59 - ns

Altera Corporation 107

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Tables 101 through 106 describe fMAX LE Ti m ing Micr oparameters, fMAX

ESB Timing Microparameters, fMAX Routing Delays, Minimum Pulse

Width Timing Para met ers, Exte rna l Ti mi ng Parameters, and External

Bidirectional Timing Parameters for EP20K1000E APEX 20KE devices.

Table 101. EP20K1000E fMAX LE Timing Microparameters

Symbol -1 Speed G rade -2 Spee d Grade -3 Speed Gr ade Unit

Min Max Min Max Min Max

tSU 0.25 0.25 0.25 ns

tH0.25 0.25 0.25 ns

tCO 0.28 0.32 0.33 ns

tLUT 0.80 0.95 1.13 ns

Table 102. EP20K1000E fMAX ESB Ti ming Microparameters

Symbol -1 Speed Grade -2 S peed G rade -3 Speed Grade Unit

Min Max Min Max Min Max

tESBARC 1.78 2.02 1.95 ns

tESBSRC 2.52 2.91 3.14 ns

tESBAWC 3.52 4.11 4.40 ns

tESBSWC 3.23 3.84 4.16 ns

tESBWASU 0.62 0.67 0.61 ns

tESBWAH 0.41 0.55 0.55 ns

tESBWDSU 0.77 0.79 0.81 ns

tESBWDH 0.41 0.55 0.55 ns

tESBRASU 1.74 1.92 1.85 ns

tESBRAH 0.00 0.01 0.23 ns

tESBWESU 2.07 2.28 2.41 ns

tESBWEH 0.00 0.00 0.00 ns

tESBDATASU 0.25 0.27 0.29 ns

tESBWADDRSU 0.11 0.04 0.11 ns

tESBRADDRSU 0.14 0.11 0.16 ns

tESBDATACO1 1.29 1.50 1.63 ns

tESBDATACO2 2.55 2.99 3.22 ns

tESBDD 3.12 3.57 3.85 ns

tPD 1.84 2.13 2.32 ns

tPTERMSU 1.08 1.19 1.32 ns

tPTERMCO 1.31 1.53 1.66 ns

108 Altera Corp ora t ion

APEX 20K Programmable Logic Device Family Data Sheet

Table 103. EP20 K1000E fMAX Routing Dela ys

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tF1-4 0.27 0.27 0.27 ns

tF5-20 1.45 1.63 1.75 ns

tF20+ 4.15 4.33 4.97 ns

Table 104. EP20K1000E Mi ni mu m Pulse Wid th Ti ming Param et er s

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tCH 1.25 1.43 1.67 ns

tCL 1.25 1.43 1.67 ns

tCLRP 0.20 0.20 0.20 ns

tPREP 0.20 0.20 0.20 ns

tESBCH 1.25 1.43 1.67 ns

tESBCL 1.25 1.43 1.67 ns

tESBWP 1.28 1.51 1.65 ns

tESBRP 1.11 1.29 1.41 ns

Table 105. EP20K1000 E External Timing Parameters

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tINSU 2.70 2.84 2.97 ns

tINH 0.00 0.00 0.00 ns

tOUTCO 2.00 5.75 2.00 6.33 2.00 6.90 ns

tINSUPLL 1.64 2.09 - ns

tINHPLL 0.00 0.00 - ns

tOUTCOPLL 0.50 2.25 0.50 2.99 - - ns

Altera Corporation 109

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Tables 107 through 112 describe fMAX LE Ti m ing Micr oparameters, fMAX

ESB Timing Microparameters, fMAX Routing Delays, Minimum Pulse

Width Timing Para met ers, Exte rna l Ti mi ng Parameters, and External

Bidirectional Timing Parameters for EP20K1500E APEX 20KE devices.

Table 106. EP20K1000E External Bidirectional Timing Parameters

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tINSUBIDIR 3.22 3.33 3.51 ns

tINHBIDIR 0.00 0.00 0.00 ns

tOUTCOBIDIR 2.00 5.75 2.00 6.33 2.00 6.90 ns

tXZBIDIR 6.31 7.09 7.76 ns

tZXBIDIR 6.31 7.09 7.76 ns

tINSUBIDIRPLL 3.25 3.26 ns

tINHBIDIRPLL 0.00 0.00 ns

tOUTCOBIDIRPLL 0.50 2.25 0.50 2.99 ns

tXZBIDIRPLL 2.81 3.80 ns

tZXBIDIRPLL 2.81 3.80 ns

Table 107. EP20K1500E fMAX LE Timing Microparameters

Symbol -1 Speed G rade -2 Spee d Grade -3 Speed Gr ade Unit

Min Max Min Max Min Max

tSU 0.25 0.25 0.25 ns

tH0.25 0.25 0.25 ns

tCO 0.28 0.32 0.33 ns

tLUT 0.80 0.95 1.13 ns

110 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Table 108. EP20 K1500E fMAX ESB Timing Mi cropa rameter s

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tESBARC 1.78 2.02 1.95 ns

tESBSRC 2.52 2.91 3.14 ns

tESBAWC 3.52 4.11 4.40 ns

tESBSWC 3.23 3.84 4.16 ns

tESBWASU 0.62 0.67 0.61 ns

tESBWAH 0.41 0.55 0.55 ns

tESBWDSU 0.77 0.79 0.81 ns

tESBWDH 0.41 0.55 0.55 ns

tESBRASU 1.74 1.92 1.85 ns

tESBRAH 0.00 0.01 0.23 ns

tESBWESU 2.07 2.28 2.41 ns

tESBWEH 0.00 0.00 0.00 ns

tESBDATASU 0.25 0.27 0.29 ns

tESBWADDRSU 0.11 0.04 0.11 ns

tESBRADDRSU 0.14 0.11 0.16 ns

tESBDATACO1 1.29 1.50 1.63 ns

tESBDATACO2 2.55 2.99 3.22 ns

tESBDD 3.12 3.57 3.85 ns

tPD 1.84 2.13 2.32 ns

tPTERMSU 1.08 1.19 1.32 ns

tPTERMCO 1.31 1.53 1.66 ns

Table 109. EP20 K1500E fMAX Routing Dela ys

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max

tF1-4 0.28 0.28 0.28 ns

tF5-20 1.36 1.50 1.62 ns

tF20+ 4.43 4.48 5.07 ns

Altera Corporation 111

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Table 110. EP20K1500E Minimum Pulse Width Timing Parameters

Symbol -1 Speed G rade -2 Spee d Grade -3 Speed Gr ade Unit

Min Max Min Max Min Max

tCH 1.25 1.43 1.67 ns

tCL 1.25 1.43 1.67 ns

tCLRP 0.20 0.20 0.20 ns

tPREP 0.20 0.20 0.20 ns

tESBCH 1.25 1.43 1.67 ns

tESBCL 1.25 1.43 1.67 ns

tESBWP 1.28 1.51 1.65 ns

tESBRP 1.11 1.29 1.41 ns

Table 111. EP20K1500E External Timing Parameters

Symbol -1 Speed G rade -2 Spee d Grade -3 Speed Gr ade Unit

Min Max Min Max Min Max

tINSU 3.09 3.30 3.58 ns

tINH 0.00 0.00 0.00 ns

tOUTCO 2.00 6.18 2.00 6.81 2.00 7.36 ns

tINSUPLL 1.94 2.08 - ns

tINHPLL 0.00 0.00 - ns

tOUTCOPLL 0.50 2.67 0.50 2.99 - - ns

112 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Tables 113 and 114 show selectable I/O standard input and output

delays for APEX 20KE devices. If you select an I/O standard input or

output delay other than LVCMOS, add or subtract the selected speed

grade to or from the LVCMOS value.

Table 112. EP20K1500E External Bidirectional Timing Parameters

Symbol -1 Spe ed Grade -2 Sp eed Gr ade -3 Spe ed Gr ade Uni t

Min Max Min Max Min Max

tINSUBIDIR 3.47 3.68 3.99 ns

tINHBIDIR 0.00 0.00 0.00 ns

tOUTCOBIDIR 2.00 6.18 2.00 6.81 2.00 7.36 ns

tXZBIDIR 6.91 7.62 8.38 ns

tZXBIDIR 6.91 7.62 8.38 ns

tINSUBIDIRPLL 3.05 3.26 ns

tINHBIDIRPLL 0.00 0.00 ns

tOUTCOBIDIRPLL 0.50 2.67 0.50 2.99 ns

tXZBIDIRPLL 3.41 3.80 ns

tZXBIDIRPLL 3.41 3.80 ns

Table 113. Select able I/O Stand ard Input Dela ys

Symbol -1 Spee d Gra de -2 Speed Grade - 3 Spee d G rade Unit

Min Max Min Max Min Max Min

LVCMOS 0.00 0.00 0.00 ns

LVTTL 0.00 0.00 0.00 ns

2. 5 V 0. 00 0 .0 4 0.05 ns

1.8 V –0.11 0.03 0.04 ns

PCI 0.01 0.09 0.10 ns

GTL+ –0.24 –0.23 –0.19 ns

SSTL-3 Class I –0.32 –0.21 –0.47 ns

SSTL-3 Class II –0.08 0.03 –0.23 ns

SSTL-2 Class I –0.17 –0.06 –0.32 ns

SSTL-2 Class II –0.16 –0.05 –0.31 ns

LVDS –0.12 –0.12 –0.12 ns

CTT 0.00 0.00 0.00 ns

AGP 0.00 0.00 0.00 ns

Altera Corporation 113

APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet

Power

Consumption

To estimate device powe r consumption, use the interactive power

est imator on the Altera web site at http://www.altera.com.

Configuration &

Operation

The A PE X 20K archit ec ture support s s ever al con figu ratio n s che mes . Th is

section summarizes the device operating modes and available device

config urat ion sche mes.

Operating Modes

The A PEX ar chitecture uses SRAM configu r at io n elements that require

configuration data to be loaded each time the circuit powers up. The

process of physically loading the SRAM data into the device is called

configuration. During initialization, which occurs immediately after

conf igur at ion, the device r es ets reg ist er s, ena bl es I/ O pin s, and beg ins t o

operate as a logic device. The I/O pins are tri-stated during power-up,

and before and during configuration. Together, the configuration and

initia lizati on pr ocesses a re cal led command mode; normal device operat ion

is called user mode.

Before and during device configuration, all I/O pins are pulled to VCCIO

by a built-in weak pull-up resistor.

Table 114. Selectable I/O Standard Output Delays

Symbol -1 Speed Grade -2 Speed Grade -3 Speed Grade Unit

Min Max Min Max Min Max Min

LVCMOS 0.00 0.00 0.00 ns

LVTTL 0.00 0.00 0.00 ns

2.5 V 0.00 0.09 0. 10 ns

1.8 V 2.49 2.98 3. 03 ns

PCI –0.03 0.17 0.16 ns

GTL+ 0.75 0.75 0.76 ns

SSTL-3 Class I 1.39 1.51 1.50 ns

SSTL -3 Cla ss II 1.11 1.23 1.23 ns

SSTL-2 Class I 1.35 1.48 1.47 ns

SSTL -2 Cla ss II 1.00 1.12 1.12 ns

LVDS –0.48 –0.48 –0.48 ns

CTT 0.00 0.00 0.00 ns

AGP 0.00 0.00 0.00 ns

114 Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

SRAM configuration elements allow APEX 20K devices to be

reconfigured in-circuit by loading new configuration data into the

device. Re al-time reconfiguratio n is p erformed by forcing t he devi ce

into command mode with a device pin, loading different

configuration data, reinitializing the device, and resuming user-

mod e oper at ion. In -fiel d u pgra des c an be perfo rme d by dist ri buti ng

new configuration files.

Configur ation Sc hemes

The conf i gu rat i o n data for an APEX 20K device can be loa ded with

one of five configuration schemes (see Table 115), chosen on the basis

of the target application. An EPC2 or EPC16 configuration device,

intelligent controller, or the JTAG port can be used to control the

configuration of an APEX 2 0K device. When a configuration device

is used, the system can configure automatically at system power-up.

Multiple APEX 20K devices can be configured in any of five

configu ration s chemes b y connec ting t he conf iguration e nabl e (nCE)

and configuration enable output (nCEO) pins on each device.

fFor more information on configuration, see Application Note 116

(Configuring APEX 20K, FLEX 10K, & FLEX 6000 Devices.)

Device Pin-Outs See the Altera web sit e (http://www.altera.com) or the Altera Digital

Library for pin-out information

Table 115. Data Sources for Conf igurat ion

Configuration Scheme Da t a Source

Configurat ion device EPC1, EPC 2, EPC 16 c onf iguration dev ices

Passive serial (PS) MasterBlaster or ByteBlasterMV download cable or serial data source

Passive parallel asynchro nous (PPA) Para llel dat a s ourc e

Passive parallel synchronous (PPS) Parallel data source

JTAG MasterBlaster or ByteBlasterMV download cable or a microprocessor

wi th a J am or JBC Fil e

Altera  Corporation  115
APEX 20 K Pro grammabl e Log i c Dev ic e Fam ily D ata Sh eet
Revision 
History
The information contained in the APEX 20K Programmable Logic Device 
Fami ly Data Shee t version 4.3 supersedes information published in 
previous versions.
Version 4.3
APEX 20K Programmable Logic Device Family Data Sheet version 4.3 contains 
the following changes:
■Updated Figure 20.
■Updated Note (2) to Table 13.
■Updated notes to Tables 31 through 34.
Version 4.2
APEX 20K Programmable Logic Device Family Data Sheet version 4.2 contains 
the following changes:
■Updated Figure 29.
■Updated Note (1) to Figure 29.
Version 4.1
APEX 20K Programmable Logic Device Family Data Sheet version 4.1 contains 
the following changes:
■tESBWEH added to Figure 37 and Tables 39, 54, 60, 66, 72, 78, 90, 96, 
101, and 108.
■Updated EP20K300E device internal and external timing numbers in 
Tables 83 through 88.

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APEX 20K Programmable Logic Device Family Data Sheet

116 Altera Corporation