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EFM32HG350 DATASHEET
F64/F32
•ARM Cortex-M0+ CPU platform
• High Performance 32-bit processor @ up to 25 MHz
• Wake-up Interrupt Controller
•Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.6 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out
Detector, RAM and CPU retention
• 0.9 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz
oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 51 µA/MHz @ 3 V Sleep Mode
• 127 µA/MHz @ 3 V Run Mode, with code executed from flash
•64/32 KB Flash
•8/8 KB RAM
•22 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive
strength
• Configurable peripheral I/O locations
• 10 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
•6 Channel DMA Controller
•6 Channel Peripheral Reflex System (PRS) for autonomous in-
ter-peripheral signaling
•Hardware AES with 128-bit keys in 54 cycles
•Timers/Counters
• 3× 16-bit Timer/Counter
• 3×3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 1× 24-bit Real-Time Counter
• 1× 16-bit Pulse Counter
• Watchdog Timer with dedicated RC oscillator @ 50 nA
•Communication interfaces
• 2× Universal Synchronous/Asynchronous Receiv-
er/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• Triple buffered full/half-duplex operation
• Low Energy UART
• Autonomous operation with DMA in Deep Sleep
Mode
• I2C Interface with SMBus support
• Address recognition in Stop Mode
• Low Energy Universal Serial Bus (USB) Device
• Fully USB 2.0 compliant
• On-chip PHY and embedded 5V to 3.3V regulator
• Crystal-free operation
•Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 3 single ended channels/ differential channels
• On-chip temperature sensor
• Current Digital to Analog Converter
• Selectable current range between 0.05 and 64 uA
• 1× Analog Comparator
• Capacitive sensing with up to 2 inputs
• Supply Voltage Comparator
•Ultra efficient Power-on Reset and Brown-Out Detec-
tor
•Debug Interface
• 2-pin Serial Wire Debug interface
• Micro Trace Buffer (MTB)
•Pre-Programmed USB/UART Bootloader
•Temperature range -40 to 85 ºC
•Single power supply 1.98 to 3.8 V
•CSP36 package
32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4 microcontrollers for:
• Energy, gas, water and smart metering
• Health and fitness applications
• Smart accessories
• Alarm and security systems
• Industrial and home automation
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1 Ordering Information
Table 1.1 (p. 2) shows the available EFM32HG350 devices.
Table 1.1. Ordering Information
Ordering Code Flash (kB) RAM (kB) Max
Speed
(MHz)
Supply
Voltage
(V)
Temperature
(ºC)
Package
EFM32HG350F32G-B-CSP36 32 8 25 1.98 - 3.8 -40 - 85 CSP36
EFM32HG350F64G-B-CSP36 64 8 25 1.98 - 3.8 -40 - 85 CSP36
Adding the suffix 'R' to the part number (e.g. EFM32HG350F32G-B-CSP36R) denotes tape and reel.
Visit www.silabs.com for information on global distributors and representatives.
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2 System Summary
2.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination
of the powerful 32-bit ARM Cortex-M0+, innovative low energy techniques, short wake-up time from
energy saving modes, and a wide selection of peripherals, the EFM32HG microcontroller is well suited
for any battery operated application as well as other systems requiring high performance and low-energy
consumption. This section gives a short introduction to each of the modules in general terms and also
shows a summary of the configuration for the EFM32HG350 devices. For a complete feature set and
in-depth information on the modules, the reader is referred to the EFM32HG Reference Manual.
A block diagram of the EFM32HG350 is shown in Figure 2.1 (p. 3) .
Figure 2.1. Block Diagram
Clock Management Energy Management
Serial Interfaces I/ O Port s
Core and Memory
Timers and Triggers
32- bit bus
Peripheral Reflex System
ARM Cortex ™ M0+ processor
Flash
Program
Mem ory
Pulse
Counter
Watchdog
Tim er
RAM
Mem ory
General
Purpose
I/ O
Ex ternal
Interrupts
Pin
Reset
HG350F64/ F32
USART I2C
Power- on
Reset
Voltage
Regulat or
Voltage
Com parat or
Brown- out
Det ector
Tim er/
Counter
Real Tim e
Counter
Current
DAC
Low
Energy
UART™
Low
Energy
USB
High Freq
Crystal
Oscillator
Low Freq
Crystal
Oscillator
Low Freq
RC
Oscillator
Ult ra Low Freq
RC
Oscillator
High Freq
RC
Oscillator
48/ 24 MHz
Com m. RC
Oscillator
Aux High
Freq RC
Oscillator
Pin
Wakeup
Analog Interfaces
ADC
Securit y
Hardware
AES
DMA
Cont roller
Debug
Interface
w/ MTB
Analog
Com parat or
2.1.1 ARM Cortex-M0+ Core
The ARM Cortex-M0+ includes a 32-bit RISC processor which can achieve as much as 0.9 Dhrystone
MIPS/MHz. A Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep is in-
cluded as well. The EFM32 implementation of the Cortex-M0+ is described in detail in ARM Cortex-M0+
Devices Generic User Guide.
2.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface and a Micro
Trace Buffer (MTB) for data/instruction tracing.
2.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32HG microcontroller.
The flash memory is readable and writable from both the Cortex-M0+ and DMA. The flash memory is
divided into two blocks; the main block and the information block. Program code is normally written to
the main block. Additionally, the information block is available for special user data and flash lock bits.
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There is also a read-only page in the information block containing system and device calibration data.
Read and write operations are supported in the energy modes EM0 and EM1.
2.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.
This has the benefit of reducing the energy consumption and the workload of the CPU, and enables
the system to stay in low energy modes when moving for instance data from the USART to RAM or
from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA
controller licensed from ARM.
2.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32HG.
2.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32HG microcon-
trollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU
can also be used to turn off the power to unused SRAM blocks.
2.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the
EFM32HG. The CMU provides the capability to turn on and off the clock on an individual basis to all
peripheral modules in addition to enable/disable and configure the available oscillators. The high degree
of flexibility enables software to minimize energy consumption in any specific application by not wasting
power on peripherals and oscillators that are inactive.
2.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase appli-
cation reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a
software failure.
2.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module
communicate directly with each other without involving the CPU. Peripheral modules which send out
Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which
apply actions depending on the data received. The format for the Reflex signals is not given, but edge
triggers and other functionality can be applied by the PRS.
2.1.10 Low Energy USB
The unique Low Energy USB peripheral provides a full-speed USB 2.0 compliant device controller and
PHY with ultra-low current consumption. The device supports both full-speed (12MBit/s) and low speed
(1.5MBit/s) operation, and includes a dedicated USB oscillator with clock recovery mechanism for crys-
tal-free operation. No external components are required. The Low Energy Mode ensures the current
consumption is optimized and enables USB communication on a strict power budget. The USB device
includes an internal dedicated descriptor-based Scatter/Gather DMA and supports up to 3 OUT end-
points and 3 IN endpoints, in addition to endpoint 0. The on-chip PHY includes software controllable
pull-up and pull-down resistors.
2.1.11 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as
both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fast-
mode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s.
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Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system.
The interface provided to software by the I2C module, allows both fine-grained control of the transmission
process and close to automatic transfers. Automatic recognition of slave addresses is provided in all
energy modes.
2.1.12 Universal Synchronous/Asynchronous Receiver/Transmitter (US-
ART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible
serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI,
MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, IrDA and I2S devices.
2.1.13 Pre-Programmed USB/UART Bootloader
The bootloader presented in application note AN0042 is pre-programmed in the device at factory. The
bootloader enables users to program the EFM32 through a UART or a USB CDC class virtual UART
without the need for a debugger. The autobaud feature, interface and commands are described further
in the application note.
2.1.14 Low Energy Universal Asynchronous Receiver/Transmitter
(LEUART)
The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on
a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/
s. The LEUART includes all necessary hardware support to make asynchronous serial communication
possible with minimum of software intervention and energy consumption.
2.1.15 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse-
Width Modulation (PWM) output. TIMER0 also includes a Dead-Time Insertion module suitable for motor
control applications.
2.1.16 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal
oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also
available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where
most of the device is powered down.
2.1.17 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature
encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source.
The module may operate in energy mode EM0 - EM3.
2.1.18 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indi-
cating which input voltage is higher. Inputs can either be one of the selectable internal references or from
external pins. Response time and thereby also the current consumption can be configured by altering
the current supply to the comparator.
2.1.19 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can
be generated when the supply falls below or rises above a programmable threshold. Response time and
thereby also the current consumption can be configured by altering the current supply to the comparator.
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2.1.20 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits
at up to one million samples per second. The integrated input mux can select inputs from 3 external
pins and 6 internal signals.
2.1.21 Current Digital to Analog Converter (IDAC)
The current digital to analog converter can source or sink a configurable constant current, which can
be output on, or sinked from pin or ADC. The current is configurable with several ranges of various
step sizes.
2.1.22 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit. Encrypting or decrypting one
128-bit data block takes 52 HFCORECLK cycles with 128-bit keys. The AES module is an AHB slave
which enables efficient access to the data and key registers. All write accesses to the AES module must
be 32-bit operations, i.e. 8- or 16-bit operations are not supported.
2.1.23 General Purpose Input/Output (GPIO)
In the EFM32HG350, there are 22 General Purpose Input/Output (GPIO) pins, which are divided into
ports with up to 16 pins each. These pins can individually be configured as either an output or input. More
advanced configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 10 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
2.2 Configuration Summary
The features of the EFM32HG350 is a subset of the feature set described in the EFM32HG Reference
Manual. Table 2.1 (p. 6) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module Configuration Pin Connections
Cortex-M0+ Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO,
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
USB Full configuration USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA and I2S US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration with I2S and IrDA US1_TX, US1_RX, US1_CLK, US1_CS
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Module Configuration Pin Connections
LEUART0 Full configuration LEU0_TX, LEU0_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]
ACMP0 Full configuration ACMP0_CH[1:0], ACMP0_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:5]
IDAC0 Full configuration IDAC0_OUT
AES Full configuration NA
GPIO 22 pins Available pins are shown in
Table 4.3 (p. 56)
2.3 Memory Map
The EFM32HG350 memory map is shown in Figure 2.2 (p. 7) , with RAM and Flash sizes for the
largest memory configuration.
Figure 2.2. EFM32HG350 Memory Map with largest RAM and Flash sizes
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3 Electrical Characteristics
3.1 Test Conditions
3.1.1 Typical Values
The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in Table 3.2 (p. 8) , unless
otherwise specified.
3.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply volt-
age and frequencies, as defined in Table 3.2 (p. 8) , unless otherwise specified.
3.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions are
not guaranteed. Stress beyond the limits specified in Table 3.1 (p. 8) may affect the device reliability
or cause permanent damage to the device. Functional operating conditions are given in Table 3.2 (p.
8) .
Table 3.1. Absolute Maximum Ratings
Symbol Parameter Condition Min Typ Max Unit
TSTG Storage tempera-
ture range
-40 1501°C
TSMaximum soldering
temperature
Latest IPC/JEDEC J-STD-020
Standard
260 °C
VDDMAX External main sup-
ply voltage
0 3.8 V
VIOPIN Voltage on any I/O
pin
-0.3 VDD+0.3 V
1Based on programmed devices tested for 10000 hours at 150ºC. Storage temperature affects retention of preprogrammed cal-
ibration values stored in flash. Please refer to the Flash section in the Electrical Characteristics for information on flash data re-
tention for different temperatures.
3.3 General Operating Conditions
3.3.1 General Operating Conditions
Table 3.2. General Operating Conditions
Symbol Parameter Min Typ Max Unit
TAMB Ambient temperature range -40 85 °C
VDDOP Operating supply voltage 1.98 3.8 V
fAPB Internal APB clock frequency 25 MHz
fAHB Internal AHB clock frequency 25 MHz
3.3.2 Environmental
WLCSP devices can be handled and soldered using industry standard surface mount assembly tech-
niques. However, because WLCSP devices are essentially a piece of silicon and are not encapsulated
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in plastic, they are susceptible to mechanical damage and may be sensitive to light. When WLCSPs
must be used in an environment exposed to light, it may be necessary to cover the top and sides with
an opaque material.
3.4 Current Consumption
Table 3.3. Current Consumption
Symbol Parameter Condition Min Typ Max Unit
24 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V,
TAMB=25°C
148 158 µA/
MHz
24 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V,
TAMB=85°C
153 163 µA/
MHz
24 MHz USHFRCO, all periph-
eral clocks disabled, VDD= 3.0
V, TAMB=25°C
161 172 µA/
MHz
24 MHz USHFRCO, all periph-
eral clocks disabled, VDD= 3.0
V, TAMB=85°C
163 174 µA/
MHz
24 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
127 137 µA/
MHz
24 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
129 139 µA/
MHz
21 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
131 140 µA/
MHz
21 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
134 143 µA/
MHz
14 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
134 143 µA/
MHz
14 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
137 145 µA/
MHz
11 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
136 144 µA/
MHz
11 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
139 148 µA/
MHz
6.6 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
142 150 µA/
MHz
6.6 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
146 154 µA/
MHz
IEM0
EM0 current. No
prescaling. Running
prime number cal-
culation code from
Flash.
1.2 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
184 196 µA/
MHz
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Symbol Parameter Condition Min Typ Max Unit
1.2 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
194 208 µA/
MHz
24 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V,
TAMB=25°C
64 68 µA/
MHz
24 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V,
TAMB=85°C
67 71 µA/
MHz
24 MHz USHFRCO, all periph-
eral clocks disabled, VDD= 3.0
V, TAMB=25°C
85 91 µA/
MHz
24 MHz USHFRCO, all periph-
eral clocks disabled, VDD= 3.0
V, TAMB=85°C
86 92 µA/
MHz
24 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
51 55 µA/
MHz
24 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
52 56 µA/
MHz
21 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
53 57 µA/
MHz
21 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
54 58 µA/
MHz
14 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
56 59 µA/
MHz
14 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
57 61 µA/
MHz
11 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
58 61 µA/
MHz
11 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
59 63 µA/
MHz
6.6 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
64 68 µA/
MHz
6.6 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
67 71 µA/
MHz
1.2 MHz HFRCO. all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
106 114 µA/
MHz
IEM1 EM1 current
1.2 MHz HFRCO. all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
114 126 µA/
MHz
IEM2 EM2 current EM2 current with RTC
prescaled to 1 Hz, 32.768
0.9 1.35 µA
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Symbol Parameter Condition Min Typ Max Unit
kHz LFRCO, VDD= 3.0 V,
TAMB=25°C
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=85°C
1.6 3.50 µA
EM3 current (ULFRCO en-
abled, LFRCO/LFXO disabled),
VDD= 3.0 V, TAMB=25°C
0.6 0.90 µA
IEM3 EM3 current
EM3 current (ULFRCO en-
abled, LFRCO/LFXO disabled),
VDD= 3.0 V, TAMB=85°C
1.2 2.65 µA
VDD= 3.0 V, TAMB=25°C 0.02 0.035 µA
IEM4 EM4 current
VDD= 3.0 V, TAMB=85°C 0.18 0.480 µA
3.4.1 EM0 Current Consumption
Figure 3.1. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 24 MHz
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Figure 3.2. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 21 MHz
Figure 3.3. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 14 MHz
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Figure 3.4. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 11 MHz
Figure 3.5. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 6.6 MHz
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3.4.2 EM1 Current Consumption
Figure 3.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 24 MHz
Figure 3.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 21 MHz
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Figure 3.8. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 14 MHz
Figure 3.9. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 11 MHz
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Figure 3.10. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 6.6 MHz
3.4.3 EM2 Current Consumption
Figure 3.11. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO.
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3.4.4 EM3 Current Consumption
Figure 3.12. EM3 current consumption.
3.4.5 EM4 Current Consumption
Figure 3.13. EM4 current consumption.
3.5 Transition between Energy Modes
The transition times are measured from the trigger to the first clock edge in the CPU.
Table 3.4. Energy Modes Transitions
Symbol Parameter Min Typ Max Unit
tEM10 Transition time from EM1 to EM0 0 HF-
CORE-
CLK
cycles
tEM20 Transition time from EM2 to EM0 2 µs
tEM30 Transition time from EM3 to EM0 2 µs
tEM40 Transition time from EM4 to EM0 163 µs
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3.6 Power Management
The EFM32HG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with
optional filter) at the PCB level. For practical schematic recommendations, please see the application
note, "AN0002 EFM32 Hardware Design Considerations".
Table 3.5. Power Management
Symbol Parameter Condition Min Typ Max Unit
EM0 1.74 1.96 V
VBODextthr-
BOD threshold on
falling external sup-
ply voltage EM2 1.71 1.86 1.98 V
VBODextthr+ BOD threshold on
rising external sup-
ply voltage
1.85 V
tRESET Delay from reset
is released until
program execution
starts
Applies to Power-on Reset,
Brown-out Reset and pin reset.
163 µs
CDECOUPLE Voltage regulator
decoupling capaci-
tor.
X5R capacitor recommended.
Apply between DECOUPLE pin
and GROUND
1 µF
CUSB_VREGO USB voltage regu-
lator out decoupling
capacitor.
X5R capacitor recommended.
Apply between USB_VREGO
pin and GROUND
1 µF
CUSB_VREGI USB voltage regula-
tor in decoupling ca-
pacitor.
X5R capacitor recommended.
Apply between USB_VREGI
pin and GROUND
4.7 µF
3.7 Flash
Table 3.6. Flash
Symbol Parameter Condition Min Typ Max Unit
ECFLASH Flash erase cycles
before failure
20000 cycles
TAMB<150°C 10000 h
TAMB<85°C 10 yearsRETFLASH Flash data retention
TAMB<70°C 20 years
tW_PROG Word (32-bit) pro-
gramming time
20 µs
tP_ERASE Page erase time 20 20.4 20.8 ms
tD_ERASE Device erase time 40 40.8 41.6 ms
IERASE Erase current 71mA
IWRITE Write current 71mA
VFLASH Supply voltage dur-
ing flash erase and
write
1.98 3.8 V
1Measured at 25°C
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3.8 General Purpose Input Output
Table 3.7. GPIO
Symbol Parameter Condition Min Typ Max Unit
VIOIL Input low voltage 0.30VDD V
VIOIH Input high voltage 0.70VDD V
Sourcing 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.80VDD V
Sourcing 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.90VDD V
Sourcing 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.85VDD V
Sourcing 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.90VDD V
Sourcing 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.75VDD V
Sourcing 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.85VDD V
Sourcing 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.60VDD V
VIOOH
Output high volt-
age (Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
Sourcing 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.80VDD V
Sinking 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.20VDD V
Sinking 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.10VDD V
Sinking 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.10VDD V
Sinking 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.05VDD V
Sinking 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.30VDD V
Sinking 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.20VDD V
VIOOL
Output low voltage
(Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
Sinking 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.35VDD V
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Symbol Parameter Condition Min Typ Max Unit
Sinking 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.25VDD V
IIOLEAK Input leakage cur-
rent
High Impedance IO connected
to GROUND or Vdd
±0.1 ±40 nA
RPU I/O pin pull-up resis-
tor
40 kOhm
RPD I/O pin pull-down re-
sistor
40 kOhm
RIOESD Internal ESD series
resistor
200 Ohm
tIOGLITCH Pulse width of puls-
es to be removed
by the glitch sup-
pression filter
10 50 ns
GPIO_Px_CTRL DRIVEMODE
= LOWEST and load capaci-
tance CL=12.5-25pF.
20+0.1CL 250 ns
tIOOF Output fall time
GPIO_Px_CTRL DRIVEMODE
= LOW and load capacitance
CL=350-600pF
20+0.1CL 250 ns
VIOHYST I/O pin hysteresis
(VIOTHR+ - VIOTHR-)
VDD = 1.98 - 3.8 V 0.1VDD V
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Figure 3.14. Typical Low-Level Output Current, 2V Supply Voltage
0.0 0.5 1.0 1.5 2.0
Low- Level Out put Voltage [V]
0.00
0.05
0.10
0.15
0.20
Low- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0
Low- Level Out put Voltage [V]
0
1
2
3
4
5
Low- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0
Low- Level Out put Voltage [V]
0
5
10
15
20
Low- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0
Low- Level Out put Voltage [V]
0
5
10
15
20
25
30
35
40
45
Low- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.15. Typical High-Level Output Current, 2V Supply Voltage
0.0 0.5 1.0 1.5 2.0
High- Level Out put Volt age [V]
–0.20
–0.15
–0.10
–0.05
0.00
High- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0
High- Level Out put Volt age [V]
–2.5
–2.0
–1.5
–1.0
–0.5
0.0
High- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0
High- Level Out put Volt age [V]
–20
–15
–10
–5
0
High- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0
High- Level Out put Volt age [V]
–50
–40
–30
–20
–10
0
High- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.16. Typical Low-Level Output Current, 3V Supply Voltage
0.0 0.5 1.0 1.5 2 .0 2.5 3.0
Low- Level Out put Voltage [V]
0.0
0.1
0.2
0.3
0.4
0.5
Low- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2 .0 2.5 3.0
Low- Level Out put Voltage [V]
0
2
4
6
8
10
Low- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2 .0 2.5 3.0
Low- Level Out put Voltage [V]
0
5
10
15
20
25
30
35
40
Low- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2 .0 2.5 3.0
Low- Level Out put Voltage [V]
0
10
20
30
40
50
Low- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.17. Typical High-Level Output Current, 3V Supply Voltage
0.0 0.5 1.0 1.5 2 .0 2.5 3.0
High- Level Out put Volt age [V]
–0.5
–0.4
–0.3
–0.2
–0.1
0.0
High- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2 .0 2.5 3.0
High- Level Out put Volt age [V]
–6
–5
–4
–3
–2
–1
0
High- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2 .0 2.5 3.0
High- Level Out put Volt age [V]
–50
–40
–30
–20
–10
0
High- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2 .0 2.5 3.0
High- Level Out put Volt age [V]
–50
–40
–30
–20
–10
0
High- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.18. Typical Low-Level Output Current, 3.8V Supply Voltage
0.0 0.5 1.0 1.5 2 .0 2.5 3.0 3.5
Low- Level Out put Voltage [V]
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Low- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2 .0 2.5 3.0 3.5
Low- Level Out put Voltage [V]
0
2
4
6
8
10
12
14
Low- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2 .0 2.5 3.0 3.5
Low- Level Out put Voltage [V]
0
10
20
30
40
50
Low- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2 .0 2.5 3.0 3.5
Low- Level Out put Voltage [V]
0
10
20
30
40
50
Low- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.19. Typical High-Level Output Current, 3.8V Supply Voltage
0.0 0.5 1.0 1.5 2 .0 2.5 3.0 3.5
High- Level Out put Volt age [V]
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0.0
High- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2 .0 2.5 3.0 3.5
High- Level Out put Volt age [V]
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
High- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2 .0 2.5 3.0 3.5
High- Level Out put Volt age [V]
–50
–40
–30
–20
–10
0
High- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2 .0 2.5 3.0 3.5
High- Level Out put Volt age [V]
–50
–40
–30
–20
–10
0
High- Level Out put Current [m A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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3.9 Oscillators
3.9.1 LFXO
Table 3.8. LFXO
Symbol Parameter Condition Min Typ Max Unit
fLFXO Supported nominal
crystal frequency
32.768 kHz
ESRLFXO Supported crystal
equivalent series re-
sistance (ESR)
30 120 kOhm
CLFXOL Supported crystal
external load range
5 25 pF
ILFXO Current consump-
tion for core and
buffer after startup.
ESR=30 kOhm, CL=10 pF,
LFXOBOOST in CMU_CTRL is
1
190 nA
tLFXO Start- up time. ESR=30 kOhm, CL=10 pF,
40% - 60% duty cycle has
been reached, LFXOBOOST in
CMU_CTRL is 1
1100 ms
For safe startup of a given crystal, the Configurator tool in Simplicity Studio contains a tool to help
users configure both load capacitance and software settings for using the LFXO. For details regarding
the crystal configuration, the reader is referred to application note "AN0016 EFM32 Oscillator Design
Consideration".
3.9.2 HFXO
Table 3.9. HFXO
Symbol Parameter Condition Min Typ Max Unit
fHFXO Supported frequen-
cy, any mode
4 25 MHz
Crystal frequency 25 MHz 30 100 Ohm
ESRHFXO
Supported crystal
equivalent series re-
sistance (ESR) Crystal frequency 4 MHz 400 1500 Ohm
gmHFXO The transconduc-
tance of the HFXO
input transistor at
crystal startup
HFXOBOOST in CMU_CTRL
equals 0b11
20 mS
CHFXOL Supported crystal
external load range
5 25 pF
4 MHz: ESR=400 Ohm,
CL=20 pF, HFXOBOOST in
CMU_CTRL equals 0b11
85 µA
IHFXO
Current consump-
tion for HFXO after
startup 25 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
165 µA
tHFXO Startup time 25 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
785 µs
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3.9.3 LFRCO
Table 3.10. LFRCO
Symbol Parameter Condition Min Typ Max Unit
fLFRCO Oscillation frequen-
cy , VDD= 3.0 V,
TAMB=25°C
31.3 32.768 34.3 kHz
tLFRCO Startup time not in-
cluding software
calibration
150 µs
ILFRCO Current consump-
tion
361 492 nA
TUNESTEPL-
FRCO
Frequency step
for LSB change in
TUNING value
202 Hz
Figure 3.20. Calibrated LFRCO Frequency vs Temperature and Supply Voltage
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Vdd [V]
30
32
34
36
38
40
42
Frequency [kHz]
- 40°C
25°C
85°C
–40
–15
5
25
45
65
85
Tem perat ure [°C]
30
32
34
36
38
40
42
Frequency [kHz]
2.0 V
3.0 V
3.8 V
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3.9.4 HFRCO
Table 3.11. HFRCO
Symbol Parameter Condition Min Typ Max Unit
24 MHz frequency band 23.28 24.0 24.72 MHz
21 MHz frequency band 20.37 21.0 21.63 MHz
14 MHz frequency band 13.58 14.0 14.42 MHz
11 MHz frequency band 10.67 11.0 11.33 MHz
7 MHz frequency band 6.40 6.60 6.80 MHz
fHFRCO
Oscillation frequen-
cy, VDD= 3.0 V,
TAMB=25°C
1 MHz frequency band 1.15 1.20 1.25 MHz
tHFRCO_settling Settling time after
start-up
fHFRCO = 14 MHz 0.6 Cycles
fHFRCO = 24 MHz 158 184 µA
fHFRCO = 21 MHz 143 175 µA
fHFRCO = 14 MHz 113 140 µA
fHFRCO = 11 MHz 101 125 µA
fHFRCO = 6.6 MHz 84 105 µA
IHFRCO
Current consump-
tion
fHFRCO = 1.2 MHz 27 40 µA
24 MHz frequency band 66.81 kHz
21 MHz frequency band 52.81 kHz
14 MHz frequency band 36.91 kHz
11 MHz frequency band 30.11 kHz
7 MHz frequency band 18.01 kHz
TUNESTEPH-
FRCO
Frequency step
for LSB change in
TUNING value
1 MHz frequency band 3.4 kHz
1The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment
range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature. By
using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the
frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 21 MHz across operating conditions.
Figure 3.21. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Vdd [V]
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
5
25
45
65
85
Tem perat ure [°C]
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
Frequency [MHz]
2.0 V
3.0 V
3.8 V
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Figure 3.22. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Vdd [V]
6.30
6.35
6.40
6.45
6.50
6.55
6.60
6.65
6.70
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
5
25
45
65
85
Tem perat ure [°C]
6.30
6.35
6.40
6.45
6.50
6.55
6.60
6.65
6.70
Frequency [MHz]
2.0 V
3.0 V
3.8 V
Figure 3.23. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Vdd [V]
10.6
10.7
10.8
10.9
11.0
11.1
11.2
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
5
25
45
65
85
Tem perat ure [°C]
10.6
10.7
10.8
10.9
11.0
11.1
11.2
Frequency [MHz]
2.0 V
3.0 V
3.8 V
Figure 3.24. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Vdd [V]
13.4
13.5
13.6
13.7
13.8
13.9
14.0
14.1
14.2
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
5
25
45
65
85
Tem perat ure [°C]
13.4
13.5
13.6
13.7
13.8
13.9
14.0
14.1
14.2
Frequency [MHz]
2.0 V
3.0 V
3.8 V
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Figure 3.25. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Vdd [V]
20.2
20.4
20.6
20.8
21.0
21.2
Frequency [MHz]
- 40°C
25°C
85°C
–40
–15
5
25
45
65
85
Tem perat ure [°C]
20.2
20.4
20.6
20.8
21.0
21.2
Frequency [MHz]
2.0 V
3.0 V
3.8 V
3.9.5 AUXHFRCO
Table 3.12. AUXHFRCO
Symbol Parameter Condition Min Typ Max Unit
21 MHz frequency band 20.37 21.0 21.63 MHz
14 MHz frequency band 13.58 14.0 14.42 MHz
11 MHz frequency band 10.67 11.0 11.33 MHz
7 MHz frequency band 6.40 6.60 6.80 MHz
fAUXHFRCO
Oscillation frequen-
cy, VDD= 3.0 V,
TAMB=25°C
1 MHz frequency band 1.15 1.20 1.25 MHz
tAUXHFRCO_settling
Settling time after
start-up
fAUXHFRCO = 14 MHz 0.6 Cycles
21 MHz frequency band 52.8 kHz
14 MHz frequency band 36.9 kHz
11 MHz frequency band 30.1 kHz
7 MHz frequency band 18.0 kHz
TUNESTEPAUX-
HFRCO
Frequency step
for LSB change in
TUNING value
1 MHz frequency band 3.4 kHz
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3.9.6 USHFRCO
Table 3.13. USHFRCO
Symbol Parameter Condition Min Typ Max Unit
No Clock Recovery, Full Tem-
perature and Supply Range, 48
MHz band
47.10 48.00 48.90 MHz
No Clock Recovery, Full Tem-
perature and Supply Range, 24
MHz band
23.73 24.00 24.32 MHz
No Clock Recovery, 25°C,
3.3V, 48 MHz band
47.50 48.00 48.50 MHz
No Clock Recovery, 25°C,
3.3V, 24 MHz band
23.86 24.00 24.16 MHz
fUSHFRCO
Oscillation frequen-
cy
USB Active with Clock Recov-
ery, Full Temperature and Sup-
ply Range
47.88 48.00 48.12 MHz
TCUSHFRCO Temperature coeffi-
cient
3.3V 0.0175 %/°C
VCUSHFRCO Supply voltage co-
efficient
25°C 0.0045 %/V
fUSHFRCO = 48 MHz 1.21 1.36 1.48 mA
IUSHFRCO
Current consump-
tion fUSHFRCO = 24 MHz 0.81 0.92 1.02 mA
3.9.7 ULFRCO
Table 3.14. ULFRCO
Symbol Parameter Condition Min Typ Max Unit
fULFRCO Oscillation frequen-
cy
25°C, 3V 0.70 1.75 kHz
TCULFRCO Temperature coeffi-
cient
0.05 %/°C
VCULFRCO Supply voltage co-
efficient
-18.2 %/V
3.10 Analog Digital Converter (ADC)
Table 3.15. ADC
Symbol Parameter Condition Min Typ Max Unit
Single ended 0 VREF V
VADCIN Input voltage range
Differential -VREF/2 VREF/2 V
VADCREFIN Input range of exter-
nal reference volt-
age, single ended
and differential
1.25 VDD V
VADCREFIN_CH7 Input range of ex-
ternal negative ref-
erence voltage on
channel 7
See VADCREFIN 0 VDD - 1.1 V
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Symbol Parameter Condition Min Typ Max Unit
VADCREFIN_CH6 Input range of ex-
ternal positive ref-
erence voltage on
channel 6
See VADCREFIN 0.625 VDD V
VADCCMIN Common mode in-
put range
0 VDD V
IADCIN Input current 2pF sampling capacitors <100 nA
CMRRADC Analog input com-
mon mode rejection
ratio
65 dB
1 MSamples/s, 12 bit, external
reference
392 510 µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b00
67 µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b01
63 µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b10
64 µA
IADC
Average active cur-
rent
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b11
244 µA
IADCREF Current consump-
tion of internal volt-
age reference
Internal voltage reference 65 µA
CADCIN Input capacitance 2 pF
RADCIN Input ON resistance 1 MOhm
RADCFILT Input RC filter resis-
tance
10 kOhm
CADCFILT Input RC filter/de-
coupling capaci-
tance
250 fF
fADCCLK ADC Clock Fre-
quency
13 MHz
6 bit 7 ADC-
CLK
Cycles
8 bit 11 ADC-
CLK
Cycles
tADCCONV Conversion time
12 bit 13 ADC-
CLK
Cycles
tADCACQ Acquisition time Programmable 1 256 ADC-
CLK
Cycles
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Symbol Parameter Condition Min Typ Max Unit
tADCACQVDD3 Required acquisi-
tion time for VDD/3
reference
2 µs
Startup time of ref-
erence generator
and ADC core in
NORMAL mode
5 µs
tADCSTART Startup time of ref-
erence generator
and ADC core in
KEEPADCWARM
mode
1 µs
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
59 dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
63 dB
1 MSamples/s, 12 bit, single
ended, VDD reference
65 dB
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference
60 dB
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference
65 dB
1 MSamples/s, 12 bit, differen-
tial, 5V reference
54 dB
1 MSamples/s, 12 bit, differen-
tial, VDD reference
67 dB
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference
69 dB
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
62 dB
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
63 dB
200 kSamples/s, 12 bit, single
ended, VDD reference
67 dB
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
63 dB
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
66 dB
200 kSamples/s, 12 bit, differ-
ential, 5V reference
66 dB
200 kSamples/s, 12 bit, differ-
ential, VDD reference
63 66 dB
SNRADC
Signal to Noise Ra-
tio (SNR)
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
70 dB
SINADADC
SIgnal-to-Noise
And Distortion-ratio
(SINAD)
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
58 dB
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Symbol Parameter Condition Min Typ Max Unit
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
62 dB
1 MSamples/s, 12 bit, single
ended, VDD reference
64 dB
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference
60 dB
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference
64 dB
1 MSamples/s, 12 bit, differen-
tial, 5V reference
54 dB
1 MSamples/s, 12 bit, differen-
tial, VDD reference
66 dB
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference
68 dB
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
61 dB
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
65 dB
200 kSamples/s, 12 bit, single
ended, VDD reference
66 dB
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
63 dB
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
66 dB
200 kSamples/s, 12 bit, differ-
ential, 5V reference
66 dB
200 kSamples/s, 12 bit, differ-
ential, VDD reference
62 66 dB
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
69 dB
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
64 dBc
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
76 dBc
1 MSamples/s, 12 bit, single
ended, VDD reference
73 dBc
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference
66 dBc
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference
77 dBc
1 MSamples/s, 12 bit, differen-
tial, VDD reference
76 dBc
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference
75 dBc
SFDRADC
Spurious-Free Dy-
namic Range (SF-
DR)
1 MSamples/s, 12 bit, differen-
tial, 5V reference
69 dBc
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Symbol Parameter Condition Min Typ Max Unit
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
75 dBc
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
75 dBc
200 kSamples/s, 12 bit, single
ended, VDD reference
76 dBc
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
79 dBc
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
79 dBc
200 kSamples/s, 12 bit, differ-
ential, 5V reference
78 dBc
200 kSamples/s, 12 bit, differ-
ential, VDD reference
68 79 dBc
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
79 dBc
After calibration, single ended -4 0.3 4 mV
VADCOFFSET Offset voltage
After calibration, differential 0.3 mV
-1.92 mV/°C
TGRADADCTH
Thermometer out-
put gradient -6.3 ADC
Codes/
°C
DNLADC Differential non-lin-
earity (DNL)
VDD= 3.0 V, external 2.5V ref-
erence
-1 ±0.7 4 LSB
INLADC Integral non-linear-
ity (INL), End point
method
±1.6 ±3 LSB
MCADC No missing codes 11.999112 bits
Internal 1.25V, VDD = 3V, 25°C 1.248 1.254 1.262 V
Internal 1.25V, Full tempera-
ture and supply range
1.188 1.254 1.302 V
Internal 2.5V, VDD = 3V, 25°C 2.492 2.506 2.520 V
VREFADC
ADC Internal Volt-
age Reference
Internal 2.5V, Full temperature
and supply range
2.402 2.506 2.600 V
1On the average every ADC will have one missing code, most likely to appear around 2048 ± n*512 where n can be a value in
the set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonic
at all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that is
missing, the neighbour codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full scale
input for chips that have the missing code issue.
The integral non-linearity (INL) and differential non-linearity parameters are explained in Figure 3.26 (p.
37) and Figure 3.27 (p. 37) , respectively.
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Figure 3.26. Integral Non-Linearity (INL)
Ideal t ransfer
curve
Digit al ouput code
Analog Input
INL= |[(VD- VSS
)/ VLSBIDEAL] - D| where 0 < D < 2N - 1
0
1
2
3
4092
4093
4094
4095
VOFFSET
Act ual ADC
tranfer function
before offset and
gain correction Act ual ADC
tranfer function
after offset and
gain correction
INL Error
(End Point INL)
Figure 3.27. Differential Non-Linearity (DNL)
Ideal transfer
curve
Digital
ouput
code
Analog Input
DNL= |[(VD+ 1 - VD)/ VLSBIDEAL] - 1| where 0 < D < 2N - 2
0
1
2
3
4092
4093
4094
4095
Act ual t ransfer
function wit h one
missing code.
4
5
Full Scale Range
0.5
LSB
Ideal Code Cent er
Ideal 50%
Transit ion Point
Ideal spacing
bet ween t wo
adjacent codes
VLSBIDEAL= 1 LSB
Code widt h = 2 LSB
DNL= 1 LSB
Example: Adjacent
input value VD+ 1
corrresponds t o digital
output code D+ 1
Example: Input value
VD cor rresponds to
digital output code D
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3.10.1 Typical performance
Figure 3.28. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C
1.25V Reference 2.5V Reference
2XVDDVSS Reference 5VDIFF Reference
VDD Reference
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Figure 3.29. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference 2.5V Reference
2XVDDVSS Reference 5VDIFF Reference
VDD Reference
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Figure 3.30. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference 2.5V Reference
2XVDDVSS Reference 5VDIFF Reference
VDD Reference
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Figure 3.31. ADC Absolute Offset, Common Mode = Vdd /2
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Vdd (V)
–4
–3
–2
–1
0
1
2
3
4
5
Act ual Offset [LSB]
Vref= 1V25
Vref= 2V5
Vref= 2XVDDVSS
Vref= 5VDIFF
Vref= VDD
Offset vs Supply Voltage, Temp = 25°C
–40 –15 5 25 45 65 8 5
Tem p (C)
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
Act ual Offset [LSB]
VRef= 1V25
VRef= 2V5
VRef= 2XVDDVSS
VRef= 5VDIFF
VRef= VDD
Offset vs Temperature, Vdd = 3V
Figure 3.32. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V
–40 –15 5 25 45 65 8 5
Tem perat ure [°C]
63
64
65
66
67
68
69
70
71
SNR [dB]
1V25
2V5
Vdd
5VDIFF
2XVDDVSS
Signal to Noise Ratio (SNR)
–40 –15 5 25 45 65 8 5
Tem perat ure [°C]
78.0
78.2
78.4
78.6
78.8
79.0
79.2
79.4
SFDR [dB]
1V25
2V5
Vdd
5VDIFF
2XVDDVSS
Spurious-Free Dynamic Range (SFDR)
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Figure 3.33. ADC Temperature sensor readout
–40
–15
5
25
45
65
85
Tem perat ure [°C]
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
Sensor readout
Vdd = 2.0
Vdd = 3.0
Vdd = 3.8
3.11 Current Digital Analog Converter (IDAC)
Table 3.16. IDAC Range 0 Source
Symbol Parameter Condition Min Typ Max Unit
EM0, default settings 13.0 µA
IIDAC
Active current with
STEPSEL=0x10 Duty-cycled 10 nA
I0x10 Nominal IDAC out-
put current with
STEPSEL=0x10
0.85 µA
ISTEP Step size 0.05 µA
IDCurrent drop at high
impedance load
VIDAC_OUT = VDD - 100mV 0.79 %
TCIDAC Temperature coeffi-
cient
VDD = 3.0V, STEPSEL=0x10 0.3 nA/°C
VCIDAC Voltage coefficient T = 25 °C, STEPSEL=0x10 11.7 nA/V
Table 3.17. IDAC Range 0 Sink
Symbol Parameter Condition Min Typ Max Unit
IIDAC Active current with
STEPSEL=0x10
EM0, default settings 15.1 µA
I0x10 Nominal IDAC out-
put current with
STEPSEL=0x10
0.85 µA
ISTEP Step size 0.05 µA
IDCurrent drop at high
impedance load
VIDAC_OUT = 200 mV 0.30 %
TCIDAC Temperature coeffi-
cient
VDD = 3.0 V, STEPSEL=0x10 0.2 nA/°C
VCIDAC Voltage coefficient T = 25 °C, STEPSEL=0x10 12.5 nA/V
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Table 3.18. IDAC Range 1 Source
Symbol Parameter Condition Min Typ Max Unit
EM0, default settings 14.4 µA
IIDAC
Active current with
STEPSEL=0x10 Duty-cycled 10 nA
I0x10 Nominal IDAC out-
put current with
STEPSEL=0x10
3.2 µA
ISTEP Step size 0.1 µA
IDCurrent drop at high
impedance load
VIDAC_OUT = VDD - 100mV 0.75 %
TCIDAC Temperature coeffi-
cient
VDD = 3.0 V, STEPSEL=0x10 0.7 nA/°C
VCIDAC Voltage coefficient T = 25 °C, STEPSEL=0x10 38.4 nA/V
Table 3.19. IDAC Range 1 Sink
Symbol Parameter Condition Min Typ Max Unit
IIDAC Active current with
STEPSEL=0x10
EM0, default settings 19.4 µA
I0x10 Nominal IDAC out-
put current with
STEPSEL=0x10
3.2 µA
ISTEP Step size 0.1 µA
IDCurrent drop at high
impedance load
VIDAC_OUT = 200 mV 0.32 %
TCIDAC Temperature coeffi-
cient
VDD = 3.0 V, STEPSEL=0x10 0.7 nA/°C
VCIDAC Voltage coefficient T = 25 °C, STEPSEL=0x10 40.9 nA/V
Table 3.20. IDAC Range 2 Source
Symbol Parameter Condition Min Typ Max Unit
EM0, default settings 17.3 µA
IIDAC
Active current with
STEPSEL=0x10 Duty-cycled 10 nA
I0x10 Nominal IDAC out-
put current with
STEPSEL=0x10
8.5 µA
ISTEP Step size 0.5 µA
IDCurrent drop at high
impedance load
VIDAC_OUT = VDD - 100mV 1.22 %
TCIDAC Temperature coeffi-
cient
VDD = 3.0 V, STEPSEL=0x10 2.8 nA/°C
VCIDAC Voltage coefficient T = 25 °C, STEPSEL=0x10 96.6 nA/V
Table 3.21. IDAC Range 2 Sink
Symbol Parameter Condition Min Typ Max Unit
IIDAC Active current with
STEPSEL=0x10
EM0, default settings 29.3 µA
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Symbol Parameter Condition Min Typ Max Unit
I0x10 Nominal IDAC out-
put current with
STEPSEL=0x10
8.5 µA
ISTEP Step size 0.5 µA
IDCurrent drop at high
impedance load
VIDAC_OUT = 200 mV 0.62 %
TCIDAC Temperature coeffi-
cient
VDD = 3.0 V, STEPSEL=0x10 2.8 nA/°C
VCIDAC Voltage coefficient T = 25 °C, STEPSEL=0x10 94.4 nA/V
Table 3.22. IDAC Range 3 Source
Symbol Parameter Condition Min Typ Max Unit
EM0, default settings 18.7 µA
IIDAC
Active current with
STEPSEL=0x10 Duty-cycled 10 nA
I0x10 Nominal IDAC out-
put current with
STEPSEL=0x10
33.9 µA
ISTEP Step size 2.0 µA
IDCurrent drop at high
impedance load
VIDAC_OUT = VDD - 100 mV 3.54 %
TCIDAC Temperature coeffi-
cient
VDD = 3.0 V, STEPSEL=0x10 10.9 nA/°C
VCIDAC Voltage coefficient T = 25 °C, STEPSEL=0x10 159.5 nA/V
Table 3.23. IDAC Range 3 Sink
Symbol Parameter Condition Min Typ Max Unit
IIDAC Active current with
STEPSEL=0x10
EM0, default settings 62.5 µA
I0x10 Nominal IDAC out-
put current with
STEPSEL=0x10
34.1 µA
ISTEP Step size 2.0 µA
IDCurrent drop at high
impedance load
VIDAC_OUT = 200 mV 1.75 %
TCIDAC Temperature coeffi-
cient
VDD = 3.0 V, STEPSEL=0x10 10.9 nA/°C
VCIDAC Voltage coefficient T = 25 °C, STEPSEL=0x10 148.6 nA/V
Table 3.24. IDAC
Symbol Parameter Min Typ Max Unit
tIDACSTART Start-up time, from enabled to output settled 40 µs
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Figure 3.34. IDAC Source Current as a function of voltage on IDAC_OUT
–2.0
–1.5
–1.0
–0.5
0.0
V(IDAC_OUT) - Vdd [V]
90
91
92
93
94
95
96
97
98
99
100
101
Percent age of nominal current [%]
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
Range 0
–2.0
–1.5
–1.0
–0.5
0.0
V(IDAC_OUT) - Vdd [V]
90
91
92
93
94
95
96
97
98
99
100
101
Percent age of nominal current [%]
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
Range 1
–2.0
–1.5
–1.0
–0.5
0.0
V(IDAC_OUT) - Vdd [V]
90
91
92
93
94
95
96
97
98
99
100
101
Percent age of nominal current [%]
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
Range 2
–2.0
–1.5
–1.0
–0.5
0.0
V(IDAC_OUT) - Vdd [V]
90
91
92
93
94
95
96
97
98
99
100
101
Percent age of nominal current [%]
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
Range 3
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Figure 3.35. IDAC Sink Current as a function of voltage from IDAC_OUT
0.0
0.5
1.0
1.5
2.0
V(IDAC_OUT) [V]
95
96
97
98
99
100
101
Percent age of nominal current [%]
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
Range 0
0.0
0.5
1.0
1.5
2.0
V(IDAC_OUT) [V]
95
96
97
98
99
100
101
Percent age of nominal current [%]
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
Range 1
0.0
0.5
1.0
1.5
2.0
V(IDAC_OUT) [V]
95
96
97
98
99
100
101
Percent age of nominal current [%]
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
Range 2
0.0
0.5
1.0
1.5
2.0
V(IDAC_OUT) [V]
95
96
97
98
99
100
101
Percent age of nominal current [%]
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
Range 3
Figure 3.36. IDAC linearity
0
5
10
15
20
25
30
St ep
0
1
2
3
4
5
Idd [uA]
Range 0
Range 1
0
5
10
15
20
25
30
St ep
0
10
20
30
40
50
60
70
Idd [uA]
Range 2
Range 3
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3.12 Analog Comparator (ACMP)
Table 3.25. ACMP
Symbol Parameter Condition Min Typ Max Unit
VACMPIN Input voltage range 0 VDD V
VACMPCM ACMP Common
Mode voltage range
0 VDD V
BIASPROG=0b0000, FULL-
BIAS=0 and HALFBIAS=1 in
ACMPn_CTRL register
0.1 0.4 µA
BIASPROG=0b1111, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
2.87 15 µA
IACMP Active current
BIASPROG=0b1111, FULL-
BIAS=1 and HALFBIAS=0 in
ACMPn_CTRL register
195 520 µA
Internal voltage reference off.
Using external voltage refer-
ence
0 µA
IACMPREF
Current consump-
tion of internal volt-
age reference
Internal voltage reference 5 µA
VACMPOFFSET Offset voltage BIASPROG= 0b1010, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
-12 0 12 mV
VACMPHYST ACMP hysteresis Programmable 17 mV
CSRESSEL=0b00 in
ACMPn_INPUTSEL
40 kOhm
CSRESSEL=0b01 in
ACMPn_INPUTSEL
70 kOhm
CSRESSEL=0b10 in
ACMPn_INPUTSEL
101 kOhm
RCSRES
Capacitive Sense
Internal Resistance
CSRESSEL=0b11 in
ACMPn_INPUTSEL
132 kOhm
tACMPSTART Startup time 10 µs
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference
as given in Equation 3.1 (p. 47) . IACMPREF is zero if an external voltage reference is used.
Total ACMP Active Current
IACMPTOTAL = IACMP + IACMPREF (3.1)
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Figure 3.37. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1
048 12
ACMP_CTRL_BIASPROG
0.0
0.5
1.0
1.5
2.0
2.5
Current [uA]
Current consumption, HYSTSEL = 4
0
2
4
6
8
10
12
14
ACMP_CTRL_BIASPROG
0
5
10
15
20
Response Time [us]
HYSTSEL= 0
HYSTSEL= 2
HYSTSEL= 4
HYSTSEL= 6
Response time , Vcm =
1.25V, CP+ to CP- = 100mV
012 3 4 5 67
ACMP_CTRL_HYSTSEL
0
20
40
60
80
100
Hysteresis [m V]
BIASPROG= 0.0
BIASPROG= 4.0
BIASPROG= 8.0
BIASPROG= 12.0
Hysteresis
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3.13 Voltage Comparator (VCMP)
Table 3.26. VCMP
Symbol Parameter Condition Min Typ Max Unit
VVCMPIN Input voltage range VDD V
VVCMPCM VCMP Common
Mode voltage range
VDD V
BIASPROG=0b0000 and
HALFBIAS=1 in VCMPn_CTRL
register
0.2 0.8 µA
IVCMP Active current
BIASPROG=0b1111 and
HALFBIAS=0 in VCMPn_CTRL
register. LPREF=0.
22 35 µA
tVCMPREF Startup time refer-
ence generator
NORMAL 10 µs
Single ended 10 mV
VVCMPOFFSET Offset voltage
Differential 10 mV
VVCMPHYST VCMP hysteresis 17 mV
tVCMPSTART Startup time 10 µs
The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in
accordance with the following equation:
VCMP Trigger Level as a Function of Level Setting
VDD Trigger Level=1.667V+0.034 ×TRIGLEVEL (3.2)
3.14 I2C
Table 3.27. I2C Standard-mode (Sm)
Symbol Parameter Min Typ Max Unit
fSCL SCL clock frequency 0 1001kHz
tLOW SCL clock low time 4.7 µs
tHIGH SCL clock high time 4.0 µs
tSU,DAT SDA set-up time 250 ns
tHD,DAT SDA hold time 8 34502,3 ns
tSU,STA Repeated START condition set-up time 4.7 µs
tHD,STA (Repeated) START condition hold time 4.0 µs
tSU,STO STOP condition set-up time 4.0 µs
tBUF Bus free time between a STOP and START condition 4.7 µs
1For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32HG Reference Manual.
2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10-9 [s] * fHFPERCLK [Hz]) - 5).
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Table 3.28. I2C Fast-mode (Fm)
Symbol Parameter Min Typ Max Unit
fSCL SCL clock frequency 0 4001kHz
tLOW SCL clock low time 1.3 µs
tHIGH SCL clock high time 0.6 µs
tSU,DAT SDA set-up time 100 ns
tHD,DAT SDA hold time 8 9002,3 ns
tSU,STA Repeated START condition set-up time 0.6 µs
tHD,STA (Repeated) START condition hold time 0.6 µs
tSU,STO STOP condition set-up time 0.6 µs
tBUF Bus free time between a STOP and START condition 1.3 µs
1For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32HG Reference Manual.
2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10-9 [s] * fHFPERCLK [Hz]) - 5).
Table 3.29. I2C Fast-mode Plus (Fm+)
Symbol Parameter Min Typ Max Unit
fSCL SCL clock frequency 0 10001kHz
tLOW SCL clock low time 0.5 µs
tHIGH SCL clock high time 0.26 µs
tSU,DAT SDA set-up time 50 ns
tHD,DAT SDA hold time 8 ns
tSU,STA Repeated START condition set-up time 0.26 µs
tHD,STA (Repeated) START condition hold time 0.26 µs
tSU,STO STOP condition set-up time 0.26 µs
tBUF Bus free time between a STOP and START condition 0.5 µs
1For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32HG Reference Manual.
3.15 USB
The USB hardware in the EFM32HG350 passes all tests for USB 2.0 Full Speed certification. The test
report will be distributed with application note "AN0046 - USB Hardware Design Guide" when ready.
Table 3.30. USB
Symbol Parameter Condition Min Typ Max Unit
VUSBOUT USB regulator out-
put voltage
3.1 3.4 3.7 V
BIASPROG=0, TAMB=25°C 55.7 79.4 104.1 mA
BIASPROG=1, TAMB=25°C 66.0 95.9 126.4 mA
BIASPROG=2, TAMB=25°C 94.6 146.5 188.1 mA
IUSBOUT
USB regulator out-
put current
BIASPROG=3, TAMB=25°C 80.4 128.3 176.0 mA
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3.16 Digital Peripherals
Table 3.31. Digital Peripherals
Symbol Parameter Condition Min Typ Max Unit
IUSART USART current USART idle current, clock en-
abled
7.5 µA/
MHz
ILEUART LEUART current LEUART idle current, clock en-
abled
150 nA
II2C I2C current I2C idle current, clock enabled 6.25 µA/
MHz
ITIMER TIMER current TIMER_0 idle current, clock
enabled
8.75 µA/
MHz
IPCNT PCNT current PCNT idle current, clock en-
abled
100 nA
IRTC RTC current RTC idle current, clock enabled 100 nA
IAES AES current AES idle current, clock enabled 2.5 µA/
MHz
IGPIO GPIO current GPIO idle current, clock en-
abled
5.31 µA/
MHz
IPRS PRS current PRS idle current 2.81 µA/
MHz
IDMA DMA current Clock enable 8.12 µA/
MHz
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4 Pinout and Package
Note
Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for
guidelines on designing Printed Circuit Boards (PCB's) for the EFM32HG350.
4.1 Pinout
The EFM32HG350 pinout is shown in Figure 4.1 (p. 52) and Table 4.1 (p. 52) . Alternate locations
are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/").
Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module
in question.
Figure 4.1. EFM32HG350 Pinout (top view, not to scale)
Table 4.1. Device Pinout
CSP36 Pin#
and Name
Pin Alternate Functionality / Description
Pin #
Pin Name Analog Timers Communication Other
A1 PC14
TIM0_CDTI1 #1/6
TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3
US1_CS #3/4
LEU0_TX #5
USB_DM
PRS_CH0 #2
A2 PC15 TIM0_CDTI2 #1/6
TIM1_CC2 #0
US0_CLK #3
US1_CLK #3 PRS_CH1 #2
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CSP36 Pin#
and Name
Pin Alternate Functionality / Description
Pin #
Pin Name Analog Timers Communication Other
LEU0_RX #5
USB_DP
A3 VSS Ground.
A4 IOVDD_5 Digital IO power supply 5.
A5 PE12 ADC0_CH0 TIM1_CC2 #1
TIM2_CC1 #3
US0_RX #3
US0_CLK #0/6
I2C0_SDA #6
CMU_CLK1 #2
PRS_CH1 #3
A6 PA0
TIM0_CC1 #6
TIM0_CC0 #0/1/4
PCNT0_S0IN #4
USB_DMPU #0
US1_RX #4
LEU0_RX #4
I2C0_SDA #0
PRS_CH0 #0
PRS_CH3 #3
GPIO_EM4WU0
B1 USB_VREGI
B2 PF0 TIM0_CC0 #5
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
DBG_SWCLK #0
BOOT_TX
B3 PF2 TIM0_CC2 #5/6
TIM2_CC0 #3
US1_TX #4
LEU0_TX #4
CMU_CLK0 #3
PRS_CH0 #3
GPIO_EM4WU4
B4 PE10 TIM1_CC0 #1 US0_TX #0 PRS_CH2 #2
B5 PE13 ADC0_CH1 TIM2_CC2 #3
US0_TX #3
US0_CS #0/6
I2C0_SCL #6
ACMP0_O #0
PRS_CH2 #3
GPIO_EM4WU5
B6 PA1 TIM0_CC0 #6
TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0
PRS_CH1 #0
C1 USB_VREGO
C2 VDD_DREG Power supply for on-chip voltage regulator.
C3 PF1 TIM0_CC1 #5
US1_CS #2
LEU0_RX #3
I2C0_SCL #5
DBG_SWDIO #0
GPIO_EM4WU3
BOOT_RX
C4 PE11 TIM1_CC1 #1 US0_RX #0 PRS_CH3 #2
C5 PA2 TIM0_CC2 #0/1 CMU_CLK0 #0
C6 IOVDD_0 Digital IO power supply 0.
D1 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
D2 VSS_DREG Ground for on-chip voltage regulator.
D3 PD6 ADC0_CH6 TIM1_CC0 #4
PCNT0_S0IN #3
US1_RX #2/3
I2C0_SDA #1 ACMP0_O #2
D4 PC1 ACMP0_CH1 TIM0_CC2 #4
PCNT0_S1IN #2
US0_RX #5/6
US1_TX #5
US1_RX #0
I2C0_SCL #4
PRS_CH3 #0
D5 PC0 ACMP0_CH0 TIM0_CC1 #4
PCNT0_S0IN #2
US0_TX #5/6
US1_TX #0
US1_CS #5
I2C0_SDA #4
PRS_CH2 #0
D6 VSS Ground.
E1 PD7 ADC0_CH7 TIM1_CC1 #4
PCNT0_S1IN #3
US1_TX #2/3
I2C0_SCL #1 CMU_CLK0 #2
E2 VSS Ground.
E3 AVSS_0 Analog ground 0.
E4 AVDD_0 Analog power supply 0.
E5 RESETn Reset input, active low.
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CSP36 Pin#
and Name
Pin Alternate Functionality / Description
Pin #
Pin Name Analog Timers Communication Other
To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up
ensure that reset is released.
E6 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4
US1_CLK #0
F1 PD5 ADC0_CH5 LEU0_RX #0
F2 PB14 HFXTAL_N US0_CS #4/5
LEU0_RX #1
F3 PB13 HFXTAL_P US0_CLK #4/5
LEU0_TX #1
F4 AVDD_1 Analog power supply 1.
F5 PB11 IDAC0_OUT TIM1_CC2 #3
PCNT0_S1IN #4 US1_CLK #4 CMU_CLK1 #3
ACMP0_O #3
F6 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4
US1_CS #0
4.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in
Table 4.2 (p. 54) . The table shows the name of the alternate functionality in the first column, followed
by columns showing the possible LOCATION bitfield settings.
Note
Some functionality, such as analog interfaces, do not have alternate settings or a LOCA-
TION bitfield. In these cases, the pinout is shown in the column corresponding to LOCA-
TION 0.
Table 4.2. Alternate functionality overview
Alternate LOCATION
Functionality 0 1 2 3 4 5 6 Description
ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.
ACMP0_O PE13 PD6 PB11 Analog comparator ACMP0, digital output.
ADC0_CH0 PE12 Analog to digital converter ADC0, input channel number 0.
ADC0_CH1 PE13 Analog to digital converter ADC0, input channel number 1.
ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5.
ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6.
ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7.
BOOT_RX PF1 Bootloader RX.
BOOT_TX PF0 Bootloader TX.
CMU_CLK0 PA2 PD7 PF2 Clock Management Unit, clock output number 0.
CMU_CLK1 PA1 PE12 PB11 Clock Management Unit, clock output number 1.
DBG_SWCLK PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and
has a built-in pull down.
DBG_SWDIO PF1 Debug-interface Serial Wire data input / output.
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Alternate LOCATION
Functionality 0 1 2 3 4 5 6 Description
Note that this function is enabled to pin out of reset, and
has a built-in pull up.
GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4
HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as exter-
nal optional clock input pin.
HFXTAL_P PB13 High Frequency Crystal positive pin.
I2C0_SCL PA1 PD7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA PA0 PD6 PC0 PF0 PE12 I2C0 Serial Data input / output.
IDAC0_OUT PB11 IDAC0 output.
LEU0_RX PD5 PB14 PF1 PA0 PC15 LEUART0 Receive input.
LEU0_TX PB13 PF0 PF2 PC14 LEUART0 Transmit output. Also used as receive input in
half duplex communication.
LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negative
pin. Also used as an optional external clock input pin.
LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN PC0 PD6 PA0 Pulse Counter PCNT0 input number 0.
PCNT0_S1IN PC14 PC1 PD7 PB11 Pulse Counter PCNT0 input number 1.
PRS_CH0 PA0 PC14 PF2 Peripheral Reflex System PRS, channel 0.
PRS_CH1 PA1 PC15 PE12 Peripheral Reflex System PRS, channel 1.
PRS_CH2 PC0 PE10 PE13 Peripheral Reflex System PRS, channel 2.
PRS_CH3 PC1 PE11 PA0 Peripheral Reflex System PRS, channel 3.
TIM0_CC0 PA0 PA0 PA0 PF0 PA1 Timer 0 Capture Compare input / output channel 0.
TIM0_CC1 PA1 PA1 PC0 PF1 PA0 Timer 0 Capture Compare input / output channel 1.
TIM0_CC2 PA2 PA2 PC1 PF2 PF2 Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI1 PC14 PC14 Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2 PC15 PC15 Timer 0 Complimentary Deat Time Insertion channel 2.
TIM1_CC0 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0.
TIM1_CC1 PC14 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1.
TIM1_CC2 PC15 PE12 PB11 Timer 1 Capture Compare input / output channel 2.
TIM2_CC0 PF2 Timer 2 Capture Compare input / output channel 0.
TIM2_CC1 PE12 Timer 2 Capture Compare input / output channel 1.
TIM2_CC2 PE13 Timer 2 Capture Compare input / output channel 2.
US0_CLK PE12 PC15 PB13 PB13 PE12 USART0 clock input / output.
US0_CS PE13 PC14 PB14 PB14 PE13 USART0 chip select input / output.
US0_RX PE11 PE12 PB8 PC1 PC1
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output
(MISO).
US0_TX PE10 PE13 PB7 PC0 PC0
USART0 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK PB7 PF0 PC15 PB11 USART1 clock input / output.
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Alternate LOCATION
Functionality 0 1 2 3 4 5 6 Description
US1_CS PB8 PF1 PC14 PC14 PC0 USART1 chip select input / output.
US1_RX PC1 PD6 PD6 PA0
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output
(MISO).
US1_TX PC0 PD7 PD7 PF2 PC1
USART1 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
USB_DM PC14 USB D- pin.
USB_DMPU PA0 USB D- Pullup control.
USB_DP PC15 USB D+ pin.
USB_VREGI USB_VREGI USB Input to internal 3.3 V regulator
USB_VREGO USB_VREGO USB Decoupling for internal 3.3 V USB regulator and reg-
ulator output
4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32HG350 is shown in Table 4.3 (p. 56) . Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated
by a number from 15 down to 0.
Table 4.3. GPIO Pinout
Port Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin
9
Pin
8
Pin
7
Pin
6
Pin
5
Pin
4
Pin
3
Pin
2
Pin
1
Pin
0
Port A - - - - - - - - - - - - - PA2 PA1 PA0
Port B - PB14 PB13 - PB11 - - PB8 PB7 - - - - - - -
Port C PC15 PC14 - - - - - - - - - - - - PC1 PC0
Port D - - - - - - - - PD7 PD6 PD5 - - - - -
Port E - - PE13 PE12 PE11 PE10 - - - - - - - - - -
Port F - - - - - - - - - - - - - PF2 PF1 PF0
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4.4 CSP36 Package
Figure 4.2. CSP36
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Primary datum “C” and seating plane are defined by the spherical crowns of the solder balls.
4. Dimension “b” is measured at the maximum solder bump diameter, parallel to primary datum “C”.
5. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
Table 4.4. CSP36 (Dimensions in mm)
Symbol A A1 A2 b S D E e D1 E1 SD SE n aaa bbb ccc ddd
Min 0.491 0.17 0.036 0.23 0.3075
Nom 0.55 - 0.040 - 0.31
Max 0.609 0.23 0.044 0.29 0.3125
3.016
BSC.
2.891
BSC.
0.40
BSC.
2.00
BSC.
2.00
BSC. 0.2 0.2 36 0.03 0.06 0.05 0.015
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see:
http://www.silabs.com/support/quality/pages/default.aspx
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5 PCB Layout and Soldering
5.1 Recommended PCB Layout
Figure 5.1. CSP36 PCB Land Pattern
Table 5.1. CSP36 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol Dim. (mm)
X 0.20
C1 2.00
C2 2.00
E1 0.40
E2 0.40
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Figure 5.2. CSP36 PCB Solder Mask
Table 5.2. CSP36 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol Dim. (mm)
X 0.26
C1 2.00
C2 2.00
E1 0.40
E2 0.40
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Figure 5.3. CSP36 PCB Stencil Design
Table 5.3. CSP36 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol Dim. (mm)
X 0.20
C1 2.00
C2 2.00
E1 0.40
E2 0.40
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.075 mm (3 mils).
6. For detailed pin-positioning, see Figure 4.2 (p. 57) .
5.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
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6 Chip Marking, Revision and Errata
6.1 Chip Marking
In the illustration below package fields and position are shown.
Figure 6.1. Example Chip Marking (top view)
6.2 Revision
The revision of a chip can be determined from the "Revision" field in Figure 6.1 (p. 61) .
6.3 Errata
Please see the errata document for EFM32HG350 for description and resolution of device erratas. This
document is available in Simplicity Studio and online at:
http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
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7 Revision History
7.1 Revision 1.00
December 4th, 2015
Updated all specs with results of full characterization.
Updated part number to revision B.
Added the USB electrical specifications table.
7.2 Revision 0.91
May 6th, 2015
Updated current consumption table for energy modes.
Updated GPIO max leakage current.
Updated startup time for HFXO and LFXO.
Updated current consumption for HFRCO and LFRCO.
Updated ADC current consumption.
Updated IDAC characteristics tables.
Updated ACMP internal resistance.
Updated VCMP current consumption.
7.3 Revision 0.90
March 16th, 2015
Note
This datasheet revision applies to a product under development. It’s characteristics and
specifications are subject to change without notice.
Corrected EM2 current consumption condition in Electrical Characteristics section.
Updated GPIO electrical characteristics.
Updated Max ESRHFXO value for Crystal Frequency of 25 MHz.
Updated LFRCO plots.
Updated HFRCO table and plots.
Updated ADC table and temp sensor plot.
Added DMA current in Digital Peripherals section.
Updated block diagram.
Corrected leadframe type to matte-Sn.
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7.4 Revision 0.20
December 11th, 2014
Preliminary Release.
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation
of all peripherals and modules available for system and software implementers using or intending to use
the Silicon Laboratories products. Characterization data, available modules and peripherals, memory
sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and
do vary in different applications. Application examples described herein are for illustrative purposes only.
Silicon Laboratories reserves the right to make changes without further notice and limitation to product
information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the conse-
quences of use of the information supplied herein. This document does not imply or express copyright
licenses granted hereunder to design or fabricate any integrated circuits. The products must not be
used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life
Support System" is any product or system intended to support or sustain life and/or health, which, if it
fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories
products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological
or chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®,
EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most ener-
gy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISO-
modem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered
trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or reg-
istered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products
or brand names mentioned herein are trademarks of their respective holders.
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B Contact Information
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
http://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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Table of Contents
1. Ordering Information .................................................................................................................................. 2
2. System Summary ...................................................................................................................................... 3
2.1. System Introduction ......................................................................................................................... 3
2.2. Configuration Summary .................................................................................................................... 6
2.3. Memory Map ................................................................................................................................. 7
3. Electrical Characteristics ............................................................................................................................. 8
3.1. Test Conditions .............................................................................................................................. 8
3.2. Absolute Maximum Ratings .............................................................................................................. 8
3.3. General Operating Conditions ........................................................................................................... 8
3.4. Current Consumption ....................................................................................................................... 9
3.5. Transition between Energy Modes .................................................................................................... 17
3.6. Power Management ....................................................................................................................... 18
3.7. Flash .......................................................................................................................................... 18
3.8. General Purpose Input Output ......................................................................................................... 19
3.9. Oscillators .................................................................................................................................... 27
3.10. Analog Digital Converter (ADC) ...................................................................................................... 32
3.11. Current Digital Analog Converter (IDAC) .......................................................................................... 42
3.12. Analog Comparator (ACMP) .......................................................................................................... 47
3.13. Voltage Comparator (VCMP) ......................................................................................................... 49
3.14. I2C ........................................................................................................................................... 49
3.15. USB .......................................................................................................................................... 50
3.16. Digital Peripherals ....................................................................................................................... 51
4. Pinout and Package ................................................................................................................................. 52
4.1. Pinout ......................................................................................................................................... 52
4.2. Alternate Functionality Pinout .......................................................................................................... 54
4.3. GPIO Pinout Overview ................................................................................................................... 56
4.4. CSP36 Package ........................................................................................................................... 57
5. PCB Layout and Soldering ........................................................................................................................ 58
5.1. Recommended PCB Layout ............................................................................................................ 58
5.2. Soldering Information ..................................................................................................................... 60
6. Chip Marking, Revision and Errata .............................................................................................................. 61
6.1. Chip Marking ................................................................................................................................ 61
6.2. Revision ...................................................................................................................................... 61
6.3. Errata ......................................................................................................................................... 61
7. Revision History ...................................................................................................................................... 62
7.1. Revision 1.00 ............................................................................................................................... 62
7.2. Revision 0.91 ............................................................................................................................... 62
7.3. Revision 0.90 ............................................................................................................................... 62
7.4. Revision 0.20 ............................................................................................................................... 63
A. Disclaimer and Trademarks ....................................................................................................................... 64
A.1. Disclaimer ................................................................................................................................... 64
A.2. Trademark Information ................................................................................................................... 64
B. Contact Information ................................................................................................................................. 65
B.1. ................................................................................................................................................. 65
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List of Figures
2.1. Block Diagram ....................................................................................................................................... 3
2.2. EFM32HG350 Memory Map with largest RAM and Flash sizes ........................................................................ 7
3.1. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 24
MHz ........................................................................................................................................................ 11
3.2. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 21
MHz ........................................................................................................................................................ 12
3.3. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 14
MHz ........................................................................................................................................................ 12
3.4. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 11
MHz ........................................................................................................................................................ 13
3.5. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 6.6
MHz ........................................................................................................................................................ 13
3.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 24 MHz .............................. 14
3.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 21 MHz .............................. 14
3.8. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 14 MHz .............................. 15
3.9. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 11 MHz .............................. 15
3.10. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 6.6 MHz ........................... 16
3.11. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO. ....................................................... 16
3.12. EM3 current consumption. ................................................................................................................... 17
3.13. EM4 current consumption. ................................................................................................................... 17
3.14. Typical Low-Level Output Current, 2V Supply Voltage ................................................................................ 21
3.15. Typical High-Level Output Current, 2V Supply Voltage ................................................................................ 22
3.16. Typical Low-Level Output Current, 3V Supply Voltage ................................................................................ 23
3.17. Typical High-Level Output Current, 3V Supply Voltage ................................................................................ 24
3.18. Typical Low-Level Output Current, 3.8V Supply Voltage .............................................................................. 25
3.19. Typical High-Level Output Current, 3.8V Supply Voltage ............................................................................. 26
3.20. Calibrated LFRCO Frequency vs Temperature and Supply Voltage .............................................................. 28
3.21. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 29
3.22. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 30
3.23. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 30
3.24. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 30
3.25. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 31
3.26. Integral Non-Linearity (INL) ................................................................................................................... 37
3.27. Differential Non-Linearity (DNL) .............................................................................................................. 37
3.28. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C ................................................................................. 38
3.29. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C ................................................................... 39
3.30. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C ............................................................... 40
3.31. ADC Absolute Offset, Common Mode = Vdd /2 ........................................................................................ 41
3.32. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V .............................................. 41
3.33. ADC Temperature sensor readout ......................................................................................................... 42
3.34. IDAC Source Current as a function of voltage on IDAC_OUT ....................................................................... 45
3.35. IDAC Sink Current as a function of voltage from IDAC_OUT ........................................................................ 46
3.36. IDAC linearity .................................................................................................................................... 46
3.37. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1 ............................................. 48
4.1. EFM32HG350 Pinout (top view, not to scale) ............................................................................................. 52
4.2. CSP36 ................................................................................................................................................ 57
5.1. CSP36 PCB Land Pattern ...................................................................................................................... 58
5.2. CSP36 PCB Solder Mask ....................................................................................................................... 59
5.3. CSP36 PCB Stencil Design .................................................................................................................... 60
6.1. Example Chip Marking (top view) ............................................................................................................. 61
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List of Tables
1.1. Ordering Information ................................................................................................................................ 2
2.1. Configuration Summary ............................................................................................................................ 6
3.1. Absolute Maximum Ratings ...................................................................................................................... 8
3.2. General Operating Conditions ................................................................................................................... 8
3.3. Current Consumption ............................................................................................................................... 9
3.4. Energy Modes Transitions ...................................................................................................................... 17
3.5. Power Management ............................................................................................................................... 18
3.6. Flash .................................................................................................................................................. 18
3.7. GPIO .................................................................................................................................................. 19
3.8. LFXO .................................................................................................................................................. 27
3.9. HFXO ................................................................................................................................................. 27
3.10. LFRCO .............................................................................................................................................. 28
3.11. HFRCO ............................................................................................................................................. 29
3.12. AUXHFRCO ....................................................................................................................................... 31
3.13. USHFRCO ......................................................................................................................................... 32
3.14. ULFRCO ............................................................................................................................................ 32
3.15. ADC .................................................................................................................................................. 32
3.16. IDAC Range 0 Source ......................................................................................................................... 42
3.17. IDAC Range 0 Sink ............................................................................................................................. 42
3.18. IDAC Range 1 Source ......................................................................................................................... 43
3.19. IDAC Range 1 Sink ............................................................................................................................. 43
3.20. IDAC Range 2 Source ......................................................................................................................... 43
3.21. IDAC Range 2 Sink ............................................................................................................................. 43
3.22. IDAC Range 3 Source ......................................................................................................................... 44
3.23. IDAC Range 3 Sink ............................................................................................................................. 44
3.24. IDAC ................................................................................................................................................. 44
3.25. ACMP ............................................................................................................................................... 47
3.26. VCMP ............................................................................................................................................... 49
3.27. I2C Standard-mode (Sm) ...................................................................................................................... 49
3.28. I2C Fast-mode (Fm) ............................................................................................................................ 50
3.29. I2C Fast-mode Plus (Fm+) .................................................................................................................... 50
3.30. USB .................................................................................................................................................. 50
3.31. Digital Peripherals ............................................................................................................................... 51
4.1. Device Pinout ....................................................................................................................................... 52
4.2. Alternate functionality overview ................................................................................................................ 54
4.3. GPIO Pinout ........................................................................................................................................ 56
4.4. CSP36 (Dimensions in mm) .................................................................................................................... 57
5.1. CSP36 PCB Land Pattern Dimensions (Dimensions in mm) .......................................................................... 58
5.2. CSP36 PCB Solder Mask Dimensions (Dimensions in mm) ........................................................................... 59
5.3. CSP36 PCB Stencil Design Dimensions (Dimensions in mm) ........................................................................ 60
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List of Equations
3.1. Total ACMP Active Current ..................................................................................................................... 47
3.2. VCMP Trigger Level as a Function of Level Setting ..................................................................................... 49
