IRLR024, IRLU024, SiHLR024, SiHLU024 Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) * Dynamic dV/dt Rating 60 RDS(on) () VGS = 5.0 V Qg (Max.) (nC) 18 * Straight Lead (IRLU024/SiHLU024) Qgs (nC) 4.5 * Available in Tape and Reel 12 * Logic-Level Gate Drive Qgd (nC) Configuration Available * Surface Mount (IRLR024/SiHLR024) 0.10 Single RoHS* COMPLIANT * RDS(on) Specified at VGS = 4 V and 5 V * Fast Switching D * Lead (Pb)-free Available DPAK (TO-252) IPAK (TO-251) DESCRIPTION D D Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The DPAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRLU/SiHLU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 W are possible in typical surface mount applications. G G S G D S S N-Channel MOSFET ORDERING INFORMATION Package DPAK (TO-252) IRLR024PbF SiHLR024-E3 IRLR024 SiHLR024 Lead (Pb)-free SnPb DPAK (TO-252) IRLR024TRPbFa SiHLR024T-E3a IRLR024TRa SiHLR024Ta IPAK (TO-251) IRLU024PbF SiHLU024-E3 IRLU024 SiHLU024 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS TC = 25 C, unless otherwise noted PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 60 Gate-Source Voltage VGS 10 Continuous Drain Current VGS at 5.0 V TC = 25 C TC = 100 C Pulsed Drain Currenta ID IDM Linear Derating Factor Linear Derating Factor (PCB EAS Maximum Power Dissipation TC = 25 C Maximum Power Dissipation (PCB Mount)e TA = 25 C Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) for 10 s PD A 56 0.020 Single Pulse Avalanche Energyb V 14 9.2 0.33 Mount)e UNIT 91 42 2.5 dV/dt 4.5 TJ, Tstg - 55 to + 150 260d W/C mJ W V/ns C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, starting TJ = 25 C, L = 541 H, RG = 25 , IAS = 14 A (see fig. 12). c. ISD 17 A, dI/dt 140 A/s, VDD VDS, TJ 150 C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91322 S-82993-Rev. B, 19-Jan-09 www.vishay.com 1 IRLR024, IRLU024, SiHLR024, SiHLU024 Vishay Siliconix THERMAL RESISTANCE RATINGS SYMBOL MIN. TYP. MAX. Maximum Junction-to-Ambient PARAMETER RthJA - - 110 Maximum Junction-to-Ambient (PCB Mount)a RthJA - - 50 Maximum Junction-to-Case (Drain) RthJC - - 3.0 UNIT C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS TJ = 25 C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VDS VGS = 0 V, ID = 250 A 60 - - V VDS/TJ Reference to 25 C, ID = 1 mA - 0.068 - V/C VGS(th) VDS = VGS, ID = 250 A 1.0 - 2.0 V Gate-Source Leakage IGSS VGS = 10 V - - 100 nA Zero Gate Voltage Drain Current IDSS VDS = 60 V, VGS = 0 V - - 25 VDS = 48 V, VGS = 0 V, TJ = 125 C - - 250 Gate-Source Threshold Voltage Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs VGS = 5.0 V ID = 8.4 Ab - - 0.10 VGS = 4.0 V Ab - - 0.14 VDS = 25 V, ID = 8.4 Ab 7.3 - - VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 870 - - 360 - - 53 - - - 18 - - 4.5 ID = 7.0 A S Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs VGS = 5.0 V ID = 17 A, VDS = 48 V, see fig. 6 and 13b pF nC Gate-Drain Charge Qgd - - 12 Turn-On Delay Time td(on) - 11 - - 110 - - 23 - - 41 - - 4.5 - - 7.5 - - - 14 - - 56 - - 1.5 - 130 260 ns - 0.75 1.5 C Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = 30 V, ID = 17 A, RG = 9.0 , RD = 1.7 , see fig. 10b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contactc D ns nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 C, IS = 14 A, VGS = 0 Vb TJ = 25 C, IF = 17 A, dI/dt = 100 A/sb V Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 s; duty cycle 2 %. www.vishay.com 2 Document Number: 91322 S-82993-Rev. B, 19-Jan-09 IRLR024, IRLU024, SiHLR024, SiHLU024 Vishay Siliconix TYPICAL CHARACTERISTICS 25 C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC = 25 C Fig. 2 - Typical Output Characteristics, TC = 150 C Document Number: 91322 S-82993-Rev. B, 19-Jan-09 Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.com 3 IRLR024, IRLU024, SiHLR024, SiHLU024 Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area Document Number: 91322 S-82993-Rev. B, 19-Jan-09 IRLR024, IRLU024, SiHLR024, SiHLU024 Vishay Siliconix VDS VGS RD D.U.T. RG + - VDD 5V Pulse width 1 s Duty factor 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature tr td(off) tf Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 91322 S-82993-Rev. B, 19-Jan-09 www.vishay.com 5 IRLR024, IRLU024, SiHLR024, SiHLU024 Vishay Siliconix L VDS VDS Vary tp to obtain required IAS tp VDD D.U.T RG + - I AS V DD VDS 5V 0.01 tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 k QG 5V 12 V 0.2 F 0.3 F QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.vishay.com 6 Fig. 13b - Gate Charge Test Circuit Document Number: 91322 S-82993-Rev. B, 19-Jan-09 IRLR024, IRLU024, SiHLR024, SiHLU024 Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T Circuit layout considerations * Low stray inductance * Ground plane * Low leakage inductance current transformer + - - + RG + * dV/dt controlled by RG * ISD controlled by duty factor "D" * D.U.T. - device under test Driver gate drive P.W. Period D= - VDD P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple 5 % ISD * VGS = 5 V for logic level and 3 V drive devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91322. Document Number: 91322 S-82993-Rev. B, 19-Jan-09 www.vishay.com 7 Package Information Vishay Siliconix TO-252AA (HIGH VOLTAGE) E b3 E1 L3 D1 D H L4 b2 b A c2 e A1 L1 L c L2 MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. E 6.40 6.73 0.252 0.265 L 1.40 1.77 0.055 L1 2.743 REF L2 0.070 0.108 REF 0.508 BSC 0.020 BSC L3 0.89 1.27 0.035 0.050 L4 0.64 1.01 0.025 0.040 D 6.00 6.22 0.236 0.245 H 9.40 10.40 0.370 0.409 b 0.64 0.88 0.025 0.035 b2 0.77 1.14 0.030 0.045 b3 5.21 5.46 0.205 e 2.286 BSC 0.215 0.090 BSC A 2.20 2.38 0.087 A1 0.00 0.13 0.000 0.094 0.005 c 0.45 0.60 0.018 0.024 c2 0.45 0.58 0.018 0.023 D1 5.30 - 0.209 - E1 4.40 - 0.173 - 0' 10' 0' 10' ECN: S-81965-Rev. A, 15-Sep-08 DWG: 5973 Notes 1. Package body sizes exclude mold flash, protrusion or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side. 2. Package body sizes determined at the outermost extremes of the plastic body exclusive of mold flash, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. The package top may be smaller than the package bottom. 4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimension at maximum material condition. The dambar cannot be located on the lower radius of the foot. Document Number: 91344 Revision: 15-Sep-08 www.vishay.com 1 Package Information Vishay Siliconix TO-251AA (HIGH VOLTAGE) 4 3 E1 E Thermal PAD 4 b4 2 4 A 0.010 0.25 M C A B L2 4 c2 A 1 B D D1 A C 3 Seating plane 5 C L1 L3 (Datum A) C L B B A A1 3 x b2 View A - A 2xe c 3xb 0.010 0.25 M C A B Plating 5 b1, b3 Base metal Lead tip c1 (c) 5 (b, b2) Section B - B and C - C MILLIMETERS DIM. MIN. MAX. INCHES MIN. MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 2.18 2.39 0.086 0.094 D1 5.21 - 0.205 - A1 0.89 1.14 0.035 0.045 E 6.35 6.73 0.250 0.265 4.32 - 0.170 - b 0.64 0.89 0.025 0.035 E1 b1 0.65 0.79 0.026 0.031 e b2 0.76 1.14 0.030 0.045 L 8.89 9.65 0.350 0.380 b3 0.76 1.04 0.030 0.041 L1 1.91 2.29 0.075 0.090 b4 4.95 5.46 0.195 0.215 L2 0.89 1.27 0.035 0.050 2.29 BSC 2.29 BSC c 0.46 0.61 0.018 0.024 L3 1.14 1.52 0.045 0.060 c1 0.41 0.56 0.016 0.022 1 0' 15' 0' 15' c2 0.46 0.86 0.018 0.034 2 25' 35' 25' 35' D 5.97 6.22 0.235 0.245 ECN: S-82111-Rev. A, 15-Sep-08 DWG: 5968 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension are shown in inches and millimeters. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body. 4. Thermal pad contour optional with dimensions b4, L2, E1 and D1. 5. Lead dimension uncontrolled in L3. 6. Dimension b1, b3 and c1 apply to base metal only. 7. Outline conforms to JEDEC outline TO-251AA. Document Number: 91362 Revision: 15-Sep-08 www.vishay.com 1 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR DPAK (TO-252) 0.224 0.243 0.087 (2.202) 0.090 (2.286) (10.668) 0.420 (6.180) (5.690) 0.180 0.055 (4.572) (1.397) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72594 Revision: 21-Jan-08 www.vishay.com 3 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, "Vishay"), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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Material Category Policy Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant. Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Revision: 12-Mar-12 1 Document Number: 91000