Document:1G5-0187 Rev.2 Page 1
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Description
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access
mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single
5V only or 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup,
portable electronic application. Self-Refresh is supported and CBR cycles are being performed. lt is pack-
aged in JEDEC standard 26/24-pin plastic SOJ or TSOPII.
Features
• Single 5V( %) or 3.3V(3.15V~3.6V) only power supply
• High speed tRAC access time: 50/60ns
• Extended - data - out(EDO) page mode access
• I/O level: TTL compatible (Vcc = 5V)
LVTTL compatible (Vcc = 3.3V)
• 4 refresh modes:
- RAS only refresh
- CAS - before - RAS refresh
- Hidden refresh
- Self-refresh
• Refresh interval:
- RAS only refresh, CAS - before - RAS refresh and hidden refresh: 2048 cycles in 32ms
- Self-refresh: 2048 cycles
• JEDEC standard pinout: 26/24-pin plastic SOJ and TSOPII.
10
±
Document:1G5-0187 Rev.2 Page 2
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Pin Name Function
A0-A10 Address inputs
- Row address
- Column address
- Refresh address
DQ1~DQ4 Data-in / data-out
RAS Row address strobe
CAS Column address strobe
WE Write enable
OE Output enable
Vcc Power (+5 V or + 3.3V)
Vss Ground
VCC 1
DQ1 2
DQ2 3DQ3
4
DQ4
5
VCC
6
8
9
10
11
NC
12
WE
13
A0
A1 17
A2
18
A3
19
VSS
RAS CAS
OE
A8
A7
A6
A5
A4
VSS
VG26(V)(S)17405J
Pin Description
Pin Configuration
21
22
23
24
25
26
15
14
16
A10
26/24-PIN 300mil Plastic SOJ
A9
VCC 1
DQ1 2
DQ2 3DQ3
4
DQ4
5
VCC
6
8
9
10
11
NC
12
WE
13
A0
A1 17
A2
18
A3
19
VSS
RAS CAS
OE
A8
A7
A6
A5
A4
VSS
VG26(V)(S)17405T
21
22
23
24
25
26
15
14
16
A10
26/24-PIN 300mil Plastic TSOP (ll)
A9
A0-A10
A0-A10
A0-A10
Document:1G5-0187 Rev.2 Page 3
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
WE
CAS
NO. 2 CLOCK
GENERATOR
COLUMN
ADDRESS
BUFFERS (11)
REFRESH
CONTROLLER
REFRESH
COUNTER
BUFFERS (11)
ADDRESS
ROW
NO. 1 CLOCK
GENERATOR
A0
RAS
A1
A2
A3
A4
A5
A6
A7
A8
CONTROL
LOGIC DATA-IN BUFFER
DATA-OUT
BUFFER OE
DQ1
.
DQ4
.
COLUMN
DECODER
2048
SENSE AMPLIFIERS
I/O GATING
2048x4
2048x2048x4
MEMORY
ARRAY
2048
ROW
DECODER
Vcc
Vss
Block Diagram
A9
A10
Document:1G5-0187 Rev.2 Page 4
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
TRUTH TABLE
Notes: 1. EARLY WRITE only.
FUNCTION RAS CAS WE OE
ADDRESSES
DQSNotes
ROW COL
STANDBY H X X X X High-Z
READ L L H L ROW COL Data-Out
WRITE: (EARLY WRITE ) L L L X ROW COL Data-ln
READ WRITE L L ROW COL Data-Out,Data-ln
EDO-PAGE-
MODE READ 1st Cycle L H L ROW COL Data-Out
2nd Cycle L H L n/a COL Data-Out
EDO-PAGE
MODE WRITE 1st Cycle L L X ROW COL Data-In
2nd Cycle L L X n/a COL Data-In
EDO-
PAGE-MODE
READ-WRITE
1st Cycle L ROW COL Data-Out, Data-In
2nd Cycle L n/a COL Data-Out, Data-In
HIDDEN
REFRESH READ L H L ROW COL Data-Out
WRITE L L X ROW COL Data-In 1
RAS-ONLY REFRESH L H X X ROW n/a High-Z
CBR REFRESH L H X X X High-Z
H X
®
H L
®
L H
®
H L
®
H L
®
H L
®
H L
®
H L
®
H L
®
L H
®
H L
®
H L
®
L H
®
LHL
® ®
LHL
® ®
H L
®
Document:1G5-0187 Rev.2 Page 5
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Absolute Maximum Ratings
Recommended DC Operating Conditions
Capacitance
Ta = 25°C, VCC = 5V or 3.3V, f = 1MHz
Note: 1. Capacitance measured with effective capacitance measuring method.
2. RAS, CAS = VIH to disable Dout.
Parameter Symbol Value Unit
5V
Voltage on any pin relative to Vss
3.3V VT
-1.0 to + 7.0
-0.5 to + 4.6
V
5V
Supply voltage relative to Vss
3.3V VCC
-1.0 to + 7.0
-0.5 to + 4.6
V
Short circuit output current IOUT 50 mA
Power dissipation PD1.0 W
Operating temperature TOPT 0 to + 70 °C
Storage temperature TSTG -55 to + 125 °C
Parameter/Condition Symbol 5 Volt Version 3.3 Volt Version Unit
Min Typ Max Min Typ Max
Supply Voltage VCC 4.5 5.0 5.5 3.15 3.3 3.6 V
Input High Voltage, all inputs VIH 2.4 - VCC + 1.0 2.0 - VCC + 0.3 V
Input Low Voltage, all inputs VIL -1.0 - 0.8 -0.3 - 0.8 V
Parameter Symbol Typ Max Unit Note
Input capacitance (Address) CI1 - 5 pF 1
Input capacitance (RAS, CAS, OE, WE) CI2 -7 pF 1
Output capacitance
(Data-in, Data-out) CI/O -7 pF 1, 2
Document:1G5-0187 Rev.2 Page 6
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
DC Characteristics; 5- Volt Verion
(Ta = 0 to + 70 °C, VCC= + 5V %,VSS = 0V)
Notes:
1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the
device is selected. ICC max is specified at the output open condition.
2. Address can be changed once or less while RAS = VIL.
3. For ICC4, address can be changed once or less within one EDO page mode cycle time.
4. Normal version: VG26S17405FT, VG26S17405FJ
5. Low power version: VG26S17405FTL, VG26S17405FJL
Parameter Symbol Test Conditions VG26(V)(S)17405 Unit Notes
-5 -6
Min Max Min Max
Operating current ICC1 RAS cycling
CAS cycling
tRC = min
- 120 - 110 mA 1, 2
Standby Current ICC2 TTL interface
RAS, CAS = VIH
Dout = High-Z
- 2 - 2 mA
CMOS interface
RAS, -0.2V
Dout = High-Z
1 - 1 mA
RAS-only
refresh current ICC3 RAS cycling, CAS = VIH
tRC = min - 120 - 110 mA 1, 2
EDO page mode
current ICC4 tPC = min - 140 - 130 mA 1, 3
CAS-before-RAS
refresh current ICC5 tRC = min
RAS, CAS cycling - 120 - 110 mA 1, 2
Self-refresh current ICC8 600 600 4
(low power ver-
sion)
- 350 - 350 5
10
±
CAS Vcc
³
t
RAS
100
m
s
³
m
A
t
RAS
100
m
s
³
m
A
Document:1G5-0187 Rev.2 Page 7
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
DC Characteristics ; 5-Volt Version (Cont.)
(Ta = 0 to + 70°C, VCC = + 5V %,VSS = 0V)
Parameter Symbol Test Conditions
VG26(V)(S)17405
Unit Notes
-5 -6
Min Max Min Max
Input leakage current ILI + 0.5V -5 5 -5 5
Output leakage current ILO + 0.5V
Dout = Disable
-5 5 -5 5
Output high Voltage VOH IOH = - 5mA 2.4 - 2.4 - V
Output low voltage VOL IOL = + 4.2mA - 0.4 - 0.4 V
10
±
0V VIN VCC
£ £
m
A
0V VOUT VCC
£ £
m
A
Document:1G5-0187 Rev.2 Page 8
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
DC Characteristics ; 3.3 - Volt Version
(Ta = 0 to 70°C, VCC = + 3.3V(3.15V~3.6V), VSS = 0V)
Notes:
1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the
device is selected. ICC max is specified at the output open condition.
2. Address can be changed once or less while RAS = VIL.
3. For ICC4, address can be changed once or less within one EDO page mode cycle time.
4. Normal version: VG26VS17405FT, VG26VS17405FJ
5. Low power version: VG26VS17405FTL, VG26VS17405FJL
Parameter Symbol Test Conditions VG26(V)(S)17405 Unit Notes
-5 -6
Min Max Min Max
Operating current ICC1 RAS cycling
CAS cycling
tRC = min
- 120 - 110 mA 1, 2
Standby Current ICC2 LVTTL interface
RAS, CAS = VIH
Dout = High-Z
- 2 - 2 mA
CMOS interface
RAS, -0.2V
Dout = High-Z
- 0.5 - 0.5 mA
RAS- only refresh current ICC3 RAS cycling, CAS = VIH
tRC = min - 120 - 110 mA 1, 2
EDO page mode current ICC4 tPC = min - 90 - 80 mA 1, 3
CAS- before- RAS refresh
current ICC5 tRC = min
RAS, CAS cycling - 120 - 110 mA 1, 2
Self- refresh current ICC8 550 550 4
(low power
version)
- 350 - 350 5
CAS VCC
³
t
RAS
100
m
s
³
m
A
t
RAS
100
m
s
³
m
A
Document:1G5-0187 Rev.2 Page 9
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
DC Characteristics ; 3.3 - Volt Version (Cont.)
(Ta = 0 to 70°C, VCC= +3.3V(3.15V~3.6V), VSS= 0V)
Parameter Symbol Test Conditions
VG26(V)(S)17405 Unit Notes
-5 -6
Min Max Min Max
Input leakage current ILI + 0.3V -5 5 -5 5
Output leakage current ILO + 0.3V
Dout = Disable
-5 5 -5 5
Output high Voltage VOH IOH = -2mA 2.4 - 2.4 - V
Output low voltage VOL IOL = +2mA - 0.4 - 0.4 V
0V Vin V
CC
£ £
m
A
0V Vout V
CC
£ £
m
A
Document:1G5-0187 Rev.2 Page 10
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
AC Characteristics
(Ta = 0 to + 70°C, Vcc = 5V or 3.3V, Vss = 0V) *1, *2, *3, *4
Test conditions
• Output load: two TTL Loads and 100pF (VCC = 5.0V %)
one TTL Load and 100pF (VCC = 3.3V(3.15V~3.6V) )
• Input timing reference levels:
VIH = 2.4V, VIL = 0.8V (VCC = 5.0V %); VIH = 2.0V, VIL = 0.8V (VCC = 3.3V(3.15V~3.6V) )
• Output timing reference levels:
VOH = 2.0V, VOL = 0.8V (VCC = 5V %, 3.3V(3.15V~3.6V) )
10
±
10
±
10
±
Read, Write, Read- Modify- Write and Refresh Cycles
(Common Parameters)
Parameter Symbol
VG26(V)(S) 17405 Unit Notes
-5 -6
Min Max Min Max
Random read or write cycle time tRC 84 - 104 - ns
RAS precharge time tRP 30 - 40 - ns
CAS precharge time in normal mode tCPN 10 - 10 - ns
RAS pulse width tRAS 50 10000 60 10000 ns 5
CAS pulse width tCAS 8 10000 10 10000 ns 6
Row address setup time tASR 0 - 0 - ns
Row address hold time tRAH 8 - 10 - ns
Column address setup time tASC 0 - 0 - ns 7
Column address hold time tCAH 8 - 10 - ns
RAS to CAS delay time tRCD 12 37 14 45 ns 8
RAS to column address delay time tRAD 10 25 12 30 ns 9
Column address to RAS lead time tRAL 25 - 30 - ns
RAS hold time tRSH 8 - 10 - ns
CAS hold time tCSH 38 - 40 - ns
CAS to RAS precharge time tCRP 5 - 5 - ns 10
OE to Din delay time tOED 20 - 20 - ns
Transition time (rise and fall) tT1 50 1 50 ns 11
Refresh period tREF - 32 - 32 ms
CAS to output in Low- Z tCLZ 0 - 0 - ns
CAS delay time from Din tDZC 0 - 0 - ns
OE delay time from Din tDZO 0 - 0 - ns
Document:1G5-0187 Rev.2 Page 11
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Read Cycle
Write Cycle
Read- Modify- Write Cycle
Parameter Symbol
VG26(V)(S)17405 Unit Notes
-5 -6
Min Max Min Max
Access time from RAS tRAC - 50 - 60 ns 12
Access time from CAS tCAC - 14 - 15 ns 13, 14
Access time from column address tAA - 25 - 30 ns 14, 15
Access time from OE tOEA - 12 - 15 ns
Read command setup time tRCS 0 - 0 - ns 7
Read command hold time to CAS tRCH 0 - 0 - ns 10, 16
Read command hold time to RAS tRRH 0 - 0 - ns 16
Output buffer turn-off time tOFF 0 12 0 15 ns 17
Output buffer turn-off time from OE tOEZ 0 12 0 15 ns 17
Parameter Symbol
VG26(V)(S)17405 Unit Notes
-5 -6
Min Max Min Max
Write command setup time tWCS 0 - 0 - ns 7, 18
Write command hold time tWCH 8 - 10 - ns
Write command pulse width tWP 8 - 10 - ns
Write command to RAS lead time tRWL 13 - 15 - ns
Write command to CAS lead time tCWL 8 - 10 - ns
Data-in setup time tDS 0 - 0 - ns 19
Data-in hold time tDH 8 - 10 - ns 19
WE to Data-in delay tWED 10 - 10 - ns
Parameter Symbol
VG26(V)(S) 17405 Unit Notes
-5 -6
Min Max Min Max
Read-modify- write cycle time tRWC 108 - 133 - ns
RAS to WE delay time tRWD 64 - 77 - ns 18
CAS to WE dealy time tCWD 26 - 32 - ns 18
Column address to WE delay time tAWD 39 - 47 - ns 18
OE hold time from WE tOEH 8 - 10 - ns
Document:1G5-0187 Rev.2 Page 12
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Refresh Cycle
EDO Page Mode Cycle
Parameter Symbol
VG26(V)(S)17405
Unit Notes
-5 -6
Min Max Min Max
CAS setup time (CBR refresh) tCSR 5 - 5 - ns
CAS hold time (CBR refresh) tCHR 8 - 10 - ns 10
RAS precharge to CAS hold time tRPC 5 - 5 - ns 7
RAS pulse width (self refresh) tRASS 100 - 100 -
RAS precharge time (self refresh) tRPS 90 - 110 - ns
CAS hold time (CBR self refresh) tCHS -50 - -50 - ns
WE setup time tWSR 0 - 0 - ns
WE hold time tWHR 10 - 10 - ns
Parameter Symbol
VG26(V)(S) 17405
Unit Notes
-5 -6
Min Max Min Max
EDO page mode cycle time tPC 20 - 25 - ns
EDO page mode CAS precharge time tCP 10 - 10 - ns
EDO page mode RAS pulse width tRASP 50 10560 105ns 20
Access time from CAS precharge tCPA - 30 - 35 ns 10, 14
RAS hold time from CAS precharge tCPRH 30 - 35 - ns
OE high hold time from CAS high tOEHC 5 - 5 - ns
OE high pulse width tOEP 10 - 10 - ns
Data output hold time after CAS low tCOH 5 - 5 - ns
Output disable delay from WE tWHZ 3 10 3 10 ns
WE pulse width for output disable when
CAS high tWPZ 10 - 10 - ns
m
s
Document:1G5-0187 Rev.2 Page 13
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
EDO Page Mode Read Modify Write Cycle
Parameter Symbol
VG26(V)(S)17405
Unit Notes
-5 -6
Min Max Min Max
EDO page mode read- modify- write cycle
CAS precharge to WE delay time tCPW 45 - 55 - ns 10
EDO page mode read- modify- write cycle
time tPRWC 56 - 68 - ns
Document:1G5-0187 Rev.2 Page 14
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Notes :
1. AC measurements assume tT = 1ns.
2. An initial pause of 100 is required after power up, and it is followed by a minimum of eight
initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal
refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required.
3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
4. All the VCC and VSS pins shall be supplied with the same voltages.
5. tRAS(min) = tRWD(min)+tRWL(min)+tT in read-modify-write cycle.
6. tCAS(min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle.
7. tASC(min), tRCS(min), tWCS(min), and tRPC are determined by the falling edge of CAS .
8. tRCD(max) is specified as a reference point only, and tRAC(max) can be met with the tRCD(max) limit.
Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit.
9. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit.
Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit.
10. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the rising edge of CAS .
11. VIH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition
time is measured between VIH and VIL.
12. Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
13. Assumes that (max) and (max).
14. Access time is determined by the maximum of tAA, tCAC, tCPA.
15. Assumes that (max) and (max).
16. Either tRCH or tRRH must be satisfied for a read cycle.
17. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high
impedance). tOFF is determined by the later rising edge of RAS or CAS.
18. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If (min), the cycle is an early write cycle and the
data out will remain open circuit (high impedance) throughout the entire cycle. If (min),
(min), (min) and (min), the cycle is a read-modify-write and
the data output will contain data read from the selected cell. If neither of the above sets of conditions
is satisfied, the condition of the data output (at access time) is indeterminate.
19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in a
delayed write or a read-modify-write cycle.
20. tRASP defines RAS pulse width in EDO page mode cycles.
m
s
£
£
t
RCD
t
RCD
³
tRAD tRAD
£
t
RCD
t
RCD
£
tRAD tRAD
³
t
WCS
t
WCS
³
tRWD tRWD
³
tCWD tCWD
³
tAWD tAWD
³
tCPW tCPW
³
Document:1G5-0187 Rev.2 Page 15
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Timing Waveforms
• Read Cycle
tRC
tRAS tRP
tCRP
tCPN
tRRH
tRCH
tOEZ
tOFF
tOEA
tCAC
tAA
tRAC
tCLZ
D
OUT
tRCS
tASR tRAH tASC tCAH
tRAD tRAL
tCAS
tRSH
tRCD
tT
tCSH
RAS
CAS
ADDRESS
WE
DQ1~DQ4
Note : = don’t care
OE
tOFF
Row Column
= Invalid Dout
Document:1G5-0187 Rev.2 Page 16
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
•Early Write Cycle
tRC
tRAS tRP
tWCH
tDS tDH
tWCS
tRAL
tCAS
tRSH
tRCD
tT
tCSH
RAS
CAS
WE
DQ1~DQ4
tCRP
tASR tRAH tASC tCAH
ADDRESS Column
Row
tCPN
DIN
tRAD tRAL
Document:1G5-0187 Rev.2 Page 17
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
• Delayed Write Cycle
tRC
tRAS tRP
tRWL
tRCS
tCAS
tRSH
tRCD
tT
tCSH
RAS
CAS
tASR tRAH tCAH
ADDRESS Column
Row
tASC
DIN
DQ1~DQ4
WE
tCRP
tCPN
tDH
tDS
tOEH
tOED
OE
tDS
OPEN
tWP
tCWL
Document:1G5-0187 Rev.2 Page 18
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
• Read - Modify - Write Cycle
tRWC
tRAS tRP
tRWD tWP
tRAD
tRWL
tCAS
tCWL
tRCD
tT
tCPN
RAS
CAS
WE
tCRP
tASR tRAH tASC tCAH
ADDRESS Column
Row
DQ1~DQ4
tDH
tDS
OE
tRCS tAWD
tCWD
DIN
tOED tOEH
tOEZ
tOEA
tCAC
tRAC tAA
DQ1~DQ4 DOUT
OPEN
tDZC
tDZO
Document:1G5-0187 Rev.2 Page 19
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
• EDO Page Mode Read Cycle
tRASP tCPRH
tRCS
tCAS
tRSH
tRCD
tOEA
tCSH
RAS
CAS
tASR tRAH tCAH
ADDRESS
tCAS
WE
tCRP tCP
OE
DQ1~DQ4 OPEN
tOEP
DOUT 1
tPC
tCP tCAS tCPN
tCRP
tRAD
tCAH
tASC tASC tCAH tASC
tRAL
Row Column 1
tOEA
tOEHC
tRRH
tRCH
tRAC
tAA tAA tAA
tCPA tCPA tOEZ
tOFF
tOFF
tCAC
tOEZ
tCAC
tCAC
tCOH
DOUT N
WE
OE
Column 2 Column N Row
tRP
DOUT 2
Document:1G5-0187 Rev.2 Page 20
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
• EDO Page Mode Early Write Cycle
tRASP tRP
tWCS
tCAS
tRSH
tRCD
RAS
CAS
tASR tRAH tCAH
ADDRESS
tCAS
WE
tCP
DQ1~DQ4
tPC
tCP tCAS tCPN
tCRP
tCAH
tASC tASC tCAH tASC
Row Column 1
tDS
WE
Column 2 Column N
tWCH tWCS tWCH tWCS tWCH
tDH tDS tDH tDS tDH
DIN 1DIN 2DIN N
tTtCSH
Document:1G5-0187 Rev.2 Page 21
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
• EDO Page Mode Read-Early-Write Cycle
tRASP
tCPRH
tRCS
tCAS
tRSH
tRCD
tOEA
tCSH
RAS
CAS
tASR tRAH tCAH
ADDRESS
tCAS
WE
tCRP tCP
OE
DQ1~DQ4 OPEN
tWED
tPC
tCP tCAS tCPN
tCRP
tRAD
tRAH
tASC tASC tCAH tASC
tRAL
Row Column 1
tWCS
tRCH
tRAC
tAA tAA
tCPA
tDH
tWHZ
tCAC
tCAC
tCOH
WE
OE
Column 2 Column N Row
tRP
tCAL
tWCH
Data
Doutput 2
Data
Input N
Data
Doutput 1
tDS
tCSH
Document:1G5-0187 Rev.2 Page 22
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
• EDO Page Mode Read-Modify-Write Cycle
tRASP
tCPRH
tRCS
tCAS
tWP
RAS
CAS
tASR
tRAH tCAH
ADDRESS
tCAS
WE
tRCD CP
DQ1~DQ4
tPRWC
tCP tCAS
tCRP
tRAD
tCAH
tASC tASC
tCAH
tASC
Row Column 1
tRWL
tRCS
tOED
tDZO
tCAC
WE
OE
tRP
tRAL
DOUT 2 DOUT N
DOUT 1
tT
t
Column NColumn 2Column 1
tRWD
tAWD
tCWD
tCWL
tRCS tCWD
tAWD
tCPW tCWL tCPW
tAWD
tCWD
tCWL
tOED tOED
tOEH tOEH tOEH
tCAC
tCAC
tOEA
tAA
tRAC tOEZ
tOEA
tAA
tCPA tOEZ
tOEA
tAA
tCPA tOEZ
tDS
tDH
tWP
tDS
tDH
tWP
tDS
tDH
OPEN OPEN OPEN
DIN 1 DIN N
DIN 2
DQ1~DQ4
tDZC
tDZO
tDZC tDZC
tDZO
Document:1G5-0187 Rev.2 Page 23
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
• Read Cycle with WE Controlled Disable
tWPZ
tRCS
tCAS
tRCD
tT
tCSH
RAS
CAS
tASR tRAH tCAH
ADDRESS Column
Row
tASC
D
DQ1~DQ4
WE
tOEZ
tDS
tWHZ
OE
tRCH
tOEA
tCAC
tAA
tRAC
tCLZ OUT
tRAD
Document:1G5-0187 Rev.2 Page 24
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
RAS-Only Refresh Cycle
RAS
ADDRESS
tRC
tCRP
tASR tRAH
tT
tRPC
ROW
tOFF
CAS
tRAS tRP
OPEN
tCRP
DQ1~DQ4
RAS
tCSR
tWSR
tRP
tTtRPC
tOFF
CAS
tRAS tRP
OPEN
tCRP
DQ1~DQ4
tRPC
tCHR
tRAS tRP
tRC tRC
tCHR
tCSR
tWHR tWSR tWHR
WE
CAS-Before-RAS Refresh Cycle
Document:1G5-0187 Rev.2 Page 25
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
CBR Self-Refesh Cycle
RAS
WE
tRPC
tOFF
tCSR tCHS
tWSR
CAS
tRASS tRPS
OPEN
DQ1~DQ4
tWHR
High lmpedance
Document:1G5-0187 Rev.2 Page 26
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
• Hidden Refresh Cycle
tRP
tRAS
RAS
tRCD
tCRP
ADDRESS
WE
tCHR
tCAS
tRSH
tRAH
tASR tASC tCAH
tRAL
ROW
tRCH
tOEZ
CAS
DQ1~DQ4
tT
t RCS
D
tRAS
tRAS tRP
tRP
tRC tRC tRC
tRAD
tRRH
tOFF
tOFF
tOEA
tCAC
tAA
tRAC
COlumn
OUT
OE
(READ) (REFRESH) (REFRESH)
Document:1G5-0187 Rev.2 Page 27
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Ordering information
VG26(V)(S) 17405FJ-5
• VG • VIS Memory Product
• 26 • Technology
• V • 3.3V Version
• S • Self refresh
• 17405 • Device Type and Configuation
• F • Revision
• J • Package Type (J : SOJ, T : TSOP II)
• L • None: normal version, L: low power version
• 5 • Speed (5 : 50 ns, 6 : 60 ns)
Part Number Access time Package
VG26(V)(S)17405FJ(L)-5
VG26(V)(S)17405FJ(L)-6
50 ns
60 ns
300mil 26/24-Pin
Plastic SOJ
VG26(V)(S)17405FT(L)-5
VG26(V)(S)17405FT(L)-6
50 ns
60 ns
300mil 26/24-Pin
TSOP II
Packaging information
• 300 mil, 26/24-Pin Plastic SOJ
SEATING PLANE
4-e
e
b
b2
0.007"M
C
L
0.025" MIN.
0.004"
SECTION B-B
E2
A
RAD R1
A1 B
B
D
26 21
E
E1
19 14
BASE METAL
WITH PLATING
c1 c
b1
b
0.267 BASIC
0.335 BASIC
0.050 BASIC
R1
e
E1
E2 6.78 BASIC
1.27 BASIC
0.76 ---
7.49 7.62
1.02 0.030
7.75 0.295
17.02
b
D
E
c1
b2
c
b1
A1
A
DIM
0.510.41 0.016
8.51 BASIC
0.18
17.15
---
0.66
0.18
0.41 ---
---
0.46
17.27
0.28
0.670
0.007
0.81
0.30
0.48
0.007
0.026
0.016
MILLIMETERS
MIN. NOM.
2.08
3.25 ---
---
3.51
MAX. MIN.
---
3.76 0.082
0.128
0.305
0.040---
0.300
0.020
0.032
0.019
0.012
0.680
0.011
0.675
---
0.018
---
---
MAX.
0.148
---
NOM.
---
0.138
---
INCHES
2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.
MOLD PROTRUSION SHALL NOT EXCEED 0.006"(0.15mm) PER SIDE.
INTERLEAD PROTRUSION SHALL NOT EXCEED 0.01"(0.25mm) PER SIDE.
1. CONTROLLING DIMENSION : INCHES
NOTE:
3. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION OR
TO LESS THAN 0.001"(0.025mm) BELOW b2 MIN.
DAMBAR INTRUSION SHALL NOT REDUCE THE SHOULDER WIDTH
SHOULDER WIDTH TO EXCEED b2 MAX BY MORE THAN 0.005"(0.127mm)
INTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE
1 6 8 13
A2
A2 2.54 REF. 0.100 REF.
Document:1G5-0187 Rev.2 Page 28
VIS
VG26(V)(S)17405F
4,194,304 x 4 - Bit
CMOS Dynamic RAM
• 300 mil, 26/24-Pin TSOP II
D
(ZD)
bM
REF.
4-1.27
6 81
26 1921
RAD R1
A2
E
E1
SEATING PLANE
0.100(0.004")
e
A
RAD R
A1 L
DETAIL A
13
DETAIL A
0 ~5
Bc
B
14
bSECTION B-B
BASE METAL
WITH PLATING
b1
c
c1
0.0240.0200.60 0.0160.40 0.50
L
0.12
0.12
R
R1 ------
--- 0.25 0.005
0.005 ---
0.010
---
---
0.0374 BASIC
0.050 BASIC
0.16 0.005c1 0.12 0.15
17.01
9.02
7.49
e
E1
E
D
ZD
1.27 BASIC
7.62
9.22
7.75
9.42 0.355
0.295
17.2717.14
0.95 REF.
0.670
0.95
0.05
0.12
0.30
0.30
c
b1
A2
A1
b
---
0.40
0.21
0.45
0.005
0.012
1.00
---
---
1.05
0.15
0.037
0.002
0.012
0.52
(0.006)
0.006
0.305
0.371
0.300
0.363
0.680
0.675
0.008
0.018
---
0.016
0.041
0.006
0.020
0.039
---
---
---A
DIM MIN.
---
NOM.
MILLIMETERS
1.20
MAX.
---
MIN.
0.047
MAX.
---
INCHES
NOM.
0.200(0.008")
ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION.
INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25(0.01") PER SIDE.
MOLD PROTRUSION SHALL NOT EXCEED 0.15(0.006") PER SIDE.
2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.
1. CONTROLLING DIMENSION : MILLIMETERS
NOTE:
THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.
DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER
BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.
