VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM Description The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only or 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. Self-Refresh is supported and CBR cycles are being performed. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOPII. Features * Single 5V( 10 %) or 3.3V(3.15V~3.6V) only power supply * High speed tRAC access time: 50/60ns * Extended - data - out(EDO) page mode access * I/O level: TTL compatible (Vcc = 5V) LVTTL compatible (Vcc = 3.3V) * 4 refresh modes: - RAS only refresh - CAS - before - RAS refresh - Hidden refresh - Self-refresh * Refresh interval: - RAS only refresh, CAS - before - RAS refresh and hidden refresh: 2048 cycles in 32ms - Self-refresh: 2048 cycles * JEDEC standard pinout: 26/24-pin plastic SOJ and TSOPII. Document:1G5-0187 Rev.2 Page 1 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM Pin Configuration 26/24-PIN 300mil Plastic SOJ 26/24-PIN 300mil Plastic TSOP (ll) 26 VSS VCC 1 26 VSS DQ1 2 3 25 DQ4 DQ3 DQ1 2 3 25 DQ4 DQ3 DQ2 WE RAS 4 5 NC 6 A10 8 A0 A1 9 A2 A3 11 VCC 10 12 13 24 21 CAS OE A9 19 A8 23 22 18 17 16 15 14 DQ2 WE RAS A7 A6 A5 A4 5 NC 6 A10 8 A0 A1 9 A2 A3 11 VCC VSS 4 10 12 13 VG26(V)(S)17405T 1 VG26(V)(S)17405J VCC 24 21 CAS OE A9 19 A8 18 17 16 15 14 A7 A6 23 22 Pin Description Pin Name A0-A10 Function Address inputs - Row address - Column address - Refresh address DQ1~DQ4 Data-in / data-out RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable Vcc Power (+5 V or + 3.3V) Vss Ground Document:1G5-0187 A0-A10 A0-A10 A0-A10 Rev.2 Page 2 A5 A4 VSS VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM Block Diagram WE CONTROL LOGIC CAS DATA-IN BUFFER DQ1 . . DQ4 NO. 2 CLOCK GENERATOR DATA-OUT BUFFER OE COLUMN ADDRESS BUFFERS (11) COLUMN DECODER A0 A1 A2 A3 2048 REFRESH CONTROLLER A4 SENSE AMPLIFIERS I/O GATING A5 A6 REFRESH COUNTER 2048x4 A7 A8 RAS ROW ADDRESS BUFFERS (11) 2048 A10 ROW DECODER A9 2048x2048x4 MEMORY ARRAY Vcc NO. 1 CLOCK GENERATOR Document:1G5-0187 Vss Rev.2 Page 3 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM TRUTH TABLE ADDRESSES FUNCTION RAS CAS WE OE ROW COL STANDBY H H(R)X X X X X READ L L H L ROW COL Data-Out WRITE: (EARLY WRITE ) L L L X ROW COL Data-ln READ WRITE L L H(R)L L(R)H ROW COL Data-Out,Data-ln 1st Cycle L H(R)L H L ROW COL Data-Out 2nd Cycle L H(R)L H L n/a COL Data-Out EDO-PAGE 1st Cycle MODE WRITE 2nd Cycle L H(R)L L X ROW COL Data-In L H(R)L L X n/a COL Data-In EDOPAGE-MODE READ-WRITE 1st Cycle L H(R)L H(R)L L(R)H ROW COL Data-Out, Data-In 2nd Cycle L H(R)L H(R)L L(R)H n/a COL Data-Out, Data-In HIDDEN REFRESH READ L(R)H(R)L L H L ROW COL Data-Out WRITE L(R)H(R)L L L X ROW COL Data-In L H X X ROW n/a High-Z H(R)L L H X X X High-Z EDO-PAGEMODE READ RAS-ONLY REFRESH CBR REFRESH DQS Notes High-Z 1 Notes: 1. EARLY WRITE only. Document:1G5-0187 Rev.2 Page 4 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM Absolute Maximum Ratings Parameter Symbol 5V Voltage on any pin relative to Vss Value Unit -1.0 to + 7.0 V VT 3.3V -0.5 to + 4.6 5V -1.0 to + 7.0 Supply voltage relative to Vss V VCC 3.3V -0.5 to + 4.6 Short circuit output current IOUT 50 mA PD 1.0 W Operating temperature TOPT 0 to + 70 C Storage temperature TSTG -55 to + 125 C Power dissipation Recommended DC Operating Conditions Parameter/Condition Symbol 5 Volt Version Min Typ Supply Voltage VCC 4.5 Input High Voltage, all inputs VIH 2.4 Input Low Voltage, all inputs VIL -1.0 3.3 Volt Version Max 5.0 Min Typ 5.5 3.15 - VCC + 1.0 2.0 - 0.8 -0.3 Unit Max 3.3 3.6 V - VCC + 0.3 V - V 0.8 Capacitance Ta = 25C, VCC = 5V or 3.3V, f = 1MHz Parameter Symbol Typ Max Unit Note Input capacitance (Address) CI1 - 5 pF 1 Input capacitance (RAS, CAS, OE, WE) CI2 - 7 pF 1 Output capacitance (Data-in, Data-out) CI/O - 7 pF 1, 2 Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, CAS = VIH to disable Dout. Document:1G5-0187 Rev.2 Page 5 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM DC Characteristics; 5- Volt Verion (Ta = 0 to + 70 C, VCC= + 5V 10 %,VSS = 0V) Parameter Symbol Test Conditions VG26(V)(S)17405 -5 Unit Notes 1, 2 -6 Min Max Min Max Operating current ICC1 RAS cycling CAS cycling tRC = min - 120 - 110 mA Standby Current ICC2 TTL interface RAS, CAS = VIH Dout = High-Z - 2 - 2 mA 1 - 1 mA CMOS interface RAS, CAS Vcc -0.2V Dout = High-Z RAS-only refresh current ICC3 RAS cycling, CAS = VIH tRC = min - 120 - 110 mA 1, 2 EDO page mode current ICC4 tPC = min - 140 - 130 mA 1, 3 CAS-before-RAS refresh current ICC5 tRC = min RAS, CAS cycling - 120 - 110 mA 1, 2 Self-refresh current ICC8 t RAS 100ms 600 mA 4 350 mA 5 600 t RAS 100ms (low power ver- - 350 - sion) Notes: 1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For ICC4, address can be changed once or less within one EDO page mode cycle time. 4. Normal version: VG26S17405FT, VG26S17405FJ 5. Low power version: VG26S17405FTL, VG26S17405FJL Document:1G5-0187 Rev.2 Page 6 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM DC Characteristics ; 5-Volt Version (Cont.) (Ta = 0 to + 70C, VCC = + 5V 10 %,VSS = 0V) VG26(V)(S)17405 -5 Parameter Symbol Test Conditions Min -6 Max Min Max Unit Input leakage current ILI 0V V IN V CC + 0.5V -5 5 -5 5 mA Output leakage current ILO 0V V OUT V CC + 0.5V Dout = Disable -5 5 -5 5 mA Output high Voltage VOH IOH = - 5mA 2.4 - 2.4 - V Output low voltage VOL IOL = + 4.2mA - 0.4 - 0.4 V Document:1G5-0187 Rev.2 Page 7 Notes VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM DC Characteristics ; 3.3 - Volt Version (Ta = 0 to 70C, VCC = + 3.3V(3.15V~3.6V), VSS = 0V) Parameter Symbol Test Conditions VG26(V)(S)17405 -5 Unit Notes 1, 2 -6 Min Max Min Max Operating current ICC1 RAS cycling CAS cycling tRC = min - 120 - 110 mA Standby Current ICC2 LVTTL interface RAS, CAS = VIH Dout = High-Z - 2 - 2 mA CMOS interface - 0.5 - 0.5 mA RAS, CAS V CC -0.2V Dout = High-Z RAS- only refresh current ICC3 RAS cycling, CAS = VIH tRC = min - 120 - 110 mA 1, 2 EDO page mode current ICC4 tPC = min - 90 - 80 mA 1, 3 CAS- before- RAS refresh current ICC5 tRC = min RAS, CAS cycling - 120 - 110 mA 1, 2 Self- refresh current ICC8 550 mA 4 350 mA 5 t RAS 100ms 550 t RAS 100ms (low power - 350 - version) Notes: 1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For ICC4, address can be changed once or less within one EDO page mode cycle time. 4. Normal version: VG26VS17405FT, VG26VS17405FJ 5. Low power version: VG26VS17405FTL, VG26VS17405FJL Document:1G5-0187 Rev.2 Page 8 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM DC Characteristics ; 3.3 - Volt Version (Cont.) (Ta = 0 to 70C, VCC= +3.3V(3.15V~3.6V), VSS= 0V) VG26(V)(S)17405 -5 Parameter Symbol Test Conditions Min Unit -6 Max Min Max Input leakage current ILI 0V Vin VCC + 0.3V -5 5 -5 5 mA Output leakage current ILO 0V Vout V CC + 0.3V -5 5 -5 5 mA Dout = Disable Output high Voltage VOH IOH = -2mA 2.4 - 2.4 - V Output low voltage VOL IOL = +2mA - 0.4 - 0.4 V Document:1G5-0187 Rev.2 Page 9 Notes VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM AC Characteristics (Ta = 0 to + 70C, Vcc = 5V or 3.3V, Vss = 0V) *1, *2, *3, *4 Test conditions * Output load: two TTL Loads and 100pF (VCC = 5.0V 10 %) one TTL Load and 100pF (VCC = 3.3V(3.15V~3.6V) ) * Input timing reference levels: VIH = 2.4V, VIL = 0.8V (VCC = 5.0V 10 %); VIH = 2.0V, VIL = 0.8V (VCC = 3.3V(3.15V~3.6V) ) * Output timing reference levels: VOH = 2.0V, VOL = 0.8V (VCC = 5V 10 %, 3.3V(3.15V~3.6V) ) Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters) VG26(V)(S) 17405 -5 Parameter Symbol Min Unit Notes -6 Max Min Max Random read or write cycle time tRC 84 - 104 - ns RAS precharge time tRP 30 - 40 - ns CAS precharge time in normal mode tCPN 10 - 10 - ns RAS pulse width tRAS 50 10000 60 10000 ns 5 CAS pulse width tCAS 8 10000 10 10000 ns 6 Row address setup time tASR 0 - 0 - ns Row address hold time tRAH 8 - 10 - ns Column address setup time tASC 0 - 0 - ns Column address hold time tCAH 8 - 10 - ns RAS to CAS delay time tRCD 12 37 14 45 ns 8 RAS to column address delay time tRAD 10 25 12 30 ns 9 Column address to RAS lead time tRAL 25 - 30 - ns RAS hold time tRSH 8 - 10 - ns CAS hold time tCSH 38 - 40 - ns CAS to RAS precharge time tCRP 5 - 5 - ns OE to Din delay time tOED 20 - 20 - ns tT 1 50 1 50 ns Refresh period tREF - 32 - 32 ms CAS to output in Low- Z tCLZ 0 - 0 - ns CAS delay time from Din tDZC 0 - 0 - ns OE delay time from Din tDZO 0 - 0 - ns Transition time (rise and fall) Document:1G5-0187 Rev.2 7 10 11 Page 10 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM Read Cycle VG26(V)(S)17405 -5 Parameter Min Symbol Unit Notes -6 Max Min Max Access time from RAS tRAC - 50 - 60 ns 12 Access time from CAS tCAC - 14 - 15 ns 13, 14 tAA - 25 - 30 ns 14, 15 Access time from OE tOEA - 12 - 15 ns Read command setup time tRCS 0 - 0 - ns 7 Read command hold time to CAS tRCH 0 - 0 - ns 10, 16 Read command hold time to RAS tRRH 0 - 0 - ns 16 Output buffer turn-off time tOFF 0 12 0 15 ns 17 Output buffer turn-off time from OE tOEZ 0 12 0 15 ns 17 Unit Notes 7, 18 Access time from column address Write Cycle VG26(V)(S)17405 -5 Parameter Symbol Min -6 Max Min Max Write command setup time tWCS 0 - 0 - ns Write command hold time tWCH 8 - 10 - ns Write command pulse width tWP 8 - 10 - ns Write command to RAS lead time tRWL 13 - 15 - ns Write command to CAS lead time tCWL 8 - 10 - ns Data-in setup time tDS 0 - 0 - ns 19 Data-in hold time tDH 8 - 10 - ns 19 tWED 10 - 10 - ns WE to Data-in delay Read- Modify- Write Cycle VG26(V)(S) 17405 -5 Parameter Symbol Min Unit Notes -6 Max Min Max Read-modify- write cycle time tRWC 108 - 133 - ns RAS to WE delay time tRWD 64 - 77 - ns 18 CAS to WE dealy time tCWD 26 - 32 - ns 18 Column address to WE delay time tAWD 39 - 47 - ns 18 OE hold time from WE tOEH 8 - 10 - ns Document:1G5-0187 Rev.2 Page 11 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM Refresh Cycle VG26(V)(S)17405 -5 Parameter -6 Min Symbol Max Min Max Unit Notes CAS setup time (CBR refresh) tCSR 5 - 5 - ns CAS hold time (CBR refresh) tCHR 8 - 10 - ns 10 RAS precharge to CAS hold time tRPC 5 - 5 - ns 7 RAS pulse width (self refresh) tRASS 100 - 100 - ms RAS precharge time (self refresh) tRPS 90 - 110 - ns CAS hold time (CBR self refresh) tCHS -50 - -50 - ns WE setup time tWSR 0 - 0 - ns WE hold time tWHR 10 - 10 - ns EDO Page Mode Cycle VG26(V)(S) 17405 -5 Parameter Symbol -6 Min Max Min Max Unit Notes EDO page mode cycle time tPC 20 - 25 - ns EDO page mode CAS precharge time tCP 10 - 10 - ns EDO page mode RAS pulse width tRASP 50 105 60 105 ns 20 Access time from CAS precharge tCPA - 30 - 35 ns 10, 14 RAS hold time from CAS precharge tCPRH 30 - 35 - ns OE high hold time from CAS high tOEHC 5 - 5 - ns OE high pulse width tOEP 10 - 10 - ns Data output hold time after CAS low tCOH 5 - 5 - ns Output disable delay from WE tWHZ 3 10 3 10 ns WE pulse width for output disable when CAS high tWPZ 10 - 10 - ns Document:1G5-0187 Rev.2 Page 12 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM EDO Page Mode Read Modify Write Cycle VG26(V)(S)17405 -5 Parameter Symbol -6 Min Max Min Max Unit Notes 10 EDO page mode read- modify- write cycle CAS precharge to WE delay time tCPW 45 - 55 - ns EDO page mode read- modify- write cycle time tPRWC 56 - 68 - ns Document:1G5-0187 Rev.2 Page 13 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM Notes : 1. AC measurements assume tT = 1ns. 2. An initial pause of 100 ms is required after power up, and it is followed by a minimum of eight initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required. 3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 4. All the VCC and VSS pins shall be supplied with the same voltages. 5. tRAS(min) = tRWD(min)+tRWL(min)+tT in read-modify-write cycle. 6. tCAS(min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle. 7. tASC(min), tRCS(min), tWCS(min), and tRPC are determined by the falling edge of CAS . 8. tRCD(max) is specified as a reference point only, and tRAC(max) can be met with the tRCD(max) limit. Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit. 9. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit. Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit. 10. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the rising edge of CAS . 11. VIH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition time is measured between VIH and VIL. 12. Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 13. Assumes that t RCD t RCD (max) and t RAD t RAD (max). 14. Access time is determined by the maximum of tAA, tCAC, tCPA. 15. Assumes that t RCD t RCD (max) and t RAD t RAD (max). 16. Either tRCH or tRRH must be satisfied for a read cycle. 17. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high impedance). tOFF is determined by the later rising edge of RAS or CAS. 18. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS t WCS (min), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If t RWD t CWD t CWD (min), t AWD t AWD (min) and t CPW t RWD (min), t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate. 19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in a delayed write or a read-modify-write cycle. 20. tRASP defines RAS pulse width in EDO page mode cycles. Document:1G5-0187 Rev.2 Page 14 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM Timing Waveforms * Read Cycle t RC t t RP RAS RAS t CRP t CSH t RCD t RSH t T t CPN t CAS CAS t RAL t RAD t ASR ADDRESS t ASC t RAH t CAH Column Row t RRH t RCH t RCS WE OE t OEA t CAC t OEZ t OFF t AA t OFF t RAC D OUT DQ1~DQ4 t CLZ Note : = don't care = Invalid Dout Document:1G5-0187 Rev.2 Page 15 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM *Early Write Cycle t RC t RAS t RP RAS t CRP t CSH t RCD t RSH t T t CAS t CPN CAS t RAD t ASR ADDRESS t RAH t RAL t ASC Row t CAH Column t RAL t WCS t WCH WE t DS DQ1~DQ4 Document:1G5-0187 t DH D IN Rev.2 Page 16 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM * Delayed Write Cycle t RC t t RP RAS RAS t CSH t CRP t RCD t RSH t T t CPN t CAS CAS t ASR ADDRESS Row t RAH t CAH t ASC Column t CWL t RCS t RWL t WP WE t OED OE t OEH t DS t DS DQ1~DQ4 Document:1G5-0187 OPEN t DH DIN Rev.2 Page 17 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM * Read - Modify - Write Cycle t RWC t t RP RAS RAS t T t RCD t CAS t CRP t CPN CAS t RAD t ASR ADDRESS t ASC t RAH Row t CAH Column t RCS t CWL t RWL t CWD t AWD t RWD t WP WE t DZC t DH t DS OPEN DQ1~DQ4 t DZO DIN t OED t OEH OE t RAC t OEA t CAC t AA t OEZ DQ1~DQ4 Document:1G5-0187 DOUT Rev.2 Page 18 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM * EDO Page Mode Read Cycle t RP t RASP t CPRH RAS t CRP t PC t CSH t RCD t CRP t CAS t CAS t CP t RSH t CAS t CP t CPN CAS t RAD t ASR ADDRESS t RAL t ASC t RAH Row t CAH Column 1 t ASC t ASC t CAH t CAH Column N Column 2 t RRH t RCH t RCS WE Row WE t OEHC t OEA t OEP t OEA OE OE t RAC t CPA t CPA t AA t AA t OEZ t AA t OFF t OEZ t CAC t CAC t CAC t OFF t COH DQ1~DQ4 DOUT 1 DOUT N DOUT 2 Document:1G5-0187 Rev.2 Page 19 OPEN VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM * EDO Page Mode Early Write Cycle t t RP RASP RAS tT t CSH t RSH t CAS t PC t RCD t CAS t CAS t CP t CP t CRP t CPN CAS t ASR ADDRESS Row t RAH t ASC t CAH Column 1 t WCS WE Document:1G5-0187 t WCH t CAH Column 2 t ASC t CAH Column N t WCS t WCH t WCS t WCH t DS t DH t DS t DH WE t DS DQ1~DQ4 t ASC t DH DIN 2 DIN 1 Rev.2 DIN N Page 20 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM * EDO Page Mode Read-Early-Write Cycle t t RP RASP t CPRH RAS t CRP t PC t CSH t RCD t CRP t CAS t CAS t CP t RSH t CAS t CP t CPN CAS t CAL t CSH t RAD t ASR ADDRESS t RAL t ASC t RAH Row t RAH t ASC t CAH Column N Column 2 Column 1 t RCH t RCS WE t ASC t CAH Row t WCS t WCH WE t OEA t WED OE OE t RAC t CPA t AA t AA t WHZ t CAC t CAC t DH t DS t COH DQ1~DQ4 OPEN Data Doutput 1 Data Doutput 2 Data Input N Document:1G5-0187 Rev.2 Page 21 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM * EDO Page Mode Read-Modify-Write Cycle t RASP tCPRH t RP RAS t T t RCD t CP t CAS t PRWC t CRP t CP t CAS t CAS CAS t RAD t ASR t ASC t RAH ADDRESS t ASC t CAH Column 2 t CWL t RWD t AWD t CWD WE t CAH t CAH Column 1 Column 1 Row t RAL t ASC t RCS Column N t CWL t CPW t AWD t CWD t RCS t t CWL CPW t AWD t CWD t RWL WE t RCS t WP t WP t DZC t DS t DZC t DS t DH OPEN DQ1~DQ4 t WP t DZC DIN 1 t DH OPEN DIN 2 t DZO t DH OPEN DIN N t DZO t DZO t OED t OED t DS t OEH t OEH t OED t OEH OE t OEA t OEA t CAC t CAC t RAC t AA t CPA t AA t CPA t AA t OEA t CAC t OEZ t OEZ t OEZ DQ1~DQ4 DOUT 1 Document:1G5-0187 DOUT Rev.2 2 DOUT N Page 22 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM * Read Cycle with WE Controlled Disable RAS t CSH t RCD t CAS t T CAS t RAD t ASR ADDRESS t ASC t RAH Row t CAH Column t RCH t RCS t WPZ WE t WHZ t DS OE tOEA tCAC tOEZ tAA tRAC DQ1~DQ4 DOUT tCLZ Document:1G5-0187 Rev.2 Page 23 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM RAS-Only Refresh Cycle t RC t RP t RAS RAS tT tRPC t CRP tCRP CAS tASR ADDRESS tRAH ROW tOFF OPEN DQ1~DQ4 CAS-Before-RAS Refresh Cycle tRC tRP RAS tRC tRAS tT t RAS tRP tRPC tRPC t RP tCRP t CSR t CHR tCSR tCHR tWSR tWHR tWSR tWHR CAS WE tOFF OPEN DQ1~DQ4 Document:1G5-0187 Rev.2 Page 24 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM CBR Self-Refesh Cycle t RPS t RASS RAS t RPC tCSR CAS tCHS tOFF High lmpedance DQ1~DQ4 tWSR tWHR OPEN WE Document:1G5-0187 Rev.2 Page 25 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM * Hidden Refresh Cycle t RC t RC t RC t RP tRAS (READ) tRAS t RP (REFRESH) tRAS t RP (REFRESH) RAS tT t CHR tCRP t RSH tRCD tCAS CAS t RAD t ASR ADDRESS t RAH t RAL tASC tCAH COlumn ROW tRRH t RCS tRCH WE OE t OEZ t OEA t CAC t OFF t AA t OFF t RAC D OUT DQ1~DQ4 Document:1G5-0187 Rev.2 Page 26 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM Ordering information Part Number Access time Package VG26(V)(S)17405FJ(L)-5 50 ns 300mil 26/24-Pin VG26(V)(S)17405FJ(L)-6 60 ns Plastic SOJ VG26(V)(S)17405FT(L)-5 50 ns 300mil 26/24-Pin VG26(V)(S)17405FT(L)-6 60 ns TSOP II VG26(V)(S) 17405FJ-5 * VG * VIS Memory Product * 26 * Technology *V * 3.3V Version *S * Self refresh * 17405 * Device Type and Configuation *F * Revision *J * Package Type (J : SOJ, T : TSOP II) *L * None: normal version, L: low power version *5 * Speed (5 : 50 ns, 6 : 60 ns) Packaging information * 300 mil, 26/24-Pin Plastic SOJ D DIM MILLIMETERS MIN. NOM. MAX. 3.51 3.76 ----2.54 REF. b INCHES MIN. NOM. MAX. A A1 A2 3.25 2.08 0.128 0.082 b 0.41 --- 0.51 0.016 b1 b2 0.41 0.66 0.46 --- 0.48 0.81 0.016 0.026 c c1 D E E1 E2 e R1 0.18 0.18 17.02 --0.30 --0.28 17.15 17.27 8.51 BASIC 7.49 7.62 7.75 6.78 BASIC 1.27 BASIC 0.76 --1.02 0.007 0.007 0.670 21 26 19 14 b1 0.138 0.148 ----0.100 REF. --0.018 ------- c1 c E1 0.020 E BASE METAL 0.019 0.032 WITH PLATING 0.012 0.011 0.675 0.680 0.335 BASIC 0.295 0.300 0.305 0.267 BASIC 0.050 BASIC 0.030 --0.040 1 6 8 13 SECTION B-B CL 0.025" MIN. A2 B B A A1 NOTE: 1. CONTROLLING DIMENSION : INCHES 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.006"(0.15mm) PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.01"(0.25mm) PER SIDE. 3. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE SHOULDER WIDTH TO EXCEED b2 MAX BY MORE THAN 0.005"(0.127mm) DAMBAR INTRUSION SHALL NOT REDUCE THE SHOULDER WIDTH TO LESS THAN 0.001"(0.025mm) BELOW b2 MIN. Document:1G5-0187 RAD R1 e b2 b 4-e 0.004" E2 SEATING PLANE 0.007" M Rev.2 Page 27 VIS VG26(V)(S)17405F 4,194,304 x 4 - Bit CMOS Dynamic RAM * 300 mil, 26/24-Pin TSOP II DIM MILLIMETERS MIN. NOM. INCHES NOM. RAD R1 MAX. MIN. --- --- 1.20 --- A1 0.05 --- 0.15 A2 0.95 1.00 1.05 b 0.30 --- 0.52 0.012 b1 0.30 0.40 0.45 0.012 0.016 0.018 c 0.12 --- 0.21 0.005 --- 0.008 c1 0.12 0.15 0.16 0.005 D 17.01 17.14 17.27 0.670 A MAX. --- 0.047 0.002 --- 0.006 0.037 0.039 0.041 --- 0.020 0.006 (0.006) 0.675 0.680 ZD 0.95 REF. 0.0374 BASIC e 1.27 BASIC 0.050 BASIC 21 19 14 RAD R A2 c B E1 E B A1 DETAIL A L 0 ~5 b 1 6 8 b1 13 SECTION B-B D E 9.02 9.22 9.42 0.355 0.363 0.371 E1 7.49 7.62 7.75 0.295 0.300 0.305 L 0.40 0.50 0.60 0.016 0.020 0.024 R 0.12 --- 0.25 0.005 --- 0.010 R1 0.12 --- --- 0.005 --- --- NOTE: 1. CONTROLLING DIMENSION : MILLIMETERS 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15(0.006") PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25(0.01") PER SIDE. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm. DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER THAN THE MIN b DIMENSION BY MORE THAN 0.07mm. Document:1G5-0187 26 c1 c BASE METAL WITH PLATING DETAIL A (ZD) A 4-1.27 REF. b e SEATING PLANE 0.200(0.008") M Rev.2 0.100(0.004") Page 28