1
TM
August 1997
HI1171
8-Bit, 40 MSPS, High Sp ee d D/A Converter
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . 40MHz
• Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit
• Integral Linearity Error . . . . . . . . . . . . . . . . . . 0.25 LSB
• Low Glitch Noise
• Single Suppl y Operation. . . . . . . . . . . . . . . . . . . . . .+5V
• Low Power Consumption (Max) . . . . . . . . . . . . . .80mW
• Evaluation Board Available (HI 1171-EV)
• Direct Replacement for the Sony CXD1171
Applications
• Wireless Telecommunications
• Signal Reconstruction
• Direct Digital Synthesis
• Imaging
• Presentati on and Broadcast Vide o
• Graphics Displays
• Signal Generators
Description
The HI1171 is an 8-bit, 40MHz, high speed D/A converter.
The conver ter incorporat es an 8-bit input data regist er with
blanking capability, and current outputs. The HI1171 fea-
tures low glitch outputs. The architecture is a current cell
arrangem ent t o provide l ow li neari ty er rors.
The HI1171 is available in an Ind ustrial temperature rang e
and is offered in a 24 lead ( 200 m il) SO IC plas tic package.
For dual version, please refer to the HI1177 Data Sheet.
For triple versi on, pl ease refer t o the HI1178 Dat a Shee t.
Ordering Information
PART
NUMBER TEMP. RANGE
(oC) PACKAGE PKG. NO.
HI1171JCB -40 to 85 24 Ld SOIC M24.2-S
HI 11 71- EV 25 Ev al ua tion B oa rd
Pinout
HI1171
(SOIC)
T OP VIEW
Typical Application Circuit
1
2
3
4
5
6
7
8
9
10
11
12
(LSB) D0
D1
D2
D3
D4
D5
D6
D7
BLNK
DVSS
VB
CLK
16
17
18
19
20
21
22
23
24
15
14
13
DVDD
AVDD
IOUT2
IOUT1
AVDD
VG
IREF
AVSS
DVSS
DVDD
AVDD
VREF
D7 (MSB)(8)
D6 (7)
D5 (6)
D4 (5)
D3 (4)
D2 (3)
D1 (2)
D0 (LSB) (1)
D7
D6
D5
D4
D3
D2
D1
D0
+5V
DVDD (23, 24)
0.1µF
DVSS (10, 13)
CLK (12)
BLNK (9)
+5V
0.1µF
(18, 19, 22) AVDD
(14) AVSS
D/A
(20) IOUT1
(21) IOUT2
(15) IREF
VB (11)
0.1µF3.3kΩ
200Ω
0.1µF
1kΩ
(17) VG
(16) VREF
HI1171
OUT
FN3662.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
2
Functi onal Block Diagram
DECODER
DECODER
8-BIT
LATCH
CLOCK
GENERATOR
6 MSBs
CURRENT
CELLS
CURRENT CELLS
(FOR FULL SCALE)
BIAS VOLTAGE
GENERATOR
2 LSBs
CURRENT
CELLS
+
-IREF
VREF
VG
IOUT1
IOUT2
(LSB) D0
D1
D2
D3
D4
D5
D6
(MSB) D7
BLNK
VB
CLK
HI1171
3
Absolute Maximum Ratings Thermal Information
Digital Supply Voltage DVDD to DVSS . . . . . . . . . . . . . . . . . . .+7.0V
Analog Supply Voltage AVDD to AVSS . . . . . . . . . . . . . . . . . .+7.0V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0mA to 15mA
Ope rat i ng Condi t io ns
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1) θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Maximum Junction Temperature, Plastic Package . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Solderin g 10s). . . . . . . . . . . . 300oC
(SOIC - Lead T ips Only)
CAUTIO N: Stresses abov e those listed i n “Abso lute Ma ximum Rati ngs” ma y cause pe rmanent dam age to the dev ice. T his is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is me asured wi th the component mounted on an evalua tion PC board in free air.
Electrical Specifications AVDD = +4.75V to +5.25V, DVDD = +4.75 to +5.25V, VREF = +2.0V, fS = 40MHz,
CLK Pulse Width = 12.5ns, TA = 25oC (N ot e 4)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
SYSTEM PERFORMANCE
Resolution, n -8-Bits
Integral Linearity Error, INL fS = 40MHz (End Point) -0.5 - 1.3 LSB
Differential Linearity Error, DNL fS = 40MHz - - ±0.25 LSB
Of fset Error, VOS (Note 2) - - 1 mV
Full Scale Error, FSE (Adjustable to Zero) (Note 2) - - ±13 LSB
Full Scale Outp ut Current, IFS -1015mA
Full Scale Outp ut Voltage, VFS 1.9 2.0 2.1 V
Ou tput Vol tage Ra ng e, VFSR 0.5 2.0 2.1 V
DYNAMIC CHARACTERISTICS
Throughput Rate See Figure 7 40.0 - - M Hz
Glitch Energy, GE ROUT = 75Ω-30- pV-s
Differential Gain, ∆AV (Note 3) - 1.2 - %
Differential Phase, ∆φ (Note 3) - 0.5 - Degree
REFERENCE INPUT
V ol tage R ef er e nc e Inp ut Ra ng e 0.5 - 2.0 V
Ref erence Input Resistance (Note 3) 1.0 - - MΩ
DIGITAL INPUTS
Input Logic High Voltage, VIH (Note 3) 3.0 - - V
Input Logic Low Voltage, VIL (Note 3) - - 1.5 V
Input Logic Current, IIL, IIH (Note 3) - - ±5.0 µA
Digital Input Capacitanc e, CIN (Note 3) - 5.0 - pF
TIMING CHARACTERISTICS
Data Setup Time, tSU See Figure 1 5 - - ns
Data Hold Time, tHLD See Figur e 1 10 - - ns
HI1171
4
Propagation Delay Time, tPD See Figure 9 - 10 - ns
Settling Time, tSET (to 1/2 LSB) See Figure 1 - 10 15 ns
CLK Pulse Width, tPW1, tPW2 See Figure 1 12.5 - - ns
POWER SUPPLY CHARACTERISITICS
IAVDD 14.3MHz, at Color Bar Data Input - 10.9 11.5 mA
IDVDD 14.3MHz, at Color Bar Data Input - 4.2 4.8 mA
Power Dissipation 200Ω load at 2VP-P Output - - 80 mW
NOTES:
2. Excludes error due to external reference drift.
3. Parameter guaranteed by design or characterization and not production tested.
4. Electrical specifications guaranteed only under the stated operating conditions.
Electrical Specifications AVDD = +4.75V to +5.25V, DVDD = +4.75 to +5.25V, VREF = +2.0V, fS = 40MHz,
CLK Pulse Width = 12.5ns, TA = 25oC (N ot e 4) (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Timing Diagram
FIGURE 1.
CLK
DATA
D/AOUT
100%
50%
0%
tPW1 tPW2
tSU
tHLD
tSU tSU
tPD
tPD tPD
tHLD tHLD
HI1171
5
Typical Performance Curves
FIGURE 2. OUTPUT FULL SCALE VOLTAGE vs REFERENCE
VOLTAGE FIGURE 3. OUTPUT RESISTANCE vs GLITCH ENERGY
FIGURE 4. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE
Pin D escr ipt ion s
24 PIN
SOIC PIN
NAME PIN DESCRIPTION
1-8 D0(LS B) t hru
D7(MSB) Digital Data Bit 0, the Least Significant Bit thru Digital Data Bit 7, the Most Significant Bit.
9 BLN K Blanking Line, used to clear the inter nal data register to the zero condition w hen High, normal op eration
when Low.
10, 13 DVSS Digital Ground.
11 VB Voltag e Bias, co nnec t a 0.1µF ca pac itor to D VSS.
12 CLK Data Clock Pin 100kHz to 40MHz.
14 AVSS Analog Ground.
15 IREF C urre nt R efer enc e, us ed t o set th e cu rren t ra nge . Co nnec t a resi st or to AVSS that is 16 times great er
than the resi stor on IOUT1. (See Typical Applications Circuit).
16 VREF Input Reference Voltage used to set the output full scale range.
2
1
12
VDD = 5.0V, R = 200Ω
16R = 3.3kΩ, TA = 25oC
OUTPUT FULL SCALE VOLTAGE (V)
REFERENCE VOLTAG E (V) 100 200
100
200
OUTPUT RESISTANCE (Ω)
GLITCH ENERGY (p V/s)
2.0
1.9
0-25 0 25 50 75
VDD = 5.0V, VREF = 2.0V
R = 200Ω, 16R = 3.3kΩ
TA = 25oC
OUTPUT FULL SCALE VOLTAGE (V)
AMBIENT TEMPERATURE (oC)
HI1171
6
All Intersil U.S. products are manuf actured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corpor ation’ s qualit y cert ifications can be viewed at www.inte rsil.com /design/q uality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes i n circuit des ign, s oftware and/or specifications at any time wi thout
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Inter sil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Detailed Description
The HI1171 is an 8-bit, current out D/A converter. The DAC
can convert at 40MHz and run on a single +5V supply. The
architecture is an encoded, switched current cell
arrangement.
Voltage Output Mode
The ou tput current of t he HI1171 ca n be co nverted into a vol t-
age by con necti ng an exte rnal r esist or to I OUT1. To c alcu late
the output resistor use the following equation:
ROUT = VFS /IFS,
where VFS can range from +0.5V to +2.0V and IFS can
range from 0mA to 15mA.
In setting the output current the IREF pin should have a resistor
connected to i t t hat is 16 times greater than the output r esistor :
RREF = 16 x ROUT
As the values of both ROUT and RREF increase, power
consumption is decreased, but glitch energy and output
settling time i s increased.
Clock Phase Relationship
The internal latch is closed when the clock line is high. The
latch can be cleared by the BLNK line. When BLNK is set
(HIGH) the contents of the internal data latch will be cleared.
When BLNK is low dat a is updated by the CLK.
Noise Reduction
To reduce power supply noise separate analog and digital
power supplies should be used with 0.1µF ceramic capaci-
tors placed as close to the body of the HI1171 as possible.
The analog (AVSS) and digi tal (DVSS) ground returns shoul d
be connected together back at the power supply to ensure
proper operation from power up.
17 VG Voltage Ground, connec t a 0.1µF capacitor to AVDD.
18, 19, 22 AVDD Analog Su pply 4. 75V to 7V.
20 IOUT1 Current Output Pin.
21 IOUT2 Current Output pin used for a virtual ground connection. Usually connected to AVSS.
23, 24 DV DD Digital Supply 4.75V to 7V.
Pin D escr ipt ion s (Continued)
24 PIN
SOIC PIN
NAME PIN DESCRIPTION
Test Circuits
FIGURE 5. MAXIMUM CONVERSION SPEED TEST CIRCUIT
OSCILLOSCOPE
8-BIT
WITH LATCH
CLK
40MHz
SQUARE WAV E
COUNTER
1
2
8
9
11
12 15
16
17
20
CLK
VB
0.1µF
BLK
D7
(LSB) D0 IO
VG
VREF
2V
IREF
AVDD
1kΩ
AVSS
3.3kΩ
200Ω
0.1µF
HI1171
7
FIGURE 6. DC CHARACTERISTICS TEST CIRCUIT
FIGURE 7. PROPAGATION DELAY TIME TEST CIRCUIT
FIGURE 8. SET UP HOLD TIME AND GLITCH ENERGY TEST CIRCUIT
Test Circuits (Continued)
DVM
CLK
40MHz
SQUARE WAVE
CONTROLLER
1
2
8
9
11
12 15
16
17
20
CLK
VB
0.1µF
BLK
D7
(LSB) D0 IO
VG
VREF
2V
IREF
AVDD
1kΩ
AVSS
3.3kΩ
200Ω
0.1µF
OSCILLOSCOPE
DEMULTIPLIER
CLK
10MHz
SQUARE WAVE
FREQUENCY
1
2
8
9
11
12 15
16
17
20
CLK
VB
0.1µF
BLK
D7
(LSB) D0 IO
VG
VREF
2V
IREF
AVDD
1kΩ
AVSS
3.3kΩ
200Ω
0.1µF
OSCILLOSCOPE
8-BIT
WITH LATCH
CLK
1MHz
SQUARE WAVE
COUNTER
1
2
8
9
11
12 15
16
17
20
CLK
VB
0.1µF
BLK
D7
(LSB) D0 IO
VG
VREF
2V
IREF
AVDD
1kΩ
AVSS
1.2kΩ
75Ω
0.1µF
DELAY
CONTROLLER
DELAY
CONTROLLER
HI1171
