SLLS447C - OCTOBER 2000 - REVISED AUGUST 2008 D Designed for TIA/EIA-485, TIA/EIA-422, D Driver Positive- and Negative-Current and ISO 8482 Applications Signaling Rates up to 30 Mbps Propagation Delay Times <11 ns Low Standby Power Consumption 1.5 mA Max Output ESD Protection 12 kV D D D D D D D Limiting Power-Up and Power-Down Glitch-Free for Live Insertion Applications Thermal Shutdown Protection Industry Standard Pin-Out, Compatible With SN75172, AM26LS31, DS96172, LTC486, and MAX3045 description The SN65LBC172A and SN75LBC172A are quadruple differential line drivers with 3-state outputs, designed for TIA/EIA-485 (RS-485), TIA/EIA-422 (RS-422), and ISO 8482 applications. 1A 1Y 1Z G 2Z 2Y 2A GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 logic diagram (positive logic) 16-DW PACKAGE (TOP VIEW) N PACKAGE (TOP VIEW) G VCC 4A 4Y 4Z G 3Z 3Y 3A 1 2 3 4 5 6 7 8 1A 1Y 1Z G 2Z 2Y 2A GND 16 15 14 13 12 11 10 9 VCC 4A 4Y 4Z G 3Z 3Y 3A G 1A 2A 3A 4A 20-DW PACKAGE (TOP VIEW) 1A 1Y NC 1Z G 2Z NC 2Y 2A GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 4 12 1 7 9 15 2 3 6 5 10 11 14 13 1Y 1Z 2Y 2Z 3Y 3Z 4Y 4Z logic diagram (positive logic) VCC 4A 4Y NC 4Z G 3Z NC 3Y 3A G G 1A 2A 3A 4A 5 15 1 9 11 19 2 4 8 6 12 14 18 16 1Y 1Z 2Y 2Z 3Y 3Z 4Y 4Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS is a trademark of Texas Instruments. The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). Copyright 2008 - 2003, Texas Instruments Incorporated !"# $ %&'# "$ (&)*%"# +"#', +&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$ $#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+' #'$#1 "** (""!'#'$, POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLLS447C - OCTOBER 2000 - REVISED AUGUST 2008 description (continued) These devices are optimized for balanced multipoint bus transmission at signalling rates up to 30 million bits per second. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. Each driver features current limiting and thermal-shutdown circuitry making it suitable for high-speed mulitpoint data transmission applications in noisy environments. These devices are designed using LinBiCMOSt, facilitating low power consumption and robustness. The G and G inputs provide driver enable control using either positive or negative logic. When disabled or powered off, the driver outputs present a high-impedance to the bus for reduced system loading. The SN75LBC172A is characterized for operation over the temperature range of 0C to 70C. The SN65LBC172A is characterized over the temperature range from -40C to 85C. AVAILABLE OPTIONS PACKAGE TA 16-PIN PLASTIC SMALL OUTLINE (JEDEC MS-013) SN75LBC172A16DW 0C to 70C 20-PIN PLASTIC SMALL OUTLINE (JEDEC MS-013) 16-PIN PLASTIC THROUGH-HOLE (JEDEC MS-001) SN75LBC172ADW SN75LBC172AN Marked as 75LBC172A SN65LBC172A16DW SN65LBC172ADW -40C to 85C Marked as 65LBC172A Add R suffix for taped and reeled version. FUNCTION TABLE (EACH DRIVER) INPUT ENABLES OUTPUTS A G G Y Z L H X L H L X L L H H H X H L H X L H L OPEN H X H L OPEN X L H L H OPEN X H L L OPEN X L H X L H Z Z X L OPEN Z Z H = high level, L = low level, X = irrelevant, Z = high impedance (off) 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN65LBC172AN SLLS447C - OCTOBER 2000 - REVISED AUGUST 2008 equivalent input and output schematic diagrams Y or Z Output A, G, or G Input VCC VCC 16 V 20 V 100 k 16 V 1 k Input Output 16 V 9V 17 V 16 V absolute maximum ratings Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V Output voltage range, VO, at any bus (steady state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10 V to 15 V Output voltage range, VO, at any bus (transient pulse through 100 , see Figure 8) . . . . . . . . . . . -30 V to 30 V Input voltage range, VI, at any A, G, or G terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Electrostatic discharge: Human body model (see Note 2) Y, Z, and GND . . . . . . . . . . . . . . . . . . . . . 12 kV All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 kV Charged-device model (see Note 3) All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to GND. 2. Tested in accordance with JEDEC standard 22, Test Method A114-A. 3. Tested in accordance with JEDEC standard 22, Test Method C101. PACKAGE 16-PIN DW 20-PIN DW 16-PIN N DISSIPATION RATING TABLE DERATING FACTOR ABOVE TA = 25C JEDEC BOARD MODEL TA 25C POWER RATING TA = 70C POWER RATING TA = 85C POWER RATING Low K 1200 mW 9.6 mW/C 769 mW 625 mW High K 2240 mW 17.9 mW/C 1434 mW 1165 mW Low K 1483 mW 11.86 mW/C 949 mW 771 mW High K 2753 mW 22 mW/C 1762 mW 1432 mW Low K 1150 mW 9.2 mW/C 736 mW 598 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SLLS447C - OCTOBER 2000 - REVISED AUGUST 2008 recommended operating conditions Supply voltage, VCC Voltage at any bus terminal High-level input voltage, VIH Low-level input voltage, VIL Y, Z A, G, G Output current Operating free-air temperature, TA MIN NOM MAX UNIT 4.75 5 5.25 V -7 12 V 2 0 VCC 0.8 V -60 60 SN75LBC172A 0 70 SN65LBC172A -40 85 mA C electrical characteristics over recommended operating conditions PARAMETER TEST CONDITIONS VIK VO Input clamp voltage II = -18 mA Y or Z, No load VOD(SS) Steady-state differential output voltage magnitude Open-circuit output voltage MIN TYP -1.5 -0.77 0 1.6 2.5 1 1.6 2.5 VOC(SS) Steady-state common-mode output voltage See Figure 3 2 VOC(SS) Change in steady-state common-mode output voltage between logic states See Figure 3 II Input current A, G, G Short-circuit output current ICC Supply current V 1 With common-mode loading, see Figure 2 -0.1 High-impedance-state output current V 3 See Figure 1 IOZ IO(OFF) V RL = 54 , see Figure 1 Change in steady-state differential output voltage between logic states VTEST = -7 V to 12 V, See Figure 7 Output current with power off VI = 0 V or VCC, No load UNIT VCC VCC No load (open circuit) VOD(SS) IOS MAX 0.1 V 2.8 V -0.02 0.02 V -50 50 A -200 200 mA G at 0 V, G at VCC -50 50 VCC = 0 V All drivers enabled -10 10 VI = 0 V VI = VCC All drivers disabled 2.4 A A 23 1.5 mA All typical values are at VCC = 5 V and 25C. The minimum VOD may not fully comply with TIA/EIA-485-A at operating temperatures below 0C. System designers should take the possibly of lower output signal into account in determining the maximum signal transmission distance. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLLS447C - OCTOBER 2000 - REVISED AUGUST 2008 switching characteristics over recommended operating conditions PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH tPHL Propagation delay time, low-to-high level output 5.5 8 11 ns Propagation delay time, high-to-low level output 5.5 8 11 ns tr tf Differential output voltage rise time 3 7.5 11 ns 3 7.5 11 ns tsk(p) tsk(o) Pulse skew |tPLH - tPHL| 0.6 2 ns Output skew 2 ns tsk(pp) tPZH Part-to-part skew 3 ns 25 ns tPHZ Propagation delay time, high-level-output-to-high impedance 25 ns RL = 54 ,, CL = 50 pF, see Figure 4 Differential output voltage fall time Propagation delay time, high-impedance-to-high-level output See Figure 5 tPZL Propagation delay time, high-impedance-to-low-level output See Figure 6 30 ns tPLZ Propagation delay time, low-level-output-to-high impedance 20 ns Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together. Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test circuits. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SLLS447C - OCTOBER 2000 - REVISED AUGUST 2008 PARAMETER MEASUREMENT INFORMATION IOY Y II A Z IOZ VOD VOY 54 GND VI VOZ Figure 1. Test Circuit, VOD Without Common-Mode Loading 375 Y A Input VOD 60 Z VTEST = -7 V to 12 V 375 VTEST VI Figure 2. Test Circuit, VOD With Common-Mode Loading Y 27 A Z Signal Generator 27 CL = 50 pF 50 PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Includes probe and jig capacitance Figure 3. VOC Test Circuit 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 VOC SLLS447C - OCTOBER 2000 - REVISED AUGUST 2008 Y A CL = 50 pF VOD RL = 54 Z Signal Generator 50 PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Includes probe and jig capacitance 3V 1.5 V Input 0V tPLH tPHL 1.5 V 90% 0V 10% Output tr -1.5 V tf Figure 4. Output Switching Test Circuit and Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SLLS447C - OCTOBER 2000 - REVISED AUGUST 2008 PARAMETER MEASUREMENT INFORMATION Y S1 A 0 V or 3 V w Output Z Input Signal Generator CL = 50 pF G G 50 3V PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Includes probe and jig capacitance 3-V if testing Y output, 0 V if testing Z output 3V 1.5 V Input 0V tPZH 0.5 V VOH 2.3 V 0V Output tPHZ Figure 5. Enable Timing Test Circuit and Waveforms, tPZH and tPHZ 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 RL = 110 SLLS447C - OCTOBER 2000 - REVISED AUGUST 2008 PARAMETER MEASUREMENT INFORMATION 5V RL = 110 Y S1 A 0 V or 3 V w Output Z Input Signal Generator CL = 50 pF G G 50 3V PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Includes probe and jig capacitance 3-V if testing Y output, 0 V if testing Z output 3V 1.5 V Input 0V tPZL tPLZ 5V Output 2.3 V VOL 0.5 V Figure 6. Enable Timing Test Circuit and Waveforms, tPZL and tPLZ POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SLLS447C - OCTOBER 2000 - REVISED AUGUST 2008 Y IO VI Z VTEST Voltage Source VTEST = -7 V to 12 V Slew Rate 1.2 V/s Figure 7. Test Circuit, Short-Circuit Output Current Y Z 100 VTEST 0V Pulse Generator 15 s Duration, 1% Duty Cycle 15 s 1.5 ms Figure 8. Test Circuit and Waveform, Transient Over-Voltage 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 -VTEST SLLS447C - OCTOBER 2000 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT DIFFERENTIAL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 2.5 3.5 VOD - Differential Output Voltage - V VOD - Differential Output Voltage - V 4 3 VCC = 5.25 V 2.5 VCC = 5 V 2 1.5 VCC = 4.75 V 1 0.5 0 0 20 40 60 80 IO - Output Current - mA VCC = 5.25 V 2 VCC = 5 V 1.5 VCC = 4.75 V 1 0.5 0 -60 100 -40 Figure 9 100 SUPPLY CURRENT (FOUR CHANNELS) vs SIGNALING RATE 8.5 I CC - Supply Current (Four Channels) - mA 144 8 Propigation Delay Time - ns 80 Figure 10 PROPAGATION DELAY TIME vs TEMPERATURE VCC = 5.25 V 7.5 VCC = 4.75 V 7 6.5 6 5.5 5 -40 -20 0 20 40 60 TA - Free-Air Temperature - C RL = 54 CL = 50 pF (Each Channel) 142 140 138 136 134 132 130 128 -20 0 20 40 T - Temperature - C 60 80 1 Figure 11 10 Signaling Rate - Mbps 100 Figure 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SLLS447C - OCTOBER 2000 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS RL = 54 CL = 50 pF Figure 13. Eye Pattern, Pseudorandom Data at 30 Mbps APPLICATION INFORMATION TMS320F243 DSP (Controller) SN65LBC172A SN65LBC175A SPISIMO TMS320F241 DSP (Embedded Application) SPISIMO IOPA1 (Enable) SPISTE SPISTE IOPA1 IOPA2 SPICLK SPICLK IOPA0 (Handshake /Status) IOPA0 SPISOMI SPISOMI Figure 14. Typical Application Circuit, DSP-to-DSP Link via Serial Peripheral Interface 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Jul-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LBC172A16DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC172A16DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC172A16DWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC172A16DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC172ADW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC172ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC172ADWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC172ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LBC172AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPD N / A for Pkg Type SN65LBC172ANE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPD N / A for Pkg Type SN75LBC172A16DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC172A16DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC172A16DWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC172A16DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC172ADW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC172ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC172ADWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC172ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LBC172AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPD N / A for Pkg Type SN75LBC172ANE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPD N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 10-Jul-2008 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) SN65LBC172A16DWR SOIC DW 16 2000 330.0 16.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.75 10.7 2.7 12.0 16.0 Q1 SN65LBC172ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN75LBC172A16DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 SN75LBC172ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LBC172A16DWR SOIC DW 16 2000 367.0 367.0 38.0 SN65LBC172ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN75LBC172A16DWR SOIC DW 16 2000 367.0 367.0 38.0 SN75LBC172ADWR SOIC DW 20 2000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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