Dual Wideband, Current Feedback
OPERATIONAL AMPLIFIER With Disable
DESCRIPTION
The OPA2681 sets a new level of performance for broadband dual
current feedback op amps. Operating on a very low 6mA/ch
supply current, the OPA2681 offers a slew rate and output power
normally associated with a much higher supply current. A new
output stage architecture delivers a high output current with
minimal voltage headroom and crossover distortion. This gives
exceptional single supply operation. Using a single +5V supply,
the OPA2681 can deliver a 1V to 4V output swing with over
100mA drive current and 150MHz bandwidth. This combination
of features makes the OPA2681 an ideal RGB line driver or single
supply ADC input driver.
OPA2681
FEATURES
●
WIDEBAND +5V OPERATION: 225MHz (G = +2)
●
UNITY GAIN STABLE: 280MHz (G = 1)
●HIGH OUTPUT CURRENT: 150mA
●OUTPUT VOLTAGE SWING: ±4.0V
●HIGH SLEW RATE: 2100V/µs
●LOW SUPPLY CURRENT: 6mA/ch
●LOW DISABLED CURRENT: 200µA/ch
●ENABLE/DISABLE TIME: 25ns/100ns
APPLICATIONS
●xDSL LINE DRIVER
●MATCHED I/Q CHANNEL AMPLIFIER
●BROADBAND VIDEO BUFFERS
●HIGH SPEED IMAGING CHANNELS
●PORTABLE INSTRUMENTS
●DIFFERENTIAL ADC DRIVERS
●ACTIVE FILTERS
●WIDEBAND INVERTING SUMMING
The OPA2681’s low 6mA/ch supply current is precisely trimmed
at 25°C. This trim, along with low drift over temperature, guaran-
tees lower guaranteed maximum supply current than competing
products. System power may be further reduced by using the
optional disable control pin (SO-14 only). Leaving this disable
pin open, or holding it high, gives normal operation. If pulled low,
the OPA2681 supply current drops to less than 400 µA while the
output goes into a high impedance state. This feature may be used
for either power savings or for video MUX applications.
Copyright © 1997, Texas Instruments Incorporated SBOS091A Printed in U.S.A. January, 2001
Single Supply ADSL Upstream Driver
100Ω
2kΩ
2kΩ1µF
12.4Ω
100Ω
2Vp-p
324Ω
324Ω
1/2
OPA2681
1/2
OPA2681
+12V
1:2
15Vp-p
12.4Ω
+6.5V
OPA2681 RELATED PRODUCTS
SINGLES DUALS TRIPLES
Voltage Feedback OPA680 OPA2680 OPA3680
Current Feedback OPA681 OPA2681 OPA3681
Fixed Gain OPA682 OPA2682 OPA3682
OPA2681
OPA2681
TM
www.ti.com
OPA2681
2SBOS091A
SPECIFICATIONS: VS = ±5V
RF = 402Ω, RL = 100Ω, and G = +2, (Figure 1 for AC performance only), unless otherwise noted.
OPA2681U, N
TYP GUARANTEED
0
°
C to –40
°
C to
MIN/
TEST
PARAMETER CONDITIONS +25°C +25°C(2) 70°C(3) +85°C(3) UNITS MAX
LEVEL
(1)
AC PERFORMANCE (Figure 1)
Small-Signal Bandwidth (VO = 0.5Vp-p) G = +1, RF = 453Ω280 MHz typ C
G = +2, RF = 402Ω220 220 210 190 MHz min B
G = +5, RF = 261Ω185 MHz typ C
G = +10, RF = 180Ω125 MHz typ C
Bandwidth for 0.1dB Gain Flatness G = +2, VO = 0.5Vp-p 90 50 45 45 MHz min B
Peaking at a Gain of +1 RF = 453, VO = 0.5Vp-p 0.4 2 4 dB max B
Large-Signal Bandwidth G = +2, VO = 5Vp-p 150 MHz typ C
Slew Rate G = +2, 4V Step 2100 1600 1600 1200 V/µs min B
Rise/Fall Time G = +2, VO = 0.5V Step 1.7 ns typ C
G = +2, 5V Step 2.0 ns typ C
Settling Time to 0.02% G = +2, VO = 2V Step 12 ns typ C
0.1% G = +2, VO = 2V Step 8 ns typ C
Harmonic Distortion G = +2, f = 5MHz, VO = 2Vp-p
2nd Harmonic RL = 100Ω–79 –73 –70 –68 dBc max B
RL ≥ 500Ω–85 –77 –70 –69 dBc max B
3rd Harmonic RL = 100Ω–74 –71 –71 –68 dBc max B
RL ≥ 500Ω–77 –75 –74 –72 dBc max B
Input Voltage Noise f > 1MHz 2.5 3.0 3.4 3.6 nV/√Hz max B
Non-Inverting Input Current Noise f > 1MHz 12 14 15 15 pA/√Hz max B
Inverting Input Current Noise f > 1MHz 15 18 18 19 pA/√Hz max B
Differential Gain G = +2, NTSC, VO = 1.4Vp, RL = 150Ω0.001 % typ C
RL = 37.5Ω0.008 % typ C
Differential Phase G = +2, NTSC, VO = 1.4Vp, RL = 150Ω0.01 deg typ C
RL = 37.5Ω0.05 deg typ C
Channel-to-Channel Crosstalk f = 5MHz –70 dBc typ C
DC PERFORMANCE(4)
Open-Loop Transimpedance Gain (Z
OL
)
VO = 0V, RL = 100Ω100 56 56 56 kΩmin A
Input Offset Voltage VCM = 0V ±1.3 ±5±6.5 ±7.5 mV max A
Average Offset Voltage Drift VCM = 0V +35 +40 µV/°C max B
Non-Inverting Input Bias Current VCM = 0V +30 +55 ±65 ±85 µA max A
Average Non-Inverting Input Bias Current Drift VCM = 0V –400 –450 nA/°C max B
Inverting Input Bias Current VCM = 0V ±10 ±40 ±50 ±55 µA max A
Average Inverting Input Bias Current Drift VCM = 0V –125 –150 nA°/C max B
INPUT
Common-Mode Input Range (CMIR)(5) ±3.5 ±3.4 ±3.3 ±3.2 V min A
Common-Mode Rejection (CMR) VCM = 0V 52 47 46 45 dB min A
Non-Inverting Input Impedance 100 || 2 kΩ || pF typ C
Inverting Input Resistance (R
I
)
Open-Loop 42 Ωtyp C
OUTPUT
Voltage Output Swing No Load ±4.0 ±3.8 ±3.7 ±3.6 V min A
100Ω Load ±3.9 ±3.7 ±3.6 ±3.3 V min A
Current Output, Sourcing VO = 0 +190 +160 +140 +80 mA min A
Current Output, Sinking VO = 0 –150 –135 –130 –80 mA min A
Closed-Loop Output Impedance G = +2, f = 100kHz 0.03 Ωtyp C
DISABLE
(Disabled Low) (SO-14 only)
Power Down Supply Current (+VS)V
DIS = 0, Both Channels –640 µA typ C
Disable Time 100 ns typ C
Enable Time 25 ns typ C
Off Isolation G = +2, 5MHz 70 dB typ C
Output Capacitance in Disable 4 pF typ C
Turn On Glitch G = +2, RL = 150Ω, VIN = 0 ±50 mV typ C
Turn Off Glitch G = +2, RL = 150Ω, VIN = 0 ±20 mV typ C
Enable Voltage 3.3 3.5 3.6 3.7 V min A
Disable Voltage 1.8 1.7 1.6 1.5 V max A
Control Pin Input Bias Current (DIS) VDIS = 0, Each Channel 100 160 160 160 µA max A
POWER SUPPLY
Specified Operating Voltage ±5 V typ C
Maximum Operating Voltage Range ±6±6±6 V max A
Max Quiescent Current VS = ±5V 12 12.8 13.4 13.6 mA max A
Min Quiescent Current VS = ±5V 12 11.2 10.7 9.7 mA min A
Power Supply Rejection Ratio (–PSRR) Input Referred 58 52 50 49 dB min A
TEMPERATURE RANGE
Specification: U, N
–40 to +85
°C typ C
Thermal Resistance,
θ
JA Junction-to-Ambient
U SO-8 125 °C/W typ C
N SO-14 100 °C/W typ C
NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information. (2) Junction temperature = ambient for 25°C guaranteed specifications. (3) Junction temperature = ambient at low temperature
limit: junction temperature = ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out of node. VCM
is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ± CMIR limits.
3
OPA2681
SBOS091A
SPECIFICATIONS: VS = +5V
RF = 499Ω, RL = 100Ω to VS/ 2, G = +2, (Figure 2 for AC performance only), unless otherwise noted.
OPA2681U, N
TYP GUARANTEED
0
°
C to –40
°
C to
MIN/
TEST
PARAMETER CONDITIONS +25°C +25°C(2) 70°C(3) +85°C(3) UNITS MAX
LEVEL
(1)
AC PERFORMANCE (Figure 2)
Small Signal Bandwidth (VO = 0.5Vp-p) G = +1, RF = 649Ω250 MHz typ C
G = +2, RF = 499Ω225 180 140 110 MHz min B
G = +5, RF = 360Ω180 MHz typ C
G = +10, RF = 200Ω165 MHz typ C
Bandwidth for 0.1dB Gain Flatness G = +2, VO < 0.5Vp-p 100 50 45 45 MHz min B
Peaking at a Gain of +1 RF = 649Ω, VO < 0.5Vp-p 0.4 2 4 dB max B
Large Signal Bandwidth G = +2, VO = 2Vp-p 200 MHz min B
Slew Rate G = +2, 2V Step 830 700 680 570 V/µs min B
Rise/Fall Time G = +2, VO = 0.5V Step 1.5 ns typ C
G = +2, VO = 2V Step 2.0 ns typ C
Settling Time to 0.02% G = +2, VO = 2V Step 14 ns typ C
0.1% G = +2, VO = 2V Step 9 ns typ C
Harmonic Distortion G = +2, f = 5MHz, VO = 2Vp-p
2nd Harmonic RL = 100Ω to VS/2 –70 –68 –67 –63 dBc max B
RL ≥ 500Ω to VS/2 –72 –70 –70 –68 dBc max B
3rd Harmonic RL = 100Ω to VS/2 –72 –65 –65 –62 dBc max B
RL ≥ 500Ω to VS/2 –73 –68 –67 –67 dBc max B
Input Voltage Noise f > 1MHz 2.2 3 3.4 3.6 nV/√Hz max B
Non-Inverting Input Current Noise f > 1MHz 12 14 14 15 pA/√Hz max B
Inverting Input Current Noise f > 1MHz 15 18 18 19 pA/√Hz max B
DC PERFORMANCE(4)
Open-Loop Transimpedance Gain (Z
OL
)
VO = VS/2, RL = 100Ω to VS/2 100 60 53 51 kΩmin A
Input Offset Voltage VCM = 2.5V ±1±5±6.0 ±7 mV max A
Average Offset Voltage Drift VCM = 2.5V +15 +20 µV/°C max B
Non-Inverting Input Bias Current VCM = 2.5V +40 +65 +75 +95 µA max A
Average Non-Inverting Input Bias Current Drift VCM = 2.5V –300 –350 nA/°C max B
Inverting Input Bias Current VCM = 2.5V ±5±20 ±25 ±35 µA max A
Average Inverting Input Bias Current Drift VCM = 2.5V –125 –175 nA/°C max B
INPUT
Least Positive Input Voltage(5) 1.5 1.6 1.7 1.8 V max A
Most Positive Input Voltage(5) 3.5 3.4 3.3 3.2 V min A
Common-Mode Rejection (CMR) VCM = 2.5V 51 45 44 44 dB min A
Non-Inverting Input Impedance 100 || 2 kΩ || pF typ C
Minimum Inverting Input Resistance (R
I
)
Open-Loop 45 32 30 29 Ωmin A
Maximum Inverting Input Resistance (R
I
)
Open-Loop 45 65 67 74 Ωmax A
OUTPUT
Most Positive Output Voltage No Load 4 3.8 3.7 3.5 V min A
RL = 100Ω, 2.5V 3.9 3.7 3.6 3.4 V min A
Least Positive Output Voltage No Load 1 1.2 1.3 1.5 V max A
RL = 100Ω, 2.5V 1.1 1.3 1.4 1.6 V max A
Current Output, Sourcing VO = VS/2 150 110 110 60 mA min A
Current Output, Sinking VO = VS/2 –110 –75 –70 –50 mA min A
Closed-Loop Output Impedance G = +2, f = 100kHz 0.03 Ωtyp C
DISABLE (Disable Low) (SO-14 only)
Power Down Supply Current (+VS)V
DIS = 0, Both Channels –540 µA typ C
Disable Time 100 ns typ C
Enable Time 25 ns typ C
Off Isolation G = +2, 5MHz 65 dB typ C
Output Capacitance in Disable 4 pF typ C
Turn On Glitch G = +2, RL = 150Ω, VIN = VS /2 ±50 mV typ C
Turn Off Glitch G = +2, RL = 150Ω, VIN = VS /2 ±20 mV typ C
Enable Voltage 3.3 3.5 3.6 3.7 V min A
Disable Voltage 1.8 1.7 1.6 1.5 V max A
Control Pin Input Bias Current (DIS) VDIS = 0, Each Channel 100 µA typ C
POWER SUPPLY
Specified Single Supply Operating Voltage 5 V typ C
Maximum Single Supply Operating Voltage 12 12 12 V max A
Max Quiescent Current VS = +5V 9.6 10.8 11 11 mA max A
Min Quiescent Current VS = +5V 9.6 8.2 8.0 8.0 mA min A
Power Supply Rejection Ratio (–PSRR) Input Referred 48 dB typ C
TEMPERATURE RANGE
Specification: U, N
–40 to +85
°C typ C
Thermal Resistance,
θ
JA
U SO-8 125 °C/W typ C
N SO-14 100 °C/W typ C
NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information. (2) Junction temperature = ambient for 25°C guaranteed specifications. (3) Junction temperature = ambient at low temperature
limit: junction temperature = ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out of node. VCM
is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ±CMIR limits.
OPA2681
4SBOS091A
1
2
3
4
5
6
7
14
13
12
11
10
9
8
–In A
+In A
DIS A
–VS
DIS B
+In B
–In B
Out A
NC
NC
+VS
NC
NC
Out B
ABSOLUTE MAXIMUM RATINGS
Power Supply ..............................................................................±6.5VDC
Internal Power Dissipation(1) ............................ See Thermal Information
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range............................................................................ ±VS
Storage Temperature Range: U, N................................–40°C to +125°C
Lead Temperature (soldering, 10s).............................................. +300°C
Junction Temperature (TJ ) ........................................................... +175°C
NOTE:: (1) Packages must be derated based on specified
θ
JA. Maximum TJ
must be observed.
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from perfor-
mance degradation to complete device failure. Burr-Brown
Corporation recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet published specifica-
tions.
PIN CONFIGURATIONS
Top View SO-8
SO-14
PACKAGE SPECIFIED
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE NUMBER(1) RANGE MARKING NUMBER(2) MEDIA
OPA2681U SO-8 Surface Mount 182 –40°C to +85°C OPA2681U OPA2681U Rails
" " " " " OPA2681U/2K5 Tape and Reel
OPA2681N SO-14 Surface Mount 235 –40°C to –85°C OPA2681N OPA2681N Rails
" " " " " OPA2681N/2K5 Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet. (2) Models with a slash (/) are available only as Tape and Reel in the quantity
indicated after the slash (e.g. /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of the OPA2681U/2K5 will get a single 2500-piece Tape and Reel.
PACKAGE/ORDERING INFORMATION
1
2
3
4
8
7
6
5
+VS
Out B
–In B
+In B
Out A
–In A
+In A
–VS
5
OPA2681
SBOS091A
TYPICAL PERFORMANCE CURVES: VS = ±5V
G = +2, RF = 402Ω, RL = 100Ω, unless otherwise noted (see Figure 1).
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
Frequency (25MHz/div)
0 250MHz125MHz
SMALL-SIGNAL FREQUENCY RESPONSE
Normalized Gain (1dB/div)
G = +10, R
F
= 180Ω
G = +5, R
F
= 261Ω
G = +1, R
F
= 453ΩG = +2, R
F
= 402Ω
8
7
6
5
4
3
2
1
0
–1
–2
Frequency (25MHz/div)
0 250MHz125MHz
LARGE-SIGNAL FREQUENCY RESPONSE
Gain (1dB/div)
2Vp-p
G = +2, R
L
= 100Ω
1Vp-p
4Vp-p
7Vp-p
400
300
200
100
0
–100
–200
–300
–400
SMALL-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (100mV/div)
G = +2
V
O
= 0.5Vp-p
+4
+3
+2
+1
0
–1
–2
–3
–4
LARGE-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (1V/div)
G = +2
V
O
= 5Vp-p
5.0
4.0
2.0
0
2.0
1.6
1.2
0.8
0.4
0
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
Time (50ns/div)
Output Voltage (400mV/div)
6.0
4.0
2.0
0
VDIS (2V/div)
VDIS
Output Voltage
(SO-14 only)
G = +2
VIN = +1V
CHANNEL-TO-CHANNEL CROSSTALK
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Frequency (MHz)
1 10 100
Crosstalk (10dB/div)
OPA2681
6SBOS091A
TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.)
G = +2, RF = 402Ω, RL = 100Ω, unless otherwise noted (see Figure 1).
–60
–65
–70
–75
–80
–85
–90
5MHz 2ND HARMONIC DISTORTION
vs OUTPUT VOLTAGE
Output Voltage Swing (Vp-p)
0.1 1 10
2nd Harmonic Distortion (dBc)
R
L
= 200Ω
R
L
= 500Ω
R
L
= 100Ω
–60
–65
–70
–75
–80
–85
–90
5MHz 3RD HARMONIC DISTORTION
vs OUTPUT VOLTAGE
Output Voltage Swing (Vp-p)
0.1 1 10
3rd Harmonic Distortion (dBc)
RL = 200Ω
RL = 100Ω
RL = 500Ω
–60
–65
–70
–75
–80
–85
–90
10MHz 2ND HARMONIC DISTORTION
vs OUTPUT VOLTAGE
Output Voltage Swing (Vp-p)
0.1 1 10
2nd Harmonic Distortion (dBc)
R
L
= 500Ω
R
L
= 100Ω
R
L
= 200Ω
–60
–65
–70
–75
–80
–85
–90
10MHz 3RD HARMONIC DISTORTION
vs OUTPUT VOLTAGE
Output Voltage Swing (Vp-p)
0.1 1 10
3rd Harmonic Distortion (dBc)
RL = 500Ω
RL = 100Ω
RL = 200Ω
–50
–55
–60
–65
–70
–75
–80
20MHz 2ND HARMONIC DISTORTION
vs OUTPUT VOLTAGE
Output Voltage Swing (Vp-p)
0.1 1 10
2nd Harmonic Distortion (dBc)
R
L
= 500Ω
R
L
= 100Ω
R
L
= 200Ω
–50
–55
–60
–65
–70
–75
–80
20MHz 3RD HARMONIC DISTORTION
vs OUTPUT VOLTAGE
Output Voltage Swing (Vp-p)
0.1 1 10
3rd Harmonic Distortion (dBc)
RL = 500Ω
RL = 100Ω
RL = 200Ω
7
OPA2681
SBOS091A
TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.)
G = +2, RF = 402Ω, RL = 100Ω, unless otherwise noted (see Figure 1).
–40
–50
–60
–70
–80
–90
2ND HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
0.1 1 10 20
2nd Harmonic Distortion (dBc)
VO = 2Vp-p
RL = 100Ω
G = +2, RF = 402Ω
G = +10, RF = 180Ω
G = +5, RF = 261Ω
–40
–50
–60
–70
–80
–90
3RD HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
0.1 1 10 20
3rd Harmonic Distortion (dBc)
VO = 2Vp-p
RL = 100Ω
G = +2,
RF = 402Ω
G = +10, RF = 180Ω
G = +5, RF = 261Ω
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
TWO-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
Single-Tone Load Power (dBm)
–8–6–4–20246810
3rd-Order Spurious Level (dBc)
dBc = dB below carriers
50MHz
20MHz
10MHz
Load Power at Matched 50Ω Load
60
50
40
30
20
10
0
RECOMMENDED R
S
vs CAPACITIVE LOAD
Capacitive Load (pF)
1 10 100
R
S
(Ω)
15
12
9
6
3
0
–3
–6
–9
–12
–15
Frequency (30MHz/div)
0 300MHz150MHz
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Gain to Capacitive Load (3dB/div)
R
S
V
IN
V
O
C
L
1kΩ
402Ω
402Ω
1kΩ is optional.
C
L
= 22pF
C
L
= 10pF
C
L
= 47pF
C
L
= 100pF
100
10
1
INPUT VOLTAGE AND CURRENT NOISE DENSITY
Frequency (Hz)
100 1k 10k 100k 1M 10M
Current Noise (pA/√Hz)
Voltage Noise (nV/√Hz)
Non-Inverting Input Current Noise
Inverting Input Current Noise
12.2pA/√Hz
15.1pA/√Hz
Voltage Noise 2.2nV/√Hz
OPA2681
8SBOS091A
TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.)
G = +2, RF = 402Ω, RL = 100Ω, unless otherwise noted (see Figure 1).
70
65
60
55
50
45
40
35
30
25
20
Frequency (Hz)
10
2
10
3
10
4
10
5
10
6
10
7
10
8
CMR AND PSR vs FREQUENCY
Rejection Ratio (dB)
+PSR
–PSR
CMR
5
4
3
2
1
0
–1
–2
–3
–4
–5
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
I
O
(mA)
–300 –200 –100 0 100 200 300
V
O
(Volts)
100Ω Load Line
50Ω Load Line
25Ω
Load Line
Output Current Limited
1W Internal
Power Limit
1-Channel
Only
1W Internal
Power Limit
Output Current Limit
10
7.5
5
2.5
0
200
150
100
50
0
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Ambient Temperature (°C)
–40 –20 0 20 40 60 80 100 120 140
Supply Current (2.5mA/div)
Output Current (mA)
Quiescent Supply Current
Sourcing Output Current
Sinking Output Current
120
100
80
60
40
20
0
OPEN-LOOP TRANSIMPEDANCE GAIN/PHASE
Frequency (Hz)
10
4
10
5
10
6
10
7
10
8
10
9
Transimpedance Gain (20dBΩ/div)
0
–40
–80
–120
–160
–200
–240
Transimpedance Phase (40°/div)
|Z
OL
|
∠ Z
OL
0.05
0.04
0.03
0.02
0.01
0
Number of 150Ω Loads
1234
COMPOSITE VIDEO dG/dP
Positive Video
Negative Sync
dP
dG
dG/dP (%/°)
5
4
3
2
1
0
–1
–2
–3
–4
–5
TYPICAL DC DRIFT OVER TEMPERATURE
Ambient Temperature (°C)
–40 –20
VIO
0 20 40 60 80 100 120 140
Input Offset Voltage (mV)
50
40
30
20
10
0
–10
–20
–30
–40
–50
Input Bias Currents (µA)
Non-Inverting Input Bias Current
Inverting
9
OPA2681
SBOS091A
TYPICAL PERFORMANCE CURVES: VS = +5V
G = +2, RF = 499Ω, RL = 100Ω to +2.5V, unless otherwise noted (see Figure 2).
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
Frequency (25MHz/div)
0 250125
SMALL-SIGNAL FREQUENCY RESPONSE
Normalized Gain (1dB/div)
G = +2,
R
F
= 499Ω
G = +10,
R
F
= 200Ω
G = +5,
R
F
= 360Ω
G = +1,
R
F
= 649Ω
2.10
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
SMALL-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (100mV/div)
G = +2
V
O
= 0.5Vp-p
70
60
50
40
30
20
10
0
RECOMMENDED RS vs CAPACITIVE LOAD
Capacitive Load (pF)
1 10 100
RS (Ω)
15
12
9
6
3
0
–3
–6
–9
–12
–15
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Frequency (20MHz/div)
0 200MHz100MHz
Gain to Capacitive Load (3dB/div)
C
L
= 22pF
C
L
= 10pF
C
L
= 47pF
C
L
= 100pF
499Ω
499Ω
57.6Ω806Ω
806Ω
1kΩ
V
I
+5V
0.1µF
V
O
R
S
C
L
0.1µF
0.1µF
8
7
6
5
4
3
2
1
0
–1
–2
Frequency (25MHz/div)
0 250125
LARGE-SIGNAL FREQUENCY RESPONSE
Gain (1dB/div)
G = +2
R
L
= 100Ω to 2.5V V
O
= 0.5Vp-p
V
O
= 1Vp-p
V
O
= 2Vp-p
4.5
4.1
3.7
3.3
2.9
2.5
2.1
1.7
1.3
0.9
0.5
LARGE-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (400mV/div)
G = +2
V
O
= 2Vp-p
OPA2681
10 SBOS091A
TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.)
G = +2, RF = 499Ω, RL = 100Ω to +2.5V, unless otherwise noted (see Figure 2).
–40
–50
–60
–70
–80
2ND HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
0.1 1 10 20
2nd Harmonic Distortion (dBc)
VO = 2Vp-p
RL = 100Ω to 2.5V
G = +2, RF = 499Ω
G = +10, RF = 200Ω
G = +5, RF = 360Ω
3RD HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
0.1 1 10 20
3rd Harmonic Distortion (dBc)
–40
–50
–60
–70
–80
V
O
= 2Vp-p
R
L
= 100Ω to 2.5V
G = +10, R
F
= 200Ω
G = +5, R
F
= 360Ω
G = +2, R
F
= 499Ω
3RD HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
0.1 1 10 20
3rd Harmonic Distortion (dBc)
–50
–60
–70
–80
–90
V
O
= 2Vp-p
G = +2
R
L
= 100Ω
R
L
= 500Ω
R
L
= 200Ω
Loads to 2.5V
–45
–50
–55
–60
–65
–70
–75
–80
–85
Single-Tone Load Power (dBm)
–14 –12 –10 –8–6–4–20 2
TWO-TONE, 3RD ORDER SPURIOUS LEVEL
3rd Order Spurious (dBc)
50MHz
dBc = dB Below Carrier
Load Power at Matched 50Ω Load
20MHz
10MHz
10
1
0.1
0.01
CLOSED-LOOP OUTPUT IMPEDANCE
Frequency (Hz)
10k 100M100k 1M 10M
Output Impedance (Ω)
402Ω
+5
1/2
OPA2681
–5
402Ω
50ΩZ
O
2ND HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
0.1 1 10 20
2nd Harmonic Distortion (dBc)
–50
–60
–70
–80
–90
V
O
= 2Vp-p
G = +2
Loads to 2.5V
R
L
= 500Ω
R
L
= 200Ω
R
L
= 100Ω
11
OPA2681
SBOS091A
APPLICATIONS INFORMATION
WIDEBAND CURRENT FEEDBACK OPERATION
The OPA2681 gives the exceptional AC performance of a
wideband current feedback op amp with a highly linear, high
power output stage. Requiring only 6mA/ch. quiescent cur-
rent, the OPA2681 will swing to within 1V of either supply
rail and deliver in excess of 135mA guaranteed at room
temperature. This low output headroom requirement, along
with supply voltage independent biasing, gives remarkable
single (+5V) supply operation. The OPA2681 will deliver
greater than 200MHz bandwidth driving a 2Vp-p output into
100Ω on a single +5V supply. Previous boosted output stage
amplifiers have typically suffered from very poor crossover
distortion as the output current goes through zero. The
OPA2681 achieves a comparable power gain with much
better linearity. The primary advantage of a current feedback
op amp over a voltage feedback op amp is that AC perfor-
mance (bandwidth and distortion) is relatively independent
of signal gain. For similar AC performance with improved
DC accuracy, consider the high slew rate, unity gain stable,
voltage feedback OPA2680.
Figure 1 shows the DC coupled, gain of +2, dual power
supply circuit configuration used as the basis of the ±5V
Specifications and Typical Performance Curves. For test
purposes, the input impedance is set to 50Ω with a resistor
to ground and the output impedance is set to 50Ω with a
series output resistor. Voltage swings reported in the speci-
fications are taken directly at the input and output pins while
load powers (dBm) are defined at a matched 50Ω load. For
the circuit of Figure 1, the total effective load will be 100Ω
|| 804Ω = 89Ω. The disable control line (DIS) is typically left
open (SO-14 only) to guarantee normal amplifier operation.
One optional component is included in Figure 1. In addition
to the usual power supply de-coupling capacitors to ground,
a 0.1µF capacitor is included between the two power supply
pins. In practical PC board layouts, this optional added
capacitor will typically improve the 2nd harmonic distortion
performance by 3dB to 6dB.
Figure 2 shows the AC coupled, gain of +2, single supply
circuit configuration used as the basis of the +5V Specifica-
tions and Typical Performance Curves. Though not a “rail-
to-rail” design, the OPA2681 requires minimal input and
output voltage headroom compared to other very wideband
current feedback op amps. It will deliver a 3Vp-p output
swing on a single +5V supply with greater than 150MHz
bandwidth. The key requirement of broadband single supply
operation is to maintain input and output signal swings
within the usable voltage ranges at both the input and the
output. The circuit of Figure 2 establishes an input midpoint
bias using a simple resistive divider from the +5V supply
(two 806Ω resistors). The input signal is then AC coupled
into this midpoint voltage bias. The input voltage can swing
to within 1.5V of either supply pin, giving a 2Vp-p input
signal range centered between the supply pins. The input
impedance matching resistor (57.6Ω) used for testing is
adjusted to give a 50Ω input match when the parallel
combination of the biasing divider network is included. The
gain resistor (RG) is AC coupled, giving the circuit a DC
gain of +1—which puts the input DC bias voltage (2.5V) on
the output as well. The feedback resistor value has been
adjusted from the bipolar supply condition to re-optimize for
a flat frequency response in +5V, gain of +2, operation (see
Setting Resistor Values to Optimize Bandwidth). Again, on
a single +5V supply, the output voltage can swing to within
1V of either supply pin while delivering more than 75mA
output current. A demanding 100Ω load to a midpoint bias
is used in this characterization circuit. The new output stage
used in the OPA2681 can deliver large bipolar output cur-
rents into this midpoint load with minimal crossover distor-
tion, as shown by the +5V supply, 3rd harmonic distortion
plots.
FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specifi-
cation and Test Circuit. FIGURE 2. AC-Coupled, G = +2, Single Supply Specifica-
tion and Test Circuit.
1/2
OPA2681
+5V
+
DIS
–5V
50Ω Load
50Ω50ΩV
O
V
I
50Ω Source
R
G
402Ω
R
F
402Ω
+
6.8µF
0.1µF 6.8µF
0.1µF
0.1µF
+V
S
–V
S
1/2
OPA2681
+5V
+V
S
DIS
V
S
/2
806Ω100ΩV
O
V
I
57.6Ω
806Ω
R
F
499Ω
R
G
499Ω
0.1µF
0.1µF
6.8µF
+
0.1µF
OPA2681
12 SBOS091A
SINGLE SUPPLY DIFFERENTIAL A/D
CONVERTER DRIVER
Figure 3 shows a gain of +10 Diff. In/Diff. Out single supply
ADC driver. Using a dual amplifier like the OPA2681 helps
reducing the necessary board space, as it also reduces the
amount of required supply bypassing components. From a
signal point of view, dual amplifiers provide excellent per-
formance matching, e.g., gain and phase matching. The
differential ADC driver circuit shown in Figure 3 takes
advantage of this fact. A transformer converts the single-
ended input signal into a low level differential signal which
is applied to the high impedance non-inverting inputs of
each of the two amplifiers in the OPA2681. Resistor RG
between the inverting inputs controls the ac-gain of this
circuit according to equation G = 1 + 2RF/RG. With the
resistor values shown the AC-gain is set to 10. Adding a
capacitor (0.1µF) in series with RG blocks the dc-path giving
a DC gain of +1 for the common-mode voltage. This allows,
in a very simple way, to apply the required DC bias voltage
of +2.5V to the inputs of the amplifiers, which will also
appear at their outputs. Like the OPA2681 the A/D converter
ADS823 operates on a single +5V supply. Its internal
common-mode voltage is typically +2.5V which equals the
required bias voltage for the OPA2681. Connecting two
resistors between the top-reference (REFT = +3.5V) and
bottom reference (REFB = +1.5V) develop a +2.5V voltage
level at their midpoint. Applying that to the center tap of the
transformer biases amplifiers appropriately. Sufficient by-
passing at the center tap must be provided to keep this point
at a solid AC ground. Resistors RS isolate the op amp output
from the capacitive input of the converter, as well as forming
a first order low-pass filter with capacitor CI to attenuate
some of the wideband noise. This interface will provide
> 150MHz full scale input bandwidth to the ADS823.
WIDEBAND VIDEO MULTIPLEXING
One common application for video speed amplifiers which
include a disable pin is to wire multiple amplifier outputs
together, then select which one of several possible video
inputs to source onto a single line. This simple “Wired-OR
Video Multiplexer” can be easily implemented using the
OPA2681N as shown in Figure 4.
Typically, channel switching is performed either on sync or
retrace time in the video signal. The two inputs are approxi-
mately equal at this time. The “make-before-break” disable
characteristic of the OPA2681 ensures that there is always
one amplifier controlling the line when using a wired-OR
circuit like that shown in Figure 4. Since both inputs may be
on for a short period during the transition between channels,
the outputs are combined through the output impedance
matching resistors (82.5Ω in this case). When one channel is
disabled, its feedback network forms part of the output
impedance and slightly attenuates the signal in getting out
onto the cable. The gain and output matching resistor have
been slightly increased to get a signal gain of +1 at the
matched load and provide a 75Ω output impedance to the
cable. The video multiplexer connection (Figure 4) also
insures that the maximum differential voltage across the
inputs of the unselected channel do not exceed the rated
±1.2V maximum for standard video signal levels.
The section on Disable Operation shows the turn-on and
turn-off switching glitches using a grounded input for a
single channel is typically less than ±50mV. Where two
outputs are switched (as shown in Figure 4), the output line
is always under the control of one amplifier or the other due
to the “make-before-break” disable timing. In this case, the
switching glitches for two 0V inputs drop to < 20mV.
FIGURE 3. Wideband, Single Supply, Differential ADC Driver.
R
F
200ΩR
S
24.9Ω
50Ω
ADS823
10-Bit
60MSPS
R
S
24.9Ω
0.1µF
IN
IN
GND
R
F
200Ω
R
G
44Ω
V
BIAS
= +2.5V
REFT
(+3.5V) REFB
(+1.5V)
C
1
10pF
C
1
10pF
1/2
OPA2681
1/2
OPA2681
2kΩ
2kΩ
0.1µF0.1µF
+V
S
+5V
+5V
V
I
1:1
0.1µF
G = 1 + = 10
2 R
F
R
G
4.7µF
+
13
OPA2681
SBOS091A
FIGURE 4. Two-Channel Video Multiplexer.
FIGURE 5. Buffered, Single Supply Active Filter.
HIGH SPEED ACTIVE FILTERS
Wideband current feedback op amps make ideal elements
for implementing high speed active filters where the ampli-
fier is used as fixed gain block inside a passive RC circuit
network. Their relatively constant bandwidth vs gain, pro-
vides low interaction between the actual filter poles and the
required gain for the amplifier. Figure 5 shows an example
single-supply buffered filter application. In this case, one of
the OPA2681 channels is used to set-up the DC operating
point and provide impedance isolation from the signal source
into the 2nd stage filter. That stage is set up to implement a
20MHz maximally flat Butterworth frequency response and
provide an AC gain of +4.
The 51Ω input matching resistor is optional in this case. The
input signal is AC coupled to the 2.5V DC reference voltage
developed through the resistor divider from the +5V power
supply. This first stage acts as a gain of +1 voltage buffer for
the signal where the 600Ω feedback resistor is required for
2kΩ
82.5Ω
75Ω Cable
RG-59
82.5Ω
75Ω
402Ω340Ω
Video 1
+5V
+5V
–5V
1/2
OPA2681N
1/2
OPA2681N
2kΩ
75Ω
402Ω340Ω
Video 2
–5V
+5V
VDIS
DIS
DIS
Power supply
de-coupling not shown
600Ω
20MHz, 2nd Order Butterworth Low Pass
1/2
OPA2681
+5V
Power supply
de-coupling not shown
32.3Ω105Ω
5kΩ
5kΩ51Ω
VI
0.1µF
375Ω
1/2
OPA2681
4VI
100pF
125Ω
0.1µF
150pF
OPA2681
14 SBOS091A
stability. This first stage easily drives the low input resistors
required at the input of this high frequency filter. The 2nd
stage is set for a DC gain of +1—carrying the 2.5V operating
point through to the output pin, and an AC gain of +4. The
feedback resistor has been adjusted to optimize bandwidth
for the amplifier itself. As the single-supply frequency
response plots show, the OPA2681 in this configuration will
give > 200MHz small signal bandwidth. The capacitor
values were chosen as low as possible but adequate to
swamp out the parasitic input capacitance of the amplifier.
The resistor values were slightly adjusted to give the desired
filter frequency response while accounting for the approxi-
mate 1ns propagation delay through each channel of the
OPA2681.
HIGH POWER TWISTED PAIR DRIVER
A very demanding application for a high-speed amplifier is to
drive a low load impedance while maintaining a high output
voltage swing to high frequencies. Using the dual current
feedback op amp OPA2681, a 15Vp-p output signal swing
into a twisted-pair line with a typical impedance of 100Ω can
be realized. Configured as shown in the front page the two
amplifiers of the OPA2681 drive the output transformer in a
push-pull configuration thus doubling the peak-to-peak signal
swing at each op amp’s output to 15Vp-p. The transformer has
a turns ratio of 2. In order to provide a matched source, this
requires a 25Ω source impedance (RS), for the primary side,
given the transformer equation n2 = RL/RS. Dividing this
impedance equally between the outputs requires a series
termination matching resistor at each output of 12.4Ω. Taking
the total resistive load of 25Ω (for the differential output
signal) and drawing a load line on the Output Voltage and
Current Limitations plot it can be seen a 1.5V headroom is
required at the positive peak current of 150mA, while a 2.5V
headroom is required at the negative peak current of 150mA.
The full 7.5Vp-p out of each amplifier is achieved on a single
+12V supply by shifting the DC operating point positive 0.5V
to 6.5V—as shown on the front page ADSL upstream driver.
Line driver applications usually have a high demand for
transmitting the signal with low distortion. Current-feedback
amplifiers like the OPA2681 are ideal for delivering low
distortion performance to higher gains. The example shown is
set for a differential gain of 7.5. This circuit can deliver the
maximum 15Vp-p signal with over 60 MHz bandwidth.
WIDEBAND (160MHz) INSTRUMENTATION AMPLIFIER
As discussed previously, the current feedback topology of
the OPA2681 provides a nearly constant bandwidth as signal
gain is increased. The three op amp wideband instrumenta-
tion amplifier depicted in Figure 6 takes advantage of this,
achieving a differential bandwidth of 160MHz. The signal is
applied to the high-impedance non-inverting inputs of the
OPA2681. The differential gain is set by (1 + 2RF/RG) —
which equal to 5 using the values shown in Figure 6. The
feedback resistors, RF, are optimized at this particular gain.
Gain adjustments can be made by adjusting RG. The differ-
ential to single-ended conversion is performed by voltage
feedback amplifier OPA680 configured as a standard differ-
ence amplifier. To maintain good distortion performance for
the OPA2681, the loading at each amplifier output has been
matched by setting R3 + R4 = R1, rather than using the same
resistor values within the difference amplifier.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Several PC boards are available to assist in the initial
evaluation of circuit performance using the OPA2681 in its
2 package styles. Both of these are available free as an
unpopulated PC board delivered with descriptive documen-
tation. The summary information for these boards is shown
in the table below.
FIGURE 6. Wideband, 3-Op Amp Instrumentation Diff. Amp.
RF
261Ω
RG
130Ω
R3
249Ω
R4
249Ω
R1
499ΩR2
499Ω
RF
261Ω
1/2
OPA2681
1/2
OPA2681
+5V
VIN
VO
VIN
OPA680
–5V
–5V
+5V
VO
(VIN – VIN)= 5
Contact the TI applications support line to request any of
these boards.
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for Video and
RF amplifier circuits where parasitic capacitance and induc-
tance can have a major effect on circuit performance. A
SPICE model for the OPA2681 is available through either
the TI web site (www.ti.com) or as one model on a disk from
the TI Applications department (1-800-548-6132). The Ap-
plication department is also available for design assistance at
this number. These models do a good job of predicting small
signal AC and transient performance under a wide variety of
DEMO BOARD ORDERING
PRODUCT PACKAGE NUMBER NUMBER
OPA2681U 8-Pin SO-8 DEM-OPA268xU MKT-352
OPA2681N 14-Pin SO-14 DEM-OPA268xN MKT-353
15
OPA2681
SBOS091A
operating conditions. They do not do as well in predicting
the harmonic distortion or dG/dP characteristics. These
models do not attempt to distinguish between the package
types in their small signal AC performance, nor do they
attempt to simulate channel-to-channel coupling.
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO
OPTIMIZE BANDWIDTH
A current feedback op amp like the OPA2681 can hold an
almost constant bandwidth over signal gain settings with the
proper adjustment of the external resistor values. This is shown
in the Typical Performance Curves; the small signal bandwidth
decreases only slightly with increasing gain. Those curves also
show that the feedback resistor has been changed for each gain
setting. The resistor “values” on the inverting side of the circuit
for a current feedback op amp can be treated as frequency
response compensation elements while their “ratios” set the
signal gain. Figure 7 shows the small signal frequency response
analysis circuit for the OPA2681.
The key elements of this current feedback op amp model are:
A current feedback op amp senses an error current in the
inverting node (as opposed to a differential input error
voltage for a voltage feedback op amp) and passes this on to
the output through an internal frequency dependent
transimpedance gain. The Typical Performance Curves show
this open loop transimpedance response. This is analogous
to the open loop voltage gain curve for a voltage feedback
op amp. Developing the transfer function for the circuit of
Figure 7 gives Equation 1:
This is written in a loop gain analysis format where the
errors arising from a non-infinite open loop gain are shown
in the denominator. If Z(s) were infinite over all frequencies,
the denominator of Equation 1 would reduce to 1 and the
ideal desired signal gain shown in the numerator would be
achieved. The fraction in the denominator of Equation 1
determines the frequency response. Equation 2 shows this as
the loop gain equation:
If 20 x log (RF + NG x RI) were drawn on top of the open
loop transimpedance plot, the difference between the two
would be the loop gain at a given frequency. Eventually,
Z(s) rolls off to equal the denominator of Equation 2 at
which point the loop gain has reduced to 1 (and the curves
have intersected). This point of equality is where the
amplifier’s closed loop frequency response given by Equa-
tion 1 will start to roll off, and is exactly analogous to the
frequency at which the noise gain equals the open loop
voltage gain for a voltage feedback op amp. The difference
here is that the total impedance in the denominator of
Equation 2 may be controlled somewhat separately from the
desired signal gain (or NG).
The OPA2681 is internally compensated to give a maxi-
mally flat frequency response for RF = 402Ω at NG = 2 on
±5V supplies. Evaluating the denominator of Equation 2
(which is the feedback transimpedance) gives an optimal
target of 492Ω. As the signal gain changes, the contribution
of the NG x RI term in the feedback transimpedance will
change, but the total can be held constant by adjusting RF.
Equation 3 gives an approximate equation for optimum RF
over signal gain:
As the desired signal gain increases, this equation will
eventually predict a negative RF. A somewhat subjective
limit to this adjustment can also be set by holding RG to a
V
O
V
I
=α1+R
F
R
G
1+R
F
+R
I
1+R
F
R
G
Z
(S)
=αNG
1+R
F
+R
I
NG
Z
(S)
NG ≡1+R
F
R
G
Eq. 1
Z
(S)
R
F
+R
I
NG =Loop Gain
Eq. 2
R
F
V
O
R
G
R
I
Z
(S)
I
ERR
I
ERR
α
V
I
FIGURE 7. Current Feedback Transfer Function Analysis
Circuit.
α → Buffer gain from the non-inverting input to the inverting input
R
I
→ Buffer output impedance
i
ERR
→ Feedback error current signal
Z(s) → Frequency dependent open loop transimpedance gain from i
ERR
to V
O
The buffer gain is typically very close to 1.00 and is
normally neglected from signal gain considerations. It will,
however set the CMRR for a single op amp differential
amplifier configuration. For a buffer gain α < 1.0, the
CMRR = -20 x log (1– α) dB.
RI, the buffer output impedance, is a critical portion of the
bandwidth control equation. The OPA2681 is typically about
45Ω.
RF=492Ω–NGRI
Eq. 3
OPA2681
16 SBOS091A
minimum value of 20Ω. Lower values will load both the
buffer stage at the input and the output stage if RF gets too
low—actually decreasing the bandwidth. Figure 8 shows the
recommended RF vs NG for both ±5V and a single +5V
operation. The values for RF vs Gain shown here are ap-
proximately equal to the values used to generate the Typical
Performance Curves. They differ in that the optimized val-
ues used in the Typical Performance Curves are also correct-
ing for board parasitics not considered in the simplified
analysis leading to Equation 3. The values shown in Figure
8 give a good starting point for design where bandwidth
optimization is desired.
the OPA2681. Figure 9 shows a typical inverting configura-
tion where the I/O impedances and signal gain from Figure
1 are retained in an inverting circuit configuration.
The total impedance going into the inverting input may be
used to adjust the closed loop signal bandwidth. Inserting a
series resistor between the inverting input and the summing
junction will increase the feedback impedance (denominator
of Equation 2), decreasing the bandwidth. The internal
buffer output impedance for the OPA2681 is slightly influ-
enced by the source impedance looking out of the non-
inverting input terminal. High source resistors will have the
effect of increasing RI, decreasing the bandwidth. For those
single supply applications which develop a midpoint bias at
the non-inverting input through high valued resistors, the
decoupling capacitor is essential for power supply ripple
rejection, non-inverting input noise current shunting, and to
minimize the high frequency value for RI in Figure 7.
INVERTING AMPLIFIER OPERATION
Since the OPA2681 is a general purpose, wideband current
feedback op amp, most of the familiar op amp application
circuits are available to the designer. Those dual op amp
applications that require considerable flexibility in the feed-
back element (e.g. integrators, transimpedance, some filters)
should consider the unity gain stable voltage feedback
OPA2680, since the feedback resistor is the compensation
element for a current feedback op amp. Wideband inverting
operation (and especially summing) is particularly suited to
FIGURE 8. Recommended Feedback Resistor vs Noise Gain.
600
500
400
300
200
100
0
Noise Gain
02010 155
FEEDBACK RESISTOR vs NOISE GAIN
Feedback Resistor (Ω)
+5V
±5V
1/2
OPA2681
RF
365Ω
RG
182Ω
+5V
–5V
50Ω50Ω Load
VO
Power supply
de-coupling
not shown
V
I
50Ω
Source
R
M
68.1Ω
FIGURE 9. Inverting Gain of –2 with Impedance Matching.
In the inverting configuration, two key design consider-
ations must be noted. The first is that the gain resistor (RG)
becomes part of the signal channel input impedance. If input
impedance matching is desired (which is beneficial when-
ever the signal is coupled through a cable, twisted pair, long
PC board trace or other transmission line conductor), it is
normally necessary to add an additional matching resistor to
ground. RG by itself is normally not set to the required input
impedance since its value, along with the desired gain, will
determine an RF which may be non-optimal from a fre-
quency response standpoint. The total input impedance for
the source becomes the parallel combination of RG and RM.
The second major consideration, touched on in the previous
paragraph, is that the signal source impedance becomes part
of the noise gain equation and will have slight effect on the
bandwidth through Equation 1. The values shown in Figure
9 have accounted for this by slightly decreasing RF (from
Figure 1) to re-optimize the bandwidth for the noise gain of
Figure 9 (NG = 2.74) In the example of Figure 9, the RM
value combines in parallel with the external 50Ω source
impedance, yielding an effective driving impedance of
50Ω || 68Ω = 28.8Ω. This impedance is added in series with
RG for calculating the noise gain—which gives NG = 2.74.
This value, along with the RF of Figure 8 and the inverting
input impedance of 45Ω, are inserted into Equation 3 to get
a feedback transimpedance nearly equal to the 492Ω opti-
mum value.
Note that the non-inverting input in this bipolar supply
inverting application is connected directly to ground. It is
often suggested that an additional resistor be connected to
ground on the non-inverting input to achieve bias current
error cancellation at the output. The input bias currents for
a current feedback op amp are not generally matched in
either magnitude or polarity. Connecting a resistor to ground
on the non-inverting input of the OPA2681 in the circuit of
17
OPA2681
SBOS091A
Figure 9 will actually provide additional gain for that input’s
bias and noise currents, but will not decrease the output DC
error since the input bias currents are not matched.
OUTPUT CURRENT AND VOLTAGE
The OPA2681 provides output voltage and current capabili-
ties that are unsurpassed in a low cost dual monolithic op
amp. Under no-load conditions at 25°C, the output voltage
typically swings closer than 1V to either supply rail; the
guaranteed swing limit is within 1.2V of either rail. Into a
15Ω load (the minimum tested load), it is guaranteed to
deliver more than ±135mA.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage x current, or V-I product,
which is more relevant to circuit operation. Refer to the
“Output Voltage and Current Limitations” plot in the Typi-
cal Performance Curves. The X and Y axes of this graph
show the zero-voltage output current limit and the zero-
current output voltage limit, respectively. The four quad-
rants give a more detailed view of the OPA2681’s output
drive capabilities, noting that the graph is bounded by a
“Safe Operating Area” of 1W maximum internal power
dissipation (in this case for 1 channel only). Superimposing
resistor load lines onto the plot shows that the OPA2681 can
drive ±2.5V into 25Ω or ±3.5V into 50Ω without exceeding
the output capabilities or the 1W dissipation limit. A 100Ω
load line (the standard test circuit load) shows the full ±3.9V
output swing capability, as shown in the Typical Specifica-
tions.
The minimum specified output voltage and current over
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup will the output
current and voltage decrease to the numbers shown in the
guaranteed tables. As the output transistors deliver power,
their junction temperatures will increase, decreasing their
VBE’s (increasing the available output voltage swing) and
increasing their current gains (increasing the available out-
put current). In steady state operation, the available output
voltage and current will always be greater than that shown
in the over-temperature specifications since the output stage
junction temperatures will be higher than the minimum
specified operating ambient.
To maintain maximum output stage linearity, no output
short circuit protection is provided. This will not normally
be a problem since most applications include a series match-
ing resistor at the output that will limit the internal power
dissipation if the output side of this resistor is shorted to
ground. However, shorting the output pin directly to the
adjacent positive power supply pin (8 pin package) will, in
most cases, destroy the amplifier. If additional short circuit
protection is required, consider a small series resistor in the
power supply leads. This will, under heavy output loads,
reduce the available output voltage swing. A 5Ω series
resistor in each power supply lead will limit the internal
power dissipation to less than 1W for an output short circuit
while decreasing the available output voltage swing only
0.5V for up to 100mA desired load currents. Always place
the 0.1uF power supply decoupling capacitors after these
supply current limiting resistors directly on the supply pins.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter—including
additional external capacitance which may be recommended
to improve A/D linearity. A high speed, high open-loop gain
amplifier like the OPA2681 can be very susceptible to
decreased stability and closed-loop response peaking when
a capacitive load is placed directly on the output pin. When
the amplifier’s open loop output resistance is considered,
this capacitive load introduces an additional pole in the
signal path that can decrease the phase margin. Several
external solutions to this problem have been suggested.
When the primary considerations are frequency response
flatness, pulse response fidelity and/or distortion, the sim-
plest and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series isolation
resistor between the amplifier output and the capacitive
load. This does not eliminate the pole from the loop
response, but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the phase lag
from the capacitive load pole, thus increasing the phase
margin and improving stability.
The Typical Performance Curves show the recommended
RS vs Capacitive Load and the resulting frequency response
at the load. Parasitic capacitive loads greater than 2pF can
begin to degrade the performance of the OPA2681. Long PC
board traces, unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA2681 output
pin (see Board Layout Guidelines).
DISTORTION PERFORMANCE
The OPA2681 provides good distortion performance into a
100Ω load on ±5V supplies. Relative to alternative solutions,
it provides exceptional performance into lighter loads and/or
operating on a single +5V supply. Generally, until the funda-
mental signal reaches very high frequency or power levels, the
2nd harmonic will dominate the distortion with a negligible
3rd harmonic component. Focusing then on the 2nd harmonic,
increasing the load impedance improves distortion directly.
Remember that the total load includes the feedback network—
in the non-inverting configuration (Figure 1) this is the sum of
RF + RG, while in the inverting configuration it is just RF. Also,
providing an additional supply de-coupling capacitor (0.1µF)
between the supply pins (for bipolar operation) improves the
2nd order distortion slightly (3 to 6dB).
In most op amps, increasing the output voltage swing in-
creases harmonic distortion directly. The Typical Perfor-
mance Curves show the 2nd harmonic increasing at a little
less than the expected 2X rate while the 3rd harmonic
increases at a little less than the expected 3X rate. Where the
test power doubles, the difference between it and the 2nd
OPA2681
18 SBOS091A
Evaluating these two equations for the OPA2681 circuit and
component values shown in Figure 1 will give a total output
spot noise voltage of 8.4nV/√Hz and a total equivalent input
spot noise voltage of 4.2nV/√Hz. This total input referred
spot noise voltage is higher than the 2.2nV/√Hz specifica-
tion for the op amp voltage noise alone. This reflects the
noise added to the output by the inverting current noise times
the feedback resistor. If the feedback resistor is reduced in
high gain configurations (as suggested previously), the total
input referred voltage noise given by Equation 5 will ap-
proach just the 2.2nV/√Hz of the op amp itself. For example,
going to a gain of +10 using RF = 180Ω will give a total
input referred noise of 2.4nV/√Hz .
harmonic decreases less than the expected 6dB while the
difference between it and the 3rd decreases by less than the
expected 12dB. This also shows up in the 2-tone 3rd order
intermodulation spurious (IM3) response curves. The 3rd
order spurious levels are extremely low at low output power
levels. The output stage continues to hold them low even as
the fundamental power reaches very high levels. As the
Typical Performance Curves show, the spurious
intermodulation powers do not increase as predicted by a
traditional intercept model. As the fundamental power level
increases, the dynamic range does not decrease significantly.
For 2 tones centered at 20MHz, with 10dBm/tone into a
matched 50Ω load (i.e. 2Vp-p for each tone at the load,
which requires 8Vp-p for the overall 2-tone envelope at the
output pin), the Typical Performance Curves show 62dBc
difference between the test tone power and the 3rd order
intermodulation spurious levels. This exceptional perfor-
mance improves further when operating at lower frequen-
cies.
NOISE PERFORMANCE
Wideband current feedback op amps generally have a higher
output noise than comparable voltage feedback op amps.
The OPA2681 offers an excellent balance between voltage
and current noise terms to achieve low output noise. The
inverting current noise (15pA/√Hz) is significantly lower
than earlier solutions while the input voltage noise
(2.2nV/√Hz) is lower than most unity gain stable, wideband,
voltage feedback op amps. This low input voltage noise was
achieved at the price of higher non-inverting input current
noise (12pA/√Hz). As long as the AC source impedance
looking out of the non-inverting node is less than 100Ω, this
current noise will not contribute significantly to the total
output noise. The op amp input voltage noise and the two
input current noise terms combine to give low output noise
under a wide variety of operating conditions. Figure 10
shows the op amp noise analysis model with all the noise
terms included. In this model, all noise terms are taken to
be noise voltage or current density terms in either nV/√Hz or
pA/√Hz.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 4 shows the general form for the
output noise voltage using the terms shown in Figure 10.
Dividing this expression by the noise gain (NG = (1+RF/RG))
will give the equivalent input referred spot noise voltage at the
non-inverting input as shown in Equation 5.
DC ACCURACY AND OFFSET CONTROL
A current feedback op amp like the OPA2681 provides
exceptional bandwidth in high gains, giving fast pulse set-
tling but only moderate DC accuracy. The Typical Specifi-
cations show an input offset voltage comparable to high
speed voltage feedback amplifiers. However, the two input
bias currents are somewhat higher and are unmatched.
Whereas bias current cancellation techniques are very effec-
tive with most voltage feedback op amps, they do not
generally reduce the output DC offset for wideband current
feedback op amps. Since the two input bias currents are
unrelated in both magnitude and polarity, matching the
source impedance looking out of each input to reduce their
error contribution to the output is ineffective. Evaluating the
configuration of Figure 1, using worst case +25°C input
offset voltage and the two input bias currents, gives a worst
case output offset range equal to:
± (NG x VOS(MAX)) + (IBN x RS/ 2 x NG) ± (IBI x RF)
where NG = non-inverting signal gain
= ± (2 x 5.0mV) + (55uA x 25Ω x 2) ± (402Ω x 40µA)
= ±10mV + 2.75mV ± 16mV
= –23.25mV → +28.25mV
4kT
R
G
R
G
R
F
R
S
1/2
OPA2681
I
BI
E
O
I
BN
4kT = 1.6E –20J
at 290°K
E
RS
E
NI
4kTR
S
÷
4kTR
F
÷
FIGURE 10. Op Amp Noise Analysis Model.
EO=ENI2+IBNRS
()
2+4kTRS
()
NG2+IBIRF
()
2+4kTRFNG
E
N
=E
NI2
+I
BN
R
S
()
2
+4kTR
S
+I
BI
R
F
NG
2
+4kTR
F
NG
19
OPA2681
SBOS091A
DISABLE OPERATION (SO-14 ONLY)
The OPA2681N provides an optional disable feature that
may be used either to reduce system power or to implement
a simple channel multiplexing operation. If the DIS control
pin is left unconnected, the OPA2681N will operate nor-
mally. To disable, the control pin must be asserted low.
Figure 11 shows a simplified internal circuit for the disable
control feature.
The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 12, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 1V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
VDIS pin from a higher speed logic line. If extremely fast
transition logic is used, a 2kΩ series resistor between the
logic gate and the VDIS input pin will provide adequate
bandlimiting using just the parasitic input capacitance on the
VDIS pin while still ensuring adequate logic level swing.
In normal operation, base current to Q1 is provided through
the 110kΩ resistor while the emitter current through the
15kΩ resistor sets up a voltage drop that is inadequate to
turn on the two diodes in Q1’s emitter. As VDIS is pulled
low, additional current is pulled through the 15kΩ resistor
eventually turning on these two diodes (≈ 100uA). At this
point, any further current pulled out of VDIS goes through
those diodes holding the emitter-base voltage of Q1 at
approximately zero volts. This shuts off the collector current
out of Q1, turning the amplifier off. The supply current in
the disable mode are only those required to operate the
circuit of Figure 11. Additional circuitry ensures that turn-on
time occurs faster than turn-off time (make-before-break).
When disabled, the output and input nodes go to a high
impedance state. If the OPA2681 is operating in a gain of
+1, this will show a very high impedance (4pF || 1MΩ) at the
output and exceptional signal isolation. If operating at a
gain greater than +1, the total feedback network resistance
(RF + RG) will appear as the impedance looking back into the
output, but the circuit will still show very high forward and
reverse isolation. If configured as an inverting amplifier, the
input and output will be connected through the feedback
network resistance (RF + RG) giving relatively poor input to
output isolation.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 12
shows these glitches for the circuit of Figure 1 with the input
signal set to zero volts. The glitch waveform at the output
pin is plotted along with the DIS pin voltage.
FIGURE 11. Simplified Disable Control Circuit, Each
Channel.
25kΩ110kΩ
15kΩ
I
S
Control –V
S
+V
S
V
DIS
Q1
FIGURE 12. Disable/Enable Glitch.
THERMAL ANALYSIS
Due to the high output power capability of the OPA2681,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction tempera-
ture will set the maximum allowed internal power dissipa-
tion as described below. In no case should the maximum
junction temperature be allowed to exceed 175°C. Operating
junction temperature (TJ) is given by TA + PD •
θ
JA. The total
internal power dissipation (PD) is the sum of quiescent
power (PDQ) and additional power dissipation in the output
stage (PDL) to deliver load power. Quiescent power is simply
the specified no-load supply current times the total supply
voltage across the part. PDL will depend on the required
output signal and load but would, for a grounded resistive
load, be at a maximum when the output is fixed at a voltage
equal to 1/2 of either supply voltage (for equal bipolar
supplies). Under this condition, PDL = VS2/(4 • RL) where RL
includes feedback network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using an
OPA2681 SO-8 in the circuit of Figure 1 operating at the
maximum specified ambient temperature of +85°C with
both outputs driving a grounded 20Ω load to +2.5V.
PD = 10V • 14.4mA + 2 • [52/(4 • (20Ω || 804Ω))] = 785mW
Maximum TJ = +85°C + (0.79 • 125°C/W) = 184°C
This absolute worst case condition exceeds specified maxi-
mum junction temperature. Normally this extreme case will
not be encountered. Careful attention to internal power
dissipation is required.
OPA2681
20 SBOS091A
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA2681 requires careful attention to
board layout parasitics and external component types. Rec-
ommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the non-
inverting input, it can react with the source impedance to
cause unintentional bandlimiting.. To reduce unwanted ca-
pacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbro-
ken elsewhere on the board.
b) Minimize the distance (< 0.25") from the power supply
pins to high frequency 0.1uF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power supply
connections (on pins 4 and 7) should always be decoupled
with these capacitors. An optional supply de-coupling ca-
pacitor across the two power supplies (for bipolar operation)
will improve 2nd harmonic distortion performance. Larger
(2.2uF to 6.8uF) decoupling capacitors, effective at lower
frequency, should also be used on the main supply pins.
These may be placed somewhat farther from the device and
may be shared among several devices in the same area of the
PC board.
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance of
the OPA2681. Resistors should be a very low reactance
type. Surface mount resistors work best and allow a tighter
overall layout. Metal film and carbon composition axially
leaded resistors can also provide good high frequency per-
formance. Again, keep their leads and PC board trace length
as short as possible. Never use wirewound type resistors in
a high frequency application. Since the output pin and
inverting input pin are the most sensitive to parasitic capaci-
tance, always position the feedback and series output resis-
tor, if any, as close as possible to the output pin. Other
network components, such as non-inverting input termina-
tion resistors, should also be placed close to the package.
Where double side component mounting is allowed, place
the feedback resistor directly under the package on the other
side of the board between the output and inverting input
pins. The frequency response is primarily determined by the
feedback resistor value as described previously. Increasing
its value will reduce the bandwidth, while decreasing it will
give a more peaked frequency response. The 402Ω feedback
resistor used in the typical performance specifications at a
gain of +2 on ±5V supplies is a good starting point for
design. Note that a 453Ω feedback resistor, rather than a
direct short, is recommended for the unity gain follower
application. A current feedback op amp requires a feedback
resistor even in the unity gain follower configuration to
control stability.
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50 to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set RS from the
plot of recommended RS vs Capacitive Load. Low parasitic
capacitive loads (< 5pF) may not need an RS since the
OPA2681 is nominally compensated to operate with a 2pF
parasitic load. If a long trace is required, and the 6dB signal
loss intrinsic to a doubly terminated transmission line is
acceptable, implement a matched impedance transmission
line using microstrip or stripline techniques (consult an ECL
design handbook for microstrip and stripline layout tech-
niques). A 50Ω environment is normally not necessary on
board, and in fact a higher impedance environment will
improve distortion as shown in the Distortion vs Load plots.
With a characteristic board trace impedance defined based
on board material and trace dimensions, a matching series
resistor into the trace from the output of the OPA2681 is
used as well as a terminating shunt resistor at the input of the
destination device. Remember also that the terminating
impedance will be the parallel combination of the shunt
resistor and the input impedance of the destination device:
this total effective impedance should be set to match the
trace impedance. The high output voltage and current capa-
bility of the OPA2681 allows multiple destination devices to
be handled as separate transmission lines, each with their
own series and shunt terminations. If the 6dB attenuation of
a doubly terminated transmission line is unacceptable, a
long trace can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case and set the
series resistor value as shown in the plot of RS vs Capacitive
Load. This will not preserve signal integrity as well as a
doubly terminated line. If the input impedance of the desti-
nation device is low, there will be some signal attenuation
due to the voltage divider formed by the series output into
the terminating impedance.
e) Socketing a high speed part like the OPA2681 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an ex-
tremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA2681
onto the board.
INPUT AND ESD PROTECTION
The OPA2681 is built using a very high speed complemen-
tary bipolar process. The internal junction breakdown volt-
ages are relatively low for these very small geometry de-
vices. These breakdowns are reflected in the Absolute Maxi-
mum Ratings table. All device pins have limited ESD
protection using internal diodes to the power supplies as
shown in Figure 13.
21
OPA2681
SBOS091A
External
Pin
+V
CC
–V
CC
Internal
Circuitry
FIGURE 13. Internal ESD Protection.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g. in systems with ±15V supply parts
driving into the OPA681), current limiting series resistors
should be added into the two inputs. Keep these resistor
values as low as possible since high values degrade both
noise performance and frequency response.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
OPA2681N OBSOLETE SOIC D 14 TBD Call TI Call TI
OPA2681N-1 OBSOLETE SOIC D 14 TBD Call TI Call TI
OPA2681N-1/2K5 OBSOLETE SOIC D 14 TBD Call TI Call TI
OPA2681N-12 NRND SOIC D 14 TBD Call TI Call TI
OPA2681N/2K5 OBSOLETE SOIC D 14 TBD Call TI Call TI
OPA2681N/2K5G4 OBSOLETE SOIC D 14 TBD Call TI Call TI
OPA2681N1 NRND SOIC D 14 TBD Call TI Call TI
OPA2681U OBSOLETE SOIC D 8 TBD Call TI Call TI
OPA2681U/2K5 OBSOLETE SOIC D 8 TBD Call TI Call TI
OPA2681UG4 OBSOLETE SOIC D 8 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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PACKAGE OPTION ADDENDUM
www.ti.com 15-Aug-2005
Addendum-Page 1
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