Semiconductor Components Industries, LLC, 2001
October, 2001 – Rev. 7 1Publication Order Number:
SN74LS122/D
SN74LS122, SN74LS123
Retriggerable Monostable
Multivibrators
These dc triggered multivibrators feature pulse width control by
three methods. The basic pulse width is programmed by selection of
external resistance and capacitance values. The LS122 has an internal
timing resistor that allows the circuits to be used with only an external
capacitor. Once triggered, the basic pulse width may be extended by
retriggering the gated low-level-active (A) or high-level-active (B)
inputs, or be reduced by use of the overriding clear.
•Overriding Clear Terminates Output Pulse
•Compensated for VCC and Temperature Variations
•DC Triggered from Active-High or Active-Low Gated Logic Inputs
•Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle
•Internal Timing Resistors on LS122
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V
TAOperating Ambient
Temperature Range 0 25 70 °C
IOH Output Current – High –0.4 mA
IOL Output Current – Low 8.0 mA
Rext External Timing Resistance 5.0 260 k
Cext External Capacitance No Restriction
Rext/Cext Wiring Capacitance at
Rext/Cext Terminal 50 pF
LOW POWER SCHOTTKY
SOIC
D SUFFIX
CASE 751A
PLASTIC
N SUFFIX
CASE 646
14
1
14
1
SOIC
D SUFFIX
CASE 751B
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
Device Package Shipping
ORDERING INFORMATION
SN74LS122N 14 Pin DIP 2000 Units/Box
SN74LS122D SOIC–14 55 Units/Rail
SN74LS122DR2 SOIC–14 2500/Tape & Reel
SN74LS123N 16 Pin DIP 2000 Units/Box
SN74LS123D SOIC–16 38 Units/Rail
SN74LS123DR2 SOIC–16 2500/Tape & Reel
SOEIAJ
M SUFFIX
CASE 966
16
1
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
SN74LS123M SOEIAJ–16 See Note 1
SN74LS123MEL SOEIAJ–16 See Note 1
http://onsemi.com
SN74LS122, SN74LS123
http://onsemi.com
2
SN74LS122 (TOP VIEW)
(SEE NOTES 1 THRU 4)
SN74LS123 (TOP VIEW)
(SEE NOTES 1 THRU 4)
NOTES:
1. An external timing capacitor may be connected between Cext and Rext/Cext (positive).
2. To use the internal timing resistor of the LS122, connect Rint to VCC.
3. For improved pulse width accuracy connect an external resistor between Rext/Cext and VCC with Rint opencircuited.
4. To obtain variable pulse widths, connect an external variable resistance between Rint/Cext and VCC.
14 13 12 11 10 9
123456
8
7
VCC
Rext/
Cext NC Cext NC Rint Q
A1 A2 B1 B2 CLR Q GND
CLR Q
Q
Rint
2
Rext/
Cext
1
Cext
1Rext/
Cext
14 13 12 11 10 9
123456 7
16 15
8
VCC
1A
1Q 2Q 2B
2
CLR 2A
1B 1
CLR
1Q 2Q 2
Cext
GND
Q
QQ
Q
CLR
CLR
NC  NO INTERNAL CONNECTION.
SN74LS122, SN74LS123
http://onsemi.com
3
LS122 FUNCTIONAL TABLE
INPUTS OUTPUTS
CLEAR A1 A2 B1 B2 Q Q
L X X X X L H
X H HXXLH
X X XLXLH
X X XXLLH
H L X ↑H
H L XH↑
H X L ↑H
H X LH↑
H H ↓HH
H↓ ↓ HH
H↓HHH
↑LXHH
↑X L H H
LS123 FUNCTIONAL TABLE
INPUTS OUTPUTS
CLEAR A B Q Q
L X X L H
X H XLH
X X LLH
H L ↑
H↓H
↑L H
TYPICAL APPLICATION DATA
The output pulse tW is a function of the external
components, C ext and Rext or Cext and Rint on the LS122.
For values of Cext ≥ 1000 pF, the output pulse at VCC = 5.0
V and VRC = 5.0 V (see Figures 1, 2, and 3) is given by
tW = K Rext Cext where K is nominally 0.45
If C ext is on pF and Rext is in kΩ then tW is in nanoseconds.
The Cext terminal of the LS122 and LS123 is an internal
connection to ground, however for the best system
performance Cext should be hard-wired to ground.
Care should be taken to keep Rext and Cext as close to the
monostable as possible with a minimum amount of
inductance between the Rext/Cext junction and the Rext/Cext
pin. Good groundplane and adequate bypassing should be
designed into the system for optimum performance to ensure
that no false triggering occurs.
It should be noted that the Cext pin is internally connected
to ground on the LS122 and LS123, but not on the LS221.
Therefore, if Cext is hard-wired externally to ground,
substitution of a LS221 onto a LS123 socket will cause the
LS221 to become non-functional.
The switching diode is not needed for electrolytic
capacitance application and should not be used on the LS122
and LS123.
T o find the value of K for Cext ≥ 1000 pF, refer to Figure 4.
Variations on VCC or VRC can cause the value of K to
change, as can the temperature of the LS123, LS122.
Figures 5 and 6 show the behavior of the circuit shown in
Figures 1 and 2 if separate power supplies are used for V CC
and V RC. If VCC is tied to VRC, Figure 7 shows how K will
vary with VCC and temperature. Remember, the changes in
Rext and Cext with temperature are not calculated and
included in the graph.
As long as Cext ≥ 1000 pF and 5K ≤ Rext ≤ 260K, the
change in K with respect to Rext is negligible.
If C ext ≤ 1000 pF the graph shown on Figure 8 can be used
to determine the output pulse width. Figure 9 shows how K
will change for Cext ≤ 1000 pF if VCC and VRC are connected
to the same power supply. The pulse width tW in
nanoseconds is approximated by
tW = 6 + 0.05 Cext (pF) + 0.45 Rext (kΩ) Cext + 11.6 Rext
In order to trim the output pulse width, it is necessary to
include a variable resistor between V CC and the Rext/Cext pin
or between VCC and the Rext pin of the LS122. Figure 10, 11,
and 12 show how this can be done. Rext remote should be
kept as close to the monostable as possible.
Retriggering of the part, as shown in Figure 3, must not
occur before Cext is discharged or the retrigger pulse will not
have any effect. The discharge time of Cext in nanoseconds
is guaranteed to be less than 0.22 Cext (pF) and is typically
0.05 Cext (pF).
For the smallest possible deviation in output pulse widths
from various devices, it is suggested that Cext be kept
≥1000 pF.
SN74LS122, SN74LS123
http://onsemi.com
4
WAVEFORMS
EXTENDING PULSE WIDTH
OVERRIDING THE OUTPUT PULSE
B INPUT
Q OUTPUT
B INPUT
CLEAR INPUT CLEAR PULSE
Q OUTPUT OUTPUT WITHOUT CLEAR PULSE
RETRIGGER
PULSE (See Application Data)
OUTPUT WITHOUT RETRIGGER
tW
SN74LS122, SN74LS123
http://onsemi.com
5
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage 0.8 VGuaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Out
p
ut LOW Voltage
0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN VIL or VIH
VOL Output LOW Voltage 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH
per Truth Table
IIH
In
p
ut HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
IIH Input HIGH Current 0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 2) –20 –100 mA VCC = MAX
ICC
Power Su
pp
ly Current
LS122 11
mA
VCC = MAX
ICC Power Supply Current LS123 20 mA VCC = MAX
2. Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
t
PLH
Propa
g
ation Dela
y
, A to Q 23 33
ns
tPLH
tPHL
Pro agation
Delay
,
A
to
Q
Propagation Delay, A to Q 32 45 ns C
ext
= 0
t
PLH
Propa
g
ation Dela
y
, B to Q 23 44
ns
C
ex
t
=
0
CL = 15 pF
tPLH
tPHL
Pro agation
Delay
,
B
to
Q
Propagation Delay, B to Q 34 56 ns R
ext
= 5.0 kΩ
t
PLH
Propa
g
ation Dela
y
, Clear to Q 28 45
ns
Rext
=
5
.
0
kΩ
RL = 2.0 kΩ
tPLH
tPHL
Pro agation
Delay
,
Clear
to
Q
Propagation Delay, Clear to Q 20 27 ns
tWmin A or B to Q 116 200 ns C
ext
= 1000 pF, R
ext
= 10 kΩ,
tWQA to B to Q 4.0 4.5 5.0 µs
Cext
=
1000
F
,
Rext
=
10
kΩ
,
CL = 15 pF, RL = 2.0 kΩ
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
tWPulse Width 40 ns
SN74LS122, SN74LS123
http://onsemi.com
6
Figure 1. Figure 2.
Figure 3.
Figure 4.
VCC VRC VCC
Cext 0.1 µF
Pout
Cext Rext/
Cext VCC
Q
CLR
B
CLR
B2
B1
A2
A1
1/2 LS123 LS122
Rext
Q
GND
A
51 Ω
Pin
Pin
Pout tW
RETRIGGER
5K ≤ Rext ≤ 260K
10
1
0.1
0.01
0.001 0.3 0.35 0.4 0.45 0.5 0.55
K
EXTERNAL CAPACITANCE, C ( F)
µ
ext
VCC VRC VCC
Cext 0.1 µF
Pout
Cext Rext/
Cext VCC
Q
Rext
Q
GND
51 Ω
Pin
SN74LS122, SN74LS123
http://onsemi.com
7
Figure 5. K versus VCC Figure 6. K versus VRC Figure 7. K versus VCC and VRC
VCC
VCC = 5 V
Cext = 1000 pF
VRC
Cext = 1000 pF
0.55
0.5
K
0.45
0.4
0.35 4.5 5 5.5
VCC
= VRC
125°C
70°C
25°C
0°C
-55°C
VRC = 5 V
Cext = 1000 pF
125°C
70°C
0°C-55°C
125°C
25°C
0°C
-55°C
70°C
25°C
100000
10000
1000
100
10 1 10 100 1000
tW
Cext, EXTERNAL TIMING CAPACITANCE (pF)
Rext = 80 kΩ
Rext = 40 kΩ
Rext = 20 kΩ
Rext = 10 kΩ
Rext = 5 kΩ
, OUTPUT PULSE WIDTH (ns)
Rext = 260 kΩ
Rext = 160 kΩ
4.5 5 5.54.5 5 5.5
0.55
0.5
K
0.45
0.4
0.35
0.55
0.5
K
0.45
0.4
0.35
Figure 8.
SN74LS122, SN74LS123
http://onsemi.com
8
Figure 9.
Figure 10. LS123 Remote Trimming Circuit
Cext = 200 pF
0.65
0.6
K0.55
0.5
4.5 4.75 5 5.25 5.5
VCC VOLTS
125°C
70°C
25°C
0°C
-55°C
VCC
Rext
REMOTE
Rext
Cext
PIN 7
OR 15
PIN 6
OR 14
SN74LS122, SN74LS123
http://onsemi.com
9
Figure 11. LS122 Remote Trimming Circuit Without Rext
Figure 12. LS122 Remote Trimming Circuit with Rint
OPEN
VCC
Rext
REMOTE
Rext
Cext
PIN 13
PIN 11
PIN 9
VCC
Rext
REMOTE
PIN 13
PIN 11
PIN 9
SN74LS122, SN74LS123
http://onsemi.com
10
PACKAGE DIMENSIONS
17
14 8
B
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 18.80
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L
M--- 10 --- 10
N0.015 0.039 0.38 1.01

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
HG DK
C
SEATING
PLANE
N
–T–
14 PL
M
0.13 (0.005)
L
M
J0.290 0.310 7.37 7.87
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P7 PL
14 8
71 M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
–T–
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
 
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE M
SN74LS122, SN74LS123
http://onsemi.com
11
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
FC
S
HGD
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45
G
8 PLP
–B–
–A–
M
0.25 (0.010) B S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019

SN74LS122, SN74LS123
http://onsemi.com
12
PACKAGE DIMENSIONS
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
10 0
10
LEQ1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
M SUFFIX
SOEIAJ PACKAGE
CASE 966–01
ISSUE O
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
SN74LS122/D
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
N. American Technical Support: 800–282–9855 Toll Free USA/Canada