ADS900E/1KG4 - Texas Instruments

FEATURES

●+2.7V TO +3.7V SUPPLY OPERATION

●INTERNAL REFERENCE

●LOW POWER: 52mW at +3V

●SINGLE-ENDED INPUT RANGE: 1V to 2V

●WIDEBAND TRACK/HOLD: 350MHz

●SSOP-28 PACKAGE

DESCRIPTION

The ADS900 is a high-speed pipelined Analog-to-Digital

Converter (ADC). This complete converter includes a high

bandwidth track-and-hold, a 10-bit quantizer, and an inter-

nal reference.

The ADS900 employs digital error correction techniques to

provide excellent differential linearity for demanding im-

aging applications. Its low distortion and high SNR give the

extra margin needed for telecommunications, video and

test instrumentation applications.

This high-performance ADC is specified for performance

at a 20MHz sampling rate. The ADS900 is available in an

SSOP-28 package.

10-Bit, 20MHz, +3V Supply

ANALOG-TO-DIGITAL CONVERTER

APPLICATIONS

●PORTABLE INSTRUMENTATION

●IF AND BASEBAND COMMUNICATIONS

●CABLE MODEMS

●SET-TOP BOXES

●PORTABLE TEST EQUIPMENT

●COMPUTER SCANNERS

Pipeline

A/D

Internal

Reference

Timing

Circuitry

Error

Correction 3-State

Outputs

T/H 10-Bit

Digital

Data

CLK

ADS900

LVDD

OEPwrdn1VREF

LnByCMLpBy

(Opt.)

ADS900

SBAS058A – MAY 2001

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ADS900E

ADS900

2SBAS058A

ELECTRICAL CHARACTERISTICS

At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

+VS....................................................................................................... +6V

Analog Input ...............................................................................+VS +0.3V

Logic Input .................................................................................+VS +0.3V

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature..................................................................... +150°C

ABSOLUTE MAXIMUM RATINGS

ADS900E

PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS

Resolution 10 Bits

Specified Temperature Range Ambient Air –40 +85 °C

ANALOG INPUT

Single-Ended Full Scale Input Range (1Vp-p) +1.0 +2.0 V

Differential Full Scale Input Range (0.5Vp-pX 2)

+1.25 +1.75 V

Common-Mode Voltage 1.5 V

Analog Input Bias Current 1µA

Input Impedance 1.25 || 5 MΩ || pF

DIGITAL INPUTS

Logic Family TTL/HCT COMPATIBLE CMOS

High Input Voltage, VIH 2.0 VDD V

Low Input Voltage, VIL 0.8 V

High Input Current, IIH ±10 µA

Low Input Current, IIL ±10 µA

Input Capacitance 5pF

CONVERSION CHARACTERISTICS

Start Conversion

RISING EDGE OF CONVERT CLOCK

Sample Rate Full 10k 20M Samples/s

Data Latency 5 Clk Cyc

PACKAGE SPECIFIED

DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER(1) MEDIA

ADS900E SSOP-28 324 –40°C to +85°C ADS900E ADS900E Rails

""""ADS900E ADS900E/1K Tape and Reel

NOTE: (1) Models with a slash ( /) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces

of “ADS900E/1K” will get a single 1000-piece Tape and Reel.

PACKAGE/ORDERING INFORMATION

ADS900 3

SBAS058A

ELECTRICAL CHARACTERISTICS (Cont.)

At TA = +25°C, VS = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified.

ADS900E

PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS

DYNAMIC CHARACTERISTICS

Differential Linearity Error

f = 500kHz (Largest Code Error) Full ±0.7 LSBs

f = 10MHz (Largest Code Error) Full ±0.7 ±1.0 LSBs

No Missing Codes Full Guaranteed

Integral Nonlinearity Error, f = 500kHz Full ±3.5 LSBs

Spurious Free Dynamic Range(1)

f = 500kHz (–1dBFS(2) input) Full 53 dBFS(2)

f = 10MHz (–1dBFS(2) input) Full 47 53 dBFS

Two-Tone Intermodulation Distortion(3)

f = 4.5MHz and 5.0MHz (–7dBFS each tone) +25°C 50 dBc

Signal-to-Noise Ratio (SNR)

f = 500kHz (–1dBFS input) Full 49 dB

f = 10MHz (–1dBFS input) Full 45 49 dB

Signal-to-(Noise + Distortion) (SINAD)

f = 500kHz (–1dBFS input) Full 48 dB

f = 3.58MHz (–1dBFS input) Full 48 dB

f = 10MHz (–1dBFS input) Full 44 48 dB

Differential Gain Error NTSC, PAL 2.3 %

Differential Phase Error NTSC, PAL 1 degrees

Output Noise Input Grounded 0.2 LSBs rms

Aperture Delay Time 2ns

Aperture Jitter 7 ps rms

Analog Input Bandwidth

Small Signal –20dBFS Input +25°C 350 MHz

Full Power 0dBFS Input +25°C 100 MHz

Overvoltage Recovery Time(4) 1.5X FS Input +25°C2 ns

DIGITAL OUTPUTS CL = 15pF

Logic Family TTL/HCT COMPATIBLE CMOS

Logic Coding Straight Offset Binary

High Output Voltage, VOH +2.4 LVDD V

Low Output Voltage, VOL +0.4 V

3-State Enable Time OE = L 20 40 ns

3-State Disable Time OE = H 2 10 ns

Internal Pull-Down 50 kΩ

Power-Down Enable Time PwrDn = L 133 ns

Power-Down Disable Time PwrDn = H 18 ns

Internal Pull-Down 50 kΩ

ACCURACY fS = 2.5MHz

Gain Error +25°C8±10 %FS

Input Offset Referred to Ideal Midscale Full 15 ±60 mV

Power Supply Rejection (Gain) ∆ VS = +10% Full 55 dB

Power Supply Rejection (Offset) Full 62 dB

Internal Positive Reference Voltage Full +1.75 V

Internal Negative Reference Voltage Full +1.25 V

POWER SUPPLY REQUIREMENTS

Supply Voltage: +VSOperating Full +2.7 +3 +3.7 V

Supply Current: +ISOperating Full 18 22 mA

Power Dissipation Operating, +3V Full 54 66 mW

25°C52mW

Power Dissipation (Power Down) +3V Full 10 mW

Thermal Resistance,

SSOP-28 89 °C/W

NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to full scale. (3) Two-tone intermodulation

distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (4) No

rollover of bits.

ADS900

4SBAS058A

5 Clock Cycles

Data Invalid

CONV

N–5N–4N–3N–2N–1 N N+1 N+2

Data Out

Clock

Analog In N

N+1 N+2 N+3 N+4 N+5 N+6 N+7

PIN CONFIGURATION

PIN DESIGNATOR DESCRIPTION

1+V

SAnalog Supply

2LV

DD Output Logic Driver Supply Voltage

3 Bit 10 Data Bit 10 (D0) (LSB)

4 Bit 9 Data Bit 9 (D1)

5 Bit 8 Data Bit 8 (D2)

6 Bit 7 Data Bit 7 (D3)

7 Bit 6 Data Bit 6 (D4)

8 Bit 5 Data Bit 5 (D5)

9 Bit 4 Data Bit 4 (D6)

10 Bit 3 Data Bit 3 (D7)

11 Bit 2 Data Bit 2 (D8)

12 Bit 1 Data Bit 1 (D9) (MSB)

13 GND Analog Ground

14 GND Analog Ground

15 CLK Convert Clock Input

16 OE Output Enable, Active Low

17 Pwrdn Power Down Pin

18 +VSAnalog Supply

19 GND Analog Ground

20 GND Analog Ground

21 LpBy Positive Ladder Bypass

22 NC No Connection

23 1VREF 1V Reference Output

24 IN Complementary Input

25 LnBy Negative Ladder Bypass

26 CM Common-Mode Voltage Output

27 IN Analog Input

28 +VSAnalog Supply

PIN DESCRIPTIONS

Top View SSOP

TIMING DIAGRAM

SYMBOL DESCRIPTION MIN TYP MAX UNITS

tCONV Convert Clock Period 50 100µsns

tLClock Pulse Low 24 25 ns

tHClock Pulse High 24 25 ns

tDAperture Delay 2 ns

t1Data Hold Time, CL = 0pF 3.9 ns

t2New Data Delay Time, CL = 15pF max 12 ns

LSB Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

MSB Bit 1

GND

LnBy

REF

LpBy

GND

Pwrdn

CLK

ADS900

ADS900 5

SBAS058A

TWO-TONE INTERMODULATION

Frequency (MHz)

–20

–40

–60

–80

–100 024 8610

Magnitude (dBFS)

= 3.5MHz at –7dBFS

= 3.4MHz at –7dBFS

SPECTRAL PERFORMANCE

Frequency (MHz)

–20

–40

–60

–80

–100 0246810

Amplitude (dB)

= 9MHz

SPECTRAL PERFORMANCE

Frequency (MHz)

–20

–40

–60

–80

–100 0246810

Amplitude (dB)

= 3MHz

SPECTRAL PERFORMANCE

Frequency (MHz)

–20

–40

–60

–80

–100 0246810

Amplitude (dB)

= 500kHz

0 256 512 768 1024

DIFFERENTIAL LINEARITY ERROR

Output Code

2.0

1.0

0.0

–1.0

–2.0

Error (LSB)

= 10MHz

DIFFERENTIAL LINEARITY ERROR

Output Code

2.0

1.0

0.0

–1.0

–2.0 0 256 512 768 1024

DLE (LSB)

= 500kHz

TYPICAL CHARACTERISTICS

At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified.

ADS900

6SBAS058A

UNDERSAMPLING (With Differential Input)

Frequency (MHz)

–20

–40

–60

–80

–100

–120 02468

Amplitude (dB)

= 20MHz

= 16MHz

INTEGRAL LINEARITY ERROR

Output Code

10.0

5.0

–5.0

–10.0 0 200 400 600 800 1000

ILE (LSB)

= 500kHz

TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified.

SWEPT POWER SFDR

Input Amplitude

0–80 –40–60 –30 –20 –10 0

SFDR (dBFS, dBc)

dBFS

dBc

DYNAMIC PERFORMANCE vs INPUT FREQUENCY

Frequency (MHz)

490.1 1 10 100

SFDR, SNR (dB)

SFDR

SNR

DIFFERENTIAL LINEARITY ERROR

vs TEMPERATURE

Temperature (°C)

0.8

0.7

0.6

0.5–50 0 25–25 50 75 100

DLE (LSBs)

fIN = 500kHz

fIN = 10MHz

SPURIOUS FREE DYNAMIC RANGE (SFDR)

vs TEMPERATURE

Temperature (°C)

45–50 0 25–25 50 75 100

SFDR (dBFS)

fIN = 500kHz

fIN = 10MHz

ADS900 7

SBAS058A

TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, VS = LVDD = +3V, Single-Ended Input, Sampling Rate = 20MHz, unless otherwise specified.

GAIN ERROR vs TEMPERATURE

Temperature (°C)

6.5

6.0

5.5

5.0

4.5–50 0 25–25 50 75 100

Gain (%FSR)

OFFSET ERROR vs TEMPERATURE

Temperature (°C)

–25

–30

–35

–40

–45–50 0 25–25 50 75 100

Offset Error (mV)

POWER DISSIPATION vs TEMPERATURE

Temperature (°C)

50–50 0 25–25 50 75 100

Power (mW)

OUTPUT NOISE HISTOGRAM (DC Input)

Output Code

500

400

300

200

100

0N-3 N-1 NN-2 N+1 N+2 N+3

Counts

SIGNAL-TO-NOISE RATIO (SNR) vs TEMPERATURE

Temperature (°C)

40 025–25–50 50 75 100

SNR (dB)

= 10MHz

= 500kHz

ADS900

8SBAS058A

FIGURE 1. Input Track-And-Hold Configuration with

Timing Signals.

FIGURE 2. Pipeline A/D Architecture.

THEORY OF OPERATION

The ADS900 is a high speed sampling ADC that utilizes a

pipeline architecture. The fully differential topology and

digital error correction guarantee 10-bit resolution. The

track-and-hold circuit is shown in Figure 1. The switches are

controlled by an internal clock which has a non-overlapping

two phase signal, φ1 and φ2. At the sampling time the input

signal is sampled on the bottom plates of the input capaci-

tors. In the next clock phase, φ2, the bottom plates of the

input capacitors are connected together and the feedback

capacitors are switched to the op amp output. At this time the

charge redistributes between CI and CH, completing one

track-and-hold cycle. The differential output is a held DC

representation of the analog input at the sample time. In the

normal mode of operation, the complementary input is tied

to the common-mode voltage. In this case, the track-and-

hold circuit converts a single-ended input signal into a fully

differential signal for the quantizer. Consequently, the input

signal gets amplified by a gain or two, which improves the

signal-to-noise performance. Other parameters such as small-

signal and full-power bandwidth, and wideband noise are

also defined in this stage.

(Opt.)

OUT

Op Amp

Bias V

Op Amp

Bias V

Input Clock (50%)

Internal Non-overlapping Clock

+–

B1 (MSB)

B10 (LSB)

2-Bit

DAC

2-Bit

Flash

Input

T/H Digital Delay

2-Bit

DAC

2-Bit

Flash

Digital Delay

2-Bit

Flash Digital Delay

2-Bit

DAC

2-Bit

Flash

Digital Delay

Digital Error Correction

STAGE 1

STAGE 2

STAGE 8

STAGE 9

+–

(Opt.)

ADS900 9

SBAS058A

The pipelined quantizer architecture has 9 stages with each

stage containing a two-bit quantizer and a two bit Digital-

to-Analog Converter (DAC), as shown in Figure 2. Each

two-bit quantizer stage converts on the edge of the sub-

clock, which is the same frequency of the externally applied

clock. The output of each quantizer is fed into its own delay

line to time-align it with the data created from the following

quantizer stages. This aligned data is fed into a digital error

correction circuit which can adjust the output data based on

the information found on the redundant bits. This technique

provides the ADS900 with excellent differential linearity

and guarantees no missing codes at the 10-bit level.

The ADS900 includes an internal reference circuit that

provides the bias voltages for the internal stages (for details

see “Internal Reference”). A midpoint voltage is established

by the built-in resistor ladder that is made available at pin 26

“CM”. This voltage can be used to bias the inputs up to the

recommended common-mode voltage or used to level shift

the input driving circuitry. The ADS900 can be used in both

a single-ended or differential input configuration. When

operated in single-ended mode, the reference midpoint (pin

26) should be tied to the inverting input, pin 24.

To accommodate a bipolar signal swing, the ADS900 oper-

ates with a common-mode voltage (VCM) which is derived

from the internal references. Due to the symmetric resistor

ladder inside the ADS900, the VCM is situated between the

top and bottom reference voltage. The following equation

can be used for calculating the common-mode voltage level.

VCM = (REFT +REFB)/2 (1)

DIGITAL OUTPUT DATA

The 10-bit output data is provided at CMOS logic levels.

There is a 5.0 clock cycle data latency from the start convert

signal to the valid output data. The standard output coding

is Straight Offset Binary where a full scale input signal

corresponds to all “1’s” at the output. The digital outputs of

the ADS900 can be set to a high impedance state by driving

the OE (pin 16) with a logic “HI”. Normal operation is

achieved with pin 16 “LO” or Floating due to internal pull-

down resistor. This function is provided for testability

purposes but is not recommended to be used dynamically.

The capacitive loading on the digital outputs should be kept

below 15pF.

APPLICATIONS

DRIVING THE ANALOG INPUTS

Figure 3 shows an example of an ac-coupled, single-ended

interface circuit using high-speed op amps that operate on

dual supplies (OPA650, OPA658, OPA680 and OPA681).

The common-mode reference voltage (VCM), here +1.5V,

biases the bipolar, ground-referenced input signal. The ca-

pacitor C1 and resistor R1 form a high-pass filter with the

–3dB frequency set at

f–3dB = 1/(2 π R1 C1)(2)

TABLE I. Coding Table for the ADS900.

+FS (IN = +2V) 1111111111

+FS –1LSB 1111111111

+FS –2LSB 1111111110

+3/4 Full Scale 1110000000

+1/2 Full Scale 1100000000

+1/4 Full Scale 1010000000

+1LSB 1000000001

Bipolar Zero (IN +1.5V) 1000000000

–1LSB 0111111111

–1/4 Full Scale 0110000000

–1/2 Full Scale 0100000000

–3/4 Full Scale 0010000000

–FS +1LSB 0000000001

–FS (IN = +1V) 0000000000

STRAIGHT OFFSET BINARY

(SOB)

SINGLE-ENDED INPUT PIN 12

(IN = 1.5V DC) FLOATING or LO

FIGURE 3. AC-Coupled Driver.

The values for C1 and R1 are not critical in most applications

and can be set freely. The values shown correspond to a

–3dB corner frequency of 1.6kHz.

Figure 4 depicts a circuit that can be used in single-supply

applications. The common-mode voltage biases the op amp

up to the appropriate common-mode voltage, for example

VCM = +1.5V. With the use of capacitor CG the DC gain for

the non-inverting op amp input is set to +1V/V. As a result

the transfer function is modified to

VOUT = VIN {(1 + RF/RG) + VCM}(3)

Again, the input coupling capacitor C1 and resistor R1 form

a high-pass filter. At the same time the input impedance is

defined by R1. Resistor RS isolates the op amp’s output from

the capacitive load to avoid gain peaking or even oscillation.

It can also be used to establish a defined roll-off for the

wideband noise. Its value is usually between 10Ω and 100Ω.

DIFFERENTIAL MODE OF OPERATION

Some minor performance improvements in SFDR and THD

can be realized by operating the ADS900 in its optional

differential configuration. A RF-transformer with a center

tap provides the best method of performing a single-ended to

differential conversion and interface directly to the ADS900.

402Ω

OPA65x

OPA68x

402Ω

1kΩ

0.1µF

ININ

1.5V

+5V

–5V

+3V

ADS900

10 SBAS058A

OPA680

VIN

VCM = 1.5V

I = 250µA

0.1µF

+1.5V

REFB

+1.25V

RIN

+3V

+5V

VOS

0.1µF

22pF

0.1µF

ADS900

1kΩ

OPA68x

VIN

402Ω

VCM = 1.5V

0.1µF

ININ CM

+5V

50Ω

+3V

402Ω

0.1µF

22pF ADS900

As a passive component, a transformer can be used to step-

up the signal amplitude without adding noise or distortion.

At the same time it electrically isolates the front-end from

the converter. In order to achieve optimum performance and

to bias the converter inputs up to the correct common-mode

voltage the mid-reference pin “CM” can be tied directly to

the center tap of the transformer.

Figure 6 shows an example for a single-ended DC-coupled

interface circuit using one high-speed op amp to level-shift

the ground-referenced input signal to condition it for the

input requirements of the ADS900. With a +3V supply the

input signal swings 1Vp-p centered around a typical com-

mon-mode voltage of +1.5V. This voltage can be derived

from the internal bottom reference (REFB = +1.25V) and

then fed back through a resistor divider (R1, R2) to level shift

the driving op amp (OPA680). A capacitor across R2 will

shunt most of the wideband noise to ground. Depending on

the configured gain the values of resistors R1 and R2 must be

adjusted since the offsetting voltage (VOS) is amplified by

the non-inverting gain, 1+(RF/RIN). This example assumes

the sum of R1 and R2 to be 5kΩ, drawing only 250µA from

the bottom reference. Considerations for the selection of a

FIGURE 6. Single-Ended DC-Coupled Input Circuit.

FIGURE 4. Driver Circuit Using Single Supply.

FIGURE 5. Single-Ended to Differential Drive Circuit Using a Transformer.

OPA65x

VIN

RF Transformer: Minicircuits TT1-6 0.1µF

RST1

22pF

ADS900

+3V

ADS900 11

SBAS058A

proper op amp should include its output swing, input com-

mon-mode range, and bias current. It should be noted that

any DC voltage difference between the inputs, IN and IN,

will show up as an offset at the output. At the same time an

offset adjustment can be accomplished.

INTERNAL REFERENCE

The ADS900 features an internal pipeline reference that

provides fixed reference voltages for the internal stages. As

shown in Figure 7 a buffer for each the top and bottom

reference is connected to the resistor ladder, which has a

nominal resistance of 4kΩ (±15%). The two outputs of the

buffers are brought out at pin 21 (LpBy) and pin 25 (LnBy),

primarily to connect external bypass capacitors, typically

0.1µF, which will improve the performance. The buffers can

drive limited external loads, for example for level shifting of

the converter’s interface circuit, however, the current draw

should be limited to approximately 1mA.

Derived from the top reference of +1.75V is an additional

voltage of +1.0V. Note that this voltage, available on pin 23,

is not buffered and care should be taken when external loads

are applied. In normal operation, this pin is left unconnected

and no bypassing components are required.

CLOCK INPUT REQUIREMENTS

The clock input of the ADS900 is designed to accommodate

either +5V or +3V CMOS logic levels. To drive the clock

input with a minimum amount of duty cycle variation and

support maximum sampling rates (20Msps) high speed or

advanced CMOS logic should be used (HC/HCT, AC/ACT).

When digitizing at high sampling rates, a 50% duty cycle

along with fast rise and fall times (2ns or less) are recom-

mended to meet the rated performance specifications. How-

ever, the ADS900 performance is tolerant to duty cycle

variations of as much as ±10% without degradation. For

applications operating with input frequencies up to Nyquist

or undersampling applications, special considerations must

be made to provide a clock with very low jitter. Clock jitter

leads to aperture jitter (tA) which can be the ultimate limita-

tion in achieving good SNR performance. The following

equation shows the relationship between aperture jitter,

input frequency and the signal-to-noise ratio:

SNR = 20log10 [1/(2 π fIN tA)] (4)

For example, in the case of a 10MHz full-scale input signal

and an aperture jitter of tA = 20ps the SNR is clock jitter

limited to 58dB.

DIGITAL OUTPUTS

The digital outputs of the ADS900 are standard CMOS

stages and designed to be compatible to both high speed

TTL and CMOS logic families. The logic thresholds are for

low-voltage CMOS: VOL = 0.4V, VOH = 2.4V, which allows

the ADS900 to directly interface to 3V-logic. The digital

outputs of the ADS900 uses a dedicated digital supply pin

(pin 2, LVDD) see Figure 8. By adjusting the voltage on

LVDD, the digital output levels will vary respectively. It is

recommended to limit the fan-out to one to keep the capaci-

tive loading on the data lines below the specified 15pF. If

necessary, external buffers or latches may be used which

provide the added benefit of isolating the ADC from any

digital activities on the bus coupling back high frequency

noise and degrading the performance.

FIGURE 7. Internal Reference Structure and Recommended Reference Bypassing.

ADS900

2.8kΩ

2kΩ

+1.75V

+1.25V

2.1kΩ0.1µF

REFT

REFB

LpBy

+1V

REF

0.1µF LnBy

0.1µF

ADS900

12 SBAS058A

+VS

113 14

GND

ADS900

0.1µF

+VS

18 19 20

GND

0.1µF

+VS

0.1µF

POWER-DOWN MODE

The ADS900’s low power consumption can be reduced even

further by initiating a power down mode. For this, the Power

Down Pin (Pin 17) must be tied to a logic “High” reducing

the current drawn from the supply by about 70%. In normal

operation the power-down mode is disabled by an internal

pull-down resistor (50kΩ).

During power-down the digital outputs are set in 3-state.

With the clock applied, the converter does not accurately

process the sampled signal. After removing the power-down

condition the output data from the following 5 clock cycles

is invalid (data latency).

DECOUPLING AND GROUNDING

CONSIDERATIONS

The ADS900 has several supply pins, one of which is

dedicated to only supply the output driver (LVDD). The

remaining supply pins are not divided into analog and digital

supply pins since they are internally connected on the chip.

For this reason it is recommended to treat the converter as an

analog component and to power it from the analog supply

only. Digital supply lines often carry high levels of noise

which can couple back into the converter and limit the

performance.

Because of its fast switching architecture, the converter also

generates high frequency transients and noise that are fed

back into the supply and reference lines. This requires that

the supply and reference pins be sufficiently bypassed.

Figure 9 shows the recommended decoupling scheme for the

analog supplies. In most cases 0.1µF ceramic chip capacitors

are adequate to keep the impedance low over a wide fre-

quency range. Their effectiveness largely depends on the

proximity to the individual supply pin. Therefore they should

be located as close to the supply pins are possible.

FIGURE 8. Independent Supply Connection for Output

Stage.

+LV

ADS900 Digital

Output

Stage

FIGURE 9. Recommended Bypassing for Analog Supply

Pins.

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

ADS900E ACTIVE SSOP DB 28 50 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS900E/1K ACTIVE SSOP DB 28 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

ADS900E/1KG4 ACTIVE SSOP DB 28 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

ADS900EG4 ACTIVE SSOP DB 28 50 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 26-Sep-2008

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm) W

(mm) Pin1

Quadrant

ADS900E/1K SSOP DB 28 1000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 9-May-2008

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS900E/1K SSOP DB 28 1000 346.0 346.0 33.0

PACKAGE MATERIALS INFORMATION

www.ti.com 9-May-2008

Pack Materials-Page 2

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