do not initiate the watchdog timer until the device receives
its first valid watchdog input transition (there is no fixed
period by which the first input must be received). These
two extended startup delay modes are useful for applications
requiring more than 60s for system initialization.
All the MAX6369–MAX6374 devices may be disabled with
the proper logic control pin setting (Table 1).
Applications Information
Input Signal Considerations
Watchdog timing is measured from the last WDI rising
or falling edge associated with a pulse of at least 100ns
in width. WDI transitions are ignored when WDO is
asserted, and during the startup delay period (Figure 1).
Watchdog input transitions are also ignored for a setup
period, tSETUP, of up to 300μs after power-up or a setting
change (Figure 2).
Selecting Device Timing
SET2, SET1, and SET0 program the startup delay and
watchdog timeout periods (Table 1). Timeout settings
can be hard wired, or they can be controlled with logic
gates and modified during operation. To ensure smooth
transitions, the system should strobe WDI immediately
before the timing settings are changed. This minimizes
the risk of initializing a setting change too late in the timer
countdown period and generating undesired watchdog
outputs. After changing the timing settings, two outcomes
are possible based on WDO. If the change is made while
WDO is asserted, the previous setting is allowed to finish, the
characteristics of the new setting are assumed, and the
new startup phase is entered after a 300μs setup time
(tSETUP) elapses. If the change is made while WDO is not
asserted, the new setting is initiated immediately, and the
new startup phase is entered after the 300μs setup time
elapses.
Selecting 011 (SET2 = 0, SET1 = 1, SET0 = 1) disables
the watchdog timer function on all devices in the family.
Operation can be reenabled without powering down by
changing the set inputs to the new desired setting. The
device assumes the new selected timing characteristics
and enter the startup phase after the 300μs setup time
elapses (Figure 2). WDO is high when the watchdog timer
is disabled.
The MAX6373/MAX6374 offer a first-edge feature. In first-
edge mode (settings 101 or 110, Table 1), the internal timer
does not control the startup delay period. Instead, startup
terminates when WDI sees a transition. If changing to first-
edge mode while the device is operating, disable mode
must be entered first. It is then safe to select first-edge
mode. Entering disable mode first ensures the output is
unasserted when selecting first-edge mode and removes
the danger of WDI being masked out.
Output
The MAX6369/MAX6371/MAX6373 have an active-low,
open-drain output that provides a watchdog output pulse
of 100ms. This output structure sinks current when WDO
is asserted. Connect a pullup resistor from WDO to any
supply voltage up to +5.5V.
Select a resistor value large enough to register a logic
low (see Electrical Characteristics), and small enough
to register a logic high while supplying all input current
and leakage paths connected to the WDO line. A 10kΩ
pullup is sufficient in most applications. The MAX6370/
MAX6372/MAX6374 have push-pull outputs that provide
an active-low watchdog output pulse of 1ms. When WDO
deasserts, timing begins again at the beginning of the
watchdog timeout period (Figure 1).
Figure 2. Setting Change Timing
tWD
tWD
tWD
tSETUP tDELAY tWD tSETUP tDELAY tWD
* * * * *
*IGNORED EDGE
WDI
WDO
SET_
MAX6369–MAX6374 Pin-Selectable Watchdog Timers
www.maximintegrated.com Maxim Integrated
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