LM20124
LM20124 4A, 1MHz PowerWise ® Synchronous Buck Regulator
Literature Number: SNVS507D
January 16, 2008
LM20124
4A, 1MHz PowerWise® Synchronous Buck Regulator
General Description
The LM20124 is a full featured 1 MHz synchronous buck reg-
ulator capable of delivering up to 4A of continuous output
current. The current mode control loop can be compensated
to be stable with virtually any type of output capacitor. For
most cases, compensating the device only requires two ex-
ternal components, providing maximum flexibility and ease of
use. The device is optimized to work over the input voltage
range of 2.95V to 5.5V making it suited for a wide variety of
low voltage systems.
The device features internal over voltage protection (OVP)
and over current protection (OCP) circuits for increased sys-
tem reliability. A precision enable pin and integrated UVLO
allows the turn-on of the device to be tightly controlled and
sequenced. Start-up inrush currents are limited by both an
internally fixed and externally adjustable Soft-Start circuit.
Fault detection and supply sequencing is possible with the
integrated power good circuit.
The LM20124 is designed to work well in multi-rail power
supply architectures. The output voltage of the device can be
configured to track a higher voltage rail using the SS/TRK pin.
If the output of the LM20124 is pre-biased at startup it will not
sink current to pull the output low until the internal soft-start
ramp exceeds the voltage at the feedback pin.
The LM20124 is offered in a 16-pin eTSSOP package with an
exposed pad that can be soldered to the PCB, eliminating the
need for bulky heatsinks.
Features
■Input voltage range 2.95V to 5.5V
■Accurate current limit minimizes inductor size
■96% efficiency at 1 MHz switching frequency
■32 mΩ integrated FET switches
■Starts up into pre-biased loads
■Output voltage tracking
■Peak current mode control
■Adjustable output voltage down to 0.8V
■Adjustable Soft-Start with external capacitor
■Precision enable pin with hysteresis
■Integrated OVP, UVLO, power good and thermal
shutdown
■eTSSOP-16 exposed pad package
Applications
■Simple to design, high efficiency point of load regulation
from a 5V or 3.3V bus
■High Performance DSPs, FPGAs, ASICs and
microprocessors
■Broadband, Networking and Optical Communications
Infrastructure
Typical Application Circuit
30014201
PowerWise® is a registered trademark of National Semiconductor Corporation.
© 2008 National Semiconductor Corporation 300142 www.national.com
LM20124 4A, 1MHz PowerWise® Synchronous Buck Regulator
Connection Diagram
30014202
Top View
eTSSOP-16 Package
Ordering Information
Order Number Package Type NSC Package Drawing Package Marking Supplied As
LM20124MH eTSSOP-16 MXA16A 20124MH 92 Units of Rail
LM20124MHE 250 Units of Tape and Reel
LM20124MHX 2500 Units of Tape and Reel
Pin Descriptions
Pin # Name Description
1 SS/TRK Soft-Start or Tracking control input. An internal 5 µA current source charges an external capacitor to
set the Soft-Start ramp rate. If driven by a external source less than 800mV, this pin overrides the
internal reference that sets the output voltage. If left open, an internal 1ms Soft-Start ramp is activated.
2 FB Feedback input to the error amplifier from the regulated output. This pin is connected to the inverting
input of the internal transconductance error amplifier. An 800 mV reference connected to the non-
inverting input of the error amplifier sets the closed loop regulation voltage at the FB pin.
3 PGOOD Power good output signal. Open drain output indicating the output voltage is regulating within
tolerance. A pull-up resistor of 10 kΩ to 100 kΩ is recommend for most applications.
4 COMP External compensation pin. Connect a resistor and capacitor to this pin to compensate the device.
5,16 NC These pins must be connected to GND to ensure proper operation.
6,7 PVIN Input voltage to the power switches inside the device. These pins should be connected together at the
device. A low ESR capacitor should be placed near these pins to stabilize the input voltage.
8,9 SW Switch pin. The PWM output of the internal power switches.
10,11 PGND Power ground pin for the internal power switches.
12 EN Precision enable input for the device. An external voltage divider can be used to set the device turn-
on threshold. If not used the EN pin should be connected to PVIN.
13 VCC Internal 2.7V sub-regulator. This pin should be bypassed with a 1 µF ceramic capacitor.
14 AVIN Analog input supply that generates the internal bias. Must be connected to VIN through a low pass
RC filter.
15 AGND Quiet analog ground for the internal bias circuitry.
EP Exposed Pad Exposed metal pad on the underside of the package with a weak electrical connection to ground. It is
recommended to connect this pad to the PC board ground plane in order to improve heat dissipation.
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LM20124
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltages from the indicated pins to GND
AVIN, PVIN, EN, PGOOD, SS/
TRK, COMP, FB
-0.3V to +6V
Storage Temperature -65°C to 150°C
Junction Temperature 150°C
Power Dissipation (Note 2) 2.6W
Lead Temperature (Soldering,
10 sec)
260°C
Minimum ESD Rating (Note 3) ±2kV
Operating Ratings
PVIN, AVIN to GND 2.95V to 5.5V
Junction Temperature −40°C to + 125°C
Electrical Characteristics Unless otherwise stated, the following conditions apply: AVIN = PVIN = VIN = 5V.
Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to
+125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the
most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
Symbol Parameter Conditions Min Typ Max Unit
VFB Feedback pin voltage VIN = 2.95V to 5.5V 0.788 0.8 0.812 V
ΔVOUT/ΔIOUT Load Regulation IOUT = 100 mA to 4A 0.08 %/A
ICL Switch Current Limit Threshold VIN = 3.3V 5.4 6.0 6.6 A
RDS_ON High-Side Switch On Resistance ISW = 3.5A 36 55 mΩ
RDS_ON Low-Side Switch On Resistance ISW = 3.5A 32 52 mΩ
IQOperating Quiescent Current Non-switching, VFB = VCOMP 3.5 6mA
ISD Shutdown Quiescent current VEN = 0V 90 180 µA
VUVLO VIN Under Voltage Lockout Rising VIN 2.45 2.7 2.95 V
VUVLO_HYS VIN Under Voltage Lockout Hysteresis Falling VIN 45 100 mV
VVCC VCC Voltage IVCC = 0 µA 2.45 2.7 2.95 V
ISS Soft-Start Pin Source Current VSS/TRK = 0V 24.5 7µA
VTRACK SS/TRK Accuracy, VSS - VFB VSS/TRK = 0.4V -10 315 mV
Oscillator
FOSC Oscillator Frequency 900 1000 1100 kHz
DCMAX Maximum Duty Cycle ILOAD = 0A 85 %
TON_TIME Minimum On Time 100 ns
TCL_BLANK Current Sense Blanking Time After Rising VSW 80 ns
Error Amplifier and Modulator
IFB Feedback pin bias current VFB = 0.8V 1 100 nA
ICOMP_SRC COMP Output Source Current VFB = VCOMP = 0.6V 80 100 µA
ICOMP_SNK COMP Output Sink Current VFB = 1.0V, VCOMP = 0.6V 80 100 µA
gmError Amplifier Transconductance ICOMP = ± 50 µA 450 510 600 µmho
AVOL Error Amplifier Voltage Gain 2000 V/V
Power Good
VOVP Over Voltage Protection Rising Threshold With respect to VFB 105 108 111 %
VOVP_HYS Over Voltage Protection Hysteresis 2 3%
VPGTH PGOOD Rising Threshold With respect to VFB 92 94 96 %
VPGHYS PGOOD Falling Hysteresis 2 3%
TPGOOD PGOOD deglitch time 16 µs
IOL PGOOD Low Sink Current VPGOOD = 0.4V 0.6 1 mA
IOH PGOOD High Leakage Current VPGOOD = 5V 5 100 nA
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LM20124
Symbol Parameter Conditions Min Typ Max Unit
Enable
VIH_EN EN Pin turn-on Threshold VEN Rising 1.08 1.18 1.28 V
VEN_HYS EN Pin Hysteresis 66 mV
Thermal Shutdown
TSD Thermal Shutdown 160 °C
TSD_HYS Thermal Shutdown Hysteresis 10 °C
Thermal Resistance
θJA Junction to Ambient 38 °C/W
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junctions-to-ambient thermal resistance, θJA,
and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD_MAX = (TJ_MAX – TA)/θJA. The
maximum power dissipations of 2.6W is determined using TA = 25°C, θJA = 38°C/W, and TJ_MAX = 125°C.
Note 3: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor to each pin.
Typical Performance Characteristics Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH
(Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, TA = 25°C for efficiency curves, loop gain plots and waveforms, and
TJ = 25°C for all others.
Efficiency vs. Load Current (VIN = 5V)
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Efficiency vs. Load Current (VIN = 3.3V)
30014230
High-Side FET resistance vs. Temperature
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Low-Side FET resistance vs. Temperature
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LM20124
Error Amplifier Gain vs. Frequency
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Line Regulation
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Load Regulation
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Feedback Voltage vs. Temperature
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Switching Frequency vs. Temperature
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Quiescent Current vs. VIN (Not Switching)
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LM20124
Shutdown Current vs. Temperature
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Enable Threshold vs. Temperature
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UVLO Threshold vs. Temperature
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Peak Current Limit vs. Temperature
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Peak Current Limit vs. VOUT
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Peak Current Limit vs. VIN
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LM20124
Load Transient Response
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Line Transient Response
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Start-Up (Soft-Start)
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Start-Up (Tracking)
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Power Down
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Short Circuit Input Current vs. VIN
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LM20124
PGOOD vs. IPGOOD
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LM20124
Block Diagram
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LM20124
Operation Description
GENERAL
The LM20124 switching regulator features all of the functions
necessary to implement an efficient low voltage buck regula-
tor using a minimum number of external components. This
easy to use regulator features two integrated switches and is
capable of supplying up to 4A of continuous output current.
The regulator utilizes peak current mode control with nonlin-
ear slope compensation to optimize stability and transient
response over the entire output voltage range. Peak current
mode control also provides inherent line feed-forward, cycle-
by-cycle current limiting and easy loop compensation. The
fixed 1 MHz operating frequency minimizes the inductor size
while still achieving efficiencies up to 96%. The precision in-
ternal voltage reference allows the output to be set as low as
0.8V. Fault protection features include: current limiting, ther-
mal shutdown, over voltage protection, and shutdown capa-
bility. The device is available in the eTSSOP-16 package
featuring an exposed pad to aid thermal dissipation. The
LM20124 can be used in numerous applications to efficiently
step-down from a 5V or 3.3V bus. The typical application cir-
cuit for the LM20124 is shown in Figure 2 in the design guide.
PRECISION ENABLE
The enable (EN) pin allows the output of the device to be en-
abled or disabled with an external control signal. This pin is a
precision analog input that enables the device when the volt-
age exceeds 1.18V (typical). The EN pin has 66 mV of hys-
teresis and will disable the output when the enable voltage
falls below 1.11V (typical). If the EN pin is not used, it should
be connected to VIN. Since the enable pin has a precise turn-
on threshold it can be used along with an external resistor
divider network from VIN to configure the device to turn-on at
a precise input voltage. The precision enable circuitry will re-
main active even when the device is disabled.
PEAK CURRENT MODE CONTROL
In most cases, the peak current mode control architecture
used in the LM20124 only requires two external components
to achieve a stable design. The compensation can be select-
ed to accommodate any capacitor type or value. The external
compensation also allows the user to set the crossover fre-
quency and optimize the transient performance of the device.
For duty cycles above 50% all current mode control buck
converters require the addition of an artificial ramp to avoid
sub-harmonic oscillation. This artificial linear ramp is com-
monly referred to as slope compensation. What makes the
LM20124 unique is the amount of slope compensation will
change depending on the output voltage. When operating at
high output voltages the device will have more slope com-
pensation than when operating at lower output voltages. This
is accomplished in the LM20124 by using a non-linear
parabolic ramp for the slope compensation. The parabolic
slope compensation of the LM20124 is much better than the
traditional linear slope compensation because it optimizes the
stability of the device over the entire output voltage range.
CURRENT LIMIT
The precise current limit of the LM20124 is set at the factory
to be within 10% over the entire operating temperature range.
This enables the device to operate with smaller inductors that
have lower saturation currents. When the peak inductor cur-
rent reaches the current limit threshold, an over current event
is triggered and the internal high-side FET turns off and the
low-side FET turns on allowing the inductor current to ramp
down until the next switching cycle. For each sequential over-
current event, the reference voltage is decremented and
PWM pulses are skipped resulting in a current limit that does
not aggressively fold back for brief over-current events, while
at the same time providing frequency and voltage foldback
protection during hard short circuit conditions.
SOFT-START AND VOLTAGE TRACKING
The SS/TRK pin is a dual function pin that can be used to set
the start up time or track an external voltage source. The start
up or Soft-Start time can be adjusted by connecting a capac-
itor from the SS/TRK pin to ground. The Soft-Start feature
allows the regulator output to gradually reach the steady state
operating point, thus reducing stresses on the input supply
and controlling start up current. If no Soft-Start capacitor is
used the device defaults to the internal Soft-Start circuitry re-
sulting in a start up time of approximately 1 ms. For applica-
tions that require a monotonic start up or utilize the PGOOD
pin, an external Soft-Start capacitor is recommended. The
SS/TRK pin can also be set to track an external voltage
source. The tracking behavior can be adjusted by two external
resistors connected to the SS/TRK pin as shown in Figure 7
in the design guide.
PRE-BIAS START UP CAPABILITY
The LM20124 is in a pre-biased state when the device starts
up with an output voltage greater than zero. This often occurs
in many multi-rail applications such as when powering an FP-
GA, ASIC, or DSP. In these applications the output can be
pre-biased through parasitic conduction paths from one sup-
ply rail to another. Even though the LM20124 is a syn-
chronous converter it will not pull the output low when a pre-
bias condition exists. During start up the LM20124 will not sink
current until the Soft-Start voltage exceeds the voltage on the
FB pin. Since the device can not sink current it protects the
load from damage that might otherwise occur if current is
conducted through the parasitic paths of the load.
POWER GOOD AND OVER VOLTAGE FAULT HANDLING
The LM20124 has built in under and over voltage compara-
tors that control the power switches. Whenever there is an
excursion in output voltage above the set OVP threshold, the
part will terminate the present on-pulse, turn-on the low-side
FET, and pull the PGOOD pin low. The low-side FET will re-
main on until either the FB voltage falls back into regulation
or the zero cross detection is triggered which in turn tri-states
the FETs. If the output reaches the UVP threshold the part will
continue switching and the PGOOD pin will be asserted and
go low. Typical values for the PGOOD resistor are on the or-
der of 100 kΩ or less. To avoid false tripping during transient
glitches the PGOOD pin has 16 µs of built in deglitch time to
both rising and falling edges.
UVLO
The LM20124 has a built-in under-voltage lockout protection
circuit that keeps the device from switching until the input
voltage reaches 2.7V (typical). The UVLO threshold has 45
mV of hysteresis that keeps the device from responding to
power-on glitches during start up. If desired the turn-on point
of the supply can be changed by using the precision enable
pin and a resistor divider network connected to VIN as shown
in Figure 6 in the design guide.
THERMAL PROTECTION
Internal thermal shutdown circuitry is provided to protect the
integrated circuit in the event that the maximum junction tem-
perature is exceeded. When activated, typically at 160°C, the
LM20124 tri-states the power FETs and resets soft start. After
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LM20124
the junction cools to approximately 150°C, the part starts up
using the normal start up routine. This feature is provided to
prevent catastrophic failures from accidental device over-
heating.
LIGHT LOAD OPERATION
The LM20124 offers increased efficiency when operating at
light loads. Whenever the load current is reduced to a point
where the peak to peak inductor ripple current is greater than
two times the load current, the part will enter the diode emu-
lation mode preventing significant negative inductor current.
The point at which this occurs is the critical conduction bound-
ary and can be calculated by the following equation:
Several diagrams are shown in Figure 1 illustrating continu-
ous conduction mode (CCM), discontinuous conduction
mode, and the boundary condition.
It can be seen that in diode emulation mode, whenever the
inductor current reaches zero the SW node will become high
impedance. Ringing will occur on this pin as a result of the LC
tank circuit formed by the inductor and the parasitic capaci-
tance at the node. If this ringing is of concern an additional
RC snubber circuit can be added from the switch node to
ground.
At very light loads, usually below 100 mA, several pulses may
be skipped in between switching cycles, effectively reducing
the switching frequency and further improving light-load effi-
ciency.
30014205
FIGURE 1. Modes of Operation for LM20124
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LM20124
Design Guide
This section walks the designer through the steps necessary
to select the external components to build a fully functional
power supply. As with any DC-DC converter numerous trade-
offs are possible to optimize the design for efficiency, size, or
performance. These will be taken into account and highlight-
ed throughout this discussion. To facilitate component selec-
tion discussions the circuit shown in Figure 2 below may be
used as a reference. Unless otherwise indicated all formulas
assume units of amps (A) for current, farads (F) for capaci-
tance, henries (H) for inductance and volts (V) for voltages.
30014223
FIGURE 2. Typical Application Circuit
The first equation to calculate for any buck converter is duty-
cycle. Ignoring conduction losses associated with the FETs
and parasitic resistances it can be approximated by:
INDUCTOR SELECTION (L)
The inductor value is determined based on the operating fre-
quency, load current, ripple current, and duty cycle.
The inductor selected should have a saturation current rating
greater than the peak current limit of the device. Keep in mind
the specified current limit does not account for delay of the
current limit comparator, therefore the current limit in the ap-
plication may be higher than the specified value. To optimize
the performance and prevent the device from entering current
limit at maximum load, the inductance is typically selected
such that the ripple current, ΔiL, is less than 30% of the rated
output current. Figure 3, shown below illustrates the switch
and inductor ripple current waveforms. Once the input volt-
age, output voltage, operating frequency, and desired ripple
current are known, the minimum value for the inductor can be
calculated by the formula shown below:
30014209
FIGURE 3. Switch and Inductor Current Waveforms
If needed, slightly smaller value inductors can be used, how-
ever, the peak inductor current, IOUT + ΔiL/2, should be kept
below the peak current limit of the device. In general, the in-
ductor ripple current, ΔiL, should be greater than 10% of the
rated output current to provide adequate current sense infor-
mation for the current mode control loop. If the ripple current
in the inductor is too low, the control loop will not have suffi-
cient current sense information and can be prone to instability.
OUTPUT CAPACITOR SELECTION (COUT)
The output capacitor, COUT, filters the inductor ripple current
and provides a source of charge for transient load conditions.
A wide range of output capacitors may be used with the
LM20124 that provide excellent performance. The best per-
formance is typically obtained using ceramic, SP, or OSCON
type chemistries. Typical trade-offs are that the ceramic ca-
pacitor provides extremely low ESR to reduce the output
ripple voltage and noise spikes, while the SP and OSCON
capacitors provide a large bulk capacitance in a small volume
for transient loading conditions.
When selecting the value for the output capacitor the two per-
formance characteristics to consider are the output voltage
ripple and transient response. The output voltage ripple can
be approximated by using the formula shown below.
Where, ΔVOUT (V) is the amount of peak to peak voltage ripple
at the power supply output, RESR (Ω) is the series resistance
of the output capacitor, fSW(Hz) is the switching frequency,
and COUT (F) is the output capacitance used in the design.
The amount of output ripple that can be tolerated is applica-
tion specific; however a general recommendation is to keep
the output ripple less than 1% of the rated output voltage.
Keep in mind ceramic capacitors are sometimes preferred
because they have very low ESR; however, depending on
package and voltage rating of the capacitor the value of the
capacitance can drop significantly with applied voltage. The
output capacitor selection will also affect the output voltage
droop during a load transient. The peak droop on the output
voltage during a load transient is dependent on many factors;
however, an approximation of the transient droop ignoring
loop bandwidth can be obtained using the following equation.
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LM20124
Where, COUT (F) is the minimum required output capacitance,
L (H) is the value of the inductor, VDROOP (V) is the output
voltage drop ignoring loop bandwidth considerations, ΔIOUT-
STEP (A) is the load step change, RESR (Ω) is the output
capacitor ESR, VIN (V) is the input voltage, and VOUT (V) is
the set regulator output voltage. Both the tolerance and volt-
age coefficient of the capacitor needs to be examined when
designing for a specific output ripple or transient drop target.
INPUT CAPACITOR SELECTION (CIN)
Good quality input capacitors are necessary to limit the ripple
voltage at the VIN pin while supplying most of the switch cur-
rent during the on-time. In general it is recommended to use
a ceramic capacitor for the input as they provide both a low
impedance and small footprint. One important note is to use
a good dielectric for the ceramic capacitor such as X5R or
X7R. These provide better over temperature performance
and also minimize the DC voltage derating that occurs on Y5V
capacitors. For most applications, a 22 µF, X5R, 6.3V input
capacitor is sufficient; however, additional capacitance may
be required if the connection to the input supply is far from the
PVIN pins. The input capacitor should be placed as close as
possible PVIN and PGND pins of the device.
Non-ceramic input capacitors should be selected for RMS
current rating and minimum ripple voltage. A good approxi-
mation for the required ripple current rating is given by the
relationship:
As indicated by the RMS ripple current equation, highest re-
quirement for RMS current rating occurs at 50% duty cycle.
For this case, the RMS ripple current rating of the input ca-
pacitor should be greater than half the output current. For best
performance, low ESR ceramic capacitors should be placed
in parallel with higher capacitance capacitors to provide the
best input filtering for the device.
SETTING THE OUTPUT VOLTAGE (RFB1, RFB2)
The resistors RFB1 and RFB2 are selected to set the output
voltage for the device. Table 1, shown below, provides sug-
gestions for RFB1 and RFB2 for common output voltages.
TABLE 1. Suggested Values for RFB1 and RFB2
RFB1(kΩ) RFB2(kΩ) VOUT
short open 0.8
4.99 10 1.2
8.87 10.2 1.5
12.7 10.2 1.8
21.5 10.2 2.5
31.6 10.2 3.3
If different output voltages are required, RFB2 should be se-
lected to be between 4.99 kΩ to 49.9 kΩ and RFB1 can be
calculated using the equation below.
LOOP COMPENSATION (RC1, CC1)
The purpose of loop compensation is to meet static and dy-
namic performance requirements while maintaining adequate
stability. Optimal loop compensation depends on the output
capacitor, inductor, load, and the device itself. Table 2 below
gives values for the compensation network that will result in
a stable system when using a 100 µF, 6.3V ceramic X5R out-
put capacitor and 1 µH inductor.
TABLE 2. Recommended Compensation for
COUT = 100 µF and L = 1 µH
VIN VOUT CC1 (nF) RC1 (kΩ)
5.00 3.30 3.3 20.5
5.00 2.50 3.3 16.2
5.00 1.80 3.3 11.8
5.00 1.50 3.3 9.71
5.00 1.20 3.3 6.49
5.00 0.80 4.7 1.5
3.30 2.50 3.3 17.8
3.30 1.80 3.3 12.7
3.30 1.50 3.3 9.09
3.30 1.20 3.3 5.36
3.30 0.80 3.3 1.82
If the desired solution differs from the table above the loop
transfer function should be analyzed to optimize the loop
compensation. The overall loop transfer function is the prod-
uct of the power stage and the feedback network transfer
functions. For stability purposes, the objective is to have a
loop gain slope that is -20db/decade from a very low frequen-
cy to beyond the crossover frequency. Figure 4, shown below,
shows the transfer functions for power stage, feedback/com-
pensation network, and the resulting closed loop system for
the LM20124.
30014213
FIGURE 4. LM20124 Loop Compensation
The power stage transfer function is dictated by the modula-
tor, output LC filter, and load; while the feedback transfer
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LM20124
function is set by the feedback resistor ratio, error amp gain,
and external compensation network.
To achieve a -20dB/decade slope, the error amplifier zero,
located at fZ(EA), should positioned to cancel the output filter
pole (fP(FIL)). An additional error amp pole, located at fP2(EA),
can be added to cancel the output filter zero at fZ(FIL). Can-
cellation of the output filter zero is recommended if larger
value, non-ceramic output capacitors are used.
Compensation of the LM20124 is achieved by adding an RC
network as shown in Figure 5 below.
30014214
FIGURE 5. Compensation Network for LM20124
A good starting value for CC1 for most applictions is 4.7 nF.
Once the value of CC1 is chosen the value of RC1 should be
calculated using the equation below to cancel the output filter
pole (fP(FIL)) as shown in Figure 4.
A higher crossover frequency can be obtained, usually at the
expense of phase margin, by lowering the value of CC1 and
recalculating the value of RC1. Likewise, increaseing CC1 and
recalculating RC1 will provide additional phase margin at a
lower crossover frequency. As with any attempt to compen-
sate the LM20124 the stability of the system should be verified
for desired transient droop and settling time.
If the output filter zero, fZ(FIL) approaches the crossover fre-
quency (FC), an additional capacitor (CC2) should be placed
at the COMP pin to ground. This capacitor adds a pole to
cancel the output filter zero assuring the crossover frequency
will occur before the double pole at fSW/2 degrades the phase
margin. The output filter zero is set by the output capacitor
value and ESR as shown in the equation below.
If needed, the value for CC2 should be calculated using the
equation shown below.
Where RESR is the output capacitor series resistance and
RC1 is the calculated compensation resistance.
AVIN FILTERING COMPONENTS (CF and RF)
To prevent high frequency noise spikes from disturbing the
sensitive analog circuitry connected to the AVIN and AGND
pins, a high frequency RC filter is required between PVIN and
AVIN. These components are shown in Figure 2. as CF and
RF. The required value for RF is 1Ω. CF must be used. Rec-
ommended value of CF is 1.0 µF. The filter capacitor, CF
should be placed as close to the IC as possible with a direct
connection from AVIN to AGND. A good quality X5R or X7R
ceramic capacitor should be used for CF.
SUB-REGULATOR BYPASS CAPACITOR (CVCC)
The capacitor at the VCC pin provides noise filtering and sta-
bility for the internal sub-regulator. The recommended value
of CVCC should be no smaller than 1 µF and no greater than
10 µF. The capacitor should be a good quality ceramic X5R
or X7R capacitor. In general, a 1 µF ceramic capacitor is rec-
ommended for most applications.
SETTING THE START UP TIME (CSS)
The addition of a capacitor connected from the SS pin to
ground sets the time at which the output voltage will reach the
final regulated value. Larger values for CSS will result in longer
start up times. Table 3, shown below provides a list of soft
start capacitors and the corresponding typical start up times.
TABLE 3. Start Up Times for Different Soft-Start
Capacitors
Start Up Time (ms) CSS (nF)
1 none
5 33
10 68
15 100
20 120
If different start up times are needed the equation shown be-
low can be used to calculate the start up time.
As shown above, the start up time is influenced by the value
of the Soft-Start capacitor CSS(F) and the 5 µA Soft-Start pin
current ISS(A). that may be found in the electrical character-
istics table.
While the Soft-Start capacitor can be sized to meet many start
up requirements, there are limitations to its size. The Soft-
Start time can never be faster than 1ms due to the internal
default 1 ms start up time. When the device is enabled there
is an approximate time interval of 50 µs when the Soft-Start
capacitor will be discharged just prior to the Soft-Start ramp.
If the enable pin is rapidly pulsed or the Soft-Start capacitor
is large there may not be enough time for CSS to completely
discharge resulting in start up times less than predicted. To
aid in discharging the Soft-Start capacitor during long disable
periods an external 1 MΩ resistor from SS/TRK to ground can
be used without greatly affecting the start-up time.
USING PRECISION ENABLE AND POWER GOOD
The precision enable (EN) and power good (PGOOD) pins of
the LM20124 can be used to address many sequencing re-
quirements. The turn-on of the LM20124 can be controlled
with the precision enable pin by using two external resistors
as shown in Figure 6.
www.national.com 14
LM20124
30014226
FIGURE 6. Sequencing LM20124 with Precision Enable
The value for resistor RB can be selected by the user to control
the current through the divider. Typically this resistor will be
selected to be between 10 kΩ and 1 MΩ. Once the value for
RB is chosen the resistor RA can be solved using the equation
below to set the desired turn-on voltage.
When designing for a specific turn-on threshold (VTO) the tol-
erance on the input supply, enable threshold (VIH_EN), and
external resistors needs to be considered to insure proper
turn-on of the device.
The LM20124 features an open drain power good (PGOOD)
pin to sequence external supplies or loads and to provide fault
detection. This pin requires an external resistor (RPG) to pull
PGOOD high while when the output is within the PGOOD tol-
erance window. Typical values for this resistor range from 10
kΩ to 100 kΩ.
TRACKING AN EXTERNAL SUPPLY
By using a properly chosen resistor divider network connect-
ed to the SS/TRK pin, as shown in Figure 7, the output of the
LM20124 can be configured to track an external voltage
source to obtain a simultaneous or ratiometric start up.
30014220
FIGURE 7. Tracking an External Supply
Since the Soft-Start charging current ISS is always present on
the SS/TRK pin, the size of R2 should be less than 10 kΩ to
minimize the errors in the tracking output. Once a value for
R2 is selected the value for R1 can be calculated using ap-
propriate equation in Figure 8, to give the desired start up.
Figure 8 shows two common start up sequences; the top
waveform shows a simultaneous start up while the waveform
at the bottom illustrates a ratiometric start up.
30014221
FIGURE 8. Common Start Up Sequences
A simultaneous start up is preferred when powering most FP-
GAs, DSPs, or other microprocessors. In these systems the
higher voltage, VOUT1, usually powers the I/O, and the lower
voltage, VOUT2, powers the core. A simultaneous start up pro-
vides a more robust power up for these applications since it
avoids turning on any parasitic conduction paths that may ex-
ist between the core and the I/O pins of the processor.
The second most common power on behavior is known as a
ratiometric start up. This start up is preferred in applications
where both supplies need to be at the final value at the same
time.
Similar to the Soft-Start function, the fastest start up possible
is 1ms regardless of the rise time of the tracking voltage.
When using the track feature the final voltage seen by the SS/
TRACK pin should exceed 1V to provide sufficient overdrive
and transient immunity.
THERMAL CONSIDERATIONS
The thermal characteristics of the LM20124 are specified us-
ing the parameter θJA, which relates the junction temperature
to the ambient temperature. Although the value of θJA is de-
pendant on many variables, it still can be used to approximate
the operating junction temperature of the device.
To obtain an estimate of the device, junction temperature, one
may use the following relationship:
TJ = PDθJA + TA
and
PD = PIN x (1 - Efficiency) - 1.1 x IOUT2 x DCR
Where:
TJ is the junction temperature in °C.
PIN is the input power in Watts (PIN = VIN x IIN).
θJA is the junction to ambient thermal resistance for the
LM20124.
15 www.national.com
LM20124
TA is the ambient temperature in °C.
IOUT is the output load current.
DCR is the inductor series resistance.
It is important to always keep the operating junction temper-
ature (TJ) below 125°C for reliable operation. If the junction
temperature exceeds 160°C the device will cycle in and out
of thermal shutdown. If thermal shutdown occurs it is a sign
of inadequate heatsinking or excessive power dissipation in
the device.
Figure 9, shown below, provides a better approximation of the
θJA for a given PCB copper area. The PCB heatsink area
consists of 2oz. copper located on the bottom layer of the PCB
directly under the eTSSOP exposed pad. The bottom copper
area is connected to the eTSSOP exposed pad by means of
a 4 x 4 array of 12 mil thermal vias.
30014235
FIGURE 9. Thermal Resistance vs PCB Area
PCB LAYOUT CONSIDERATIONS
PC board layout is an important part of DC-DC converter de-
sign. Poor board layout can disrupt the performance of a DC-
DC converter and surrounding circuitry by contributing to EMI,
ground bounce, and resistive voltage loss in the traces. These
can send erroneous signals to the DC-DC converter resulting
in poor regulation or instability.
Good layout can be implemented by following a few simple
design rules.
1. Minimize area of switched current loops. In a buck regulator
there are two loops where currents are switched very fast. The
first loop starts from the input capacitor, to the regulator VIN
pin, to the regulator SW pin, to the inductor then out to the
output capacitor and load. The second loop starts from the
output capacitor ground, to the regulator PGND pins, to the
inductor and then out to the load (see Figure 10). To minimize
both loop areas the input capacitor should be placed as close
as possible to the PVIN pin. Grounding for both the input and
output capacitor should consist of a small localized top side
plane that connects to PGND and the die attach pad (DAP).
The inductor should be placed as close as possible to the SW
pin and output capacitor.
2. Minimize the copper area of the switch node. Since the
LM20124 has the SW pins on opposite sides of the package
it is recommended to via these pins down to the bottom or
internal layer with 2 to 4 vias on each SW pin. The SW pins
should be directly connected with a trace that runs across the
bottom of the package. To minimize IR losses this trace
should be no smaller that 50 mils wide, but no larger than 100
mils wide to keep the copper area to a minimum. In general
the SW pins should not be connected on the top layer since
it could block the ground return path for the power ground.
The inductor should be placed as close as possible to one of
the SW pins to further minimize the copper area of the switch
node.
3. Have a single point ground for all device analog grounds
located under the DAP. The ground connections for the com-
pensation, feedback, and Soft-Start components should be
connected together then routed to the AGND pin of the de-
vice. The AGND pin should connect to PGND under the DAP.
This prevents any switched or load currents from flowing in
the analog ground plane. If not properly handled poor ground-
ing can result in degraded load regulation or erratic switching
behavior.
4. Minimize trace length to the FB pin. Since the feedback
node can be high impedance the trace from the output resistor
divider to FB pin should be as short as possible. This is most
important when high value resistors are used to set the output
voltage. The feedback trace should be routed away from the
SW pin and inductor to avoid contaminating the feedback sig-
nal with switch noise.
5. Make input and output bus connections as wide as possi-
ble. This reduces any voltage drops on the input or output of
the converter and can improve efficiency. If voltage accuracy
at the load is important make sure feedback voltage sense is
made at the load. Doing so will correct for voltage drops at the
load and provide the best output accuracy.
6. Provide adequate device heatsinking. Use as many vias as
is possible to connect the DAP to the power plane heatsink.
For best results use a 4x4 via array with a minimum via di-
ameter of 12 mils. See the Thermal Considerations section to
insure enough copper heatsinking area is used to keep the
junction temperature below 125°C.
www.national.com 16
LM20124
30014222
FIGURE 10. Schematic of LM20124 Highlighting Layout Sensitive Nodes
17 www.national.com
LM20124
Typical Application Circuits
This section provides several application solutions with a bill
of materials. All bill of materials reference the below figure.
The compensation for these solutions were optimized to work
over a wide range of input and output voltages; if a faster
transient response is needed reduce the value of CC1 and
calculate the new value for RC1 as outline in the design guide.
30014201
FIGURE 11.
Bill of Materials (VIN = 5V, VOUT = 3.3V, IOUTMAX = 4A)
Designator Description Part Number Manufacturer Qty
U1 Synchronous Buck Regulator LM20124 National Semiconductor 1
CIN 100 µF, 1210, X5R, 6.3V GRM32ER60J107ME20 Murata 1
COUT 100 µF, 1210, X5R, 6.3V GRM32ER60J107ME20 Murata 1
L1 µH, 6 mΩMSS1038-102NL Coilcraft 1
RF1Ω, 0603 CRCW06031R0J-e3 Vishay-Dale 1
CF100 nF, 0603, X7R, 16V GRM188R71C104KA01 Murata 1
CVCC 1 µF, 0603, X5R, 6.3V GRM188R60J105KA01 Murata 1
RC1 6.65 kΩ, 0603 CRCW06037871F-e3 Vishay-Dale 1
CC1 2.2 nF, 0603, X7R, 25V VJ0603Y222KXXA Vishay-Vitramon 1
CSS 33 nF, 0603, X7R, 25V VJ0603Y333KXXA Vishay-Vitramon 1
RFB1 31.6 kΩ, 0603 CRCW06033162F-e3 Vishay-Dale 1
RFB2 10.2 kΩ, 0603 CRCW06031022F-e3 Vishay-Dale 1
Bill of Materials (VIN = 3.3V to 5V, VOUT = 1.2V, IOUTMAX = 4A)
Designator Description Part Number Manufacturer Qty
U1 Synchronous Buck Regulator LM20124 National Semiconductor 1
CIN 100 µF, 1210, X5R, 6.3V GRM32ER60J107ME20 Murata 1
COUT 100 µF, 1210, X5R, 6.3V GRM32ER60J107ME20 Murata 1
L1 µH, 6 mΩMSS1038-102NL Coilcraft 1
RF1Ω, 0603 CRCW06031R0J-e3 Vishay-Dale 1
CF100 nF, 0603, X7R, 16V GRM188R71C104KA01 Murata 1
CVCC 1 µF, 0603, X5R, 6.3V GRM188R60J105KA01 Murata 1
RC1 6.65 kΩ, 0603 CRCW06036651F-e3 Vishay-Dale 1
CC1 2.2 nF, 0603, X7R, 25V VJ0603Y222KXXA Vishay-Vitramon 1
CSS 33 nF, 0603, X7R, 25V VJ0603Y333KXXA Vishay-Vitramon 1
RFB1 4.99 kΩ, 0603 CRCW06034991F-e3 Vishay-Dale 1
RFB2 10 kΩ, 0603 CRCW06031002F-e3 Vishay-Dale 1
www.national.com 18
LM20124
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead eTSSOP Package
NS Package Number MXA16A
19 www.national.com
LM20124
Notes
LM20124 4A, 1MHz PowerWise® Synchronous Buck Regulator
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