Advance Information MPC8272EC Rev. 0.1 9/2003 MPC8272 Family Hardware Specifications This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC8272 family of devices--the MPC8272, the MPC8248, the MPC8271, and the MPC8247. The CPU on these devices is a 32-bit PowerPCTM core that incorporates memory management units (MMUs) and instruction and data caches and that implements the PowerPC instruction set. These devices are .13m (HiP7) members of the PowerQUICC IITM family of integrated communications processors. They include a modified communications processor module (CPM) and an integrated security engine (SEC) for encryption (the MPC8272 and the MPC8248 only). All four devices are collectively referred to throughout this hardware specification as `the MPC8272' unless otherwise noted. The following topics are addressed: Topic Page Section 1, "Features" 2 Section 2, "Electrical and Thermal Characteristics" 6 Section 2.1, "DC Electrical Characteristics" 6 Section 2.2, "Thermal Characteristics" 10 Section 2.3, "AC Electrical Characteristics" 11 Section 3, "Clock Configuration Modes" 18 Section 4, "Pinout" 34 Section 5, "Package" 45 Section 6, "Ordering Information" 48 Section 7, "Document Revision History" 48 PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Features Figure 1 shows the superset block diagram. 16 Kbytes I-Cache Security (SEC) 1 I-MMU System Interface Unit (SIU) G2_LE Core 16 Kbytes D-Cache Bus Interface Unit D-MMU 60x-to-PCI Bridge 60x Bus PCI Bus 32 bits, up to 66 MHz Memory Controller Communication Processor Module (CPM) Timers Parallel I/O Baud Rate Generators FCC1 4 KB Interrupt Controller Instruction RAM Clock Counter 16 KB Data RAM Serial DMA 32-bit RISC Microcontroller and Program ROM FCC2 SCC1 SCC3 System Functions Virtual IDMAs SCC4 SMC1 SMC2 SPI I2C USB 2.0 Time Slot Assigner Serial interface Serial Interface 2 TDM Ports 2 MII/RMII Ports 1 8-bit Utopia Port2 Non-Multiplexed I/O Note 1 MPC8272/8248 only 2 MPC8272/8271 only Figure 1. Block Diagram 1 Features The major features of the MPC8272 are as follows: * 2 Dual-issue integer (G2_LE) core -- A core version of the MPC603e microprocessor -- System core microprocessor supporting frequencies of 266-400 MHz -- Separate 16-Kbyte data and instruction caches: - Four-way set associative - Physically addressed - LRU replacement algorithm -- PowerPC architecture-compliant memory management unit (MMU) -- Common on-chip processor (COP) test interface -- Supports bus snooping for cache coherency -- Floating-point unit (FPU) supports floating-point arithmetic -- Support for cache locking MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Features * * * * * * * * * * Low-power consumption Separate power supply for internal logic (1.5 V) and for I/O (3.3 V) Separate PLLs for G2_LE core and for the communications processor module (CPM) -- G2_LE core and CPM can run at different frequencies for power/performance optimization -- Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 5.5:1, 6:1, 7:1, and 8:1 ratios -- Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, and 6:1 ratios 64-bit data and 32-bit address 60x bus -- Bus supports multiple master designs--up to two external masters -- Supports single transfers and burst transfers -- 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller 60x-to-PCI bridge -- Programmable host bridge and agent -- 32-bit data bus, 66 MHz, 3.3 V -- Synchronous and asynchronous 60x and PCI clock modes -- All internal address space available to external PCI host -- DMA for memory block transfers -- PCI-to-60x address remapping System interface unit (SIU) -- Clock synthesizer -- Reset controller -- Real-time clock (RTC) register -- Periodic interrupt timer -- Hardware bus monitor and software watchdog timer -- IEEE 1149.1 JTAG test access port Eight bank memory controller -- Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other user-definable peripherals -- Byte write enables -- 32-bit address decodes with programmable bank size -- Three user programmable machines, general-purpose chip-select machine, and page mode pipeline SDRAM machine -- Byte selects for 64-bit bus width (60x) -- Dedicated interface logic for SDRAM Disable CPU mode Integrated security engine (SEC) (MPC8272 and MPC8248 only) -- Supports DES, 3DES, MD-5, SHA-1, AES, PKEU, RNG and RC-4 encryption algorithms in hardware Communications processor module (CPM) -- Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications peripherals MOTOROLA MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 3 Features * 4 -- Interfaces to G2_LE core through on-chip dual-port RAM and DMA controller. (Dual-port RAM size is 16 Kbyte plus 4Kbyte dedicated instruction RAM.) Universal serial bus (USB) controller -- Supports USB 2.0 full/low rate compatible -- USB host mode - Supports control, bulk, interrupt, and isochronous data transfers - CRC16 generation and checking - NRZI encoding/decoding with bit stuffing - Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data rate configuration). Note that low-speed operation requires an external hub. - Flexible data buffers with multiple buffers per frame - Supports local loopback mode for diagnostics (12 Mbps only) -- Supports USB slave mode - Four independent endpoints support control, bulk, interrupt, and isochronous data transfers - CRC16 generation and checking - CRC5 checking - NRZI encoding/decoding with bit stuffing - 12- or 1.5-Mbps data rate - Flexible data buffers with multiple buffers per frame - Automatic retransmission upon transmit error -- Serial DMA channels for receive and transmit on all serial channels -- Parallel I/O registers with open-drain and interrupt capability -- Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers -- Two fast communication controllers (FCCs) supporting the following protocols: - 10-/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII) - Transparent - HDLC--up to T3 rates (clear channel) - One of the FCCs supports ATM (MPC8272 and MPC8271 only)--full-duplex SAR at 155 Mbps, 8-bit UTOPIA interface 31 Mphys, AAL5, AAL1, AAL2, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 64-K external connections -- Three serial communications controllers (SCCs) identical to those on the MPC860 supporting the digital portions of the following protocols: - Ethernet/IEEE 802.3 CDMA/CS - HDLC/SDLC and HDLC bus - Universal asynchronous receiver transmitter (UART) - Synchronous UART - Binary synchronous (BiSync) communications - Transparent - QUICC multichannel controller (QMC) up to 64 channels * Independent transmit and receive routing, frame synchronization. MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Features * * Serial-multiplexed (full-duplex) input/output 2048-, 1544-, and 1536-Kbps PCM highways * Compatible with T1/DS1 24-channel and CEPT E1 32-channel PCM highway, ISDN basic rate, ISDN primary rate, and user defined. * Subchanneling on each time slot. * Independent transmit and receive routing, frame synchronization and clocking * Concatenation of any not necessarily consecutive time slots to channels independently for Rx/Tx * Supports H1,H11, and H12 channels * Allows dynamic allocation of channels - SCC3 in NMSI mode is not usable when USB is enabled. -- Two serial management controllers (SMCs), identical to those of the MPC860 - Provides management for BRI devices as general-circuit interface (GCI) controllers in time-division-multiplexed (TDM) channels - Transparent - UART (low-speed operation) -- One serial peripheral interface identical to the MPC860 SPI -- One I2C controller (identical to the MPC860 I2C controller) - Microwire compatible - Multiple-master, single-master, and slave modes -- Up to two TDM interfaces - Supports one group of two TDM channels - 1024 bytes of SI RAM -- Eight independent baud rate generators and 14 input clock pins for supplying clocks to FCC, SCC, SMC, and USB serial channels -- Four independent 16-bit timers that can be interconnected as two 32-bit timers PCI bridge -- PCI Specification revision 2.2-compliant and supports frequencies up to 66 MHz -- On-chip arbitration -- Support for PCI to 60x memory and 60x memory to PCI streaming -- PCI host bridge or peripheral capabilities -- Includes four DMA channels for the following transfers: - PCI-to-60x to 60x-to-PCI - 60x-to-PCI to PCI-to-60x - PCI-to-60x to PCI-to-60x - 60x-to-PCI to 60x-to-PCI -- Includes the configuration registers required by the PCI standard (which are automatically loaded from the EPROM to configure the MPC8272) and message and doorbell registers -- Supports the I2O standard -- Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August 3, 1998) -- Support for 66-MHz, 3.3-V specification MOTOROLA MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 5 Electrical and Thermal Characteristics -- 60x-PCI bus core logic, which uses a buffer pool to allocate buffers for each port 2 Electrical and Thermal Characteristics This section provides AC and DC electrical specifications and thermal characteristics for the MPC8272. 2.1 DC Electrical Characteristics Table 1 shows the maximum electrical ratings. Table 1. Absolute Maximum Ratings 1 Rating Symbol Value Unit VDD -0.3 - 2.25 V VCCSYN -0.3 - 2.25 V VDDH -0.3 - 4.0 V VIN GND(-0.3) - 3.6 V Tj 120 C TSTG (-55) - (+150) C Core supply voltage 2 PLL supply voltage2 I/O supply voltage 3 Input voltage 4 Junction temperature Storage temperature range 1 Absolute maximum ratings are stress ratings only; functional operation (see Table 2) at the maximums is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage. 2 Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset. 3 Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should not exceed VDD/VCCSYN by more than 2.5 V during normal operation. 4 Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset. Table 2 lists recommended operational voltage conditions. Table 2. Recommended Operating Conditions 1 Rating Symbol Value Unit Core supply voltage VDD 1.425 - 1.575 V PLL supply voltage VCCSYN 1.425 - 1.575 V I/O supply voltage VDDH 3.135 - 3.465 V VIN GND (-0.3) - 3.465 V Tj 105 2 C TA 0-702 C Input voltage Junction temperature (maximum) Ambient temperature 1 Caution: These are the recommended and tested operating conditions. Proper operation outside of these conditions is not guaranteed. 2 Note that for extended temperature parts the range is (-40) - 105 . T Tj A NOTE: Core, PLL, and I/O Supply Voltages VDDH, VCCSYN, and VDD must track each other and vary in the same direction--either in the positive direction (+0.165 VDDH and +0.075 VDD) or in the negative direction (-0.165 VDDH and -0.075 VDD). 6 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Electrical and Thermal Characteristics This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either GND or VCC). Figure 2 shows the undershoot and overshoot voltage of the 60x bus memory interface of the MPC8272. Note that in PCI mode the I/O interface is different. 4V GVDD + 5% GVDD VIH GND GND - 0.3 V VIL GND - 1.0 V Not to exceed 10% of tSDRAM_CLK Figure 2. Overshoot/Undershoot Voltage Table 3 shows DC electrical characteristics. Table 3. DC Electrical Characteristics 1 Characteristic Symbol Min Max Unit Input high voltage, all inputs except CLKIN 2 VIH 2.0 3.465 V Input low voltage VIL GND 0.8 V CLKIN input high voltage VIHC 2.4 3.465 V CLKIN input low voltage VILC GND 0.4 V IIN -- 10 A IOZ -- 10 A Signal low input current, VIL = 0.8 V IL -- 1 A Signal high input current, VIH = 2.0 V IH -- 1 A VOH 2.4 -- V VOL -- 0.5 V Input leakage current, VIN = VDDH 3 Hi-Z (off state) leakage current, VIN = VDDH3 Output high voltage, IOH = -2 mA except UTOPIA mode, and open drain pins In UTOPIA mode 4 (UTOPIA pins only): IOH = -8.0mA PA[8-31] PB[18-31] PC[0-1,4-29] PD[7-25, 29-31] In UTOPIA mode4 (UTOPIA pins only): IOL = 8.0mA PA[8-31] PB[18-31] PC[0-1,4-29] PD[7-25, 29-31] MOTOROLA MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 7 Electrical and Thermal Characteristics Table 3. DC Electrical Characteristics 1 (continued) Characteristic IOL = 6.0mA BR BG/IRQ6 ABB/IRQ2 TS A[0-31] TT[0-4] TBST TSIZE[0-3] AACK ARTRY DBG/IRQ7 DBB/IRQ3 D[0-63] IRQ3/CKSTP_OUT/EXT_BR3 IRQ4/CORE_SRESET/EXT_BG3 IRQ5/TBEN/EXT_DBG3/CINT PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 BADDR31/IRQ5/CINT CPU_BR/INT_OUT IRQ0/NMI_OUT PORESET/PCI_RST HRESET SRESET RSTCONF 8 Symbol Min Max Unit VOL -- 0.4 V MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Electrical and Thermal Characteristics Table 3. DC Electrical Characteristics 1 (continued) Characteristic IOL = 5.3mA CS[0-5] CS6/BCTL1/SMI CS7/TLBSYNC BADDR27/ IRQ1 BADDR28/ IRQ2 ALE/ IRQ4 BCTL0 PWE[0-7]/PSDDQM[0-7]/PBS[0-7] PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4 PSDAMUX/PGPL5 PCI_HOST PCI_ARB_EN DLL_ENABLE MODCK1/RSRV/TC(0)/BNKSEL(0) MODCK2/CSE0/TC(1)/BNKSEL(1) MODCK3/CSE1/TC(2)/BNKSEL(2) IOL = 3.2mA PAR FRAME/SMI TRDY IRDY STOP DEVSEL IDSEL PERR SERR REQ0 REQ1 GNT0 GNT1 GNT2 RST INTA REQ2 DLLOUT AD(0-31) C/BE(0-3) PA[8-31] PB[18-31] PC[0-1,4-29] PD[7-25, 29-31] TDO Symbol Min Max Unit VOL -- 0.4 V 1 The default configuration of the CPM pins (PA[8-31], PB[18-31], PC[0-1,4-29], PD[7-25, 29-31]) is input. To prevent excessive DC current, it is recommended either to pull unused pins to GND or VDDH, or to configure them as outputs. 2 Minimum V for TRST and PORESET is 2.2 mA. IH 3 The leakage current is measured for nominal VDDH,VCCSYN, and VDD. 4 MPC8272 and MPC8271 only. MOTOROLA MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 9 Electrical and Thermal Characteristics 2.2 Thermal Characteristics Table 4 describes thermal characteristics. Table 4. Thermal Characteristics Characteristic Symbol Value Unit Air Flow Junction-to-ambient-- single-layer board 1 JA Junction-to-ambient-- four-layer board JA Junction-to-board 2 JB 11 C/W -- Junction-to-case 3 JC 8 C/W -- 27 21 Natural convection C/W 19 16 1 m/s Natural convection C/W 1 m/s 1 Assumes no thermal vias Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 3 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 2 2.2.1 Layout Practices Each VCC pin should be provided with a low-impedance path to the board's power supply. Each ground pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four 0.1 F bypass capacitors located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC and ground should be kept to less than half an inch per capacitor lead. A four-layer board employing two inner layers as VCC and GND planes is recommended. All output pins on the MPC8272 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize overdamped conditions and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. Table 5 provides preliminary, estimated power dissipation for various configurations. Note that suitable thermal management is required to ensure the junction temperature does not exceed the maximum specified value. Also note that the I/O power should be included when determining whether to use a heat sink. 10 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Electrical and Thermal Characteristics Table 5. Estimated Power Dissipation for Various Configurations 1 PINT(W) 2, 3 CPM Multiplication Factor Bus (MHz) CPM (MHz) CPU Multiplication Factor CPU (MHz) Vddl 1.5 Volts Nominal Maximum 66.67 3 200 4 266 0.75 0.8 100 2 200 3 300 0.85 0.9 100 2 200 4 400 1 1.05 1 Test temperature = 105 C) PINT = IDD x VDD Watts 3 Values do not include I/O. Add the following estimates for active I/O based on the following bus speeds: 66.7 MHz = 0.35 W (nominal), 0.4 W (maximum) 83.3 MHz = 0.4 W (nominal), 0.5 W (maximum) 100 MHz = 0.5 W (nominal), 0.6 W (maximum) 2 2.3 AC Electrical Characteristics The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and inputs for 66.67-/83.33-/100-MHz MPC8272 devices. Note that AC timings are based on a 50-pf load. Typical output buffer impedances are shown in Table 6. Table 6. Output Buffer Impedances 1 Output Buffers Typical Impedance () 60x bus 45 Memory controller 45 Parallel I/O 45 PCI 25 1 These are typical values at 65 C. Impedance may vary by 25% with process and temperature. 2.3.1 CPM AC Characteristics Table 7 lists CPM output characteristics. Table 7. AC Characteristics for CPM Outputs 1 Spec Number Max Characteristic Min Value (ns) Maximum Delay Minimum Delay 66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz sp36a sp37a FCC outputs--internal clock (NMSI) 6 5.5 5.5 1 1 1 sp36b sp37b FCC outputs--external clock (NMSI) 14 12 12 2 2 2 sp38a sp39a SCC/SMC/SPI/I2C outputs--internal clock (NMSI) 19 16 16 1 0.5 0.5 MOTOROLA MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 11 Electrical and Thermal Characteristics Table 7. AC Characteristics for CPM Outputs 1 (continued) Spec Number Max 1 Characteristic Min Value (ns) Maximum Delay Minimum Delay 66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz sp38b sp39b SCC/SMC/SPI/I2C outputs--external clock (NMSI) 19 16 16 2 2 2 sp40 sp41 TDM outputs/SI 14 12 12 5 3 3 sp42 sp43 TIMER/IDMA outputs 14 11 11 1 0.5 0.5 sp42a sp43a PIO outputs 14 11 11 0.5 0.5 0.5 Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. Table 8 lists CPM input characteristics. Table 8. AC Characteristics for CPM Inputs 1 Spec Number Setup 1 Characteristic Value (ns) Hold Setup Hold 66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz sp16a sp17a FCC inputs--internal clock (NMSI) 10 8 8 0 0 0 sp16b sp17b FCC inputs--external clock (NMSI) 3 2.5 2.5 2 2 2 sp18a sp19a SCC/SMC/SPI/I2C inputs--internal clock (NMSI) 20 16 16 0 0 0 sp18b sp19b SCC/SMC/SPI/I2C inputs--external clock (NMSI) 5 4 4 2 2 2 sp20 sp21 TDM inputs/SI 7 5 5 4 3 3 sp22 sp23 PIO/TIMER/IDMA inputs 10 8 8 0.5 0.5 0.5 Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. NOTE Although the specifications generally reference the rising edge of the clock, the following AC timing diagrams also apply when the falling edge is the active edge. 12 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Electrical and Thermal Characteristics Figure 3 shows the FCC internal clock. BRG_OUT sp17a sp16a FCC input signals sp36a/sp37a FCC output signals Note: When GFMR[TCI] = 0 sp36a/sp37a FCC output signals Note: When GFMR.[TCI] = 1 Figure 3. FCC Internal Clock Diagram Figure 4 shows the FCC external clock. Serial ClKin sp17b sp16b FCC input signals sp36b/sp37b FCC output signals Note: When GFMR[TCI] = 0 sp36b/sp37b FCC output signals Note: When GFMR[TCI] = 1 Figure 4. FCC External Clock Diagram MOTOROLA MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 13 Electrical and Thermal Characteristics Figure 5 shows the SCC/SMC/SPI/I2C external clock. Serial CLKin sp18b sp19b SCC/SMC/SPI/I2C input signals (See note) sp38b/sp39b SCC/SMC/SPI/I2C output signals (See note) Note: There are four possible timing conditions for SCC and SPI: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4. Input sampled on the falling edge and output driven on the rising edge. Figure 5. SCC/SMC/SPI/I2C External Clock Diagram Figure 6 shows the SCC/SMC/SPI/I2C internal clock. BRG_OUT sp18a sp19a SCC/SMC/SPI/I2C input signals (See note) sp38a/sp39a SCC/SMC/SPI/I2C output signals (See note) Note: There are four possible timing conditions for SCC and SPI: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4. Input sampled on the falling edge and output driven on the rising edge. Figure 6. SCC/SMC/SPI/I2C Internal Clock Diagram 14 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Electrical and Thermal Characteristics Figure 7 shows TDM input and output signals. Serial CLKin sp20 sp21 TDM input signals sp40/sp41 TDM output signals Note: There are four possible TDM timing conditions: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4. Input sampled on the falling edge and output driven on the rising edge. Figure 7. TDM Signal Diagram Figure 8 shows PIO and timer signals. Sys clk sp23 sp22 PIO/IDMA/TIMER[TGATE assertion] input signals (See note) sp23 sp22 TIMER input signal [TGATE deassertion] (See note) sp42/sp43 IDMA output signals sp42/sp43 sp42a/sp43a TIMER(sp42/43)/ PIO(sp42a/sp43a) output signals Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge. Figure 8. PIO and Timer Signal Diagram 15 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Electrical and Thermal Characteristics 2.3.2 SIU AC Characteristics Table 9 lists SIU input characteristics. NOTE: PCI AC Timing The MPC8272 meets the timing requirements of PCI Specification Revision 2.2. Refer to Section 3, "Clock Configuration Modes" and "Note: Tval (Output Hold)" to determine if a specific clock configuration is compliant. Table 9. AC Characteristics for SIU Inputs 1 Spec Number Setup 1 Characteristic Value (ns) Hold Setup Hold 66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz sp11 sp10 AACK/TA/TS/DBG/BG/BR 6 5 3.5 0.5 0.5 0.5 sp11a sp10 ARTRY/ TEA 6 5 4 0.5 0.5 0.5 sp12 sp10 Data bus in normal mode 5 4 3.5 0.5 0.5 0.5 sp13 sp10 Data bus in pipeline mode 5 4 2.5 0.5 0.5 0.5 sp15 sp10 All other pins 5 4 3.5 0.5 0.5 0.5 Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. Table 10 lists SIU output characteristics. Table 10. AC Characteristics for SIU Outputs 1 Spec Number Max Characteristic Min Value (ns) Maximum Delay Minimum Delay 66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz sp31 sp30 PSDVAL/TEA/TA 7 6 5.5 1 1 1 sp32 sp30 ADD/ADD_atr./BADDR/CI/GBL/W T 8 6.5 5.5 1 1 1 sp33 sp30 Data bus 2 6.5 6.5 5.5 0.5 0.5 0.5 sp34 sp30 Memory controller signals/ALE 6 5.5 5.5 1 1 1 sp35 sp30 All other signals 6 5.5 5.5 1 1 1 1 Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2 To achieve 1 ns of hold time at 66.67/83.33/100 MHZ, a minimum loading of 20 pF is required. NOTE Activating data pipelining (setting BRx[DR] in the memory controller) improves the AC timing. 16 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Electrical and Thermal Characteristics Figure 9 shows the interaction of several bus signals. CLKin sp11 sp10 sp11a sp10 sp12 sp10 sp15 sp10 AACK/TA/TS/ DBG/BG/BR input signals ARTRY/TEA input signals DATA bus normal mode input signal All other input signals sp31 sp30 sp32 sp30 PSDVAL/TEA/TA output signals ADD/ADD_atr/BADDR/CI/ GBL/WT output signals DATA bus output signals sp33 sp30 sp35 sp30 All other output signals (except AP) sp10 sp13 DATA bus pipeline mode input signal Figure 9. Bus Signals Figure 10 shows signal behavior in MEMC mode. CLKin V_CLK Memory controller signals sp34/sp30 Figure 10. MEMC Mode Diagram 17 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Electrical and Thermal Characteristics NOTE Generally, all MPC8272 bus and system output signals are driven from the rising edge of the input clock (CLKin). Memory controller signals, however, trigger on four points within a CLKin cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge, and T3 at the falling edge, of CLKin. However, the spacing of T2 and T4 depends on the PLL clock ratio selected, as shown in Table 11. Table 11. Tick Spacing for Memory Controller Signals Tick Spacing (T1 Occurs at the Rising Edge of CLKin) PLL Clock Ratio T2 T3 T4 1:2, 1:3, 1:4, 1:5, 1:6 1/4 CLKin 1/2 CLKin 3/4 CLKin 1:2.5 3/10 CLKin 1/2 CLKin 8/10 CLKin 1:3.5 4/14 CLKin 1/2 CLKin 11/14 CLKin Figure 11 is a representation of the information in Table 11. CLKin for 1:2, 1:3, 1:4, 1:5, 1:6 T1 T2 T3 T4 CLKin for 1:2.5 T1 T2 T3 T4 for 1:3.5 CLKin T1 T2 T3 T4 Figure 11. Internal Tick Spacing for Memory Controller Signals NOTE The UPM machine outputs change on the internal tick determined by the memory controller programming; the AC specifications are relative to the internal tick. Note that SDRAM and GPCM machine outputs change on CLKin's rising edge. 18 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes 3 Clock Configuration Modes The clocking mode is set according to two input pins--PCI_CFG[0] and PCI_MODCK--as shown in Table 12. Table 12. MPC8272 Clocking Modes Pins 1 PCI_CFG[0] PCI_MODCK 1 0 0 0 1 1 0 1 1 Clocking Mode PCI Clock Frequency Range (MHZ) Reference PCI host 50-66 Table 13 25-50 Table 14 50-66 Table 15 25-50 Table 16 PCI agent Determines PCI clock frequency range Within each mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven bits during the power-on reset--three hardware configuration pins (MODCK[1-3]) and four bits from hardware configuration word[28-31] (MODCK_H). Both the PLLs and the dividers are set according to the selected clock operation mode as described in the following sections. NOTE Clock configurations change only after POR is asserted. NOTE: Tval (Output Hold) The minimum Tval = 2 when PCI_MODCK = 1, and the minimum Tval = 1 when PCI_MODCK = 0. Therefore, designers should use clock configurations that fit this condition to achieve PCI-compliant AC timing. 3.1 PCI Host Mode Table 13 and Table 14 show configurations for PCI host mode. The frequency values listed are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user's device. Note that in PCI host mode the input clock is the bus clock. Table 13. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2 Mode 3 MODCK_HMODCK[1-3] Bus Clock (MHz) Low High CPM Multiplication Factor 4 CPM Clock (MHz) Low High CPU Multiplication Factor 5 CPU Clock (MHz) Low High PCI Division Factor PCI Clock (MHz) Low High Default Modes (MODCK_H=0000) 19 0000_000 50.0 66.7 2 100.0 133.3 2.5 125.0 166.7 2 50.0 66.7 0000_001 50.0 66.7 2 100.0 133.3 3 150.0 200.0 2 50.0 66.7 0000_010 60.0 80.0 2.5 150.0 200.0 3 180.0 240.0 3 50.0 66.7 0000_011 71.4 80.0 2.5 178.6 200.0 3.5 250.0 280.0 3 59.5 66.7 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes Table 13. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2 (continued) Mode 3 Bus Clock (MHz) CPM Multiplication Factor 4 CPM Clock (MHz) CPU Multiplication Factor 5 CPU Clock (MHz) MODCK_HMODCK[1-3] Low High 0000_100 62.5 80.0 2.5 156.3 200.0 4 250.0 320.0 0000_101 50.0 66.7 3 150.0 200.0 3 150.0 200.0 0000_110 0000_111 Low High Low High PCI Division Factor PCI Clock (MHz) Low High 3 52.1 66.7 3 50.0 66.7 250.0 266.6 3 62.5 66.7 PCI host mode (PCI_MODCK=1) only (refer to Table 14) 62.5 66.7 3 187.5 200.0 4 Full Configuration Modes 0001_000 50.0 66.7 3 150.0 200.0 5 250.0 333.3 3 50.0 66.7 0001_001 50.0 66.7 3 150.0 200.0 6 300.0 400.0 3 50.0 66.7 0001_010 50.0 66.7 3 150.0 200.0 7 350.0 466.6 3 50.0 66.7 0001_011 50.0 66.7 3 150.0 200.0 8 400.0 533.3 3 50.0 66.7 0010_000 50.0 66.7 4 200.0 266.6 5 250.0 333.3 4 50.0 66.7 0010_001 50.0 66.7 4 200.0 266.6 6 300.0 400.0 4 50.0 66.7 0010_010 50.0 66.7 4 200.0 266.6 7 350.0 466.6 4 50.0 66.7 0010_011 50.0 66.7 4 200.0 266.6 8 400.0 533.3 4 50.0 66.7 0010_100 75.0 100.0 4 300.0 400.0 5 375.0 500.0 6 50.0 66.7 0010_101 75.0 100.0 4 300.0 400.0 5.5 412.5 549.9 6 50.0 66.7 0010_110 75.0 100.0 4 300.0 400.0 6 450.0 599.9 6 50.0 66.7 0011_000 50.0 66.7 5 250.0 333.3 5 250.0 333.3 5 50.0 66.7 0011_001 50.0 66.7 5 250.0 333.3 6 300.0 400.0 5 50.0 66.7 0011_010 50.0 66.7 5 250.0 333.3 7 350.0 466.6 5 50.0 66.7 0011_011 50.0 66.7 5 250.0 333.3 8 400.0 533.3 5 50.0 66.7 0100_000 20 Reserved 0100_001 50.0 66.7 6 300.0 400.0 6 300.0 400.0 6 50.0 66.7 0100_010 50.0 66.7 6 300.0 400.0 7 350.0 466.6 6 50.0 66.7 0100_011 50.0 66.7 6 300.0 400.0 8 400.0 533.3 6 50.0 66.7 0101_000 50.0 66.7 2 100.0 133.3 2.5 125.0 166.7 2 50.0 66.7 0101_001 50.0 66.7 2 100.0 133.3 3 150.0 200.0 2 50.0 66.7 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes Table 13. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2 (continued) Mode 3 MODCK_HMODCK[1-3] Bus Clock (MHz) Low High 0101_010 CPM Multiplication Factor 4 CPM Clock (MHz) Low High CPU Clock (MHz) Low High PCI Division Factor PCI Clock (MHz) Low High PCI host mode (PCI_MODCK=1) only (refer to Table 14) 0101_011 62.5 66.7 2 125.0 133.3 4 250.0 266.6 2 62.5 66.7 0101_100 55.6 66.7 2 111.1 133.3 4.5 250.0 300.0 2 55.6 66.7 0101_101 83.3 111.1 3 250.0 333.3 3.5 291.7 388.9 5 50.0 66.7 0101_110 83.3 111.1 3 250.0 333.3 4 333.3 444.4 5 50.0 66.7 0101_111 83.3 111.1 3 250.0 333.3 4.5 375.0 500.0 5 50.0 66.7 0110_000 60.0 80.0 2.5 150.0 200.0 2.5 150.0 200.0 3 50.0 66.7 0110_001 60.0 80.0 2.5 150.0 200.0 3 180.0 240.0 3 50.0 66.7 0110_010 71.4 80.0 2.5 178.6 200.0 3.5 250.0 280.0 3 59.5 66.7 0110_011 62.5 80.0 2.5 156.3 200.0 4 250.0 320.0 3 52.1 66.7 0110_100 60.0 80.0 2.5 150.0 200.0 4.5 270.0 360.0 3 50.0 66.7 0110_101 60.0 80.0 2.5 150.0 200.0 5 300.0 400.0 3 50.0 66.7 0110_110 60.0 80.0 2.5 150.0 200.0 6 360.0 480.0 3 50.0 66.7 150.0 200.0 3 50.0 66.7 0111_000 0111_001 Reserved 50.0 66.7 0111_010 3 150.0 200.0 3 PCI host mode (PCI_MODCK=1) only (refer to Table 14) 0111_011 62.5 66.7 3 187.5 200.0 4 250.0 266.6 3 62.5 66.7 0111_100 55.6 66.7 3 166.7 200.0 4.5 250.0 300.0 3 55.6 66.7 1000_000 21 CPU Multiplication Factor 5 Reserved 1000_001 66.7 88.9 3 200.0 266.6 3 200.0 266.6 4 50.0 66.7 1000_010 71.4 88.9 3 214.3 266.6 3.5 250.0 311.1 4 53.6 66.7 1000_011 66.7 88.9 3 200.0 266.6 4 266.7 355.5 4 50.0 66.7 1000_100 66.7 88.9 3 200.0 266.6 4.5 300.0 400.0 4 50.0 66.7 1000_101 66.7 88.9 3 200.0 266.6 6 400.0 533.3 4 50.0 66.7 1000_110 66.7 88.9 3 200.0 266.6 6.5 433.3 577.7 4 50.0 66.7 1001_000 57.1 76.2 3.5 200.0 266.6 2.5 142.9 190.5 4 50.0 66.7 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes Table 13. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2 (continued) Mode 3 Bus Clock (MHz) CPM Multiplication Factor 4 CPM Clock (MHz) CPU Multiplication Factor 5 CPU Clock (MHz) MODCK_HMODCK[1-3] Low High 1001_001 57.1 76.2 3.5 200.0 266.6 3 171.4 228.5 1001_010 71.4 76.2 3.5 250.0 266.6 3.5 1001_011 62.5 76.2 3.5 218.8 266.6 1001_100 57.1 76.2 3.5 1001_101 85.7 114.3 1001_110 Low High 22 High PCI Clock (MHz) Low High 4 50.0 66.7 250.0 266.6 4 62.5 66.7 4 250.0 304.7 4 54.7 66.7 200.0 266.6 4.5 257.1 342.8 4 50.0 66.7 3.5 300.0 400.0 5 428.6 571.4 6 50.0 66.7 85.7 114.3 3.5 300.0 400.0 5.5 471.4 628.5 6 50.0 66.7 1001_111 85.7 114.3 3.5 300.0 400.0 6 514.3 685.6 6 50.0 66.7 1010_000 75.0 100.0 2 150.0 200.0 2 150.0 200.0 3 50.0 66.7 1010_001 75.0 100.0 2 150.0 200.0 2.5 187.5 250.0 3 50.0 66.7 1010_010 75.0 100.0 2 150.0 200.0 3 225.0 300.0 3 50.0 66.7 1010_011 75.0 100.0 2 150.0 200.0 3.5 262.5 350.0 3 50.0 66.7 1010_100 75.0 100.0 2 150.0 200.0 4 300.0 400.0 3 50.0 66.7 1010_101 100.0 133.3 2 200.0 266.6 2.5 250.0 333.3 4 50.0 66.7 1010_110 100.0 133.3 2 200.0 266.6 3 300.0 400.0 4 50.0 66.7 1010_111 100.0 133.3 2 200.0 266.6 3.5 350.0 466.6 4 50.0 66.7 1011_000 Low PCI Division Factor Reserved 1011_001 80.0 106.7 2.5 200.0 266.6 2.5 200.0 266.6 4 50.0 66.7 1011_010 80.0 106.7 2.5 200.0 266.6 3 240.0 320.0 4 50.0 66.7 1011_011 80.0 106.7 2.5 200.0 266.6 3.5 280.0 373.3 4 50.0 66.7 1011_100 80.0 106.7 2.5 200.0 266.6 4 320.0 426.6 4 50.0 66.7 1011_101 80.0 106.7 2.5 200.0 266.6 4.5 360.0 480.0 4 50.0 66.7 1101_000 100.0 133.3 2.5 250.0 333.3 3 300.0 400.0 5 50.0 66.7 1101_001 100.0 133.3 2.5 250.0 333.3 3.5 350.0 466.6 5 50.0 66.7 1101_010 100.0 133.3 2.5 250.0 333.3 4 400.0 533.3 5 50.0 66.7 1101_011 100.0 133.3 2.5 250.0 333.3 4.5 450.0 599.9 5 50.0 66.7 1101_100 100.0 133.3 2.5 250.0 333.3 5 500.0 666.6 5 50.0 66.7 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes Table 13. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2 (continued) Mode 3 MODCK_HMODCK[1-3] 1 2 3 4 5 Bus Clock (MHz) Low High CPM Multiplication Factor 4 CPM Clock (MHz) Low High CPU Multiplication Factor 5 CPU Clock (MHz) Low High PCI Division Factor PCI Clock (MHz) Low High 1101_101 125.0 166.7 2 250.0 333.3 3 375.0 500.0 5 50.0 66.7 1101_110 125.0 166.7 2 250.0 333.3 4 500.0 666.6 5 50.0 66.7 1110_000 100.0 133.3 3 300.0 400.0 3.5 350.0 466.6 6 50.0 66.7 1110_001 100.0 133.3 3 300.0 400.0 4 400.0 533.3 6 50.0 66.7 1110_010 100.0 133.3 3 300.0 400.0 4.5 450.0 599.9 6 50.0 66.7 1110_011 100.0 133.3 3 300.0 400.0 5 500.0 666.6 6 50.0 66.7 1110_100 100.0 133.3 3 300.0 400.0 5.5 550.0 733.3 6 50.0 66.7 1100_000 Reserved 1100_001 Reserved 1100_010 Reserved The "low" values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock mode. For modes with a CPU multiplication factor 3, the minimum CPU frequency is 125 MHz or 150 MHz, as shown in the table. For modes with a CPU multiplication factor 3.5, the minimum CPU frequency is 250 MHz. The "high" values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user's device. PCI_MODCK determines the PCI clock frequency range. Refer to Table 14 for lower range configurations. MODCK_H = hard reset configuration word [28-31] (refer to Section 5.4 in the MPC8260 User's Manual). MODCK[1-3] = three hardware configuration pins. CPM multiplication factor = CPM clock/bus clock CPU multiplication factor = Core PLL multiplication factor Table 14. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 1, 2 Mode 3 MODCK_HMODCK[1-3] Bus Clock (MHz) Low High CPM Multiplication Factor 4 CPM Clock (MHz) Low High CPU Multiplication Factor 5 CPU Clock (MHz) Low High PCI Division Factor PCI Clock (MHz) Low High Default Modes (MODCK_H=0000) 23 0000_000 50.0 100.0 2 100.0 200.0 2.5 125.0 250.0 4 25.0 50.0 0000_001 50.0 100.0 2 100.0 200.0 3 150.0 300.0 4 25.0 50.0 0000_010 60.0 120.0 2.5 150.0 300.0 3 180.0 360.0 6 25.0 50.0 0000_011 71.4 120.0 2.5 178.6 300.0 3.5 250.0 420.0 6 29.8 50.0 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes Table 14. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 1, 2 (continued) Mode 3 MODCK_HMODCK[1-3] Bus Clock (MHz) Low High CPM Multiplication Factor 4 CPM Clock (MHz) Low High CPU Multiplication Factor 5 CPU Clock (MHz) Low High PCI Division Factor PCI Clock (MHz) Low High 0000_100 62.5 120.0 2.5 156.3 300.0 4 250.0 480.0 6 26.0 50.0 0000_101 50.0 100.0 3 150.0 300.0 3 150.0 300.0 6 25.0 50.0 0000_110 71.4 100.0 3 214.3 300.0 3.5 250.0 350.0 6 35.7 50.0 0000_111 62.5 100.0 3 187.5 300.0 4 250.0 400.0 6 31.3 50.0 Full Configuration Modes 0001_000 50.0 100.0 3 150.0 300.0 5 250.0 500.0 6 25.0 50.0 0001_001 50.0 100.0 3 150.0 300.0 6 300.0 600.0 6 25.0 50.0 0001_010 50.0 100.0 3 150.0 300.0 7 350.0 700.0 6 25.0 50.0 0001_011 50.0 100.0 3 150.0 300.0 8 400.0 800.0 6 25.0 50.0 0010_000 50.0 100.0 4 200.0 400.0 5 250.0 500.0 8 25.0 50.0 0010_001 50.0 100.0 4 200.0 400.0 6 300.0 600.0 8 25.0 50.0 0010_010 50.0 100.0 4 200.0 400.0 7 350.0 700.0 8 25.0 50.0 0010_011 50.0 100.0 4 200.0 400.0 8 400.0 800.0 8 25.0 50.0 0010_100 50.0 75.0 4 200.0 300.0 5 250.0 375.0 6 33.3 50.0 0010_101 45.5 75.0 4 181.8 300.0 5.5 250.0 412.5 6 30.3 50.0 0010_110 41.7 75.0 4 166.7 300.0 6 250.0 450.0 6 27.8 50.0 0011_000 50.0 50.0 5 250.0 250.0 5 250.0 250.0 5 50.0 50.0 0011_001 41.7 50.0 5 208.3 250.0 6 250.0 300.0 5 41.7 50.0 0011_010 35.7 50.0 5 178.6 250.0 7 250.0 350.0 5 35.7 50.0 0011_011 31.3 50.0 5 156.3 250.0 8 250.0 400.0 5 31.3 50.0 0100_000 24 Reserved 0100_001 41.7 50.0 6 250.0 300.0 6 250.0 300.0 6 41.7 50.0 0100_010 35.7 50.0 6 214.3 300.0 7 250.0 350.0 6 35.7 50.0 0100_011 31.3 50.0 6 187.5 300.0 8 250.0 400.0 6 31.3 50.0 0101_000 50.0 100.0 2 100.0 200.0 2.5 125.0 250.0 4 25.0 50.0 0101_001 50.0 100.0 2 100.0 200.0 3 150.0 300.0 4 25.0 50.0 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes Table 14. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 1, 2 (continued) Mode 3 MODCK_HMODCK[1-3] Bus Clock (MHz) Low High CPM Multiplication Factor 4 CPM Clock (MHz) Low High CPU Clock (MHz) Low High PCI Division Factor PCI Clock (MHz) Low High 0101_010 71.4 100.0 2 142.9 200.0 3.5 250.0 350.0 4 35.7 50.0 0101_011 62.5 100.0 2 125.0 200.0 4 250.0 400.0 4 31.3 50.0 0101_100 55.6 100.0 2 111.1 200.0 4.5 250.0 450.0 4 27.8 50.0 0101_101 71.4 83.3 3 214.3 250.0 3.5 250.0 291.7 5 42.9 50.0 0101_110 62.5 83.3 3 187.5 250.0 4 250.0 333.3 5 37.5 50.0 0101_111 55.6 83.3 3 166.7 250.0 4.5 250.0 375.0 5 33.3 50.0 0110_000 60.0 120.0 2.5 150.0 300.0 2.5 150.0 300.0 6 25.0 50.0 0110_001 60.0 120.0 2.5 150.0 300.0 3 180.0 360.0 6 25.0 50.0 0110_010 71.4 120.0 2.5 178.6 300.0 3.5 250.0 420.0 6 29.8 50.0 0110_011 62.5 120.0 2.5 156.3 300.0 4 250.0 480.0 6 26.0 50.0 0110_100 60.0 120.0 2.5 150.0 300.0 4.5 270.0 540.0 6 25.0 50.0 0110_101 60.0 120.0 2.5 150.0 300.0 5 300.0 600.0 6 25.0 50.0 0110_110 60.0 120.0 2.5 150.0 300.0 6 360.0 720.0 6 25.0 50.0 0111_000 Reserved 0111_001 50.0 100.0 3 150.0 300.0 3 150.0 300.0 6 25.0 50.0 0111_010 71.4 100.0 3 214.3 300.0 3.5 250.0 350.0 6 35.7 50.0 0111_011 62.5 100.0 3 187.5 300.0 4 250.0 400.0 6 31.3 50.0 0111_100 55.6 100.0 3 166.7 300.0 4.5 250.0 450.0 6 27.8 50.0 1000_000 Reserved 1000_001 66.7 133.3 3 200.0 400.0 3 200.0 400.0 8 25.0 50.0 1000_010 71.4 133.3 3 214.3 400.0 3.5 250.0 466.7 8 26.8 50.0 1000_011 66.7 133.3 3 200.0 400.0 4 266.7 533.3 8 25.0 50.0 1000_100 66.7 133.3 3 200.0 400.0 4.5 300.0 600.0 8 25.0 50.0 1000_101 66.7 133.3 3 200.0 400.0 6 400.0 800.0 8 25.0 50.0 1000_110 66.7 133.3 3 200.0 400.0 6.5 433.3 866.7 8 25.0 50.0 1001_000 25 CPU Multiplication Factor 5 Reserved MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes Table 14. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 1, 2 (continued) Mode 3 MODCK_HMODCK[1-3] Bus Clock (MHz) Low High CPM Multiplication Factor 4 CPM Clock (MHz) Low High 1001_001 CPU Clock (MHz) Low High PCI Division Factor PCI Clock (MHz) Low High Reserved 1001_010 71.4 114.3 3.5 250.0 400.0 3.5 250.0 400.0 8 31.3 50.0 1001_011 62.5 114.3 3.5 218.8 400.0 4 250.0 457.1 8 27.3 50.0 1001_100 57.1 114.3 3.5 200.0 400.0 4.5 257.1 514.3 8 25.0 50.0 1001_101 50.0 85.7 3.5 175.0 300.0 5 250.0 428.6 6 29.2 50.0 1001_110 45.5 85.7 3.5 159.1 300.0 5.5 250.0 471.4 6 26.5 50.0 1001_111 42.9 85.7 3.5 150.0 300.0 6 257.1 514.3 6 25.0 50.0 1010_000 75.0 150.0 2 150.0 300.0 2 150.0 300.0 6 25.0 50.0 1010_001 75.0 150.0 2 150.0 300.0 2.5 187.5 375.0 6 25.0 50.0 1010_010 75.0 150.0 2 150.0 300.0 3 225.0 450.0 6 25.0 50.0 1010_011 75.0 150.0 2 150.0 300.0 3.5 262.5 525.0 6 25.0 50.0 1010_100 75.0 150.0 2 150.0 300.0 4 300.0 600.0 6 25.0 50.0 1010_101 100.0 200.0 2 200.0 400.0 2.5 250.0 500.0 8 25.0 50.0 1010_110 100.0 200.0 2 200.0 400.0 3 300.0 600.0 8 25.0 50.0 1010_111 100.0 200.0 2 200.0 400.0 3.5 350.0 700.0 8 25.0 50.0 1011_000 26 CPU Multiplication Factor 5 Reserved 1011_001 80.0 160.0 2.5 200.0 400.0 2.5 200.0 400.0 8 25.0 50.0 1011_010 80.0 160.0 2.5 200.0 400.0 3 240.0 480.0 8 25.0 50.0 1011_011 80.0 160.0 2.5 200.0 400.0 3.5 280.0 560.0 8 25.0 50.0 1011_100 80.0 160.0 2.5 200.0 400.0 4 320.0 640.0 8 25.0 50.0 1011_101 80.0 160.0 2.5 200.0 400.0 4.5 360.0 720.0 8 25.0 50.0 1101_000 50.0 100.0 2.5 125.0 250.0 3 150.0 300.0 5 25.0 50.0 1101_001 71.4 100.0 2.5 178.6 250.0 3.5 250.0 350.0 5 35.7 50.0 1101_010 62.5 100.0 2.5 156.3 250.0 4 250.0 400.0 5 31.3 50.0 1101_011 55.6 100.0 2.5 138.9 250.0 4.5 250.0 450.0 5 27.8 50.0 1101_100 50.0 100.0 2.5 125.0 250.0 5 250.0 500.0 5 25.0 50.0 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes Table 14. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 1, 2 (continued) Mode 3 MODCK_HMODCK[1-3] 1 2 3 4 5 Bus Clock (MHz) Low High CPM Multiplication Factor 4 CPM Clock (MHz) Low High CPU Multiplication Factor 5 CPU Clock (MHz) Low High PCI Division Factor PCI Clock (MHz) Low High 1101_101 62.5 125.0 2 125.0 250.0 3 187.5 375.0 5 25.0 50.0 1101_110 62.5 125.0 2 125.0 250.0 4 250.0 500.0 5 25.0 50.0 1110_000 71.4 100.0 3 214.3 300.0 3.5 250.0 350.0 6 35.7 50.0 1110_001 62.5 100.0 3 187.5 300.0 4 250.0 400.0 6 31.3 50.0 1110_010 55.6 100.0 3 166.7 300.0 4.5 250.0 450.0 6 27.8 50.0 1110_011 50.0 100.0 3 150.0 300.0 5 250.0 500.0 6 25.0 50.0 1110_100 50.0 100.0 3 150.0 300.0 5.5 275.0 550.0 6 25.0 50.0 1100_000 Reserved 1100_001 Reserved 1100_010 Reserved The "low" values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock mode. For modes with a CPU multiplication factor 3, the minimum CPU frequency is 125 MHz or 150 MHz, as shown in the table. For modes with a CPU multiplication factor 3.5, the minimum CPU frequency is 250 MHz. The "high" values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user's device. PCI_MODCK determines the PCI clock frequency range. Refer to Table 13 for higher range configurations. MODCK_H = hard reset configuration word [28-31] (refer to Section 5.4 in the MPC8260 User's Manual). MODCK[1-3] = three hardware configuration pins. CPM multiplication factor = CPM clock/bus clock CPU multiplication factor = Core PLL multiplication factor 3.1.1 PCI Agent Mode Table 15 and Table 16 show configurations for PCI agent mode. The frequency values listed are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user's device. Note that in PCI agent mode the input clock is PCI clock. 27 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes Table 15. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) 1, 2 Mode 3 MODCK_HMODCK[1-3] PCI Clock (MHz) Low High CPM Multiplication Factor 4 CPM Clock (MHz) Low High CPU Multiplication Factor 5 CPU Clock (MHz) Low High Bus Division Factor Bus Clock (MHz) Low High Default Modes (MODCK_H=0000 0000_000 50.0 66.7 2 100.0 133.3 2.5 125.0 166.7 2 50.0 66.7 0000_001 50.0 66.7 2 100.0 133.3 3 150.0 200.0 2 50.0 66.7 0000_010 50.0 66.7 3 150.0 200.0 3 150.0 200.0 3 50.0 66.7 0000_011 62.5 66.7 3 187.5 200.0 4 250.0 266.6 3 62.5 66.7 0000_100 50.0 66.7 3 150.0 200.0 3 180.0 240.0 2.5 60.0 80.0 0000_101 59.5 66.7 3 178.6 200.0 3.5 250.0 280.0 2.5 71.4 80.0 0000_110 53.6 66.7 4 214.3 266.6 3.5 250.0 311.1 3 71.4 88.9 0000_111 50.0 66.7 4 200.0 266.6 3 240.0 320.0 2.5 80.0 106.7 Full Configuration Modes 0001_001 Reserved 0001_010 Reserved 0001_011 Reserved 0001_100 62.5 66.7 2 125.0 133.3 8 250.0 266.6 4 31.3 33.3 0010_001 50.0 66.7 3 150.0 200.0 3 180.0 240.0 2.5 60.0 80.0 0010_010 59.5 66.7 3 178.6 200.0 3.5 250.0 280.0 2.5 71.4 80.0 0010_011 52.1 66.7 3 156.3 200.0 4 250.0 320.0 2.5 62.5 80.0 0010_100 50.0 66.7 3 150.0 200.0 4.5 270.0 360.0 2.5 60.0 80.0 150.0 200.0 3 50.0 66.7 250.0 266.6 3 62.5 66.7 0011_000 Reserved 0011_001 Reserved 0011_010 Reserved 0011_011 Reserved 0011_100 Reserved 0100_000 Reserved 0100_001 50.0 66.7 3 150.0 200.0 0100_010 0100_011 28 3 Reserved 62.5 66.7 3 187.5 200.0 4 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes Table 15. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) 1, 2 (continued) Mode 3 PCI Clock (MHz) CPM Multiplication Factor 4 CPM Clock (MHz) CPU Multiplication Factor 5 CPU Clock (MHz) Bus Division Factor Bus Clock (MHz) MODCK_HMODCK[1-3] Low High 0100_100 55.6 66.7 3 166.7 200.0 4.5 250.0 300.0 3 0101_000 50.0 66.7 5 250.0 333.3 2.5 250.0 333.3 2.5 100.0 133.3 0101_001 50.0 66.7 5 250.0 333.3 3 300.0 400.0 2.5 100.0 133.3 0101_010 50.0 66.7 5 250.0 333.3 3.5 350.0 466.6 2.5 100.0 133.3 0101_011 50.0 66.7 5 250.0 333.3 4 400.0 533.3 2.5 100.0 133.3 0101_100 50.0 66.7 5 250.0 333.3 4.5 450.0 599.9 2.5 100.0 133.3 0101_101 50.0 66.7 5 250.0 333.3 5 500.0 666.6 2.5 100.0 133.3 0101_110 50.0 66.7 5 250.0 333.3 5.5 550.0 733.3 2.5 100.0 133.3 Low High 0110_000 High Low High 55.6 66.7 Reserved 0110_001 50.0 66.7 4 200.0 266.6 3 200.0 266.6 3 66.7 88.9 0110_010 53.6 66.7 4 214.3 266.6 3.5 250.0 311.1 3 71.4 88.9 0110_011 50.0 66.7 4 200.0 266.6 4 266.7 355.5 3 66.7 88.9 0110_100 50.0 66.7 4 200.0 266.6 4.5 300.0 400.0 3 66.7 88.9 0111_000 50.0 66.7 3 150.0 200.0 2 150.0 200.0 2 75.0 100.0 0111_001 50.0 66.7 3 150.0 200.0 2.5 187.5 250.0 2 75.0 100.0 0111_010 50.0 66.7 3 150.0 200.0 3 225.0 300.0 2 75.0 100.0 0111_011 50.0 66.7 3 150.0 200.0 3.5 262.5 350.0 2 75.0 100.0 1000_000 29 Low Reserved 1000_001 50.0 66.7 3 150.0 200.0 2.5 150.0 200.0 2.5 60.0 80.0 1000_010 50.0 66.7 3 150.0 200.0 3 180.0 240.0 2.5 60.0 80.0 1000_011 59.5 66.7 3 178.6 200.0 3.5 250.0 280.0 2.5 71.4 80.0 1000_100 52.1 66.7 3 156.3 200.0 4 250.0 320.0 2.5 62.5 80.0 1000_101 50.0 66.7 3 150.0 200.0 4.5 270.0 360.0 2.5 60.0 80.0 1001_000 Reserved 1001_001 Reserved 1001_010 Reserved MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes Table 15. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) 1, 2 (continued) Mode 3 PCI Clock (MHz) CPM Multiplication Factor 4 CPM Clock (MHz) CPU Multiplication Factor 5 CPU Clock (MHz) MODCK_HMODCK[1-3] Low High 1001_011 62.5 66.7 4 250.0 266.6 4 250.0 266.6 1001_100 55.6 66.7 4 222.2 266.6 4.5 Low High 1010_000 High Bus Clock (MHz) Low High 4 62.5 66.7 250.0 300.0 4 55.6 66.7 Reserved 1010_001 50.0 66.7 4 200.0 266.6 3 200.0 266.6 3 66.7 88.9 1010_010 53.6 66.7 4 214.3 266.6 3.5 250.0 311.1 3 71.4 88.9 1010_011 50.0 66.7 4 200.0 266.6 4 266.7 355.5 3 66.7 88.9 1010_100 50.0 66.7 4 200.0 266.6 4.5 300.0 400.0 3 66.7 88.9 1011_000 30 Low Bus Division Factor Reserved 1011_001 50.0 66.7 4 200.0 266.6 2.5 200.0 266.6 2.5 80.0 106.7 1011_010 50.0 66.7 4 200.0 266.6 3 240.0 320.0 2.5 80.0 106.7 1011_011 50.0 66.7 4 200.0 266.6 3.5 280.0 373.3 2.5 80.0 106.7 1011_100 50.0 66.7 4 200.0 266.6 4 320.0 426.6 2.5 80.0 106.7 1011_101 50.0 66.7 4 200.0 266.6 2.5 250.0 333.3 2 100.0 133.3 1011_110 50.0 66.7 4 200.0 266.6 3 300.0 400.0 2 100.0 133.3 1011_111 50.0 66.7 4 200.0 266.6 3.5 350.0 466.6 2 100.0 133.3 1100_101 50.0 66.7 6 300.0 400.0 4 400.0 533.3 3 100.0 133.3 1100_110 50.0 66.7 6 300.0 400.0 4.5 450.0 599.9 3 100.0 133.3 1100_111 50.0 66.7 6 300.0 400.0 5 500.0 666.6 3 100.0 133.3 1101_000 50.0 66.7 6 300.0 400.0 5.5 550.0 733.3 3 100.0 133.3 1101_001 50.0 66.7 6 300.0 400.0 3.5 420.0 559.9 2.5 120.0 160.0 1101_010 50.0 66.7 6 300.0 400.0 4 480.0 639.9 2.5 120.0 160.0 1101_011 50.0 66.7 6 300.0 400.0 4.5 540.0 719.9 2.5 120.0 160.0 1101_100 50.0 66.7 6 300.0 400.0 5 600.0 799.9 2.5 120.0 160.0 1110_000 50.0 66.7 5 250.0 333.3 2.5 312.5 416.6 2 125.0 166.7 1110_001 50.0 66.7 5 250.0 333.3 3 375.0 500.0 2 125.0 166.7 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes Table 15. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) 1, 2 (continued) Mode 3 1 2 3 4 5 PCI Clock (MHz) CPM Multiplication Factor 4 CPM Clock (MHz) CPU Multiplication Factor 5 CPU Clock (MHz) Bus Division Factor Bus Clock (MHz) MODCK_HMODCK[1-3] Low High 1110_010 50.0 66.7 5 250.0 333.3 3.5 437.5 583.3 2 125.0 166.7 1110_011 50.0 66.7 5 250.0 333.3 4 500.0 666.6 2 125.0 166.7 1110_100 50.0 66.7 5 250.0 333.3 4 333.3 444.4 3 83.3 111.1 1110_101 50.0 66.7 5 250.0 333.3 4.5 375.0 500.0 3 83.3 111.1 1110_110 50.0 66.7 5 250.0 333.3 5 416.7 555.5 3 83.3 111.1 1110_111 50.0 66.7 5 250.0 333.3 5.5 458.3 611.1 3 83.3 111.1 Low High 1100_000 Reserved 1100_001 Reserved 1100_010 Reserved Low High Low High The "low" values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock mode. For modes with a CPU multiplication factor 3, the minimum CPU frequency is 125 MHz or 150 MHz, as shown in the table. For modes with a CPU multiplication factor 3.5, the minimum CPU frequency is 250 MHz. The "high" values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user's device. PCI_MODCK determines the PCI clock frequency range. Refer to Table 16 for lower range configurations. MODCK_H = hard reset configuration word [28-31] (refer to Section 5.4 in the MPC8260 User's Manual). MODCK[1-3] = three hardware configuration pins. CPM multiplication factor = CPM clock/bus clock CPU multiplication factor = Core PLL multiplication factor Table 16. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) 1, 2 Mode 3 MODCK_HMODCK[1-3] PCI Clock (MHz) Low High CPM Multiplication Factor 4 CPM Clock (MHz) Low High CPU Multiplication Factor 5 CPU Clock (MHz) Low High Bus Division Factor Bus Clock (MHz) Low High Default Modes (MODCK_H=0000) 31 0000_000 25.0 50.0 4 100.0 200.0 2.5 125.0 250.0 2 50.0 100.0 0000_001 25.0 50.0 4 100.0 200.0 3 150.0 300.0 2 50.0 100.0 0000_010 25.0 50.0 6 150.0 300.0 3 150.0 300.0 3 50.0 100.0 0000_011 31.3 50.0 6 187.5 300.0 4 250.0 400.0 3 62.5 100.0 0000_100 25.0 50.0 6 150.0 300.0 3 180.0 360.0 2.5 60.0 120.0 0000_101 29.8 50.0 6 178.6 300.0 3.5 250.0 420.0 2.5 71.4 120.0 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes Table 16. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) 1, 2 (continued) Mode 3 PCI Clock (MHz) CPM Multiplication Factor 4 CPM Clock (MHz) CPU Multiplication Factor 5 CPU Clock (MHz) Bus Division Factor Bus Clock (MHz) MODCK_HMODCK[1-3] Low High 0000_110 26.8 50.0 8 214.3 400.0 3.5 250.0 466.7 3 71.4 133.3 0000_111 25.0 50.0 8 200.0 400.0 3 240.0 480.0 2.5 80.0 160.0 Low High Low High Low High Full Configuration Modes 0001_001 50.0 50.0 4 200.0 200.0 5 250.0 250.0 4 50.0 50.0 0001_010 41.7 50.0 4 166.7 200.0 6 250.0 300.0 4 41.7 50.0 0001_011 35.7 50.0 4 142.9 200.0 7 250.0 350.0 4 35.7 50.0 0001_100 31.3 50.0 4 125.0 200.0 8 250.0 400.0 4 31.3 50.0 0010_001 25.0 50.0 6 150.0 300.0 3 180.0 360.0 2.5 60.0 120.0 0010_010 29.8 50.0 6 178.6 300.0 3.5 250.0 420.0 2.5 71.4 120.0 0010_011 26.0 50.0 6 156.3 300.0 4 250.0 480.0 2.5 62.5 120.0 0010_100 25.0 50.0 6 150.0 300.0 4.5 270.0 540.0 2.5 60.0 120.0 104.3 166.7 3 41.7 66.7 0011_000 0011_001 Reserved 31.3 50.0 4 125.0 200.0 0011_010 Reserved 0011_011 46.9 50.0 4 187.5 200.0 4 250.0 266.7 3 62.5 66.7 0011_100 41.7 50.0 4 166.7 200.0 4.5 250.0 300.0 3 55.6 66.7 0100_000 32 2.5 Reserved 0100_001 25.0 50.0 6 150.0 300.0 3 150.0 300.0 3 50.0 100.0 0100_010 35.7 50.0 6 214.3 300.0 3.5 250.0 350.0 3 71.4 100.0 0100_011 31.3 50.0 6 187.5 300.0 4 250.0 400.0 3 62.5 100.0 0100_100 27.8 50.0 6 166.7 300.0 4.5 250.0 450.0 3 55.6 100.0 0101_000 25.0 50.0 5 125.0 250.0 2.5 125.0 250.0 2.5 50.0 100.0 0101_001 25.0 50.0 5 125.0 250.0 3 150.0 300.0 2.5 50.0 100.0 0101_010 35.7 50.0 5 178.6 250.0 3.5 250.0 350.0 2.5 71.4 100.0 0101_011 31.3 50.0 5 156.3 250.0 4 250.0 400.0 2.5 62.5 100.0 0101_100 27.8 50.0 5 138.9 250.0 4.5 250.0 450.0 2.5 55.6 100.0 0101_101 25.0 50.0 5 125.0 250.0 5 250.0 500.0 2.5 50.0 100.0 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes Table 16. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) 1, 2 (continued) Mode 3 PCI Clock (MHz) MODCK_HMODCK[1-3] Low High 0101_110 25.0 50.0 CPM Multiplication Factor 4 5 CPM Clock (MHz) Low High 125.0 250.0 0110_000 5.5 CPU Clock (MHz) Low High Bus Division Factor Bus Clock (MHz) Low High 275.0 550.0 2.5 50.0 100.0 Reserved 0110_001 25.0 50.0 8 200.0 400.0 3 200.0 400.0 3 66.7 133.3 0110_010 26.8 50.0 8 214.3 400.0 3.5 250.0 466.7 3 71.4 133.3 0110_011 25.0 50.0 8 200.0 400.0 4 266.7 533.3 3 66.7 133.3 0110_100 25.0 50.0 8 200.0 400.0 4.5 300.0 600.0 3 66.7 133.3 0111_000 25.0 50.0 6 150.0 300.0 2 150.0 300.0 2 75.0 150.0 0111_001 25.0 50.0 6 150.0 300.0 2.5 187.5 375.0 2 75.0 150.0 0111_010 25.0 50.0 6 150.0 300.0 3 225.0 450.0 2 75.0 150.0 0111_011 25.0 50.0 6 150.0 300.0 3.5 262.5 525.0 2 75.0 150.0 1000_000 Reserved 1000_001 25.0 50.0 6 150.0 300.0 2.5 150.0 300.0 2.5 60.0 120.0 1000_010 25.0 50.0 6 150.0 300.0 3 180.0 360.0 2.5 60.0 120.0 1000_011 29.8 50.0 6 178.6 300.0 3.5 250.0 420.0 2.5 71.4 120.0 1000_100 26.0 50.0 6 156.3 300.0 4 250.0 480.0 2.5 62.5 120.0 1000_101 25.0 50.0 6 150.0 300.0 4.5 270.0 540.0 2.5 60.0 120.0 1001_000 Reserved 1001_001 Reserved 1001_010 Reserved 1001_011 31.3 50.0 8 250.0 400.0 4 250.0 400.0 4 62.5 100.0 1001_100 27.8 50.0 8 222.2 400.0 4.5 250.0 450.0 4 55.6 100.0 1010_000 33 CPU Multiplication Factor 5 Reserved 1010_001 25.0 50.0 8 200.0 400.0 3 200.0 400.0 3 66.7 133.3 1010_010 26.8 50.0 8 214.3 400.0 3.5 250.0 466.7 3 71.4 133.3 1010_011 25.0 50.0 8 200.0 400.0 4 266.7 533.3 3 66.7 133.3 1010_100 25.0 50.0 8 200.0 400.0 4.5 300.0 600.0 3 66.7 133.3 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes Table 16. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) 1, 2 (continued) Mode 3 MODCK_HMODCK[1-3] PCI Clock (MHz) Low High CPM Multiplication Factor 4 CPM Clock (MHz) Low High 1011_000 34 CPU Multiplication Factor 5 CPU Clock (MHz) Low High Bus Division Factor Bus Clock (MHz) Low High Reserved 1011_001 25.0 50.0 8 200.0 400.0 2.5 200.0 400.0 2.5 80.0 160.0 1011_010 25.0 50.0 8 200.0 400.0 3 240.0 480.0 2.5 80.0 160.0 1011_011 25.0 50.0 8 200.0 400.0 3.5 280.0 560.0 2.5 80.0 160.0 1011_100 25.0 50.0 8 200.0 400.0 4 320.0 640.0 2.5 80.0 160.0 1011_101 25.0 50.0 8 200.0 400.0 2.5 250.0 500.0 2 100.0 200.0 1011_110 25.0 50.0 8 200.0 400.0 3 300.0 600.0 2 100.0 200.0 1011_111 25.0 50.0 8 200.0 400.0 3.5 350.0 700.0 2 100.0 200.0 1100_101 31.3 50.0 6 187.5 300.0 4 250.0 400.0 3 62.5 100.0 1100_110 27.8 50.0 6 166.7 300.0 4.5 250.0 450.0 3 55.6 100.0 1100_111 25.0 50.0 6 150.0 300.0 5 250.0 500.0 3 50.0 100.0 1101_000 25.0 50.0 6 150.0 300.0 5.5 275.0 550.0 3 50.0 100.0 1101_001 29.8 50.0 6 178.6 300.0 3.5 250.0 420.0 2.5 71.4 120.0 1101_010 26.0 50.0 6 156.3 300.0 4 250.0 480.0 2.5 62.5 120.0 1101_011 25.0 50.0 6 150.0 300.0 4.5 270.0 540.0 2.5 60.0 120.0 1101_100 25.0 50.0 6 150.0 300.0 5 300.0 600.0 2.5 60.0 120.0 1110_000 25.0 50.0 5 125.0 250.0 2.5 156.3 312.5 2 62.5 125.0 1110_001 25.0 50.0 5 125.0 250.0 3 187.5 375.0 2 62.5 125.0 1110_010 28.6 50.0 5 142.9 250.0 3.5 250.0 437.5 2 71.4 125.0 1110_011 25.0 50.0 5 125.0 250.0 4 250.0 500.0 2 62.5 125.0 1110_100 37.5 50.0 5 187.5 250.0 4 250.0 333.3 3 62.5 83.3 1110_101 33.3 50.0 5 166.7 250.0 4.5 250.0 375.0 3 55.6 83.3 1110_110 30.0 50.0 5 150.0 250.0 5 250.0 416.7 3 50.0 83.3 1110_111 27.3 50.0 5 136.4 250.0 5.5 250.0 458.3 3 45.5 83.3 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Clock Configuration Modes Table 16. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) 1, 2 (continued) Mode 3 MODCK_HMODCK[1-3] 1 2 3 4 5 PCI Clock (MHz) Low High CPM Multiplication Factor 4 CPM Clock (MHz) Low High CPU Multiplication Factor 5 1100_000 Reserved 1100_001 Reserved 1100_010 Reserved CPU Clock (MHz) Low High Bus Division Factor Bus Clock (MHz) Low High The "low" values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock mode. For modes with a CPU multiplication factor 3, the minimum CPU frequency is 125 MHz or 150 MHz, as shown in the table. For modes with a CPU multiplication factor 3.5, the minimum CPU frequency is 250 MHz. The "high" values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user's device. PCI_MODCK determines the PCI clock frequency range. Refer to Table 15 for higher range configurations. MODCK_H = hard reset configuration word [28-31] (refer to Section 5.4 in the MPC8260 User's Manual). MODCK[1-3] = three hardware configuration pins. CPM multiplication factor = CPM clock/bus clock CPU multiplication factor = Core PLL multiplication factor 35 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Pinout 4 Pinout The figure and table below show the pin assignments and pinout for the 516 PBGA package. 4.1 Pin Assignments Figure 12 shows the pinout of the 516 PBGA package as viewed from the top surface. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Not to Scale Figure 12. Pinout of the 516 PBGA Package (View from Top) 36 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Pinout Table 17 shows the pinout of the MPC8272. Note that the pins in the `MPC8272/8271 only" column relate to Utopia functionality. Table 17. Pinout 1 Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 Ball MPC8272/MPC8271 only BR A19 BG/IRQ6 D2 ABB/IRQ2 C1 TS D1 A0 A3 A1 B5 A2 D8 A3 C6 A4 A4 A5 A6 A6 B6 A7 C7 A8 B7 A9 A7 A10 D9 A11 E11 A12 C9 A13 B9 A14 D11 A15 A9 A16 B10 A17 A10 A18 B11 A19 A11 A20 D12 A21 A12 A22 D13 A23 B13 A24 C13 A25 C14 37 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Pinout Table 17. Pinout 1 (continued) Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 Ball MPC8272/MPC8271 only A26 B14 A27 D14 A28 E14 A29 A14 A30 B15 A31 A15 TT0 B3 TT1 E8 TT2 D7 TT3 C4 TT4 E7 TBST E3 TSIZ0 E4 TSIZ1 E5 TSIZ2 C3 TSIZ3 D5 AACK D3 ARTRY C2 DBG/IRQ7 F16 DBB/IRQ3 D18 D0 AC1 D1 AA1 D2 V3 D3 R5 D4 P4 D5 M4 D6 J4 D7 G1 D8 W6 D9 Y3 D10 V1 D11 N6 38 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Pinout Table 17. Pinout 1 (continued) Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 Ball MPC8272/MPC8271 only D12 P3 D13 M2 D14 J5 D15 G3 D16 AB3 D17 Y1 D18 T4 D19 T3 D20 P2 D21 M1 D22 J1 D23 G4 D24 AB2 D25 W4 D26 V2 D27 T1 D28 N5 D29 L1 D30 H1 D31 G5 D32 W5 D33 W2 D34 T5 D35 T2 D36 N1 D37 K3 D38 H2 D39 F1 D40 AA2 D41 W1 D42 U3 D43 R2 39 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Pinout Table 17. Pinout 1 (continued) Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 Ball MPC8272/MPC8271 only D44 N2 D45 L2 D46 H4 D47 F2 D48 AB1 D49 U4 D50 U1 D51 R3 D52 N3 D53 K2 D54 H5 D55 F4 D56 AA3 D57 U5 D58 U2 D59 P5 D60 M3 D61 K4 D62 H3 D63 E1 IRQ3/CKSTP_OUT/EXT_BR3 B16 IRQ4/CORE_SRESET/EXT_BG3 C15 IRQ5/TBEN/EXT_DBG3/CINT Y4 PSDVAL C19 TA AA4 TEA AB6 GBL/IRQ1 D15 CI/BADDR29/IRQ2 D16 WT/BADDR30/IRQ3 C16 BADDR31/IRQ5/CINT E17 CPU_BR/INT_OUT B20 CS0 AE6 40 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Pinout Table 17. Pinout 1 (continued) Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 Ball MPC8272/MPC8271 only CS1 AD7 CS2 AF5 CS3 AC8 CS4 AF6 CS5 AD8 BCTL1/CS6/SMI AC9 CS7/TLBISYNC AB9 BADDR27/IRQ1 AB8 BADDR28/IRQ2 AC7 ALE/IRQ4 AF4 BCTL0 AF3 PWE0/PSDDQM0/PBS0 AD6 PWE1/PSDDQM1/PBS1 AE5 PWE2/PSDDQM2/PBS2 AE3 PWE3/PSDDQM3/PBS3 AF2 PWE4/PSDDQM4/PBS4 AC6 PWE5/PSDDQM5/PBS5 AC5 PWE6/PSDDQM6/PBS6 AD4 PWE7/PSDDQM7/PBS7 AB5 PSDA10/PGPL0 AE2 PSDWE/PGPL1 AD3 POE/PSDRAS/PGPL2 AB4 PSDCAS/PGPL3 AC3 PGTA/PUPMWAIT/PGPL4 AD2 PSDAMUX/PGPL5 AC2 PCI_HOST_EN AC21 PCI_ARB_EN AE22 DLL_ENABLE AE23 PAR AF12 FRAME AD15 TRDY AF16 IRDY AF15 41 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Pinout Table 17. Pinout 1 (continued) Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 Ball MPC8272/MPC8271 only STOP AE15 DEVSEL AE14 IDSEL AC17 PERR AD14 SERR AD13 REQ0 AE20 REQ1 AF14 GNT0 AD20 GNT1 AE13 GNT2 AF21 PCI_RST AF22 INTA AE21 REQ2 AB14 DLLOUT AC22 AD0 AF7 AD1 AE10 AD2 AB10 AD3 AD10 AD4 AE9 AD5 AF8 AD6 AC10 AD7 AE11 AD8 AB11 AD9 AF10 AD10 AF9 AD11 AB12 AD12 AC12 AD13 AD12 AD14 AF11 AD15 AB13 AD16 AE16 AD17 AF17 42 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Pinout Table 17. Pinout 1 (continued) Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 Ball MPC8272/MPC8271 only AD18 AD16 AD19 AC16 AD20 AF18 AD21 AB16 AD22 AD17 AD23 AF19 AD24 AB17 AD25 AF20 AD26 AE19 AD27 AC18 AD28 AB18 AD29 AD19 AD30 AD21 AD31 AC20 C0/BE0 AE12 C1/BE1 AF13 C2/BE2 AC15 C3/BE3 AE18 IRQ0/NMI_OUT A17 TRST E21 TCK B22 TMS C23 TDI B24 TDO A22 TRIS B23 PORESET/PCI_RST C24 HRESET D22 SRESET F22 RSTCONF A24 MODCK1/RSRV/TC0/BNKSEL0 A20 MODCK2/CSE0/TC1/BNKSEL1 C20 MODCK3/CSE1/TC2/BNKSEL2 A21 43 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Pinout Table 17. Pinout 1 (continued) Pin Name Ball MPC8272/MPC8248 and MPC8271/MPC8247 MPC8272/MPC8271 only CLKIN1 D21 PA8/SMRXD2 AF25 2 PA9/SMTXD2 AA222 PA10/MSNUM5 FCC1_UT_RXD0 AB232 PA11/MSNUM4 FCC1_UT_RXD1 AD262 PA12/MSNUM3 FCC1_UT_RXD2 AD252 PA13/MSNUM2 FCC1_UT_RXD3 AA242 PA14/FCC1_MII_HDLC_RXD3 FCC1_UT_RXD4 W222 PA15/FCC1_MII_HDLC_RXD2 FCC1_UT_RXD5 Y242 PA16/FCC1_MII_HDLC_RXD1 FCC1_UT_RXD6 T222 PA17/FCC1_MII_HDLC_RXD0/ FCC1_UT_RXD7 FCC1_MII_TRAN_RXD/FCC1_RMII_R XD0 W262 PA18/FCC1_MII_HDLC_TXD0/FCC1_ MII_TRAN_TXD/ FCC1_RMII_TXD0 FCC1_UT_TXD7 V262 PA19/FCC1_MII_HDLC_TXD1/FCC1_ RMII_TXD1 FCC1_UT_TXD6 R232 PA20/FCC1_MII_HDLC_TXD2 FCC1_UT_TXD5 P252 PA21/FCC1_MII_HDLC_TXD3 FCC1_UT_TXD4 N222 PA22 FCC1_UT_TXD3 N262 PA23 FCC1_UT_TXD2 N232 PA24/MSNUM1 FCC1_UT_TXD1 H262 PA25/MSNUM0 FCC1_UT_TXD0 G252 PA26/FCC1_MII_RMIIRX_ER FCC1_UT_RXCLAV L222 PA27/FCC1_MII_RX_DV/FCC1_RMII_ FCC1_UT_RXSOC CRS_DV G242 PA28/FCC1_MII_RMII_TX_EN FCC1_UT_RXENB G232 PA29/FCC1_MII_TX_ER FCC1_UT_TXSOC B262 PA30/FCC1_MII_CRS/FCC1_RTS FCC1_UT_TXCLAV A252 PA31/FCC1_MII_COL FCC1_UT_TXENB G222 PB18/FCC2_MII_HDLC_RXD3/L1CLKOD2 T252 PB19/FCC2_MII_HDLC_RXD2/L1RQD2 P222 PB20/FCC2_MII_HDLC_RMII_RXD1 L252 44 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Pinout Table 17. Pinout 1 (continued) Pin Name Ball MPC8272/MPC8248 and MPC8271/MPC8247 MPC8272/MPC8271 only PB21/FCC2_MII_HDLC_RMII_XD0/FCC2_TRAN_RXD J262 PB22/FCC2_MII_HDLC_TXD0/FCC2_TRAN_TXD/ FCC2_RMII_TXD0 U232 PB23/FCC2_MII_HDLC_TXD1/FCC2_RMII_TXD1 U262 PB24/FCC2_MII_HDLC_TXD2/L1RSYNCB2 M242 PB25/FCC2_MII_HDLC_TXD3/L1TSYNCB2 M232 PB26/FCC2_MII_CRS/L1RXDB2 H242 PB27/FCC2_MII_COL/L1TXDB2 E252 PB28/FCC2_MII_RMII_RX_ER/FCC2_RTS/TXD1 D262 PB29/FCC2_MII_RMII_TX_EN K212 PB30/FCC2_MII_RX_DV/FCC2_RMII_CRS_DV D242 PB31/FCC2_MII_TX_ER E232 PC0/DREQ3/BRGO7/SMSYN1/L1CLKOA2 AF232 PC1/BRGO6/L1RQA2 AD232 PC4/SMRXD1/SI2_L1ST4/FCC2_CD AB222 PC5/SMTXD1/SI2_L1ST3/FCC2_CTS AE242 PC6/FCC1_CD/SI2_L1ST2 FCC1_UT_RXADDR2 AF242 PC7/FCC1_CTS FCC1_UT_TXADDR2 AE262 PC8/CD4/RTS1/SI2_L1ST2/CTS3 AC242 PC9/CTS4/L1TSYNCA2 AA232 PC10/CD3/USB_RN AB252 V222 PC11/CTS3/USB_RP/L1TXD3A2 PC12/DONE3 FCC1_UT_RXADDR1 AA262 PC13/BRGO5 FCC1_UT_TXADDR1 V232 PC14/CD1 FCC1_UT_RXADDR0 W242 PC15/CTS1 FCC1_UT_TXADDR0 U242 PC16/CLK16 T232 PC17/CLK15/BRGO8/DONE2 T262 PC18/CLK14/TGATE2 R262 PC19/CLK13/BRGO7/TGATE1 P242 PC20/CLK12/USBOE L262 PC21/CLK11/BRGO6/CP_INT L242 45 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Pinout Table 17. Pinout 1 (continued) Pin Name Ball MPC8272/MPC8248 and MPC8271/MPC8247 PC22/CLK10/DONE3 MPC8272/MPC8271 only FCC1_UT_TXPRTY L232 PC23/CLK9/BRGO5/DACK3/CD1 K242 PC24/CLK8/TIN3/TOUT4/DREQ2/BRGO1 K232 PC25/CLK7/BRGO4/DACK2/SPISEL F262 PC26/CLK6/TOUT3/TMCLK H232 PC27/CLK5/BRGO3/TOUT1 FCC1_UT_RXPRTY K222 PC28/CLK4/TIN1/TOUT2/SPICLK D252 PC29/CLK3/TIN2/BRGO2/CTS1 F242 PD7/SMSYN2 FCC1_UT_TXADDR3 AB212 PD14/I2CSCL AC262 PD15/I2CSDA Y232 PD16/SPIMISO FCC1_UT_TXPRTY AA252 PD17/BRGO2/SPIMOSI FCC1_UT_RXPRTY Y262 PD18/SPICLK FCC1_UT_RXADDR4 W252 PD19/SPISEL/BRGO1 FCC1_UT_TXADDR4 V252 PD20/RTS4/L1RSYNCA2 R242 PD21/TXD4/L1RXD0A2 P232 PD22/RXD4/L1TXD0A2 N252 PD23/RTS3/USB_TP K262 PD24/TXD3/USB_TN K252 PD25/RXD3/USB_RXD J252 PD29/RTS1 FCC1_UT_RXADDR3 C262 PD30/TXD1 E242 PD31/RXD1 B252 VCCSYN C18 VCCSYN1 K6 CLKIN2 C21 SPARE0 3 AD24 THERMAL0 4 D194 THERMAL14 J34 46 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Pinout Table 17. Pinout 1 (continued) Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 Ball MPC8272/MPC8271 only I/O power B4, F3, J2, N4, AD1, AD5, AE8, AC13, AD18, AB24, AB26, W23, R25, M25, F25, C25, C22, B17, B12, B8, E6, F6, H6, L5, L6, P6, T6, U6, V5, Y5, AA6, AA8, AA10, AA11, AA14, AA16, AA17, AB19, AB20, W21, U21, T21, P21, N21, M22, J22, H21, F21, F19, F17, E16, F14, E13, E12, F10, E10, E9 Core Power F5, K5, M5, AA5, AB7, AA13, AA19, AA21, Y22, AC25, U22, R22, L21, H22, E22, E20, E15, F13, F11, F8, L3, V4, W3, AC11, AD11, AB15, U25, T24, J24, H25, F23, B19, D17, C17, D10, C10 Ground AD22, E19, E2, K1, Y2, AE1, AE4, AD9, AC14, AE17, AC19, AE25, V24, P26, M26, G26, E26, B21, C12, C11, C8, A8, B18, A18, A2, B1, B2, A5, C5, D4, D6, G2, L4, P1, R1, R4, AC4, AE7, AC23, Y25, N24, J23, A23, D23, D20, E18, A13, A16, K10, K11, K12, K13, K14, K15, K16, K17, L10, L11, L12, L13, L14, L15, L16, L17, M10, M11, M12, M13, M14, M15, M16, M17, N10, N11, N12, N13, N14, N15, N16, N17, P10, P11, P12, P13, P14, P15, P16, P17, R10, R11,R12, R13, R14, R15, R16, R17, T10, T11, T12, T13, T14, T15, T16, T17, U10, U11, U12, U13, U14, U15, U16, U17 1 Pinout ball assignments are subject to change. Motorola will indicate to Cisco when ball assignments are finalized. The default configuration of the CPM pins (PA[8-31], PB[18-31], PC[0-1,4-29], PD[7-25, 29-31]) is input. To prevent excessive DC current, it is recommended either to pull unused pins to GND or VDDH, or to configure them as outputs. 3 Must be pulled down or left floating 4 This pin is not connected. It should be left floating. 2 47 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Package 5 Package Figure 13 shows the side profile of the PBGA package. Transfer molding compound Wire bonds Die attach Ball bond Screen-printed solder mask Plated substrate via Cu substrate traces DIE Resin glass epoxy 1 mm pitch Figure 13. Side View of the PBGA Package Remove Table 18 provides package parameters. Figure 14 provides the mechanical dimensions and bottom surface nomenclature of the 516 PBGA package. Table 18. Package Parameters 48 Outline (mm) Type Interconnects Pitch (mm) Nominal Unmounted Height (mm) 27 x 27 PBGA 516 1 2.25 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Package Figure 14. Mechanical Dimensions and Bottom Surface Nomenclature--516 PBGA 49 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Ordering Information 6 Ordering Information Figure 15 provides an example of the Motorola part numbering nomenclature for the MPC8272. In addition to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s) in the part from the original production design. Each part number also contains a revision code that refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. For more information, contact a local Motorola sales office. MPC 82XX C VR XXX X Die Revision Level Product Code Device Number CPU/CPM/Bus Frequency (MHz) B = 66 E = 100 I = 200 M = 266 P = 300 T = 400 Temperature Range Blank = 0 to 105 C C = -40 to 105 C Package ZQ = 516 PBGA (lead spheres) VR = 516 PBGA (no lead spheres) Figure 15. Motorola Part Number Key 7 Document Revision History Table 19 lists significant changes between revisions of this hardware specification. Table 19. Document Revision History Revision 50 Date Substantive Changes 0 5/2003 NDA release 0.1 9/2003 * * * * * Addition of the MPC8271 and the MPC8247 (these devices do not have a security engine) Table 3: Addition of note 2 to VIH Table 3: Changed IOL for 60x signals to 6.0 mA Modification of note 1 for Table 13, Table 14, Table 15, and Table 16 Table 17: Addition of ball AD9 to GND. In rev 0 of this document, AD8 was listed as assigned to both CS5 and GND. AD8 is only assigned to CS5. * Table 17: Addition of note 4 to Thermal0 (D19) and Thermal1(J3) * Addition of ZQ package code to Figure 15 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK 51 MPC8272 Family Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE MOTOROLA HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-480-768-2130 (800) 521-6274 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design ASIA/PACIFIC: or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre, 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without TECHNICAL INFORMATION CENTER: limitation consequential or incidental damages. "Typical" parameters which may be provided in (800) 521-6274 Motorola data sheets and/or specifications can and do vary in different applications and actual HOME PAGE: performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any www.motorola.com/semiconductors license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. The described product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc. 2003 MPC8272EC