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| MPC555.K3 01K83H Modules |

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| Current Module Revision |

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| BBC.CDR1UBUS_03_0 |

| CMF.192KB_CDR1UBUS_04_1 |

| CMF.256KA_CDR1UBUS_04_1 |

| DPTRAM.6K_CDR1IMB3_03_0 |

| JTAG.CDR1_01_0 |

| QADC64.CDR1IMB3_02_0B |

| QSMCM.CDR1IMB3_02_0 |

| TOUCAN.CDR1IMB3_04_0 |

| TPU3.CDR1IMB3_02_2 |

| UIMB.CDR1UBUSIMB3_02_0 |

| USIU.CDR1UBUS_05_1 |

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ERRATA AND INFORMATION SUMMARY

AR_678 Additional current on KAPWR

AR_697 Revised operating currents

AR_600 Updated Flash Programming Algorithm and Control Registers

AR_699 CMF: Limit set / clear cycles on censorship bits

AR_485 Disable of TPU emulation mode while MISC enabled corrupts data in RAM

AR_445 Potential trap state in MIOS MDASM in OPWM mode.

AR_468 Configure MIOS/VF/VFLS pins as all MIOS or all VF/VFLS

AR_443 MIOS: Do not write data into the MDASMBR when in an input mode.

AR_444 MIOS: Warning in MDASM OPWM mode when MDASMAR = MDASMBR.

AR_446 MIOS: Avoid 100% pulse in MDASM OPWM mode.

AR_517 MIOS: Read MIOS1VNR and MIOS1TCPR registers are undefined

AR_624 MIOS: Use even values in MPWMSMPERR

AR_440 Execute any IMUL/DIV instruction prior to entering low power modes.

AR_214 Only negate interrupts while the EE bit (MSR) disables interrupts

AR_478 QADC64: Don’t use channel 63 "End Of Queue".

AR_563 QSM/QSMCM/QADC64 corrupts data after an IACK cycle in CISC parts.

AR_754 QADC64:Do not use queue1 in external gated mode with queue2 in continuous mode.

AR_421 QADC64: Don’t switch to software triggered continuous scan after completing Q1.

AR_422 QADC64: Do not rely on set of TOR1 in external gated continuous scan mode

AR_419 QADC64: False trigger upon configuration (Does NOT apply to ALL parts)

AR_420 QADC64: Don’t change BQ2 with a set of SSE2 without a mode change.

AR_435 QADC64: TOR1 flag operates in both single and continuous external gated modes.

AR_563 QSM/QSMCM/QADC64 corrupts data after an IACK cycle in CISC parts.

AR_584 QSMCM: Do not use link baud and ECK modes

AR_627 TPU: (Microcode) Add neg_mrl with write_mer and end_of_phase

AR_577 TPU3 - TCR2PSCK2 bit does not give TCR2 divide ratios specified.

AR_498 UIMB: Read failures occur for IMB accesses when IMB clock is half speed

AR_479 USIU: The MEMC does not support external master burst cycles

AR_679 USIU: In slave mode, do not use write slave accesses

AR_389 Little Endian modes are not supported

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CDR_AR_678 Customer Information MPC555.K3

Additional current on KAPWR

DESCRIPTION:

KAPWR current exceeds the initial design targets. During operation, KAPWR may be

8ma. Currents during power-down modes have not been fully characterized, and should

be assumed to be the same value.

WORKAROUND:

Design KAPWR supply to handle the additional current. Characterize the current

DESCRIPTION:

Characterization of silicon indicates that the operating current specifications

must be updated. The total current is not anticipated to change significantly, but

will be redistributed amongst VDDL, VDDI, KAPWR, VDDSRAM, VDDSYN, and VDDF.

WORKAROUND:

Refer to electrical specification 3.3 or later for revised values.

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CDR_AR_381 Customer Information MPC555.K3

New Features on MPC555 mask revision J76N an later

DESCRIPTION:

Several new features were added to the MPC555 starting with mask revision 00J76N

and also included in revisions K02A. In the USIU, the DBCT and DBSLR clock control

bits were added ("Disable backup clock for timers", "Disable clock switch in loss

of lock and reset"). In the USIU, a mode was added to allow the WE pins to also

WORKAROUND:

Consult a revised users manual (15 September 1998 or later) to determine how to use

these features. Use the latest version of the FLASH programming tools (version 1.1

or later of CMF_DEMO routines).

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CDR_AR_412 Customer Information MPC555.K3

Avoid instruction fetches from IMB/UIMB memory map

DESCRIPTION:

Instruction fetches on the IMB or to UIMB control registers may result in improper

CDR_AR_597 Customer Information MPC555.K3

AC timing changes

DESCRIPTION:

Some of the AC timing specifications have changed. Refer to electrical

specification 3.3 or later for new values. See CDR_AR_524 for AC timing

specification 30. In addition, the following electrical specifications have changed

to the following new values: {sp7, sp7a, sp7b, sp7c, sp7d} 4ns, {sp8a, sp8c, sp8d}

14ns, sp8b 15ns, sp10 14ns, sp11 14ns, sp15 12ns, sp15b 8ns, sp22 9ns, sp28 9ns,

MASKNUM field in USIU is 0x32

DESCRIPTION:

MASKNUM field in USIU has been changed to 0x32 and will change on future revisions.

WORKAROUND:

Modify software to expect new value (0x32) for the MASKNUM field.

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CDR_AR_696 Customer Erratum CMF.192KB_CDR1UBUS_04_1

CMF: Program at reduced temperature and voltage ranges

DESCRIPTION:

There may be insufficient program margin to be able to correctly read all bits of

the array at cold with 3.0Vdd if the part was programmed at hot.

WORKAROUND:

temperature may be increased to 90C with sufficient program margin to operate over

the entire temperature range.

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CDR_AR_730 Customer Information CMF.192KB_CDR1UBUS_04_1

Excessive pulses required for setting censorship.

DESCRIPTION:

Setting the censor bits with the released driver code takes an excessive amount of

pulses (100’s when it should be 10-15).Root Cause: With the previous release driver

code which follows the old published censorship set algorithm, the row addresses to

the array varied during high voltage set operations. These row addresses caused

following fix. For Setting the censor bit, insert program interlock write prior to

writing EHV. But if the transition is from 00 to 01 and the ACCESS bit[s] is/are

not set and software is running in censored mode, do not perform the interlock

write[s], and instead after writing the EHV bit[s] ensure that U-bus addresses17:25

do not change for the 100ms pulse duration. (Perform a tight loop which lasts >

100ms, do not poll HVS bit[s] during that loop, ensure that the loop and any

associated prefetching or operand accesses does not result in addresses which alter

A[17:25] on the u-bus.)

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CDR_AR_600 Customer Information CMF.192KB_CDR1UBUS_04_1

algorithm and pulse widths are still subject to change. Additional control bits and

modes have been added for use during programming and erase. Using the previous

flash programming or erase algorithm will subject the part to additional stress,

which must be avoided.

WORKAROUND:

Update erase pulse widths. Obtain the latest programming algorithm. Do NOT program

with the previous flash programming or erase algorithms.

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CDR_AR_699 Customer Information CMF.192KB_CDR1UBUS_04_1

CMF: Limit set / clear cycles on censorship bits

DESCRIPTION:

The number of set/clear cycles for censorship bits was not previously specified.

The value will be finalized during characterization and qualification of a

censorship enabled part. The anticipated number of set / clear operations allowed

is 10.

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CDR_AR_485 Customer Information DPTRAM.6K_CDR1IMB3_03_0

Disable of TPU emulation mode while MISC enabled corrupts data in RAM

DESCRIPTION:

If the TPU emulation mode is negated while MISC is enabled, the DPTRAM data may be

corrupted.

WORKAROUND:

In test mode / TPU development mode, disable the MISCEN (DPTMCR) before negation of

TPEMEM in the TCR. In normal mode, disable MISCEN prior to performing a soft reset

DESCRIPTION:

A trap state is entered when a value of MDASMBR is written in OPWM mode, to a value

which is out of the counter bus range. For example, if the modulus value of the

MCSM driving the counter bus is $FF00 and if MDASMBR is written to a value less

than $FF00, then a match is never made on channel B hence a B1 to B2 transfer never

occurs. To get out of the trap, the MDASM mode should be reset back to idle.

WORKAROUND:

Ensure that the software never writes MDASMBR (in OPWM mode) to a value which is

less than the MCSMMOD value.

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CDR_AR_468 Customer Erratum MIOS1.CDR1IMB3_02_0

Configure MIOS/VF/VFLS pins as all MIOS or all VF/VFLS

DESCRIPTION:

The MIOS VF/VFLS multiplexer must not be individually programmed. These pins can

be configured either as VF/VFLS or as all MIOS pins. Do not configure bit[0:1] of

the MIOS1TPCR register as 2’b01 or 2’b10.

CDR_AR_443 Customer Erratum MIOS1.CDR1IMB3_02_0

MIOS: Do not write data into the MDASMBR when in an input mode.

DESCRIPTION:

The MDASMBR register can be loaded via a write from the IMB, from the counter bus

OR from a transfer from the MDASMAR to the MDASMBR register. The transfer from

MDASMAR to MDASMBR only happens in input modes, when the software should not

normally write into MDASMBR. However, no hardware exists to prevent a simultaneous

transfer from MDASMAR and write to MDASMBR. As a result, during a simultaneous

transfer and write, the resulting data in MDASMBR will be undefined. The

specification does not define what happens in this case.

MIOS: Warning in MDASM OPWM mode when MDASMAR = MDASMBR.

DESCRIPTION:

In OPWM mode when a comparison occurs simultaneously on register A and B (i.e. they

have the same value stored), the pin is reset or stays reset. The specification

states that the transfer between B1 and B2 should occur when the pin is low.

However this is not necessarily the case when a simultaneous A&B compare occurs. If

the pin was previously low then the transfer would not happen until after the next

compare.

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CDR_AR_446 Customer Erratum MIOS1.CDR1IMB3_02_0

MIOS: Avoid 100% pulse in MDASM OPWM mode.

DESCRIPTION:

A two cycle system clock "glitch" (to logic "0") may occur when 100% output state

is entered in MDASM OPWM mode. 100% pulse is entered by writing B register bit 15

high when using less than 16 bit resolution. The problem occurs only when B

register bit 15 is set while the pin is high; the glitch occurs on the next match

will not be any glitch on the pad. The change to 100% will occur 2 cycles after the

setting of B register bit 15.Invert the polarity of the output. Then setting A=B

will cause a 100% pulse. A glitch free 0% pulse is now no longer possible.

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CDR_AR_517 Customer Erratum MIOS1.CDR1IMB3_02_0

MIOS: Read MIOS1VNR and MIOS1TCPR registers are undefined

DESCRIPTION:

A read of the MIOS1VNR and MIOS1TCPR registers will produce undefined data. All

writes to the MIOS1TCPR will be performed correctly and cause the appropriate

actions, but the values read from MIOS1TCPR will undefined.

MIOS: Use even values in MPWMSMPERR

DESCRIPTION:

In some operating conditions on some parts, the MPWMSM period may be off by one

count. The load of the MIOS MPWMSM counter LSB is not guaranteed to function

correctly over all conditions. In some cases, the MIOS MPWMSM cannot load a MPWMSM

period LSB (Least significant bit of MPWMSMPERR) as a "1" into the MPWMSM counter

(MPWMSMCNTR). The counter LSB will be incorrectly loaded as a "0". The period of

the PWMSM counter will then be one MPWMSM prescaler clock period less than

programmed. There will be no problem if MPWMSM period LSB (MPWMSMPERR_PER0) is a

Use even values in the MPWMSMPERR.

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CDR_AR_452 Customer Information MIOS1.CDR1IMB3_02_0

MIOS: "non-reset" registers are undefined after reset.

DESCRIPTION:

The specification states that many of the MIOS data registers are unaffected by

reset. This should really be "undefined" after a reset. Note that after reset all

the MIOS submodules are correctly in their idle state with the pads as inputs.

150V MM ESD issues

DESCRIPTION:

Not all ESD specifications are met when tested using machine model (MM) tests. All

specifications are met at 100V MM. Vdda pin fails at 150V MM; low level leakage is

seen on 5v output pins at 200V MM; 3v pads with keep alive power exhibit low-level

leakage at 200V MM. All pads pass Human Body Model (HBM) ESD tests at 3000V and

below.

WORKAROUND:

Avoid indicated ESD levels on these pins.

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from the external data pins, the weak pulldowns on the data pads may not fully

discharge the pins during reset. If the data pins were driven high by the MPC555

just prior to the assertion of reset, the weak pulldowns will not be able to

discharge the pins due to contention with the P-channel transistor of the output

buffer. This transistor is not fully turned off by the pre-driver stage.

WORKAROUND:

Program the internal flash to provide the reset configuration word. Or, use

external resistors/drivers to drive all of the configuration word during reset

(including bits set to 0) when providing the reset configuration word from

DESCRIPTION:

The TS_B signal, when an input (spec. 30), requires an input hold time of 5ns.

WORKAROUND:

Keep asserting TS_B for the additional hold time. In a multi-555 system, the TS_B

output hold time of one MPC555 is sufficient to meet the TS_B input hold time of

another MPC555.

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CDR_AR_479 Customer Erratum USIU.CDR1UBUS_05_1

USIU: The MEMC does not support external master burst cycles

DESCRIPTION:

The MTS function will not work properly to control external devices when an

external master initiates a burst.

WORKAROUND:

DESCRIPTION:

In slave mode, a write data driven by the Core might be corrupted by the data

driven by the external master.

WORKAROUND:

When the device is in SLAVE mode, do not use write accesses from the external

master. Alternatively, use peripheral mode if write accesses from the external

master are required.

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CDR_AR_389 Customer Information USIU.CDR1UBUS_05_1

Do not activate little endian modes.

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CDR_AR_442 Customer Information USIU.CDR1UBUS_05_1

Avoid loss of clock during HRESET

DESCRIPTION:

The chip may fail to switch to backup clock. This mode may occur if the input

reference clock fails to toggle during hreset while switching from normal clock to

backup clock. This condition may occur while switching from backup clock to normal

before switching to PLL clock. Do not enable reset upon loss of lock if limp mode

is enabled, instead enable an change of lock interrupt by setting the COLIE bit

(COLIR).

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CDR_AR_594 Customer Information USIU.CDR1UBUS_05_1

USIU: Changing PLL MF to 1:1 mode can have 180 degree phase shift

DESCRIPTION:

After software changes MF from >1 to MF = 1, a 180 degree skew between EXTCLK and

CLKOUT could occur.

WORKAROUND:

DESCRIPTION:

Future revisions of the PDMCR will have additional bits to control enabling and

disabling of pad pull-up / pull-down resistors. Software should be written so that

it is compatible with these changes. In this revision, PDMCR[8] (TPRDS) does not

change the function of the TPU T2CLK pull-up resistors -- the pull-ups remain

enabled.

WORKAROUND:

To ensure identical control in future revisions, when programming the PDMCR.

PDMCR[8] should remain cleared. PDMCR[9:13] should be programmed to the same value

as PRDS (PDMCR[6]). PDMCR[16:17] should be programmed to the same value as SPRDS

___________________________________________________________________________________

CDR_AR_598 Customer Information USIU.CDR1UBUS_05_1

USIU: Ensure proper configuration for proper startup

DESCRIPTION:

In some systems, the PLL does not lock on power-up, or the system does not properly

execute software out of reset. This issue occurs on some board designs, and not on

others. Locking may be improved by board design and component selection, and can

be resolved by paying attention to the design and setup, and ensuring that the PLL

the XFC capacitor is connected to VDDSYN. Validate that the TRST_L pin is asserted

upon power-up. Do not connect TRST_L to HRESET_L or SRESET_L. Validate that all

power supplies are stable and all MODCK pins are at the correct levels in time for

the PLL and Oscillator to be stable prior to PORESET_L rising above VIL. Verify

that the proper reset configuration word is used. Validate the reset and post reset

pin state for each pin controlled by the reset configuration word, and ensure there

is not a conflict with an external driver. Preferably use the internal reset

configuration word. If using an external reset configuration word, do not rely on

the internal pull-downs to operate (refer to CDR_AR_454) and ensure that RSTCONF is

asserted until SRESET is negated. After the part exits reset with the system

running via the backup clock, validate the clock control registers settings and the

PLL status. If the PLL is slow on locking, or the register settings indicate the