LMH1982SQX/NOPB - National Semiconductor

LMH1982

March 29, 2008

Multi-Rate Video Clock Generator with Genlock

General Description

The LMH1982 is a multi-rate video clock generator ideal for

use in a wide range of 3-Gbps (3G), high-definition (HD), and

standard-definition (SD) video applications, such as video

synchronization, serial digital interface (SDI) serializer and

deserializer (SerDes), video conversion, video editing, and

other broadcast and professional video systems.

The LMH1982 can generate two simultaneous SD and HD

clocks and a Top of Frame (TOF) pulse. In genlock mode, the

device's phase locked loops (PLLs) can synchronize the out-

put signals to H sync and V sync input signals applied to either

of the reference ports. The input reference can have analog

timing from National's LMH1981 multi-format video sync sep-

arator or digital timing from an SDI deserializer and should

conform to the major SD and HD standards. When a loss of

reference occurs, the device can default to free run operation

where the output timing accuracy will be determined by the

external bias on the free run control voltage input.

The LMH1982 can replace discrete PLLs and field-pro-

grammable gate array (FPGA) PLLs with multiple voltage

controlled crystal oscillators (VCXOs). Only one 27.0000 MHz

VCXO and loop filter are externally required for genlock

mode. The external loop filter as well as programmable PLL

parameters can provide narrow loop bandwidths to minimize

jitter transfer. HD clock output jitter as low as 40 ps peak-to-

peak can help designers using FPGA SerDes meet stringent

SDI output jitter specifications.

The LMH1982 is offered in a space-saving 5 mm x 5 mm 32-

pin LLP package and provides low total power consumption

of about 250 mW (typical).

Features

■Two simultaneous LVDS output clocks with selectable

frequencies and Hi-Z capability:

—SD clock: 27 MHz or 67.5 MHz

—HD clock: 74.25 MHz, 74.25/1.001 MHz, 148.5 MHz or

148.5/1.001 MHz

■Low-jitter output clocks may be directly connected to an

FPGA serializer to meet SMPTE SDI jitter specifications

■Top of Frame (TOF) pulse with programmable output

format timing and Hi-Z capability

■Two reference ports (A and B) with H and V sync inputs

■Supports cross-locking of input and output timing

■External loop filter allows control of loop bandwidth, jitter

transfer, and lock time characteristics

■Free run or Holdover operation on loss of reference

■User-defined free run control voltage input

■I2C interface and control registers

■3.3V and 2.5V supplies

Applications

■Video genlock and synchronization

■FPGA SDI SerDes recovered clock generation

■Triple rate 3G/HD/SD-SDI SerDes

■Video capture, conversion, editing and distribution

■Video displays and projectors

■Broadcast and professional video equipment

Typical Video Genlock Block Diagram

30052407

LMH1982 Multi-Rate Video Clock Generator with Genlock

Functional Block Diagram

30052403

Typical Loop Filter Topology

30052439

Ordering Information

Package Part Number Package Marking Transport Media NSC Drawing

32-Pin LLP

LMH1982SQ

L1982SQ

1k Units Tape and Reel

SQA32ALMH1982SQE 250 Units Tape and Reel

LMH1982SQX 4.5k Units Tape and Reel

www.national.com 2

LMH1982

Connection Diagram

30052402

Top View

32-Pin LLP

3 www.national.com

LMH1982

Pin Descriptions

Pin No. Pin Name I/O Signal Level Pin Description

–DAP –Supply Die Attach Pad (Connect to GND)

1 VC_FREERUN I Analog Free Run Control Voltage Input

2, 10, 18, 22, 26, 30 GND –Supply Ground

3, 21, 27, 28, 32 VDD –Supply 3.3V Supply 1

4 HREF_A I LVCMOS H sync Input, Reference A

5 VREF_A I LVCMOS V sync Input, Reference A

6 REF_SEL I LVCMOS Reference Select 2, 3

7 HREF_B I LVCMOS H sync Input, Reference B

8 VREF_B I LVCMOS V sync Input, Reference B

9 DVDD –Supply 2.5V Supply 4

11 SDA I/O I2C I2C Data 5

12 SCL I I2C I2C Clock 5

13 I2C_ENABLE I LVCMOS I2C Enable

14 GENLOCK I LVCMOS Mode Select 6

15 RESET I LVCMOS Device Reset

16 NO_REF O LVCMOS Reference Status Flag

17 NO_LOCK O LVCMOS Lock Status Flag

19, 20 HD_CLK, HD_CLK O LVDS HD Clock Output

23, 24 SD_CLK, SD_CLK O LVDS SD Clock Output

25 TOF O LVCMOS Top of Frame Pulse

29 VCXO I LVCMOS VCXO Clock Input

31 LPF O Analog VCXO PLL Loop Filter

Notes

1. Refer to section 2.4 Power Supply Sequencing.

2. To control reference selection via the REF_SEL pin instead of the I2C interface (default), program I2C_RSEL = 0 (register 00h).

3. To override reference control via pin 6 and instead use pin 6 as an logic input for output initialization, program PIN6_OVRD = 1 (register 02h); accordingly, the

TOF_INIT bit (register 0Ah) will be ignored and reference selection must be controlled via I2C.

4. Must be ≤ VDD +0.3V. Refer to section 2.4 Power Supply Sequencing.

5. SDA and SCL pins each require a 4.7 kΩ (typ) pull-up resistor to the VDD supply.

6. To control mode selection via the GENLOCK pin instead of the I2C interface (default), program I2C_GNLK = 0 (register 00h).

www.national.com 4

LMH1982

Table of Contents

General Description .............................................................................................................................. 1

Features .............................................................................................................................................. 1

Applications ......................................................................................................................................... 1

Typical Video Genlock Block Diagram ..................................................................................................... 1

Functional Block Diagram ...................................................................................................................... 2

Typical Loop Filter Topology .................................................................................................................. 2

Ordering Information ............................................................................................................................. 2

Connection Diagram ............................................................................................................................. 3

Pin Descriptions ................................................................................................................................... 4

Absolute Maximum Ratings .................................................................................................................... 7

Operating Ratings ................................................................................................................................ 7

Electrical Characteristics ........................................................................................................................ 7

Typical Performance Characteristics ..................................................................................................... 10

Supported Standards and Timing Formats ............................................................................................. 12

Application Information ........................................................................................................................ 13

1.0 FUNCTIONAL OVERVIEW ...................................................................................................... 13

2.0 GENERAL INFORMATION ...................................................................................................... 13

2.1 148.35 MHz PLL Initialization Sequence ............................................................................ 14

2.2 Enabling Genlock Mode ................................................................................................... 14

2.3 Output Disturbance While Output Alignment Mode Enabled .................................................. 14

2.4 Power Supply Sequencing ............................................................................................... 14

2.5 Evaluating the LMH1982 .................................................................................................. 14

3.0 MODES OF OPERATION ....................................................................................................... 14

3.1 Free Run Mode ............................................................................................................... 14

3.2 Genlock Mode ................................................................................................................ 14

3.2.1 Genlock Mode State Diagram ................................................................................. 15

3.2.2 Loss of Reference (LOR) ................................................................................ 15

3.2.2.1 Free Run during LOR ........................................................................... 15

3.2.2.2 Holdover during LOR ............................................................................ 15

4.0 INPUT REFERENCE .............................................................................................................. 15

4.1 Programming the PLL 1 Dividers ....................................................................................... 16

4.2 Reference Frame Decoder ............................................................................................... 16

5.0 OUTPUT CLOCKS AND TOF .................................................................................................. 16

5.1 Programming The Output Clock Frequencies ...................................................................... 16

5.2 Programming The Output Format Timing ............................................................................ 17

5.2.1 Output TOF Clock ................................................................................................. 19

5.2.2 Output Frame Timing ............................................................................................. 19

5.2.2.1 HD Format TOF Generation using a 27 MHz TOF Clock ................................... 19

5.2.3 Reference Frame Timing ........................................................................................ 19

5.2.4 Input-Output Frame Rate Ratio ............................................................................... 20

5.2.5 Output Frame Line Offset ....................................................................................... 20

5.3 Programming The Output Initialization Sequence ................................................................ 20

5.3.1 TOF Output Delay Considerations ........................................................................... 20

5.3.2 Output Clock Initialization without TOF ..................................................................... 20

5.4 Output Behavior Upon Loss Of Reference .......................................................................... 20

6.0 REFERENCE AND PLL LOCK STATUS ................................................................................... 21

6.1 Reference Detection ........................................................................................................ 21

6.1.1 Programming the Loss of Reference (LOR) Threshold ............................................... 21

6.2 PLL Lock Detection ......................................................................................................... 21

6.2.1 Programming the PLL Lock Threshold ..................................................................... 21

6.2.2 PLL Lock Status Instability ...................................................................................... 21

TABLE 7. Summary of Genlock Status Bits and Flag Outputs ..................................................... 22

7.0 LOOP RESPONSE ................................................................................................................ 22

7.1 Loop Response Design Equations ..................................................................................... 22

7.1.1 Loop Response Optimization Tips ........................................................................... 23

7.1.2 Loop Filter Capacitors ............................................................................................ 23

7.2 Lock Time Considerations ................................................................................................ 23

7.3 VCXO Considerations ...................................................................................................... 23

7.4 Free Run Output Jitter ..................................................................................................... 23

8.0 I2C INTERFACE PROTOCOL .................................................................................................. 23

8.1 Write Sequence .............................................................................................................. 23

8.2 Read Sequence .............................................................................................................. 24

8.3 I2C Enable Control Pin .................................................................................................... 24

9.0 I2C INTERFACE CONTROL REGISTER DEFINITIONS .............................................................. 25

5 www.national.com

LMH1982

9.1 Genlock And Input Reference Control Registers .................................................................. 26

9.2 Genlock Status And Lock Control Register ......................................................................... 26

9.3 Input Control Register ...................................................................................................... 26

9.4 PLL 1 Divider Register ..................................................................................................... 27

9.5 PLL 4 Charge Pump Current Control Register ..................................................................... 27

9.6 Output Clock And TOF Control Register ............................................................................. 27

9.7 TOF Configuration Registers ............................................................................................ 27

9.8 PLL 1, 2, 3 Charge Pump Current Control Registers ............................................................ 28

9.10 Reserved Registers ....................................................................................................... 29

10.0 TYPICAL SYSTEM BLOCK DIAGRAMS .................................................................................. 30

Physical Dimensions ........................................................................................................................... 32

www.national.com 6

LMH1982

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

ESD Tolerance (Note 2)

Human Body Model 2000V

Machine Model 200V

Supply Voltage, VDD 3.6V

Supply Voltage, DVDD 2.75V

DVDD ≤ VDD +0.3V

Input Voltage Range (any input) −0.3V to VDD +0.3V

Storage Temperature Range −65°C to +150°C

Lead Temperature (Soldering 10 sec.) 300°C

Junction Temperature, TJMAX 150°C

Thermal Resistance (θJA)33°C/W

Operating Ratings

VDD 3.3V ± 5%

DVDD 2.5V ± 5%

Input Voltage 0V to VDD

Temperature Range, TA0°C to 70°C

Electrical Characteristics

Unless otherwise specified, all limits are guaranteed for TA = 25°C, VDD = 3.3V, DVDD = 2.5V, Boldface limits apply at the tem-

perature extremes.

Symbol Parameter Conditions Min

(Note 6)

Typ

(Note 5)

Max

(Note 6)

Units

IVDD VDD Supply Current Default register settings, no input reference,

27 MHz VCXO and loop filter connected,

100Ω differential load on SD_CLK and

HD_CLK outputs; no load on all other outputs

47 mA

IDVDD DVDD Supply Current 39 mA

IVDD VDD Supply Current VDD = 3.465V, DVDD = 2.75V, Genlock mode,

1080p/59 output timing, HD_CLK = 148.35

MHz, SD_CLK = 67.5 MHz, 100Ω differential

load on SD_CLK and HD_CLK outputs; no

load on all other outputs

57 70 mA

IDVDD DVDD Supply Current 44 60 mA

Free Run Voltage Control Input (Pin 1)

VIL Low Analog Input Voltage (Note 7) 0 V

VIH High Analog Input Voltage (Note 7) VDD V

Reference Inputs (Pins 4, 5, 7, 8)

VIL Low Input Voltage IIN = ±10 μA0 0.3 VDD V

VIH High Input Voltage IIN = ±10 µA 0.7 VDD VDD V

ΔTHV H-V Sync Timing Offset Input timing offset measured from H sync to V

sync pulse leading edges (Note 8)

2.0 μs

Digital Control Inputs (Pins 6, 13, 14, 15)

VIL Low Input Voltage IIN = ±10 µA 0 0.3 VDD V

VIH High Input Voltage IIN = ±10 µA 0.7 VDD VDD V

I2C Interface (Pins 11, 12)

VIL Low Input Voltage 0 0.3 VDD V

VIH High Input Voltage 0.7 VDD VDD V

IIN Input Current VIN between 0.1 VDD and 0.9 VDD −10 +10 μA

IOL Low Output Sink Current VOL = 0V or 0.4V 3 mA

Status Flag Outputs (Pin 16, 17)

VOL Low Output Voltage IOUT = +10 mA 0.4 V

VOH High Output Voltage IOUT = −10 mA VDD

−0.4V

Top of Frame Output (Pin 25)

VOL Low Output Voltage IOUT = +10 mA 0.4 V

VOH High Output Voltage IOUT = −10 mA VDD

−0.4V

7 www.national.com

LMH1982

Symbol Parameter Conditions Min

(Note 6)

Typ

(Note 5)

Max

(Note 6)

Units

IOZ Output Hi-Z Leakage Current TOF output in Hi-Z mode, output pin

connected to VDD or GND

0.4 10 |μA|

tRRise Time 15 pF load 1.5 ns

tFFall Time 15 pF load 1.5 ns

tD_TOF TOF Output Delay Time (Note

Specified for any SD or HD format generated

from 27 MHz TOF clock (Note 10), outputs

initialized (Note 11), 15 pF load

2 ns

Clock Outputs (Pins 19, 20, 23, 24)

JitterSD 27 MHz TIE Peak-to-Peak

Output Jitter (Note 12)

HD_CLK = Hi-Z 23 ps

HD_CLK = 74.176 MHz 40 ps

67.5 MHz TIE Peak-to-Peak

Output Jitter (Note 12)

HD_CLK = Hi-Z 40 ps

HD_CLK = 74.176 MHz 50 ps

JitterHD 74.176 MHz TIE Peak-to-Peak

Output Jitter (Note 12)

SD_CLK = Hi-Z 55 ps

SD_CLK = 27 MHz 65 ps

74.25 MHz TIE Peak-to-Peak

Output Jitter (Note 12)

SD_CLK = Hi-Z 40 ps

SD_CLK = 27 MHz 50 ps

148.35 MHz TIE Peak-to-Peak

Output Jitter (Note 12)

SD_CLK = Hi-Z 60 ps

SD_CLK = 27 MHz 70 ps

148.5 MHz TIE Peak-to-Peak

Output Jitter (Note 12)

SD_CLK = Hi-Z 45 ps

SD_CLK = 27 MHz 55 ps

tD_SD 27 MHz Output Delay Time

(Note 13)

SD_CLK = 27 MHz, Any valid output timing,

outputs initialized (Note 11)

4 ns

67.5 MHz Output Delay Time

(Note 13)

SD_CLK = 67.5 MHz, 525i output timing (Note

10), outputs initialized (Note 11)

6 ns

tD_HD 74.176 MHz Output Delay Time

(Note 14)

HD_CLK = 74.176 MHz, 1080i/59 output

timing (Note 10), outputs initialized (Note 11)

4.5 ns

74.25 MHz Output Delay Time

(Note 14)

HD_CLK = 74.25 MHz, 1080i/50 output timing

(Note 10), outputs initialized (Note 11)

-0.6 ns

148.35 MHz Output Delay Time

(Note 14)

HD_CLK = 148.35 MHz, 1080p/59 output

timing (Note 10), outputs initialized (Note 11)

1.5 ns

148.5 MHz Output Delay Time

(Note 14)

HD_CLK = 148.5 MHz, 1080p/50 output timing

(Note 10), outputs initialized (Note 11)

4.5 ns

VOD Differential Signal Output

Voltage (Note 15)

100Ω differential load 247 350 454 mV

VOS Common Signal Output Voltage

(Note 15)

100Ω differential load 1.125 1.250 1.375 V

|VOD| |Change to VOD| for

Complementary Output States

(Note 15)

100Ω differential load 50 |mV|

|VOS| |Change to VOS| for

Complementary Output States

(Note 15)

100Ω differential load 50 |mV|

IOS Output Short Circuit Current Differential clock output pins connected to

GND

24 |mA|

IOZ Output Hi-Z Leakage Current Output clock in Hi-Z mode, differential clock

output pins connected to VDD or GND

1 10 |µA|

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the

device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)

Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).

Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) –

TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.

www.national.com 8

LMH1982

Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. No guarantee of parametric performance is indicated in the

electrical tables under conditions different than those tested.

Note 5: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will

also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.

Note 6: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality

Control (SQC) methods.

Note 7: The input voltage to VC_FREERUN (pin 1) should also be within the input range of the external VCXO. The input voltage should be clean from noise

that may significantly modulate the VCXO control voltage and consequently produce output jitter during free run operation.

Note 8: ΔTHV is a required specification that allows for proper frame decoding and subsequent output initialization (alignment). For interlace formats, the H-V

sync timing offset must be within ΔTHV for all even fields and be outside ΔTHV for odd fields. For progressive formats, the H-V sync timing offset must be within

ΔTHV for all frames. See sections 4.2 Reference Frame Decoder and 5.2.5 Output Frame Line Offset.

Note 9: tD_TOF is measured from the TOF pulse (leading negative edge) to the 27 MHz SD_CLK output (positive edge) using 50% levels.

Note 10: For any SD and HD output formats, the TOF pulse can be generated using 27 MHz as the TOF clock by programming TOF_CLK = 0, SD_FREQ = 0,

and the alternative output counter values shown in Table 1. See section 5.2.2.1 HD Format TOF Generation using a 27 MHz TOF Clock.

Note 11: Output initialization refers to the initial alignment of the output frame clock and TOF signals to the input reference frame. See section 5.3 Programming

The Output Initialization Sequence.

Note 12: The SD and HD clock output jitter is based on VCXO clock (pin 29) with 20 ps peak-to-peak using a time interval error (TIE) jitter measurement. The

typical TIE peak-to-peak jitter was measured on the LMH1982 evaluation bench board using TDSJIT3 jitter analysis software on a Tektronix DSA70604

oscilloscope and 1 GHz active differential probe.

TDSJIT3 Clock TIE Measurement Setup: 10-12 bit error rate (BER), >1 Meg samples recorded using multiple acquisitions

Oscilloscope Setup: 20 mV/div vertical scale, 100 µs/div horizontal scale, and 25 GS/s sampling rate

Note 13: tD_SD is measured from the VCXO clock input (pin 29) to the SD_CLK output (pins 23, 24) using positive edges and 50% levels. The measurement is

taken at the leading edge of the TOF pulse (Note 10), where the input and output clocks are phase aligned at the start of frame.

Note 14: tD_HD is measured from the VCXO clock input (pin 29) to the HD_CLK output (pins 19, 20) using positive edges and 50% levels. The measurement is

taken at the leading edge of the TOF pulse (Note 10), where the input and output clocks are phase aligned at the start of frame.

Note 15: This parameter is specified for the SD_CLK output only. This parameter is guaranteed by design for the HD_CLK output.

9 www.national.com

LMH1982

Typical Performance Characteristics

Test conditions: VDD = 3.3V, DVDD = 2.5V, Genlock mode, outputs initialized. H sync and V sync signals to REF_A inputs are from

the LMH1981 sync separator, which receives an analog video reference signal from a Tektronix TG700 AVG7/AWVG7 (SD/HD)

video signal generator. See Note section below for register settings (in decimal):

NTSC TOF Pulse (Note 16)

30052433

PAL TOF Pulse (Note 17)

30052434

1080i/50 TOF Pulse (Note 18)

30052435

1080p/24 TOF Pulse (Note 19)

30052432

www.national.com 10

LMH1982

525i TOF Output Delay Using 27 MHz TOF Clock

30052431

1080i/50 TOF Output Delay Using 74.25 MHz TOF Clock

30052430

Note 16: GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 1716, SD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 1716, TOF_LPFM = 525, REF_LPFM = 525, TOF_OFFSET

= 262; all other register settings are default

Note 17: GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 1728, SD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 1728, TOF_LPFM = 625, REF_LPFM = 625, TOF_OFFSET

= 312; all other register settings are default

Note 18: GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 960, SD_FREQ = 0, HD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 960, TOF_LPFM = 1125, REF_LPFM = 1125,

TOF_OFFSET = 562; all other register settings are default

Note 19: GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 1000, SD_FREQ = 0, HD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 1000, TOF_LPFM = 1125, REF_LPFM =

1125, TOF_OFFSET = 1124; all other register settings are default

11 www.national.com

LMH1982

Supported Standards and Timing Formats

Table 1 lists the known supported standard timing formats and includes the relevant parameters that can be used to configure the

LMH1982 for the input reference and output timing. For the related programming instructions, see sections 4.0 INPUT REFER-

ENCE and 5.0 OUTPUT CLOCKS AND TOF.

Note 20: For some input reference formats, an alternative set of values for PLL 1 dividers and total lines per frame (REF_LPFM) is also shown in brackets

“[ ]”. This alternative set of values may be programmed if a lower PLL 1 phase comparison frequency is desired. The corresponding counter values for REF_LPFM

needs to be programmed for proper reference frame and output timing generation. See section 5.2.3 Reference Frame Timing.

Note 21: For any output HD format, an alternative set of counter values for total clocks per line (TOF_PPL) and total lines per frame (TOF_LPFM) is shown in

parenthesis “( )”. This alternative set of values can be programmed to generate any HD format TOF pulse using the 27 MHz SD_CLK instead of using the native

74.xx or 148.xx MHz HD_CLK. See section 5.2.2.1 HD Format TOF Generation using a 27 MHz TOF Clock.

TABLE 1. Input Reference and Output Timing Parameters

Format

INPUT TIMING PARAMETERS

(Note 20)

OUTPUT TIMING PARAMETERS

(Note 21)

PLL 1

Reference

Divider1

PLL 1

Feedback

Divider

PLL 1 Phase

Comparison

Frequency

(kHz)

Total Lines

per Frame

Counter

Clock

Frequency

(MHz)

Total Clocks

per Line

Counter

Total Lines

per Frame

Counter

Frame

Rate

(Hz)

NTSC, 525i 1 1716 15.7343 525 27.0 1716 525 29.97

PAL, 625i 1 1728 15.625 625 27.0 1728 625 25

525p 1

[5]

858

[4290]

31.4685

[6.2937]

525

[105] 27.0 858 525 59.94

625p 1

[5]

864

[4320]

31.25

[6.25]

625

[125] 27.0 864 625 50

720p/60 1

[5]

600

[3000]

45.0

[9.0]

750

[150]

74.25

(27.0)

1650

(600)

750

(750) 60

720p/59.94 5 3003 8991.0090 750 74.176

(27.0)

1650

(3003)

750

(150) 59.94

720p/50 1

[5]

720

[3600]

37.5

[7.5]

750

[150]

74.25

(27.0)

1980

(720)

750

(750) 50

720p/30 1

[5]

1200

[6000]

22.5

[4.5]

750

[150]

74.25

(27.0)

3300

(1200)

750

(150) 30

720p/29.97 5 6006 4.4955 750 74.176

(27.0)

3300

(6006)

750

(150) 29.97

720p/25 1

[5]

1440

[7200]

18.75

[3.75]

750

[150]

74.25

(27.0)

3960

(1440)

750

(750) 25

720p/24 1

[5]

1500

[7500]

18.0

[3.6]

750

[150]

74.25

(27.0)

4125

(1500)

750

(750) 24

720p/23.98 2 3003 8991.0090 750 74.176

(27.0)

4125

(3003)

750

(375) 23.98

1080p/60 1

[5]

400

[2000]

67.5

[13.5]

1125

[225]

148.5

(27.0)

2200

(400)

1125

(1125) 60

1080p/59.94 5 2002 13.4865 1125 148.35

(27.0)

2200

(2002)

1125

(225) 59.94

1080p/50 1

[5]

480

[2400]

56.25

[11.25]

1125

[225]

148.5

(27.0)

2640

(480)

1125

(1125) 50

1080p/30 1

[5]

800

[4000]

33.75

[6.75]

1125

[225]

74.25

(27.0)

2200

(800)

1125

(1125) 30

1080p/29.97 5 4004 6.7433 1125 74.176

(27)

2200

(4004)

1125

(225) 29.97

1080p/25 1

[5]

960

[4800]

28.125

[5.625]

1125

[225]

74.25

(27.0)

2640

(960)

1125

(1125) 25

1080p/24 1

[5]

1000

[5000]

27.0

[5.4]

1125

[225]

74.25

(27.0)

2750

(1000)

1125

(1125) 24

1080p/23.98 1

[5]

1001

[5005]

26.9730

[5.3946]

1125

[225]

74.176

(27.0)

2750

(1001)

1125

(1125) 23.98

www.national.com 12

LMH1982

Format

INPUT TIMING PARAMETERS

(Note 20)

OUTPUT TIMING PARAMETERS

(Note 21)

PLL 1

Reference

Divider1

PLL 1

Feedback

Divider

PLL 1 Phase

Comparison

Frequency

(kHz)

Total Lines

per Frame

Counter

Clock

Frequency

(MHz)

Total Clocks

per Line

Counter

Total Lines

per Frame

Counter

Frame

Rate

(Hz)

1080i/60 1

[5]

800

[4000]

33.75

[6.75]

1125

[225]

74.25

(27.0)

2200

(800)

1125

(1125) 30

1080i/59.94 5 4004 6.7433 1125 74.176

(27.0)

2200

(4004)

1125

(225) 29.97

1080i/50 1

[5]

960

[4800]

28.125

[5.625]

1125

[225]

74.25

(27.0)

2640

(960)

1125

(1125) 25

48 kHz AES

sample clock 2 1125 24.0 96 27.0 1125 96 250

1. The PLL 1 reference divider value is not the same as the programming value for REF_DIV_SEL. See Table 3.

Application Information

1.0 FUNCTIONAL OVERVIEW

The LMH1982 is an analog phase locked loop (PLL) clock

generator that can output simultaneous SD and HD video

clocks synchronized or “genlocked” to H sync and V sync in-

put reference timing. The LMH1982 features an output Top of

Frame (TOF) pulse generator with programmable timing that

can also be synchronized to the reference frame. Two refer-

ence ports are provided to allow a secondary input to be

selected.

The clock generator uses a two-stage PLL architecture. The

first stage is a VCXO-based PLL (PLL 1) that requires an ex-

ternal 27 MHz VCXO and loop filter. In Genlock mode, PLL 1

can phase lock the VCXO clock to the input reference after

programming the PLL divider ratio. The use of a VCXO pro-

vides a low phase noise clock source even when the

LMH1982 is configured with a low loop bandwidth, which is

necessary to attenuate input timing jitter for minimum jitter

transfer. The combination of the external VCXO, external loop

filter, and programmable PLL parameters can provide flexi-

bility for the system designer to optimize the loop bandwidth

and loop response for the application.

The second stage consists of three PLLs (PLL 2, 3, 4) with

integrated VCOs and loop filters. These PLLs will attempt to

continually track the reference VCXO clock phase from

PLL 1 regardless of the device mode. The second stage PLLs

have pre-configured divider ratios to provide frequency mul-

tiplication or translation from the VCXO clock frequency. The

VCO PLLs use a high loop bandwidth to assure PLL stability,

so the VCXO must provide a stable low-jitter clock reference

to ensure optimal output jitter performance.

Any unused clock output can be put in Hi-Z mode, which can

be useful for reducing power dissipation as well as reducing

jitter or phase noise on the active clock output.

The TOF pulse can be programmed to indicate the start (top)

of frame and even provide format cross-locking. The output

format registers should be programmed to specify the output

timing (output clocks and TOF pulse), the output timing offset

relative to the reference, and the output initialization (align-

ment) to the reference frame. If unused, the TOF output can

also be put in Hi-Z mode.

When a loss of reference occurs during genlock, PLL 1 can

default to either Free run or Holdover operation. When free

run is selected, the output frequency accuracy will be deter-

mined by the external bias on the free run control voltage input

pin, VC_FREERUN. When Holdover is selected, the loop filter

can hold the control voltage to maintain short-term output

phase accuracy for a brief period in order to allow the appli-

cation to select the secondary input reference and re-lock the

outputs. These options in combination with proper PLL 1 loop

response design can provide flexibility to manage output

clock behavior during loss and re-acquisition of the reference.

The reference status and PLL lock status flags can provide

real-time status indication to the application system. The loss

of reference and lock detection thresholds can also be con-

figured.

TABLE 2. LMH1982 PLL and Clock Summary

PLL Input Reference Divider Ratio (reduced) Output Clock

Frequency (MHz)

Output Port

PLL 1 H sync Programmable 27 SD_CLK

PLL 2 VCXO clock 11/4 or 11/2 74.25 or 148.5 HD_CLK

PLL 3 VCXO clock 250/91 or 500/91

74.25/1.001 (74.176) or

148.5/1.001 (148.35) HD_CLK

PLL 4 VCXO clock 5/2 67.5 SD_CLK

2.0 GENERAL INFORMATION

For normal operation, the RESET pin must be set high; oth-

erwise, the device cannot be programmed and will not func-

tion properly. To reset the control registers to their default

values, toggle RESET low for at least 10 µs and then set high.

The LMH1982 can be configured by programming the control

registers via the I2C interface. The I2C slave addresses are

DCh for write sequences and DDh for read sequences. The

I2C_ENABLE pin must be set low or tied to GND to allow I2C

communication; otherwise, the LMH1982 will not acknowl-

edge read/write sequences.

13 www.national.com

LMH1982

For I2C interface control register map and definitions, refer to

section 9.0 I2C INTERFACE CONTROL REGISTER DEFINI-

TIONS.

2.1 148.35 MHz PLL Initialization Sequence

The following programming sequence is required to initialize

PLL 3 and generate a correct 148.35 MHz output once it is

selected as the HD_CLK; otherwise, the clock may have duty

cycle errors, frequency errors, and/or high jitter. This PLL ini-

tialization sequence must be programmed after switching

from another HD clock frequency or Hi-Z mode, as well as

after a device reset or power cycle condition. Each program-

ming step below represents a separate write sequence.

1. Program HD_FREQ = 11b and HD_HIZ = 0 (register 08h)

to select 148.35 MHz and enable the HD_CLK output.

2. Program a value of 1 to the following register parameters

(a single write sequence is valid for this step):

—FB_DIV = 1 (register 04h-05h)

—TOF_RST = 1 (register 09h-0Ah)

—REF_LPFM = 1 (register 0Fh-10h)

—EN_TOF_RST = 1 (register 0Ah)

3. Wait at least 2 cycles of the 27 MHz VCXO clock, then

program EN_TOF_RST = 0.

After this sequence is completed, the 148.35 MHz clock will

operate correctly and normal device configuration can re-

sume. All other output clocks do not require this initialization

sequence for proper clock operation.

2.2 Enabling Genlock Mode

Upon device power up or reset, the default mode of operation

is Free Run mode. To enable Genlock mode, set GNLK = 1

(register 00h). Refer to section 3.2 Genlock Mode.

2.3 Output Disturbance While Output Alignment Mode

Enabled

When the output alignment mode is enabled (EN_TOF_RST

= 1) for a longer period than is required by the output initial-

ization sequence, the output signals can be abruptly phase-

aligned to the reference on every output frame. Continual

alignment can cause excessive phase “jumps” or jitter on the

output clock edge coinciding with the TOF pulse; this effect is

unavoidable and can be caused by slight differences in the

internal counter reset timing for the TOF generation and also

large input jitter. The characteristic of the output jitter can also

vary in severity from process variation, part variation, and the

selected clock reference frequency. This output jitter can only

be inhibited by setting EN_TOF_RST = 0 immediately follow-

ing the output initialization and before the subsequent output

frame.

2.4 Power Supply Sequencing

The VDD (3.3V) and DVDD (2.5V) power supply pins are iso-

lated by internal ESD structures that may become forward

biased when DVDD is higher than VDD. Exposure to this con-

dition, when prolonged and excessive, can trigger latch-up

and/or reduce the reliability of the device. Therefore, the

LMH1982 has a recommended power supply sequence.

On device power-up, the VDD supply must be brought up be-

fore the DVDD supply. On power-down, the DVDD supply must

be brought down before the VDD supply. The starting points

and ramp rates of the supplies should be considered to de-

termine the relative timing of the power-up and power-down

sequences such that DVDD does not exceed VDD +0.3V as

shown in the Absolute Maximum Ratings.

To minimize the potential for latch-up, a Schottky diode can

be externally connected between the DVDD supply (anode)

and VDD supply (cathode). If DVDD is brought up first, the

Schottky will ensure that VDD is within about 0.3V of DVDD until

VDD is brought up.

Additionally, the device input pins (except for SDA and SCL

inputs) should not be driven prior to power-up due to the same

reasons provided above for the power pins. Otherwise, a

small series resistor should be used on each input pin to pro-

tect the device by limiting the current whenever the internal

ESD structures become forward biased.

Once both supplies are powered up in the proper sequence,

the device has a power on reset sequence that will reset all

registers to their default values.

2.5 Evaluating the LMH1982

For information about SDI jitter performance using the

LMH1982 with the LMH1981 sync separator, please refer to

the following application notes:

•AN-1893: Demonstrating SMPTE-compliant SDI Output

Jitter using the LMH1982 and Virtex-5 GTP Transmitter

•AN-1841: LMH1982 Evaluation Board User Guide

The LMH1982SQEEVAL Evaluation Board can be ordered

from National Semiconductor's website.

3.0 MODES OF OPERATION

The mode of operation describes the operation of PLL 1,

which can operate in either Free Run mode or Genlock mode

depending on the GNLK bit setting. If desired, the GEN-

LOCK input pin can be instead used to control the mode of

operation by initially setting I2C_GNLK = 0 (register 00h).

3.1 Free Run Mode

The LMH1982 will enter Free Run mode when GNLK is set to

0. In Free Run mode, the VCXO will be free-running and in-

dependent of the input reference, and the output clocks will

maintain phase lock to the VCXO clock reference. Therefore,

the output clocks will have the same accuracy as the VCXO

clock reference.

The LMH1982 provides the designer with the option to define

the VCXO's free run control voltage by external biasing of the

VC_FREERUN input (pin 1). The analog bias voltage applied

to the VC_FREERUN input will be connected to the LPF out-

put (pin 31) though an internal switch (non-buffered, low

impedance), as shown in the Functional Block Diagram. The

resultant voltage at the LPF output will drive the control input

of the VCXO to set its free run output frequency. Thus, the

pull range of the VCXO imparts the same pull range on the

free run output clocks.

If VC_FREERUN is left floating, the VCXO control voltage will

be pulled to GND potential as the residual charge stored

across the loop filter will discharge through any existing leak-

age path.

3.2 Genlock Mode

The LMH1982 will enter Genlock mode when GNLK is set to

1. In Genlock mode, PLL 1 can be phase locked to the refer-

ence H sync input of the selected port; once the VCXO clock

reference is locked and stable, the output clocks and TOF

pulse can be aligned and phase locked to the reference. The

LMH1982 supports cross-locking, which allows the outputs to

be frame-locked to a reference format that is different from

the output format.

To genlock the outputs, the following programming sequence

is suggested:

www.national.com 14

LMH1982

1. Program the output clock frequency for the desired

output format. Refer to section 5.1 Programming The

Output Clock Frequencies.

2. Program the output TOF timing for the desired output

format. Refer to section 5.2 Programming The Output

Format Timing. It is required to complete this step for

proper output clock initialization (alignment) even if the

TOF pulse is not required.

3. Program the PLL 1 divider registers for the input

reference format. Refer to section 4.1 Programming the

PLL 1 Dividers.

4. Program GNLK = 1 to enable Genlock mode. See Note

below.

5. Program the output initialization to the desired reference

frame. Refer to section 5.3 Programming The Output

Initialization Sequence.

Note: When Genlock mode is enabled, the LMH1982 will attempt to phase

lock the PLLs to the input reference regardless of input timing stability.

Timing errors or instability on the inputs will cause the PLLs and out-

puts to also have instability. If output stability is a consideration during

periods of input uncertainty, it is suggested to gate off the input signals

from the LMH1982 until they are completely stable. Input signal gating

can be achieved externally using a discrete or FPGA logic buffer with

Hi-Z (tri-state) output and a pull-up or pull-down resistor, depending

on the input pulse signal polarity.

3.2.1 Genlock Mode State Diagram

Figure 1 shows the Genlock mode state diagram for different

input reference and PLL lock conditions. It also includes Free

Run and Holdover states for the loss of reference operation,

specified by the HOLDOVER bit (register 00h). Each state

indicates the NO_REF and NO_LOCK status flag output con-

ditions.

30052436

FIGURE 1. Genlock Mode State Diagram

3.2.2 Loss of Reference (LOR)

By configuring the HOLDOVER bit, the LMH1982 can default

to either Free Run or Holdover operation when a loss of ref-

erence (LOR) occurs in Genlock mode.

If HOLDOVER = 0 when a LOR occurs, the LMH1982 will

default to Free run operation (section 3.2.2.1 Free Run during

LOR) until a reference is reapplied.

If HOLDOVER = 1 when a LOR occurs, the LMH1982 will

default to Holdover operation (section 3.2.2.2 Holdover during

LOR) until a reference is reapplied.

When the input reference is reapplied, the LMH1982 will im-

mediately attempt to phase lock the output clocks to the

reference.

3.2.2.1 Free Run during LOR

Free Run mode (GNLK = 0) differs from Free Run operation

due to LOR in Genlock mode (GNLK = 1) in the following way:

•In Free Run mode, the outputs will free run regardless of

the presence or loss of reference.

•In Genlock mode, the outputs will free run only during

LOR; once a reference is present, free run operation will

cease as the PLLs will immediately attempt to phase lock

the output clocks to the reference.

3.2.2.2 Holdover during LOR

In Holdover operation, the LPF output is put into high

impedance mode, which allows the loop filter to temporarily

hold the residual charge stored across it (i.e. the control volt-

age) immediately after LOR is indicated by the NO_REF

status flag. Holdover operation can help to temporarily sustain

the output clock accuracy upon LOR. The duration that the

residual control voltage level can be sustained within a toler-

able level depends primarily on the charge leakage on the

loop filter. A typical VCXO has an input impedance of several

tens of kΩ, which will be the dominant leakage path seen by

the loop filter. As the leakage current discharges the residual

control voltage to GND, the output frequencies of the VCXO

and LMH1982 will drift accordingly. If a longer time constant

is required, a precision op amp with low input bias current and

rail-to-rail input and output (e.g. LMP7701) can be used to

buffer the control voltage. The buffer will isolate the relatively

low input impedance of the VCXO and reduce the charge

leakage on the loop filter during Holdover.

The output frequency accuracy will degrade as the VCXO ac-

curacy drifts with the decaying control voltage. Moreover,

because the H_ERROR setting (register 00h) affects the ref-

erence error threshold for LOR indication, a higher setting for

H_ERROR may result in reduced output accuracy upon LOR

indication compared to when H_ERROR = 0. For more infor-

mation on programming H_ERROR, see section 6.1.1 Pro-

gramming the Loss of Reference (LOR) Threshold.

30052411

FIGURE 2. Loop Filter with Optional Op Amp to Isolate

VCXO's Low Input Impedance

4.0 INPUT REFERENCE

The LMH1982 features two reference ports (A and B) with H

sync and V sync inputs which are used for phase locking the

outputs in Genlock mode. The reference port can be selected

by programming RSEL (register 00h). If desired, REF_SEL

15 www.national.com

LMH1982

input can be used instead to select the reference port by ini-

tially setting I2C_RSEL = 0 (register 00h).

The reference signals should be 3.3V LVCMOS signals within

the input voltage range specified in the Electrical Character-

istics table. The H sync and V sync input signals may have

analog timing, such as from the LMH1981 multi-format analog

video sync separator, or digital timing, such as from an FPGA

SDI deserializer.

4.1 Programming the PLL 1 Dividers

To genlock the outputs to the reference, it is necessary to

phase lock the VCXO clock (PLL 1) to the H sync input signal

by programming the PLL dividers. The PLL divider values for

each supported input reference format are given in Table 1.

The divider values can be determined by reducing the follow-

ing ratio to its lowest integer factors:

fVCXO / fHSYNC = Feedback Divider / Reference Divider

Where:

fVCXO = 27 MHz VCXO frequency

fHSYNC = H sync input frequency

Feedback Divider = 1 to 8191 (0 is invalid)

Reference Divider = 1, 2 or 5

Table 3 shows the selection table with compatible PLL 1 ref-

erence divider values to program REF_DIV_SEL (register

03h). The PLL 1 feedback divider value can be directly pro-

grammed to FB_DIV (register 04h-05h).

TABLE 3. PLL 1 Reference Divider Selection

REF_DIV_SEL

Reference Divider

0h 2

1h 1

2h 5

Some supported input formats in Table 1 have two sets of

compatible divider values: reduced dividers and non-reduced

dividers. See Examples 2A and 2B below. Because the loop

response of PLL 1 is dependent on the feedback divider val-

ue, a lower loop bandwidth and phase comparison frequency

can be achieved by programming the non-reduced divider set

(see 7.0 LOOP RESPONSE ).

Examples:

1) For 1080i/59.94 input reference, the dividers are:

•Reference divider = 5 (REF_DIV_SEL = 2h)

•Feedback divider = 4004 (FB_DIV = FA4h)

2A) For 1080i/50 input reference, the reduced dividers are:

•Reference divider = 1 (REF_DIV_SEL = 1h)

•Feedback divider = 960 (FB_DIV = 3C0h)

2B) For 1080i/50 input reference, the non-reduced (alterna-

tive) dividers are:

•Reference divider = 5 (REF_DIV_SEL = 2h)

•Feedback divider = 4800 (FB_DIV = 12C0h)

4.2 Reference Frame Decoder

The LMH1982 features an internal frame decoder to deter-

mine the reference frame timing from only the H and V sync

input timing, which eliminates an extra input pin for an odd/

even field timing. The reference frame timing is required to

allow for output frame initialization (output TOF and clock

alignment) to the reference frame.

To allow for proper frame decoding and subsequent output

initialization, the H sync and V sync inputs must comply with

the H-V sync timing offset specification, ΔTHV. For interlace

formats, the H-V sync timing offset must be within ΔTHV for

even fields and be outside ΔTHV for odd fields. Compliance

with this specification will ensure the internal frame counters

are reset only once per frame. For progressive formats, the

H-V timing offset must be within ΔTHV for all frames.

Since the LMH1982 was designed for compatibility with the

LMH1981 sync separator, its H and V sync pulses will comply

with the ΔTHV specification for any input reference format.

For digital timing from an FPGA SDI deserializer, the recov-

ered H and V sync pulses may be co-timed and be within

ΔTHV for both odd and even fields. This will cause the internal

frame counters to reset twice per frame and thus preclude

proper frame decoding and output initialization. As a simple

work-around, the designer may choose to configure the FP-

GA to gate the V sync signal, allowing only the even field

V pulses and gating off the odd field V pulses.

5.0 OUTPUT CLOCKS AND TOF

The LMH1982 has simultaneous LVDS output SD and HD

clocks and an output TOF pulse. For proper output format

timing generation and subsequent output initialization, it is

highly recommended to follow the programming sequence

below:

1. Program the output clock frequencies (section 5.1

Programming The Output Clock Frequencies).

2. Program the output format timing (section 5.2.2 Output

Frame Timing).

3. Program the output initialization sequence (section 5.3

Programming The Output Initialization Sequence).

5.1 Programming The Output Clock Frequencies

The SD clock frequency can be selected from Table 4 and

programmed to SD_FREQ (register 08h). PLL 1 and PLL 4

are used to generate the two SD clock rates but only one SD

clock can be selected at a time. If the SD_CLK output is not

needed, it can be put in Hi-Z mode by setting SD_HIZ = 1

(register 08h).

If 27 MHz is selected, the VCXO clock is directly converted

from a 3.3V single-ended clock at the VCXO input (pin 29) to

an LVDS clock at the SD_CLK output port (pins 23 and 24).

If 67.5 MHz is selected, the VCXO clock is used as an input

reference for PLL 4 to generate this SD clock frequency. In

some FPGA SD-SDI SerDes applications, the 67.5 MHz fre-

quency may be required as an SD reference clock instead of

the standard 27 MHz frequency.

TABLE 4. SD Clock Frequency Selection

SD_CLK (MHz) SD_FREQ

PLL#

27 0 1

67.5 1 4

The HD clock frequency can be selected from Table 5 and

programmed to HD_FREQ (register 08h). PLL 2 and PLL 3

are used to generate the four different HD clock rates but only

one HD clock can be selected at a time. If the HD_CLK output

is not needed, it can be put in Hi-Z mode by setting HD_HIZ

= 1 (register 08h).

Note: If 148.35 MHz is selected, it is required to follow the programming

sequence described in section 2.1 148.35 MHz PLL Initialization Se-

quence.

www.national.com 16

LMH1982

TABLE 5. HD Clock Frequency Selection

HD_CLK (MHz) HD_FREQ

PLL#

74.25 0h 2

74.25/1.001 1h 3

148.5 2h 2

148.5/1.001 3h 3

5.2 Programming The Output Format Timing

When PLL 1 is stable and locked to the input reference, the

output format timing should be specified. The functional block

diagram for TOF generation and output initialization is shown

in Figure 3.

For proper output generation and initialization, the reference

format and output format timings must be fully and correctly

programmed to the output format registers 09h–12h, which

specify the following:

•Output TOF Clock

•Output Frame Timing

•Reference Frame Timing

•Input-Output Frame Rate Ratio

•Output Frame Line Offset

17 www.national.com

LMH1982

30052437

FIGURE 3. Functional Block Diagram – TOF Generation and Output Initialization Circuitry

www.national.com 18

LMH1982

5.2.1 Output TOF Clock

The TOF pulse is derived from a counter chain, which re-

ceives either output clock (SD_CLK or HD_CLK) from a 2:1

MUX block, as shown in Figure 3. The TOF clock from the

MUX can be selected by programming TOF_CLK (register

0Ch). To select SD_CLK as the TOF clock, set TOF_CLK =

0; otherwise, set TOF_CLK = 1 to select HD_CLK. The se-

lected TOF clock frequency is determined by the SD_FREQ

or HD_FREQ register setting.

The TOF output delay time (tD_TOF) for any output format gen-

erated from a TOF clock of 27 MHz is specified in the Elec-

trical Characteristics table. The TOF output delay time for 525i

and 1080i/50 generated using 27 MHz and 74.25 MHz, re-

spectively, are shown in the Typical Performance Character-

istics section. The TOF pulse width can be determined by:

TOF pulse width = (1 / fTOF_CLK) x TOF_PPL

Where:

fTOF_CLK = Nominal TOF Clock Frequency

TOF_PPL = Output Format Total Pixels per Line

5.2.2 Output Frame Timing

The TOF pulse is specified by programming TOF_CLK,

TOF_PPL (register 0Bh-0Ch) and TOF_LPFM (register

0Dh-0Eh). These registers configure the 2:1 MUX and output

pixel and line counters in the TOF Generation blocks shown

in Figure 3. The output frame or TOF pulse rate is determined

by:

TOF rate = fTOF_CLK / (TOF_PPL x TOF_LPFM)

Where:

fTOF_CLK = Nominal TOF Clock Frequency

TOF_PPL = Output Format Total Pixels per Line

TOF_LPFM = Output Format Total Lines per Frame

Example:

If the output format is 625i, then:

TOF rate = 27 MHz / (1728 x 625) = 25 Hz

Where:

fTOF_CLK = 27 MHz (SD_FREQ = 0)

TOF_PPL = 1728

TOF_LPFM = 625

5.2.2.1 HD Format TOF Generation using a 27 MHz TOF

Clock

Any HD format TOF pulse can be generated using either: Op-

tion 1) its native HD clock frequency, or Option 2) the 27 MHz

SD clock frequency.

Using Option 1 for HD output formats can result in TOF output

delay being offset by more than one TOF clock period, even

after output initialization. This is because the very short period

of the HD native clock yields little timing margin for the reset

signals to propagate through the internal logic in Figure 3. For

example, using a TOF clock of 148.5 MHz gives less than 6.7

ns (< 1 clock cycle) for all the logic to completely synchronize

and guarantee proper output initialization.

To ensure proper output initialization, Option 2 is recom-

mended for HD output formats, especially 1080p at 50, 59.94,

and 60 Hz. This is because the longer period of the 27 MHz

clock provides ample timing margin for the internal logic to

reset. The output parameters for programming the HD output

formats using the 27 MHz clock are shown in Table 1.

To illustrate both TOF clock options, an example is given be-

low for 1080p/59.94, which has a native pixel clock frequency

of 148.5/1.001 MHz and frame rate of 60/1.001 Hz:

Option 1) 1080p/59.94 TOF generation using 148.35 MHz

TOF rate = 148.5/1.001 MHz / (2200 x 1125) = 60/1.001 Hz

Where:

fTOF_CLK = 148.35 MHz (TOF_CLK = 1, HD_FREQ = 3h)

TOF_PPL = 2200

TOF_LPFM = 1125

Option 2) 1080p/59.94 TOF generation using 27 MHz

TOF rate = 27 MHz / 2002 x 225) = 60/1.001 Hz

Where:

fTOF_CLK = 27 MHz (TOF_CLK = 0, SD_FREQ = 0)

TOF_PPL = 2002

TOF_LPFM = 225

As an example, Figure 4 shows a timing illustration for 1080p/

59 TOF and clock outputs for Option 2. Once the outputs are

initialized, the SD clock and TOF pulse will have a fixed delay,

and the SD clock and HD clock will have a fixed timing offset

relative to each other. Therefore, the timing offset between

the TOF pulse and HD clock, or tTOF-HD, will also be fixed and

can be determined by:

tTOF-HD = tD_TOF + tD_SD - tD_HD

Where:

tD_TOF = TOF Output Delay Time referenced to SD_CLK

tD_SD = SD_CLK Output Delay Time

tD_HD = HD_CLK Output Delay Time

30052438

FIGURE 4. Timing Illustration Showing 1080p/59.94 TOF

and CLK Output Delays Using Option 2

5.2.3 Reference Frame Timing

The reference format frame timing is generated internally and

used for resetting the internal counters for output initialization.

The reference frame rate should be specified by programming

the reference format total lines per frame to REF_LPFM (reg-

ister 0Fh-10h) as well as the PLL 1 dividers. See Table 1 for

programming the parameter values according to each refer-

ence format. The reference frame rate is determined by:

REF rate = (fVCXO x R_DIV) / (FB_DIV x REF_LPFM)

Where:

fVCXO = 27 MHz Nominal VCXO Clock Frequency

R_DIV = Reference Divider (not REF_DIV_SEL)

FB_DIV = Feedback Divider

19 www.national.com

LMH1982

REF_LPFM = Reference Format Total Lines per Frame

5.2.4 Input-Output Frame Rate Ratio

The input-output frame rate ratio is also used for resetting the

internal counters for output initialization. The ratio is the Input

Frame Rate / Output Frame Rate, in which the numerator and

denominator values are reduced to lowest integer factors.

The numerator value of this reduced ratio should be pro-

grammed to TOF_RST (register 09h-0Ah), and the denomi-

nator value is discarded.

Example:

If the input reference is 525i with a frame rate of 30/1.001 Hz

and the output format is 625i with a frame rate of 25 Hz, then:

Frame rate ratio = (30/1.001) / 25 = 1200 / 1001

Therefore, the numerator, 1200, should be programmed to

TOF_RST.

5.2.5 Output Frame Line Offset

The output clock and TOF pulse can be aligned to any line of

the reference frame by programming TOF_OFFSET (register

11h-12h) and subsequently programming the output initial-

ization sequence. The line offset value should be directly

programmed to TOF_OFFSET to delay or advance the out-

puts' alignment relative to the decoded reference frame timing

(see section 4.2 Reference Frame Decoder).

The TOF_OFFSET value must be greater than zero but less

than or equal to the programmed value for REF_LPFM (i.e.

0 < TOF_OFFSET ≤ REF_LPFM). If no line offset is required,

then program TOF_OFFSET equal to REF_LPFM instead of

zero (invalid value).

Example:

If an input reference with PAL timing comes from the

LMH1981, the H and V pulses will be aligned to within ΔTHV

which occurs on line 313 of the reference. In this case,

TOF_OFFSET can be set to 312d (138h) so the output frame

will align to Line 1 of the PAL reference (start of frame) after

the outputs are initialized. This example is illustrated in Figure

30052434

FIGURE 5. PAL Reference and Output TOF Pulse

(TOF_OFFSET = 312)

Note: If the alternative set of divider and REF_LPFM values are pro-

grammed per (Note 20) for a lower PLL 1 phase comparison fre-

quency, then the output frame cannot be offset to any horizontal line

of the reference. Instead, the output frame can only be aligned to the

reference in 5 lines steps per 1 step of the TOF_OFFSET value, up

to a maximum of reference's total lines per frame divided by 5 (i.e.

REF_LPFM). This is because the phase comparison frequency

(H_FB signal in Figure 3) will be lower than the H sync input frequency

by 5x due to the use of the alternative divider values.

5.3 Programming The Output Initialization Sequence

Before programming the output initialization (alignment) se-

quence, the following prerequisites must be met:

1. PLL 1 must be stable and locked to the input reference.

2. The desired output clock and TOF pulse timing must be

fully specified to the output format registers.

To ensure that the output clock and TOF pulse are properly

aligned and subsequently phase locked to the reference

frame, the output initialization sequence should be pro-

grammed accordingly.

During the output frame immediately prior to the frame the

initialization is to occur:

1. Set EN_TOF_RST = 1(register 0Ah) to enable output

alignment mode.

2. Toggle TOF_INIT (register 0Ah) from 0 to 1 to reset the

internal counters. On the next frame, the output clock and

TOF pulse will be initialized (aligned) to the reference

frame with line offset programmed to TOF_OFFSET.

3. Immediately after the initialization and before the next

output frame occurs, clear EN_TOF_RST and TOF_INIT

to 0. Otherwise, the output clock will be continually

aligned on every output frame while EN_TOF_RST = 1.

Continual alignment which may cause excessive jitter on

the output clock (from PLL 2, 3, or 4) due to slight

differences in the delay paths of the internal logic. This

occurrence of excessive clock jitter can be avoided by

disabling output alignment mode (EN_TOF_RST = 0)

immediately after the initialization sequence.

5.3.1 TOF Output Delay Considerations

Due to the following conditions, the TOF pulse may be de-

layed or offset by more than one TOF clock period (tD_TOF >

1 pixel) even after output initialization:

1. The delay paths of the internal logic used to generate and

align the TOF pulse is greater than one period of the TOF

clock. This can occur for HD format TOF pulses

generated using the 148 MHz native pixel clock. For HD

format TOF generation, it is recommended to use the 27

MHz SD clock as the TOF clock instead of the native HD

pixel clock as shown in section 5.2.2 Output Frame

Timing.

2. The H sync and/or V sync input pulses have excessive

jitter equal to or larger than half of a pixel period of the

selected output clock. Input sync jitter less than 3 ns

peak-to-peak is recommended.

3. PLL 1 is not completely phase locked or stable when the

output initialization is performed. The VCXO clock phase

error with respect to the H sync input should less than

one period of the selected TOF clock.

5.3.2 Output Clock Initialization without TOF

For applications that do not require the TOF pulse, it is still

necessary to program all output format registers prior to the

output initialization sequence. This is because the output ini-

tialization circuitry relies on the full and correct specification

of the output format. If the TOF output is not needed, it can

be put in Hi-Z mode by setting TOF_HIZ = 1 (register 08h).

5.4 Output Behavior Upon Loss Of Reference

After loss of reference (LOR), the LMH1982 will maintain the

TOF pulse without the input reference according to the ter-

minal counts of the reference clock; however, output frequen-

www.national.com 20

LMH1982

cy accuracy will be determined by the VCXO, which may be

in Free Run or Holdover operation.

To disable output alignment to an arbitrary reference frame

when the reference is reapplied, set EN_TOF_RST = 0 before

the reference returns. After PLL 1 has re-locked to the refer-

ence, the outputs can be initialized to the desired reference

frame.

6.0 REFERENCE AND PLL LOCK STATUS

The LMH1982 features a reference detector and PLL lock

detector that can be used to indicate genlock status of the

input reference and device PLLs. Genlock status can be sam-

pled via the NO_REF and NO_LOCK status flag output pins

and the REF_VALID, SD_LOCK, and HD_LOCK status bits

(register 01h). Both the reference and PLL lock detectors may

be programmed for their respective detection thresholds ac-

cording to the needs of the application system. See Table 7

for a summary of the genlock status bits and status outputs

for different conditions.

The NO_REF and NO_LOCK outputs are derived from the

genlock status bits and given by the following two logic equa-

tions:

NO_REF = REF_VALID

NO_LOCK = (REF_VALID) (SD_LOCK) (HD_LOCK)

6.1 Reference Detection

In Genlock mode, a valid reference will be indicated by

NO_REF = 0 when all the criteria below are met. Otherwise,

a loss of reference (LOR) will be indicated by NO_REF = 1.

•An H sync signal is applied to the input reference and

conforms to one of the standard formats in Table 1. A

V sync signal is not used in reference detection.

•The PLL divide registers are programmed according to the

input reference format.

•The control voltage of the VCXO is not within about 500

mV of the GND or VDD supplies.

6.1.1 Programming the Loss of Reference (LOR)

Threshold

The reference detector's error threshold can be programmed

to H_ERROR (register 00h), which determines the maximum

number of missing H sync pulses before indicating an LOR.

The LOR threshold will be the H_ERROR value multiplied by

the PLL 1 reference divider value, as shown in Table 6.

TABLE 6. LOR Threshold Selection

REF_DIV_SEL

Reference

Divider

LOR Threshold

0h 2 2 x H_ERROR

1h 1 1 x H_ERROR

2h 5 5 x H_ERROR

If H_ERROR = 0, then the device will react after the first miss-

ing pulse. When the LOR threshold is exceeded, the NO_REF

output will indicate LOR, and the device will default to either

Free Run or Holdover operation for as long as the reference

is lost. As the LOR threshold value is increased, the accuracy

for counting the actual number of missing H pulses may di-

minish due to frequency drifting by PLL 1.

Note: If the input reference is missing H pulses periodically, e.g. every ver-

tical interval period, the PLL may not indicate a valid reference nor

achieve lock regardless of the H_ERROR value programmed. This is

because periodically missing pulses will translate to a lower average

frequency than expected. When the average input frequency falls

outside of the absolute pull range (APR) of the VCXO, the PLL will

not be able to frequency lock to the input reference.

6.2 PLL Lock Detection

In Genlock mode, PLL lock will be indicated by NO_LOCK =

0 when all the criteria below are met. Otherwise, a loss of lock

will be indicated by NO_LOCK = 1.

•A valid reference is indicated (REF_VALID = 1).

•PLL 1 or PLL 4 is phase locked to the input reference

(SD_LOCK = 1).

•PLL 2 or PLL 3 is phase locked to the VCXO clock

reference (HD_LOCK = 1).

PLLs 2, 3, and 4 have high loop bandwidths, which allow them

to achieve lock quickly and concurrently while PLL 1 achieves

lock. Because PLL 1 has a much lower loop bandwidth, it will

dictate the overall lock indication time.

6.2.1 Programming the PLL Lock Threshold

PLL 1's lock detector threshold can be programmed to

LOCK_CTRL (register 01h), which determines the maximum

phase error between PLL 1's phase detector (PD) inputs be-

fore indicating an unlock or lock condition. The PD inputs are

the reference signal (H sync input / reference divider) and the

feedback signal (VCXO clock / feedback divider).

The lock detector will indicate loss of lock when the phase

error between the PD inputs is greater than the lock threshold

for three consecutive phase comparison periods. Conversely,

it will indicate valid lock when the phase error is less than the

lock threshold for three consecutive phase comparison peri-

ods.

A larger value for LOCK_CTRL will yield shorter lock indica-

tion time (although not actual lock time) at the expense of

higher output phase error when lock is initially indicated,

whereas a smaller value will yield the opposite effect.

6.2.2 PLL Lock Status Instability

It is possible for excessive jitter on the H input to indicate lock

instability through the NO_LOCK output, even if the VCXO

and output clocks are properly phase locked and no system-

level errors are occurring (e.g. bit errors). To reduce the

probability of false loss of lock indication or lock status insta-

bility, LOCK_CTRL can be increased to improve the lock

detector’s ability to tolerate a larger amount of input phase

jitter or phase error. This can help to ensure the NO_LOCK

output and SD_LOCK bit are stable when the reference signal

has large input jitter.

21 www.national.com

LMH1982

TABLE 7. Summary of Genlock Status Bits and Flag Outputs

Mode Control Bits

Conditions GNLK HOLD-

OVER

NO_REF 1

(pin 16)

NO_LOCK 2

(pin 17)

HD_LOCK

bit 2

SD_LOCK

bit 1

REF_VALID

bit 0

Genlock mode, Reference

valid, PLLs locking 1 X 0 1 0 0 1

Genlock mode, Reference

valid, PLLs locked 1 X 0 0 1 1 1

Genlock mode, Reference

lost, Free Run operation 1 0 1 1 1 0 0

Genlock mode, Reference

lost, Holdover operation 1 1 1 1 1 0 0

Status flag output logic equations:

1. NO_REF = REF_VALID

2. NO_LOCK = (REF_VALID) (SD_LOCK) (HD_LOCK)

7.0 LOOP RESPONSE

The overall loop response of the LMH1982 is determined by

the design of the VCXO PLL (PLL 1). Because the integrated

VCO PLLs use the VCXO clock as the input reference to

phase lock the output clocks, the ability of PLL 1 to attenuate

the input jitter is critical to output jitter performance, especially

low-frequency jitter that occurs at the video line and field

rates. The loop response of the LMH1982 can be character-

ized by PLL 1's loop bandwidth and damping factor.

The loop response is primarily determined by the loop filter

components and the loop gain. A passive second-order loop

filter consisting of RS, CS, and CP components can provide

sufficient input jitter attenuation for most applications, al-

though a higher order passive filter or active filter may also be

used. The loop gain is a function of the VCXO gain and pro-

grammable PLL parameters.

A lower loop bandwidth will provide higher input jitter attenu-

ation (reduced jitter transfer) for improved output jitter perfor-

mance; however, increased lock time (or settling time) and

larger external component values are a couple trade-offs to a

lower loop bandwidth.

7.1 Loop Response Design Equations

The following equations can be used to design the loop re-

sponse of PLL 1.

The -3 dB loop bandwidth, BW, can be approximated by:

BW = ICP1 * RS * KVCO / FB_DIV

Where:

ICP1 = Nominal VCXO PLL charge pump current (in

amps)

programmed by setting ICP1 (register 13h).

For example:

ICP1 = 250 µA: ICP1 = 08h (default value)

ICP1 = 0 µA: ICP1 = 00h (min)

ICP1 = 62.5 µA; ICP1 = 02h (practical min)

ICP1 = 968.75 µA; ICP1 = 1Fh (max)

ICP1 step size = 31.25 µA

RS = Nominal value of series resistor (in ohms)

KVCO = Nominal 27 MHz VCXO gain (in Hz/V)

KVCO = Pull_range * 27 MHz/Vin_range

For the recommended VCXO (Mftr: CTS, P/N:

357LB3C027M0000): KVCO = 100 ppm * 27 MHz/

(3.0V- 0.3V) = 1000 Hz/V

FB_DIV = Feedback Divider value

For example:

FB_DIV =1716 for NTSC timing

Note that this BW approximation does not take into account

the effects of the damping factor or the second pole intro-

duced by Cp.

At frequencies far above the −3 dB loop bandwidth, the

closed-loop frequency response of PLL 1 will roll off at about

−40 dB/decade, which is useful attenuating input jitter at fre-

quencies above the loop bandwidth. Near the −3 dB corner

frequency, the roll-off characteristic will depend on other fac-

tors, such as damping factor and filter order.

To prevent output jitter due to the modulation of the VCXO by

the PLL’s phase comparison frequency:

BW ≤ (27 MHz / FB_DIV) / 20

PLL 1's damping factor, DF, can be approximated by:

DF = (RS / 2) * sqrt (ICP1 * CS * KVCO / FB_DIV)

Where:

CS = Nominal value of the series capacitor (in farads)

A typical design target for DF is between 0.707 to 1, which

can often yield a good trade-off between reference spur at-

tenuation and lock time. DF is related to the phase margin,

which is a measure of the PLL stability.

A secondary parallel capacitor, CP, is needed to filter the ref-

erence spurs introduced by the PLL which may modulate the

VCXO input voltage and also cause output jitter. The following

relationship should be used to determine CP:

CP = CS / 20

The PLL loop gain, K, can be calculated as:

K = ICP1 * KVCO / FB_DIV

Therefore, the BW and DF can be expressed in terms of K:

BW = RS * K

DF = (RS/2) * sqrt (CS * K)

www.national.com 22

LMH1982

7.1.1 Loop Response Optimization Tips

The need to support various input reference formats will usu-

ally require a diverse range of PLL divider values, which can

each yield a different loop response assuming all other PLL

parameters are kept the same. Typically, it is desired to de-

sign and optimize the loop response across all supported

input formats without modification to the loop filter circuit. This

requires that the loop gain, K, be kept constant across all

supported divider values because K affects both BW and DF

equations. To keep a narrow range for K, the ratio (ICP1 /

feedback divider) should be kept relatively constant. This can

be achieved by programming ICP1, so that ICP1 is scaled with

FB_DIV for each supported input format.

It is suggested to start designing the loop filter component

values from the BW and DF equations with initial assumptions

of FB_DIV = 1716 (NTSC) and ICP1 = 250 µA (default setting).

Once reasonable component values are achieved under

these initial assumptions, it is necessary to check that K can

be maintained over the expected range of FB_DIV by adjust-

ing ICP1. The usable current range of ICP1 is limited to a

practical minimum of 94 µA (ICP1 = 3d) to a maximum of 969

µA (ICP1 = 31d), which should provide adequate range to

maintain a narrow range for K assuming the suggested initial

values for FB_DIV and ICP1 were followed. If a narrow range

for K cannot be maintained within the usable range of ICP1,

then the loop filter design may need to be modified. Some

trial-and-error and iterative calculations may be necessary to

find an optimal loop filter.

In some loop filter designs, the calculated ICP1 current that is

required for a target K value may be near or below the prac-

tical minimum of the ICP1 current range. In this scenario, it may

also be possible to leverage the programmable reference and

feedback dividers by scaling up the values in proportion (i.e.

same reduced divider ratio). This would allow ICP1 to be scaled

up by the same proportion to be within the usable ICP1 current

range and maintain the same K value, since ICP1 and FB_DIV

would be scaled by the same factor. For example, by scaling

the divider values by a factor of 5x, ICP1 can also be scaled

up by 5x such that its within the usable current range. This

technique of scaling FB_DIV and ICP1 assumes that the input

format has an alternative set of compatible divider values as

shown in Table 1.

7.1.2 Loop Filter Capacitors

It is suggested to use tantalum capacitors for CS and CP in-

stead of ceramic capacitors in the PLL loop filter, which is a

sensitive analog circuit. Ferroelectric ceramics, such as X7R,

X5R, Y5V, Y5U, etc., exhibit piezoelectric effects that gener-

ate electrical noise in response to mechanical vibration and

shock. This electrical noise can modulate the VCXO control

voltage and consequently induce clock jitter at high ampli-

tudes when the board and ceramic components are subjected

to vibration or shock. Tantalum capacitors can be used to

mitigate this effect.

7.2 Lock Time Considerations

The LMH1982 lock time or settling time is determined by the

loop response of PLL 1, which has a much lower loop band-

width compared to the integrated PLLs used to derive the

other output clock frequencies. Generally, the lock time is in-

versely proportional to the loop bandwidth; however, if the

loop response is not designed or programmed for sufficient

PLL stability, the lock time may not be predicted from the loop

bandwidth alone. Therefore, any parameter that affects the

loop response can also affect the overall lock time.

One way to reduce lock time is to widen the loop bandwidth

by programming a larger or maximum value for ICP1 while PLL

1 is locking; after PLL 1 is locked, ICP1 can be reduced to pro-

vide a narrower loop bandwidth while maintaining a reason-

able damping factor.

7.3 VCXO Considerations

The recommended VCXO manufacturer part number is CTS

357LB3C027M0000, which has an absolute pull range (APR)

of ±50 ppm and operating temperature range of -20°C to +70°

C. A VCXO with a tighter APR can provide better output fre-

quency accuracy in Free Run operation; however, the APR

must be wider than the worst-case input frequency error in

order to achieve phase lock.

7.4 Free Run Output Jitter

The input voltage to VC_FREERUN (pin 1) should have suf-

ficient filtering to minimize noise over the frequency bands of

interest (i.e. SMPTE SDI jitter frequency bands) which can

cause VCXO input voltage modulation and thus free run out-

put clock jitter.

8.0 I2C INTERFACE PROTOCOL

The protocol of the I2C interface begins with the start pulse

followed by a byte comprised of a seven-bit slave device ad-

dress and a read/write bit as the LSB. Therefore, the address

of the LMH1982 for write sequences is DCh (1101 1100) and

the address for read sequences is DDh (1101 1101). Figure

6, Figure 7, and Figure 8 show a write and read sequence

across the I2C interface.

8.1 Write Sequence

The write sequence begins with a start condition, which con-

sists of the master pulling SDA low while SCL is held high.

The slave device address is sent next. The address byte is

made up of an address of seven bits (7:1) and the read/write

bit (0). Bit 0 is low to indicate a write operation. Each byte that

is sent is followed by an acknowledge (ACK) bit. When SCL

is high the master will release the SDA line. The slave must

pull SDA low to acknowledge. The address of the register to

be written to is sent next. Following the register address and

the ACK bit, the data byte for the register is sent. When more

than one data byte is sent, it is automatically incremented into

the next address location. See Figure 6. Note that each data

byte is followed by an ACK bit.

23 www.national.com

LMH1982

30052404

FIGURE 6. LMH1982 Write Sequence

8.2 Read Sequence

Read sequences are comprised of two I2C transfers. The first

is the address access transfer, which consists of a write se-

quence that transfers only the address to be accessed. The

second is the data read transfer, which starts at the address

accessed in the first transfer and increments to the next ad-

dress per data byte read until a stop condition is encountered.

The address access transfer shown in Figure 7 consists of a

start pulse, the slave device address including the read/write

bit (a zero, indicating a write), then its ACK bit. The next byte

is the address to be accessed, followed by the ACK bit and

the stop bit to indicate the end of the address access transfer.

The subsequent read data transfer shown in Figure 8 consists

of a start pulse, the slave device address including the read/

write bit (a one, indicating a read) and the ACK bit. The next

byte is the data read from the initial access address. Subse-

quent read data bytes will correspond to the next increment

address locations. Each data byte is separated from the other

data bytes by an ACK bit.

30052405

FIGURE 7. LMH1982 Read Sequence – Address Access Transfer

30052406

FIGURE 8. LMH1982 Read Sequence – Data Read Transfer

8.3 I2C Enable Control Pin

When the active low input I2C_ENABLE = 0, the LMH1982

will enable I2C communication via its fixed slave address;

otherwise, the LMH1982 will not respond. For applications

with multiple LMH1982 devices on the same I2C bus, the I2C

enable function can be useful for writing data to a specific

device(s) and for reading data from an individual device to

prevent bus contention. For single chip applications, the

I2C_ENABLE input can be tied to GND to keep the I2C inter-

face enabled.

www.national.com 24

LMH1982

9.0 I2C INTERFACE CONTROL REGISTER DEFINITIONS

TABLE 8. I2C Interface Control Register Map

Address

Default

Data

D7 D6 D5 D4 D3 D2 D1 D0

00h A3h GNLK_I2C GNLK RSEL_I2C RSEL HOLD-

OVER

H_ERROR [2:0]

01h 86h LOCK_CTRL [7:3] HD_LOCK SD_LOCK REF_VALID

02h 00h RSV RSV

PIN6_

OVRD REF_27 POL_HA POL_VA POL_HB POL_VB

03h 01h RSV RSV RSV RSV RSV RSV REF_DIV_SEL [1:0]

04h B4h FB_DIV [7:0]

05h 06h 0 0 0 FB_DIV [12:8]

06h 00h RSV RSV RSV RSV ICP4 [3:0]

07h 00h RSV RSV RSV RSV RSV RSV RSV RSV

08h 04h RSV RSV TOF_HIZ HD_HIZ HD_FREQ [3:2] SD_HIZ SD_FREQ

09h 01h TOF_RST [7:0]

0Ah 00h EN_TOF_

RST

POL_TOF TOF_INIT TOF_RST [12:8]

0Bh B4h TOF_PPL [7:0]

0Ch 06h 0 0 TOF_CLK TOF_PPL [12:8]

0Dh 0Dh TOF_LPFM [7:0]

0Eh 02h 0 0 0 0 TOF_LPFM [11:8]

0Fh 0Dh REF_LPFM [7:0]

10h 02h 0 0 0 0 REF_LPFM [11:8]

11h 00h TOF_OFFSET [7:0]

12h 00h 0 0 0 0 TOF_OFFSET [11:8]

13h 88h RSV RSV RSV ICP1 [4:0]

14h 88h ICP2 [7:4] ICP3 [3:0]

When writing to registers containing reserved bits (RSV), make sure the RSV bits are programmed with their original default data shown in column 2 of Table

8; otherwise, improper device operation may result.

25 www.national.com

LMH1982

9.1 Genlock And Input Reference Control Registers

Bits 2-0: H Input Error Max Count (H_ERROR)

The H_ERROR bits control the reference detector's error

threshold, which determines the maximum number of missing

H sync pulses before indicating a LOR. See section 6.1.1

Programming the Loss of Reference (LOR) Threshold.

Bit 3: Holdover on Loss of Reference (HOLDOVER)

The HOLDOVER bit controls the operating mode when a loss

of reference occurs. See section 3.2.2 Loss of Reference

(LOR).

Bit 4: Reference Select (RSEL)

The RSEL bit selects either REF_A or REF_B inputs as the

reference to genlock the outputs when I2C_RSEL = 1.

RSEL = 0: Select REF_A inputs.

RSEL = 1: Select REF_B inputs.

If PIN6_OVRD = 1 (register 02h), then reference selection

must be controlled by programming RSEL, regardless of

I2C_RSEL. When PIN6_OVRD = 0 and I2C_RSEL = 0, then

reference selection is controlled using the REF_SEL input pin

and the RSEL bit is ignored.

Bit 5: Reference Select Control via I2C (I2C_RSEL)

By programming I2C_RSEL, reference selection can be con-

trolled either via I2C or the REF_SEL input pin.

I2C_RSEL = 1: Control reference selection by programming

RSEL.

I2C_RSEL = 0: Control reference selection via the

REF_SEL input pin.

Note: If PIN6_OVRD = 1, then reference selection must be controlled by

programming RSEL regardless of I2C_RSEL.

Bit 6: Mode Select (GNLK)

The GNLK bit selects the operating mode when I2C_GNLK =

1. See section 3.0 MODES OF OPERATION.

GNLK = 0: Selects Free Run mode.

GNLK = 1: Selects Genlock mode.

If I2C_GNLK = 0, then the operating mode will be controlled

using the GENLOCK input pin and the GNLK bit will be ig-

nored.

Bit 7: Mode Select via I2C (I2C_GNLK)

By programming I2C_GNLK, mode selection can be con-

trolled either via I2C or the GENLOCK input pin.

I2C_GNLK = 1: Control mode selection by programming

GNLK.

I2C_GNLK = 0: Control mode selection via the GENLOCK

input pin.

9.2 Genlock Status And Lock Control Register

Bit 0: Reference Status (REF_VALID)

REF_VALID is a read-only bit and indicates the presence or

loss of reference on the selected reference port in Genlock

mode. The NO_REF output flag is an inverted copy of

REF_VALID. See section 6.1 Reference Detection.

REF_VALID = 0: Indicates loss of reference (LOR).

REF_VALID = 1: Indicates valid reference.

In Free Run mode, REF_VALID will be set to 0 to indicate the

absence of any input pulses at the selected HREF port.

Bit 1: SD Clock PLL Lock Status (SD_LOCK)

SD_LOCK is a read-only bit and indicates PLL lock status of

the selected SD clock. See section 6.2 PLL Lock Detection.

SD_LOCK = 0: Indicates loss of lock.

SD_LOCK = 1: Indicates valid lock.

Bit 2: HD Clock PLL Lock Status (HD_LOCK)

HD_LOCK is a read-only bit and indicates PLL lock status of

the selected HD clock. See section 6.2 PLL Lock Detection.

HD_LOCK = 0: Indicates loss of lock.

HD_LOCK = 1: Indicates valid lock.

Bits 7-3: Lock Control (LOCK_CTRL)

LOCK_CTRL controls the phase error threshold of PLL 1's

lock detector. A larger value for LOCK_CTRL will yield shorter

lock indication time (although not actual lock time) at the ex-

pense of higher output phase error when lock is initially indi-

cated, whereas a smaller value will yield the opposite effect.

See section 6.2.1 Programming the PLL Lock Threshold.

9.3 Input Control Register

Bit 0: VREF_B Input Signal Polarity (POL_VB)

This bit should be programmed to match the input signal po-

larity at the VREF_B input pin.

POL_VB = 0: Negative polarity or active low signal.

POL_VB = 1: Positive polarity or active high signal.

Bit 1: HREF_B Input Signal Polarity (POL_HB)

This bit should be programmed to match the input signal po-

larity at the HREF_B input pin. The positive edge of the output

clock will be phase locked to the active edge of the H sync

input signal.

POL_HB = 0: Negative polarity or active low signal.

POL_HB = 1: Positive polarity or active high signal.

Bit 2: VREF_A Input Signal Polarity (POL_VA)

This bit should be programmed to match the input signal po-

larity at the VREF_A input pin.

POL_VA = 0: Negative polarity or active low signal.

POL_VA = 1: Positive polarity or active high signal.

Bit 3: HREF_A Input Signal Polarity (POL_HA)

This bit should be programmed to match with the input signal

polarity at HREF_A input pin. The positive edge of the output

clock will be phase locked to the active edge of the H sync

input signal.

POL_HA = 0: Negative polarity or active low signal.

POL_HA = 1: Positive polarity or active high signal.

Bit 4: 27 MHz Reference Control (27M_REF)

Instead of an H sync signal, a 27 MHz clock signal can be

applied to the selected HREF input to phase lock the output

clocks. If a 27 MHz clock is used as a reference, then a value

of 1 should be programmed to 27M_REF, REF_DIV_SEL,

and FB_DIV.

27M_REF = 0: H sync input signal.

27M_REF = 1: 27 MHz clock input signal. Also, set

REF_DIV_SEL =1 and FB_DIV = 1

Note: Because the loop gain, K, for 27 MHz clock input is much larger than

for an H sync input (due to the large difference in FB_DIV), the loop

www.national.com 26

LMH1982

filter design will be necessarily different between the 27 MHz input

and H sync inputs. Alternatively, it's possible to use an external

counter circuit to divide the 27 MHz clock to a lower frequency (e.g.

like H sync) input, so only one loop filter design could support both

types of inputs.

Bit 5: Pin 6 Override (PIN6_OVRD)

The PIN6_OVRD bit can be programmed to override the de-

fault reference selection capability on pin 6 and instead use

pin 6 as an logic pulse input to initialize or reset the internal

counters for output initialization.

PIN6_OVRD = 0: Allows a logic level input to be applied to

pin 6 for reference selection if RSEL_I2C = 0 (register 00h). If

RSEL_I2C = 1, then pin 6 is ignored and reference selection

is controlled via I2C; additionally, outputs must be initialized

via I2C by programming TOF_INIT and EN_TOF_RST (reg-

ister 0Ah).

PIN6_OVRD = 1: Allows an TOF Init pulse to be applied to

pin 6 for output initialization if EN_TOF_RST = 1. If

EN_TOF_RST = 0, then any TOF Init pulse received at pin 6

will be ignored. Additionally, reference selection must be con-

trolled via I2C, regardless of I2C_RSEL.

Bits 7-6: Reserved (RSV)

These RSV bits are reserved. When writing to this register,

only write the default data to the RSV bits as specified in Table

9.4 PLL 1 Divider Register

Bits 1-0: Reference Divider Selection (REF_DIV_SEL)

REF_DIV_SEL selects the reference divider value according

to the selection table in Table 2. See section 4.1 Programming

the PLL 1 Dividers.

The reference divider value is the denominator of PLL 1's di-

vider ratio:

Feedback divider value / Reference divider value = 27 MHz /

Hsync input frequency

The numerator and denominator values of the divider ratio

should be reduced to their lowest factors to be compatible with

the range of divider values offered by REF_DIV_SEL and

FB_DIV. These registers must be programmed correctly to

phase lock the 27 MHz VCXO PLL and output clocks to the

input reference. See Table 1 for the suggested divider set-

tings for the supported timing formats.

Bits 7-3: Reserved (RSV)

These RSV bits are reserved. When writing to this register,

only write the default data to the RSV bits as specified in Table

Bits 7-0: Feedback Divider (FB_DIV)

This register contains the 8 LSBs of FB_DIV. The feedback

divider value is the numerator of PLL 1's divider ratio. FB_DIV

should be programmed using the feedback divider value after

the divide ratio has been reduced to its lowest factors. Refer

to the description for register 03h, and see Table 1 for the

suggested divider settings for the supported timing format.

Bits 4-0: Feedback Divider (FB_DIV)

This register contains the 5 MSBs of FB_DIV. See the de-

scription for register 04h.

Bits 7-5: These non-programmable bits contain zeros.

9.5 PLL 4 Charge Pump Current Control Register

Bits 3-0: Charge Pump Current Control for PLL 4 (ICP4)

ICP4 can be programmed to specify charge pump current for

PLL 4, which generates the 67.5 MHz SD clock.

Note: Bit 3 is inverted internally, so the default ICP4 value of 0000b (0h)

actually yields an effective value of 1000b (8h), which is the mid-scale

setting.

The PLL 4 charge pump current increases linearly with the

effective value. Reducing the effective value of the charge

pump current will lower its loop bandwidth at the expense of

reduced PLL stability. An effective value of 0 (ICP4 = 1000b)

should not be programmed since this corresponds to 0 µA

nominal current and will cause PLL 4 to lose phase lock.

Bits 7-4: Reserved (RSV)

These RSV bits are reserved. When writing to this register,

only write the default data to the RSV bits as specified in Table

Bits 7-0: Reserved (RSV)

This register is reserved. If necessary, only write the default

data (00h) to register 07h as specified in Table 8.

9.6 Output Clock And TOF Control Register

Bit 0: SD Clock Output Frequency Select (SD_FREQ)

This bit sets the clock frequency of the SD_CLK output pair.

SD_FREQ = 0: Selects 27 MHz from PLL 1.

SD_FREQ = 1: Selects 67.5 MHz from PLL 4.

Bit 1: SD Clock Output Mode (SD_HIZ)

Set the SD_HIZ bit to 1 to put the SD_CLK output pair in high-

impedance (Hi-Z) mode; otherwise, the SD_CLK output will

be enabled.

Bit 3-2: HD Clock Output Frequency Select (HD_FREQ)

These bits set the clock frequency of the HD_CLK output pair.

HD_FREQ = 0h: Selects 74.25 MHz from PLL 2.

HD_FREQ = 1h: Selects 74.176 MHz from PLL 3.

HD_FREQ = 2h: Selects 148.5 MHz from PLL 2.

HD_FREQ = 3h: Selects 148.35 MHz from PLL 3.

Note: When selecting the 148.35 MHz clock, you must also program the

PLL 3 initialization sequence as described in section 2.1 148.35 MHz

PLL Initialization Sequence.

Bit 4: HD Clock Output Mode (HD_HIZ)

Set the HD_HIZ bit to 1 to put the HD_CLK output pair in high-

impedance (Hi-Z) mode; otherwise, the HD_CLK output will

be enabled.

Bit 5: Top of Frame Output Mode (TOF_HIZ)

Set the TOF_HIZ bit to 1 to put the TOF output pin in high-

impedance (Hi-Z) mode; otherwise, the output will be en-

abled.

Bits 7-6: Reserved (RSV)

These RSV bits are reserved. When writing to this register,

only write the default data to the RSV bits as specified in Table

9.7 TOF Configuration Registers

27 www.national.com

LMH1982

Bits 7-0: TOF Reset (TOF_RST)

This register contains the 8 LSBs of TOF_RST. When PLL 1

is phase locked to the reference, both H sync and V sync in-

puts are used to reset the frame-based counters used for

output TOF generation. The numerator value of the reduced

frame rate ratio should be programmed to TOF_RST. See

section 5.2.4 Input-Output Frame Rate Ratio.

Once TOF_RST is programmed, the outputs must be properly

initialized by either programming TOF_INIT or otherwise us-

ing an external TOF Init pulse (when PIN6_OVRD = 1).

Bits 4-0: TOF Reset (TOF_RST)

This register contains the 5 MSBs of TOF_RST. See the de-

scription for register 09h.

Bit 5: Output Initialization (TOF_INIT)

After enabling output alignment mode (EN_TOF_RST = 1),

the TOF_INIT bit should be programmed to reset the internal

counters and initialize (align) the outputs to the desired ref-

erence frame. The output initialization is triggered by pro-

gramming a positive bit transition (0 to 1) to TOF_INIT. See

section 5.3 Programming The Output Initialization Se-

quence.

Bit 6: TOF Pulse Output Polarity (POL_TOF)

This bit should be programmed to the desired TOF pulse po-

larity at the TOF output.

POL_TOF = 0: Negative polarity or active low signal.

POL_TOF = 1: Positive polarity or active high signal.

Bit 7: Output Alignment Mode (EN_TOF_RST)

This bit must be set (EN_TOF_RST = 1) to enable output

alignment mode prior to initialization per section 5.3 Program-

ming The Output Initialization Sequence. It is recommended

to clear this bit (EN_TOF_RST = 0) immediately after the out-

put initialization sequence has been programmed to prevent

excessive output jitter, as described in section 2.3 Output

Disturbance While Output Alignment Mode Enabled.

Bits 7-0: Total Pixels per Line for the Output Format

(TOF_PPL)

This register contains the 8 LSBs of TOF_PPL. TOF_PPL

should be programmed with total pixels per line for the desired

output format. TOF_PPL is used in specifying the output

frame rate. This should be specified prior to programming the

output initialization sequence. See section 5.2.2 Output

Frame Timing.

Bits 4-0: MSBs of Total Pixels per Line for the Output

Format (TOF_PPL)

This register contains the 5 MSBs of TOF_PPL. See the de-

scription for register 0Bh.

Bit 5: Output Clock Select for Output Top of Frame

(TOF_CLK)

This bit should be programmed to select the output TOF clock

reference according to the desired output format. The select-

ed TOF clock frequency is used in specifying the output frame

rate. Any output format, including HD, can use 27 MHz as the

TOF clock to generate its TOF pulse by programming the

output counter values corresponding to the 27 MHz SD clock

as shown in Table 1. See sections 5.2.1 Output TOF Clock

and 5.2.2 Output Frame Timing.

TOF_CLK = 0: Selects the SD_CLK output as the output

clock reference, where the SD frequency is set by SD_FREQ.

TOF_CLK = 1: Selects the HD_CLK output as the output

clock reference.

Bit 7-6: These non-programmable bits contain zeros.

Bits 7-0: LSBs of Total Lines per Frame for the Output

Format (TOF_LPFM)

This register contains the 8 LSBs of TOF_LPFM. TOF_LPFM

should be programmed with the total lines per frame for the

desired output format. TOF_LPFM is used in specifying the

output frame rate. This should be specified prior to program-

ming the output initialization sequence. See section 5.2.2

Output Frame Timing.

Bits 3-0: MSBs of Total Lines per Frame for the Output

Format (TOF_LPFM)

This register contains the 4 MSBs of TOF_LPFM. See the

description for register 0Dh.

Bit 7-5: These non-programmable bits contain zeros.

Bits 7-0: LSBs of Total Lines per Frame for the Input Ref-

erence Format (REF_LPFM)

This register contains the 8 LSBs of REF_LPFM. REF_LPFM

should be programmed with the total lines per frame for the

input reference format. REF_LPFM is used in specifying the

reference frame rate. This should be specified prior to pro-

gramming the output initialization sequence (section 5.2.3

Reference Frame Timing).

Bits 3-0: MSBs of Total Lines per Frame for the Input Ref-

erence Format (REF_LPFM)

This register contains the 4 MSBs of REF_LPFM. See the

description for register 0Fh.

Bit 7-4: These non-programmable bits contain zeros.

Bits 7-0: LSBs of Output Frame Offset (TOF_OFFSET)

This register contains the 8 LSBs of TOF_OFFSET.

TOF_OFFSET should be programmed with the desired line

offset to delay or advance the output timing relative to the

reference frame. This should be specified prior to program-

ming the output initialization sequence. See section 5.2.5

Output Frame Line Offset.

Bits 3-0: MSBs of Line Offset for the Output Top of Frame

(TOF_OFFSET)

This register contains the 4 MSBs of TOF_OFFSET. See the

description for register 11h.

Bit 7-4: These bits contain zeros (non-programmable)

9.8 PLL 1, 2, 3 Charge Pump Current Control Registers

Bits 4-0: PLL 1 Charge Pump Current Control (ICP1)

ICP1 can be programmed to specify the charge pump current

for PLL 1, which generates 27 MHz from the VCXO output.

The PLL 1 charge pump current, or ICP1, is one of the loop

gain parameters can be programmed to set and optimize PLL

www.national.com 28

LMH1982

1's loop response. For more information on setting the loop

response, see section 7.0 LOOP RESPONSE .

To minimize lock time, using a large or maximum ICP1 can

result in faster PLL settling time due to a wider loop band-

width. Once phase lock has been achieved, using a lower

ICP1 (that yields sufficient stability) can provide good input jitter

rejection due to a narrower loop bandwidth; this can be helpful

to minimize low-frequency input jitter from being transferred

to the output clocks.

Note: An ICP1 value ≤ 2 corresponds to an ICP1 current ≤ 62.5 µA. A low

ICP1 setting or low damping factor (DF) can cause reduced PLL sta-

bility and performance (e.g. wander, loss of lock) due to loop filter

charge leakage and other secondary factors; therefore, it is not rec-

ommended to use an ICP1 value less than 2d nor use an insufficient

DF setting.

ICP1 register range = 0 to 31d; 0 to 2d are not recommend-

ICP1 current = ICP1 x 31.25 µA (nominal current step)

Examples:

ICP1 = 8d (default) gives ICP1 = 250 µA nominal

ICP1 = 31d (max) gives ICP1 = 968.75 µA nominal

Bits 7-5: Reserved (RSV)

These RSV bits are reserved. When writing to this register,

only write the default data to the RSV bits as specified in Table

Bits 3-0: PLL 3 Charge Pump Current Control (ICP3)

ICP3 can be programmed to specify the charge pump current

for PLL 3, which generates the 74.176 and 148.35 MHz HD

clock outputs. Reducing the value of ICP3 will reduce the PLL

3 charge pump current and lower its loop bandwidth at the

expense of reduced PLL stability. An ICP3 value of 0 should

not be programmed since this corresponds to 0 µA nominal

current, which will cause PLL 3 to lose phase lock or otherwise

be unstable.

ICP3 register range = 0 to 15d

Bit 7-4: PLL 2 Charge Pump Current Control (ICP2)

ICP2 can be programmed to specify the charge pump current

for PLL 2, which generates the 74.25 and 148.5 MHz HD clock

outputs. Reducing the value of ICP2 will reduce the PLL 2

charge pump current and lower its loop bandwidth at the ex-

pense of reduced PLL stability. An ICP2 value of 0 should not

be programmed since this corresponds to 0 µA nominal cur-

rent, which will cause PLL 2 to lose phase lock or otherwise

be unstable.

ICP2 register range = 0 to 15d

9.10 Reserved Registers

This register is reserved. Do not program any data to these

registers.

29 www.national.com

LMH1982

10.0 TYPICAL SYSTEM BLOCK DIAGRAMS

30052407

FIGURE 9. Analog Reference Genlock for Triple-rate SDI Video

30052408

FIGURE 10. SDI Reference Genlock for Triple-rate SDI Video

www.national.com 30

LMH1982

30052409

FIGURE 11. Triple-rate SDI Loop-through

30052410

FIGURE 12. Combined Genlock or Loop-through for Triple-rate SDI Video

31 www.national.com

LMH1982

Physical Dimensions inches (millimeters) unless otherwise noted

32-Pin LLP

NS Package Number SQA32A

www.national.com 32

LMH1982

Notes

33 www.national.com

LMH1982

Notes

LMH1982 Multi-Rate Video Clock Generator with Genlock

For more National Semiconductor product information and proven design tools, visit the following Web sites at:

Products Design Support

Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench

Audio www.national.com/audio App Notes www.national.com/appnotes

Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns

Data Converters www.national.com/adc Samples www.national.com/samples

Interface www.national.com/interface Eval Boards www.national.com/evalboards

LVDS www.national.com/lvds Packaging www.national.com/packaging

Power Management www.national.com/power Green Compliance www.national.com/quality/green

Switching Regulators www.national.com/switchers Distributors www.national.com/contacts

LDOs www.national.com/ldo Quality and Reliability www.national.com/quality

LED Lighting www.national.com/led Feedback/Support www.national.com/feedback

Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy

PowerWise® Solutions www.national.com/powerwise Solutions www.national.com/solutions

Serial Digital Interface (SDI) www.national.com/sdi Mil/Aero www.national.com/milaero

Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic

Wireless (PLL/VCO) www.national.com/wireless Analog University® www.national.com/AU

THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION

(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY

OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO

SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,

IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS

DOCUMENT.

TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT

NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL

PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR

APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND

APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE

NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.

EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO

LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE

AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR

PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY

RIGHT.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and

whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected

to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform

can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other

brand or product names may be trademarks or registered trademarks of their respective holders.

For the most current product information visit us at www.national.com

National Semiconductor

Americas Technical

Support Center

Email: support@nsc.com

Tel: 1-800-272-9959

National Semiconductor Europe

Technical Support Center

Email: europe.support@nsc.com

National Semiconductor Asia

Pacific Technical Support Center

Email: ap.support@nsc.com

National Semiconductor Japan

Technical Support Center

Email: jpn.feedback@nsc.com