1
File Number 1563.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
IRFF120
6.0A, 100V, 0.300 Ohm, N-Channel
Power MOSFET
This N-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdown avalanche mode of operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
Formerly developmental type TA09594.
Features
• 6.0A, 100V
•r
DS(ON) = 0.300Ω
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC TO-205AF
Ordering Information
PART NUMBER PACKAGE BRAND
IRFF120 TO-205AF IRFF120
NOTE: When ordering, use the entire part number. G
D
S
DRAIN
(CASE) SOURCE
GATE
Data Sheet March 1999
2
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
IRFF120 UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS 100 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 100 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID6.0 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 24 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS ±20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD20 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.16 W/oC
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS 36 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ= 25oC to 125oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 10) 100 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V
Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - 25 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 125oC - - 250 µA
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V 6.0 - - A
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = 3.0A, VGS = 10V (Figures 8, 9) - 0.25 0.300 Ω
Forward Transconductance (Note 2) gfs VDS > ID(ON) x rDS(ON)MAX, ID = 3.0A (Figure 12) 1.5 2.9 - S
Turn-On Delay Time td(ON) VDD ≅ 0.5 x Rated BVDSS, ID=6.0A, RG = 9.1Ω,
VGS =10V (Figures 17, 18), RL=8Ωfor VDSS = 50V,
RL = 6.3Ω for VDSS = 40V, MOSFET Switching
Times are Essentially Independent of Operating
Temperatures
-2040ns
Rise Time tr-3770ns
Turn-Off Delay Time td(OFF) - 50 100 ns
Fall Time tf-3570ns
Total Gate Charge
(Gate to Source + Gate to Drain) Qg(TOT) VGS = 10V, ID = 6.0A, VDS = 0.8 x Rated BVDSS
(Figures 14, 19, 20) Gate Charge is Essentially
Independent of Operating Temperature
-1015nC
Gate to Source Charge Qgs - 6.0 - nC
Gate to Drain (“Miller”) Charge Qgd - 4.0 - nC
Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 450 - pF
Output Capacitance COSS -20-pF
Reverse Transfer Capacitance CRSS -50-pF
Internal Drain Inductance LD Measured from the Drain
Lead, 5.0mm (0.2in) from
Header to Center of Die
Modified MOSFET
Symbol Showing the
Internal Devices
Inductances
- 5.0 - nH
Internal Source Inductance LSMeasured from the Source
Lead, 5.0mm (0.2in) from
Header to Source Bonding
Pad
-15-nH
Thermal Resistance, Junction to Case RθJC - - 6.25 oC/W
Thermal Resistance, Junction to Ambient RθJA Free Air Operation - - 175 oC/W
LS
LD
G
D
S
IRFF120
3
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current ISD Modified MOSFET
Symbol Showing the
Integral Reverse P-N
Junction Rectifier
- - 6.0 A
Pulse Source to Drain Current (Note 3) ISM - - 24 A
Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 6.0A, VGS = 0V (Figure 13) - - 2.5 V
Reverse Recovery Time trr TJ = 150oC, ISD = 6.0A, dISD/dt = 100A/µs - 230 - ns
Reverse Recovery Charge QRR TJ = 150oC, ISD = 6.0A, dISD/dt = 100A/µs - 1.0 - µC
Forward Turn-On Time tON Intrinsic Turn-on Time is Negligible, Turn-On
Speed is Substantially controlled by LS + LD--- -
NOTES:
2. Pulse test: pulse width ≤300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 25V, starting TJ= 25oC, L = 1.5mH, RG= 25Ω, peak IAS = 6.0A (Figures 15, 16).
Typical Performance Curves Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
G
D
S
0 50 100 150
0
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0.2
0.4
0.6
0.8
1.0
1.2
2.4
1.2
025 50 75 100 125 150
4.8
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
6.0
3.6
t1, RECTANGULAR PULSE DURATION (s) 10
ZθJC, NORMALIZED
THERMAL IMPEDANCE
10-3 10-2 10-1 1
10-5 10-4
1.0
0.01
0.1
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1
SINGLE PULSE
0.1
0.02
0.2
0.5
0.01
0.05 t2
IRFF120
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FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves Unless Otherwise Specified (Continued)
1.0 10.0 100.0 200.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
50.0
10.0
1.0
0.1
ID, DRAIN CURRENT (A)
100µs
1ms
10µs
OPERATION IN THIS
AREA IS LIMITED
BY rDS(ON)
TJ= MAX RATED
10ms
100ms
DC
01020304050
VDS, DRAIN TO SOURCE VOLTAGE (V)
20
16
12
8
4
0
ID, DRAIN CURRENT (A)
80µs PULSE TEST
VGS = 7V
VGS = 6V
VGS = 5V
VGS = 4V
VGS = 8V
VGS = 9V
VGS = 10V
0
2
0123 5
4
6
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
8
4
10 80µs PULSE TEST
VGS = 9V
VGS = 10V
VGS = 8V
VGS = 7V
VGS = 6V
VGS = 5V
VGS = 4V
02 6
0
4
12
ID(ON), ON-STATE DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
20
8
16
4810
-55oC
VDS > ID(ON) x rDS(ON)MAX
80µs PULSE TEST
25oC
125oC
0
0.4
0.6
0.8
10 20 30 40
rDS(ON), DRAIN TO SOURCE
ID, DRAIN CURRENT (A)
0
0.2
VGS = 10V
VGS = 20V
ON RESISTANCE (Ω)
2µs PULSE TEST 2.50
1.50
1.00
0.50
0-40 0 40
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
ON REISITANCE
120
2.00
80
VGS = 10V
ID = 3A
IRFF120
5
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Typical Performance Curves Unless Otherwise Specified (Continued)
1.25
1.05
0.95
0.85
0.75 -40 0 40
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
120
1.15
80
ID = 250µA1000
200
010 20
C, CAPACITANCE (pF)
600
VDS, DRAIN TO SOURCE VOLTAGE (V)
800
400
CRSS
30 40 500
VGS = 0V, f = 1MHz
CRSS = CGD
COSS ≈ CDS + CGD
CISS = CGS + CGD
CISS
COSS
ID, DRAIN CURRENT (A)
gfs, TRANSCONDUCTANCE (S)
00481216
1
2
3
4
5
20
125oC
25oC
-55oC
80µs PULSE TEST
0231
10
100
ISD, SOURCE TO DRAIN CURRENT (A)
VSD, SOURCE TO DRAIN VOLTAGE (V)
150oC
25oC
2
5
2
5
1.0
Qg(TOT), TOTAL GATE CHARGE (nC)
VGS, GATE TO SOURCE (V)
00481216
5
10
15
20
VDS = 20V
VDS = 50V
20
VDS = 80V
ID = 6A
IRFF120
6
Test Circuits and Waveforms
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORM
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
tP
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VGS
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RG
DUT
+
-VDD
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
0.3µF
12V
BATTERY 50kΩ
VDS
S
DUT
D
G
IG(REF)
0
(ISOLATED
VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
SAME TYPE
AS DUT
Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
IG(REF)
0
IRFF120
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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IRFF120
