2010 Microchip Technology Inc. Advance Information DS39589C-page 1
PIC16F87XA
This document includes programming
specifications for the following devices:
1.0 PROGRAMMING THE
PIC16F87XA
The PIC16F87XA is programmed using a serial
method. The Serial mode will allow the PIC16F87XA to
be programmed while in the user’s system. This allows
for increa sed design fle xibility. This prog ramming spe c-
ification applies to PIC16F87XA devices in all
packages.
1.1 Programming Algorit hm
Requirements
The programming algorithm used depends on the
operating voltage (VDD) of the PIC16F87XA device, or
whether internal or external timing is desired.
Both algo rithms can b e used with th e two availabl e pro-
gramming entry methods. The first method follows the
normal Microchip Programming mode entry of holding
pins R B6 and RB 7 low , whil e raisin g MCLR pin from VIL
to VIHH (13V ± 0.5V). The second method, called Low
Vo lt a ge IC SPTM or LVP for short, appli es VDD to MCLR
and uses the I/O pin RB3 to ent er Programmin g mode.
When RB3 is driven to VDD from ground, the
PIC16F87XA device enters Programming mode.
1.2 Programming Mode
The Programming mode for the PIC16F87XA allows
programming of user program memory, data memory,
special locations used for ID, and the configuration
word.
Pin Diagr am s
• PIC16F873A • PIC16F876A
• PIC16F874A • PIC16F877A
Algorithm
#VDD Range Timing
12.0VVDD < 5.5V Internal; 4 ms/op
24.5VVDD 5.5V External; 1 ms/op
PDIP, SOIC
PIC16F876A/873A
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
Vss
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16F877A/874A
Flash Memory Programming Specification
PIC16F87XA
DS39589C-page 2 Advance Information 2010 Microchip Technology Inc.
TABLE 1-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F87XA
Pin Name During Programming
Function Pin Type Pin Description
RB3 PGM I Low voltage ICSP™ programming input if LVP
configuration bit equals ‘1’
RB6 CLOCK I Clock input
RB7 DATA I/O Data input/output
MCLR VTEST MODE P* Program Mode Select
VDD VDD P Pow er Supply
VSS VSS P Ground
Legend:I = Input, O = Output, P = Power
* To activate t he Pro gra mm ing mo de, high v oltage needs to be app li ed to the MC L R i np ut. Si nc e MCL R is used for a
level source, this means that MCLR does not draw any significant current.
2010 Microchip Technology Inc. Advance Information DS39589C-page 3
PIC16F87XA
2.0 PROGRAM MODE ENTRY
2.1 User Program Memory Map
The user m emory spac e extends from 000 0h to 1FFFh
(8 K words). In Programming mode, the program mem-
ory space extends from 0000h to 3FFFh, with the first
half (0000h - 1FFFh) being user program memory and
the second half (2000h - 3FFFh) being configuration
memory. The PC will increment from 0000h to 1FFFh
and wrap around to 0000h. From 2000h, the PC will
increm ent up to 3FFFh an d wra p arou nd to 20 00h (not
to 0000h). Once in configuration memory, the highest
bit of the PC stays a ‘1’, thus always pointing to the con-
figuration memory. The only way to point to user pro-
gram memory is to reset the part and re-enter
Program/Verify mo de, as descr ibed i n Section 2.4.
In the configura tio n m em ory space, 2 000 h - 200Fh a re
physically implemented. However, only locations
2000h thro ugh 2007h are available. Other locations are
reserved. Locations beyond 200Fh will physically
acce ss user memor y (see Figure 2-1).
2.2 Data EEPROM Memory
The EEPROM data memory space is a separate block
of high endurance memory that the user accesses,
using a special sequence of instructions. The amount
of data EEPROM memory depends on the device and
is sh own below in number of bytes.
The con tents of dat a EEPROM memory have th e capa-
bility to be embedded into the HEX file.
The progra mmer should be a ble to read data EEPROM
information from a HEX file and conversely (as an
option), write data EEPROM contents to a HEX file,
along with program memory information and
configu r ati on bit inf orm atio n.
The 256 data memory locations are logically mapped
start ing at add ress 21 00h. The format for dat a mem ory
storage is one data byte per address location, LSB
aligned.
Device # of Bytes
PIC16F873A 128
PIC16F874A 128
PIC16F876A 256
PIC16F877A 256
PIC16F87XA
DS39589C-page 4 Advance Information 2010 Microchip Technology Inc.
2.3 ID Locations
A user may store identification information (ID) in four
ID locations. The ID locati ons are mapped in addresses
2000h - 2003h. It is recommended that the user use
only the f our Lea st Si gni fic ant bits o f each ID l oc ation .
In some devices, the ID locations read out in an
unscrambled fashion after code protection is enabled.
For these devices, it is recommended that ID location
is written as “11 1111 1000 bbbb”, where ‘bbbb’ is
ID information.
In other devices, the ID locations read out normally,
even after code protection. To understand how the
devices behave, refer to Table 5-1.
FIGURE 2-1: PIC16F87 XA PROG RAM MEMORY MAPPING
4K word
devices 8K word
devices
Implemented Implemented
Implemented Implemented
Implemented Implemented
Implemented Implemented
Implemented
Reserved Implemented
Implemented
Implemented
Reserved Reserved
Reserved Reserved
ID Location
ID Location
ID Location
ID Location
Reserved
Reserved
Device ID
Configuration Word
2000h
2001h
2002h
2003h
2004h
2005h
2006h
2007h
000h
3FFh
400h
7FFh
800h
BFFh
C00h
FFFh
1000h
1FFFh
2008h
2100h
3FFFh
13FFh
1400h
17FFh
1800h
1BFFh
1C00h
2010 Microchip Technology Inc. Advance Information DS39589C-page 5
PIC16F87XA
2.4 Program/Verify Mode
The Program/Verify mode is entered by holding pins
RB6 and RB7 l ow, whi le rais ing MCL R pin from VIL to
VIHH (high voltage). In this mode, the state of the RB3
pin does not effect programming. Low Voltage ICSP
Programm ing mo de is en tered by rais ing RB 3 from V IL
to VDD, and then applying VDD to MCLR. Once in this
mode, the u se r p rog ram m em ory and t he configur atio n
memory can be accessed and programmed in serial
fashion . The mode of oper ation is serial , and the mem-
ory accessed is the user program memory. RB6 and
RB7 are Schmitt Trigger inputs in this mode.
The seque nce that enters the de vice in to the Program-
ming/Verify mode place s all o ther log ic int o the RESET
stat e (the MC LR pin w as ini tially at VIL). This mean s all
I/O are in the RESET state (high impedance inputs).
A device RESET will clear the PC and set the address
to ‘0’. The ‘Increment Address’ command will incre-
ment the PC. The ‘Load Configuration’ command will
set the PC to 2000h. The available commands are
shown in Table 2-1.
The normal sequence for programming eight program
memory words at a time is as follows:
1. Load a word at the current program memory
address using the ‘Load Data’ command.
2. Issue an ‘Increment Address’ command.
3. Load a word at the current program memory
address using the ‘Load Data’ command.
4. Repeat Step 2 and Step 3 six times.
5. Issue a ‘B egin Programming’ co mmand to begin
programming.
6. Wait tprog (abo ut 1 ms).
7. Issue an ‘End Programming’ command.
8. Increment to the next address.
9. Repeat this sequence as required to write
program and configuration memory.
The alternative sequence for programming one
program memory word at a time i s as follows:
1. Set a word f or the current memory lo cation using
the ‘Load Data’ command.
2. Issue a ‘Begin Programming Only’ command to
begin programming.
3. Wait tprog.
4. Issue an ‘End Programming’ command.
5. Increment to the next address.
6. Repeat this alternative sequence as required to
write program and configuration memory.
The address and program counter are reset to 0000h
by resetting the device (taking MCLR below VIL) and
re-entering Programm in g mo de. Progra m and con fig u-
ration memory may then be read or verified using the
‘Read Data’ and ‘Increment Address’ commands.
2.4.1 LOW VOLTAGE ICSP
PROGRAMMING MODE
Low Voltage ICSP Programming mode allows a
PIC16F87XA device to be programmed using VDD
only. However, when this mode is enabled by a config-
uration bit (LVP), the PIC16F87XA device dedicates
RB3 to control entry/exit into Programming mode.
When LVP bit is set to ‘1’, the low voltage ICSP pro-
gramming entry is enabled. Since the LVP configura-
tion bit allows low voltage ICSP programming entry in
its erased s t ate , an eras ed dev ic e w il l ha ve the LVP b it
enabled at the factory. While LVP is ‘1’, RB3 is dedi-
cated to low voltage ICSP programming. Bring RB3
and then, MCLR to VDD to enter Programming mode.
All other specifications for high voltage ICSP apply.
To disable Low Voltage ICSP mode, the LVP bit must
be program med to ‘0’. Th is must be do ne while entere d
with the High Voltage Entry mode (LVP bit = ‘1’). RB3
is now a general purpose I/O pin.
2.4.2 SERIAL PROGRAM/VERIFY
OPERATION
The RB6 pin is used as a clock input pin, and the RB7
pin is used to enter command bits, and to input or out-
put data during serial operation. To input a command,
the clock pin (RB6) is cycled six times. Each command
bit is latched on the falling edge of the clock, with the
Least Significant bit (LSb) of the command being input
first. The data on RB7 is required to have a minimum
setup (tset1) and hold (thold1) time (see AC/DC speci-
fications), with respect to the falling edge of the clock.
Commands with associated data (read and load) are
specified to have a minimum delay (tdly1) of 1 s
between the command and the data. After this delay,
the clock pin is cycled 16 times, with the first cycle
being a Start bit (0) and the last cycle being a Stop bit
(0). Data is transferred LSb first.
During a read operation, the LSb will be transmitted
onto RB7 on the rising edge of the second cycle, and
during a load operation, the LSb will be latched on the
falling edge of th e second cycle. A mini mum 1 s delay
(tdly2) is specified between consecutive commands.
All commands and data words are tra nsmitted LSb first.
The data is tran sm itt ed on the risi ng e dge, and latc he d
on the falling edge of the clock. To allow decoding of
commands and reversal of data pin configuration, a
time separation of at least 1 s (tdly1) is required
between a command and a data word, or another
command.
The avail able command s are described in the foll owing
paragraphs and listed in Table 2-1.
Note: The OSC must not have 72 osc clocks
while the devic e MCLR i s between VIL and
VIHH.
PIC16F87XA
DS39589C-page 6 Advance Information 2010 Microchip Technology Inc.
2.4.2.1 Load Configuration
After receiving this command, the program counter
(PC) will be s et to 2000h. By the n applying 16 c ycles to
the cloc k p in, t he chip will loa d 14 bits in a “da t a w o rd,”
as described above, to be programmed into the config-
uration memory. A description of the memory mapping
schemes of the program memory for normal operation
and configuration mode operation is shown in
Figure 2-1. After the configuration memory is entered,
the only way to get back to the user program memory
is to ex it the Program/V e rify Test m ode by ta king MCLR
low ( VIL).
2.4.2.2 Load Data for Program Memory
After receiving this command, the chip will load one
word (with 14 bits as a “data word”) to be programmed
into use r program m emory when 16 cycl es are app lied.
A timing diagram for this command is shown in
Figure 6-1.
2.4.2.3 Load Data for Data Memory
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied.
However, the data memory is only 8-bits wide, and
thus, onl y the first 8 bit s of dat a after the Start bit will be
prog ram me d i nt o the da ta m em ory. It is stil l ne ce ss ary
to cycl e the clo ck the fu ll 16 cy cles in order to al low the
internal circuitry to reset properly. The data memory
contains up to 256 bytes. If the device is
code-protected, the data is read as all zeros. A timing
diagram for this command is shown in Figure 6-2.
2.4.2.4 Read Data from Program Memory
After receiving this command, the chip will transmit
data bi ts out o f the pr ogram memor y (use r or co nfigu -
ration) currently ac ce ss ed , s t art ing w i th the s ec ond ri s-
ing edge of the clock input. The RB7 pin will go into
Output mode on the second rising clock edge, and it
will revert back to Input mode (high-impedance) after
the 16th ris ing edge. A timing dia gram of this comman d
is shown in Figure 6-3.
2.4.2.5 Read Data from Data Memory
After receiving this command, the chip will transmit
data bits out of the data memory, starting with the sec-
ond rising edge of the clock input. The RB7 pin will go
into Outp ut mod e on the sec ond risin g edg e, and it will
revert back to Input mode (high-impedance) after the
16th rising edge. As previously stated, the data mem-
ory i s 8-bits wide, a nd therefore , only th e first 8 b its th at
are output are actual data. A timing diagram for this
command is shown in Figure 6-4.
2.4.2.6 Increment Address
The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 6-5.
2.4.2.7 Begin Erase/Program Cycle
Eight locations must be loaded before every
‘Begin Erase/Programming’ command. After this
command is received and decoded, eight words of
program memory will be erased and programmed with
the values contained in the program data latches. The
PC address will decode which eight words are pro-
grammed. The lower three bits of the PC are ignored,
so if the PC points to address 003h, then all eight
locations from 000h to 007h are written.
An internal timing mechanism executes an erase
before write. The user must allow the combined time
for erase and programming, as specified in the electri-
cal specs, for programming to complete. No ‘End
Programming’ command is required.
1. If the address is pointing to user memory, the
user memory alone will be affected.
2. If the address is pointing to the physic ally imple-
mented test memory (2000h - 201Fh), test mem-
ory will be written. The configuration word will not
be written unless the address is specifically
pointi ng to 2007h.
This command can be used to perform programming
over the entire VDD range of the device.
A timing diagram for this command is shown in
Figure 6-6.
2.4.2.8 Begin Programming Only
This command is similar to the ‘Erase/Programming
Cycle’ command, except that a word erase is not
done, and the internal timer is not used. Programming
of pro gram an d data memo ry wil l begi n after this com-
mand is received and decoded. The user must allow
the time for programming, as specified in the electrical
specs, for programming to complete. An ‘End
Programming’ command is required.
The intern al ti mer is not used for thi s c omma nd, so the
‘End Programming’ command must be used to stop
programming.
1. If the address is pointing to user memory, the
user memory alone will be affected.
2. If the add ress i s poin ting to the phy sically impl e-
mented test memory (2000h - 201Fh), the test
memory will be written. The configuration word
will not be written unless the address is
specifically pointing to 2007h.
A timing diagram for this command is shown in
Figure 6-7.
Note 1: The code-protect bits cannot be erased
with this command.
2: All Begin Erase/Programming operations
can take place over the entire VDD range.
Note: Begin Programming Only operations must
take place at the 4.5V to 5.5V VDD range.
2010 Microchip Technology Inc. Advance Information DS39589C-page 7
PIC16F87XA
2.4.2.9 End Programming
After receiving this command, the chip stops program-
ming the memory (test program memory or user pro-
gram memo ry) that it was programmi ng at the tim e.
TABLE 2-1: COMMAND MAPPING FOR PIC16F87XA
Note: This command will also set the write data
shift l atche s to all ‘ 1’s to av oid is sues wit h
downloading only one word before the
write.
Command Mapping (MSB … LSB) Data Voltage Range
Load Configuration 000000, data (14), 0 2.2V - 5.5V
Load Data for Program Memory 000100, data (14), 0 2.2V - 5.5V
Read Data from Program Memory 001000, data (14), 0 2.2V - 5.5V
Inc remen t Address 00110 2.2V - 5.5V
Begin Erase/Programming Cycle 010004 ms typical,
internally timed 2.2V - 5.5V
Begin Programming Only Cycle 110001 ms typical,
externally timed 4.5V - 5.5V
Bulk Erase Program Memory 01001internally timed 4.5V - 5.5V
Bulk Erase Data Memory 01011internally timed 4.5V - 5.5V
Chip Erase 111114 ms typical,
internally timed 4.5V - 5.5V
Load Data for Data Memory 000110, data (14), 0 2.2V - 5.5V
Read Data from Data Memory 001010, data (14), 0 2.2V - 5.5V
End Programming 10111
PIC16F87XA
DS39589C-page 8 Advance Information 2010 Microchip Technology Inc.
2.5 Erasing Program and Data
Memory
Depen ding on the stat e of the co de protect ion bit s, pro-
gram and data memory will be erased using different
methods. The first two commands are used when both
program and data memories are not code-protected.
The third command is used when either memory is
code-protected, or if you want to also erase the fuse
locatio ns, in cludi ng the code-p rote ct bit s. A device p ro-
grammer should determine the state of the code pro-
tection bits and then apply the proper command to
erase the desired memory.
2.5.1 ERASING NON-CODE PROTECTED
PROGRAM AND DATA MEMORY
When both program and data memories are not
code-pro tec ted, they mu st be in div id ually era sed using
the follow ing co mman ds. The onl y way that bot h mem-
ories are erased using a single command is if code pro-
tection is enabled for one of the memories. These
commands do not erase the configuration word or ID
locations.
2.5.1.1 Bulk Erase Program Memory
When this command is performed, and is followed by
a ‘Begin Erase/Programming’ command, the entire
progra m me mor y wi ll be eras ed.
If the addr ess is pointi ng t o user mem ory, only th e user
memory will be erased.
If the address is pointing to the test program memory
(2000h - 201Fh), then both the user memory and the
test memory will be erased. The configuration word
will not be erased, even if the address is pointing to
location 2007h.
Previously, a load data with 0FFh command was rec-
ommend ed befor e any Bulk E rase. On th ese devic es,
this will not be required.
The Bulk Erase command is disabled when the CP bit
is programmed to ‘0’ enabling code-protect.
A timing diagram for this command is shown in
Figure 6-8.
2.5.1.2 Bulk Erase Data Memory
When this command is performed, and is followed by
a ‘Begin Erase/Programming’ command, the entire
data memory will be erased.
The Bulk Erase Data command is disabled when the
CPD bit is programmed to ‘0’ enabling protected data
memor y. A ti ming dia gram fo r this comm and is shown
in Figure 6-9.
2.5.1.3 Chip Erase
This command, when performed, will erase the pro-
gram memory, EE data memory, and all of the fuse
locations, including the code protection bits. All
on-chip Flash and EEPROM memory is erased,
regardless of the address contained in the PC.
When a Chip Erase command is issued and the PC
points to (0000h - 1FFFh), the configuration word and
the user program memory will be erased, but not the
test row (see Section 2.5.2.1). Chip Erase can also be
used to erase co de-p rote cte d m em ory, a s desc rib ed in
Section 2.5.2.
This command will also erase the code-protect and
code-protect data fuses if they are programmed. This
is the only command that allows a user to erase the
code-protect fuses.
The Chip Erase is internally self-timed to ensure that
all program and data memory is erased before the
code-protect bits are erased. A timing diagram for this
comma nd is sh own in Figu re 6-10.
2.5.2 ERASING CODE PROTECTED
MEMORY
For the PIC16F87XA devices, once code protection is
enabled, all protected program and data memory loca-
tions read all ‘0’s and further programming is disabled.
The ID locations and configuration word read out
unscram bl ed and can be rep rogra mm ed norma ll y. The
only comma nd to erase a code-protected PIC16F8 7XA
device is the Chip Erase. This erases program mem-
ory, data memory, configuration bits and ID locations.
Since all dat a wit hin the program and data memory
will be era sed wh en this co mmand i s execu ted, the
security of the data or code is not compromised.
2.5.2.1 Chip Erase
This command, when performed, will erase the pro-
gram memory, dat a EEPROM, and al l of the fuse loc a-
tions, including the code protection bits, code-protect
fuses, and code-protect data fuses. All on-chip Flash
and EEPROM memory is erased, regardless of the
address contained in the PC.
If the PC points to user memory, the test row (2000h
through 201Fh) is not erased with a Chip Erase com-
mand, except for the configuration word (at 2007h). If
the test row is to be completely erased, the address in
the PC must point to configuration memory.
When the PC points to 2000h - 201Fh, the configura-
tion w ord, tes t prog ram m emory, and the u ser program
memory will all be er ased with a Chi p Erase comm and.
This allows the user to erase all program and configu-
ration content, including the code-protect bits, without
compromising the user ID bits (2000h through 2004h),
or any pass code s sto r ed in the tes t row.
Note: All Bulk Erase operations must take place
at the 4.5V to 5.5V VDD range.
Note: The Chip Erase operation must take place
at the 4.5V to 5.5V VDD range.
2010 Microchip Technology Inc. Advance Information DS39589C-page 9
PIC16F87XA
The Ch ip Erase is in ternally self-ti med to ensure tha t all
program and data memory is erased before the
code-protect bits are erased.
A timing diagram for this command is shown in
Figure 6-10.
FIGURE 2-2: ALGORITHM 1 FLOWCHART – PROGRAM MEMORY (2.0V VDD < 5.5V)
Note: The Chip Erase operation must take place
at the 4.5V to 5.5V VDD range.
Start
Set VDD = VDDP
All Locations
Done?
Verify all
Locations
Data Correct?
End
Increment
Address
Command
Report Verify
Error
No
No
Load Data
Eight Loads
Done?
Begin
Erase/Programming
Increment
Address
Command
No
Command
Yes
Command
Wai t tprog2
(8 ms)
PIC16F87XA
DS39589C-page 10 Advance Information 2010 Microchip Technology Inc.
FIGURE 2-3: ALGORITHM 2 FLOWCHART – PROGRAM MEMORY (4.5V VDD 5.5V)
Start
Set VDD = VDDP
Wait tprog1
All Locations
Done?
End
No
Begin
Programming Only
Command
Chip Erase
Sequence
Verify all
Data Correct?
Locations
Increment
Address
Command
No
Report Verify
Error
(1 ms)
Programming
End
Command
Load Data
Eight Loads
Done?
Increment
Address
Command
No
Command
Yes
Yes
Yes
2010 Microchip Technology Inc. Advance Information DS39589C-page 11
PIC16F87XA
FIGURE 2-4: FLOWCHART – PIC16F87XA CONFIGURATION MEMORY (2.0V VDD < 5.5V)
Program ID
Start
Load
Configuration
Data
Location? Program Four Read Data
Command
Data Correct?
Report
Programming
Failure
Increment
Address
Command
Increment
Address
Command
Increment
Address
Command
Increment
Address
Command
Program
(Config. Word)
Read Data
Command
Data Correct?
Report Program
Configuration
Word Error
End
Yes
No
Yes
No
No
Yes
Yes
No
Load Data
Command
Begin
Erase/Program
Command
Wait tprog2
Address =
2004h?
PROGRAM
FOUR LOCATIONS
Load Data
Command
Begin
Erase/Program
Command
Wait tprog2
PROGRAM
CONFIGURATION WORD
End
Start
Locations
Start
Four Loads
Done?
Increment
Address
Command
No
Yes
End
(Set PC=2000h)
Address =
2003h?
Increment
Address
Command
No
Yes
Load
Configuration
Data
(8 ms)
(8 ms)
PIC16F87XA
DS39589C-page 12 Advance Information 2010 Microchip Technology Inc.
FIGURE 2-5: FLOWCHART – PIC16F87XA CONFIGURATION MEMORY (4.5V VDD 5.5V)
Increment
Address
Command
Increment
Address
Command
Increment
Address
Command
Program
(Config. Word)
Read Data
Command
Data Correct?
Report Program
Configuration
Word Error
End
Yes
No
Load Data
Command
Begin
Erase/Program
Command
Wait tprog2
PROGRAM
FOUR LOCATIONS
Load Data
Command
Begin
Program Only
Command
Wait tprog1
PROGRAM
CONFIGURATION WORD
End
Start
Start
Four Loads
Done?
Increment
Address
Command
No
Yes
End
End
Programming
Command
Program ID
Start
Load
Configuration
Data
Location? Program Four Read Dat a
Command
Data Correct?
Report
Programming
Failure
Increment
Address
Command
Yes
No
No
Yes
Yes
No
Address =
2004h?
Locations
(Set PC=2000h)
Address =
2003h?
Increment
Address
Command
No
Yes
Load
Configuration
Data
Chip Erase
(1 ms)
(8 ms)
2010 Microchip Technology Inc. Advance Information DS39589C-page 13
PIC16F87XA
3.0 CONFIGURATION WORD
The PIC16F87XA has several configurati on bits. These
bits can be s et (reads ‘0’), or left u nchanged (reads ‘1 ’),
to select various device configurations.
3.1 Device ID W ord
The device ID word for the PIC16F87XA is located at
2006h.
REGISTER 3-1: CONFIGURATION WORD REGISTER
TABLE 3-1: DEVICE ID VALUE
Device Dev ice ID Value
Dev Rev
PIC16F873A 00 1110 0100 XXXX
PIC16F874A 00 1110 0110 XXXX
PIC16F876A 00 1110 0000 XXXX
PIC16F877A 00 1110 0010 XXXX
R/P-1 U-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 U-1 R/P-1 R/P-1 R/P-1 R/P-1
CP — DEBUG WRT1 WRT0 CPD LVP BOREN ——PWRTENWDTEN FOSC1 FOSC0
bit 13 bit 0
bit 13 CP: Flash Progra m Mem ory Code Protect ion bit
(PIC16F877A/876A):
1 = Code protection off
0 = 0000h to 1FFFh code-protected
(PIC16F874A/873A):
1 = Code protection off
0 = 0000h to 0FFFh code-protected
1000h to 1FFFh wraps to 0000h to 0FFFh
bit 12 Unimplemented: Read as ‘1’
bit 11 DEBUG: Background Debugger Mode bit
1 = Background debugger functions not enabled
0 = Background debugger functional
bit 10-9 WRT<1:0>: Flash Program Memory Write Enable bits
(PIC16F877A/876A):
11 = Write protection off
10 = 0000h to 00FFh write protected, 0100h to 1FFFh may be modified by EECON control
01 = 0000h to 07FFh write protected, 0800h to 1FFFh may be modified by EECON control
00 = 0000h to 0FFFh write protected, 1000h to 1FFFh may be modified by EECON control
(PIC16F874A/873A):
11 = Write protection off
10 = 0000h to 00FFh write protected, 0100h to 0FFFh may be modified by EECON control
01 = 0000h to 03FFh write protected, 0400h to 0FFFh may be modified by EECON control
00 = 0000h to 07FFh write protected, 0800h to 1FFFh may be modified by EECON control
bit 8 CPD: Data EE Memory Code Protection bit
1 = Code protection off
0 = Data EE memory code-pr otected
bit 7 LVP: Low Voltage Programming Enable bit
1 = RB3/PGM pin has PGM function, low voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6 BOREN: Brown-out Reset Enable bit
1 = BOR enabled
0 = BOR disabled
bit 5-4 Unimplemented: Read as ‘1’
bit 3 PWRTEN: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 2 WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0 FOSC<1:0>: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
-n = Default value 1 = Bit is erased 0 = Bit is programmed x = Bit is unknown
PIC16F87XA
DS39589C-page 14 Advance Information 2010 Microchip Technology Inc.
4.0 EMBEDDING CONFIGURATION WORD AND ID INFORMATION IN HEX FILE
To allow portab ility of code, the pro grammer is required to read the configurati on word and ID locati ons from the HEX
file whe n loading the H EX file. If conf iguration word i nformation w as not prese nt in the HEX fil e, then a simple warning
message may be issued. Similarly, while saving a HEX file, configuration word and ID information must be included.
An option to not include this information may be provided.
Specifically for the PIC16F87XA, the EEPROM data memory should also be embedded in the HEX file (see
Section 2.2).
Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.
2010 Microchip Technology Inc. Advance Information DS39589C-page 15
PIC16F87XA
5.0 CHECKSUM COMPUTATION
Checksum is calculated by reading the contents of the
PIC16F87XA memory locations and adding up the
opcodes up to the maximum user addressable location,
e.g., 0x1FF for the PIC16F87XA. Any carry bits
exceed ing 16 -bit s are neg lecte d. Fina lly, the c onfigu ra-
tion word (appropriately masked) is added to the
checksum. Checksum computation for each member of
the PIC16F87XA devices is shown in Table 5-1.
The checksum is calculated by summing the following:
• The contents of all program memory locations
• The configuration word, appropriately masked
• Masked ID locations (when applicable)
The Least Significant 16 bits of this sum are the
checksum.
The following table describes how to calculate the
checksum for each device. Note that the checksum cal-
culation differs depending on the code-protect setting.
Since the program memory locations read out differ-
ently depending on the code-protect setting, the table
describ es how t o m ani pu late the actua l p rogra m m em -
ory values to simulate the values that would be read
from a p rotecte d dev ice. W hen c alculati ng a c heck sum
by reading a device, the entire program memory can
simply be read and summed. The configuration word
and ID locations can always be read.
Note tha t some ol der devices ha ve an add itional value
added in the checksum. This is to maintain comp atibility
with older device programmer checksums.
TABLE 5-1: CHECKSUM COMPUTATION
Device Code
Protect Checksum* Blank
Value
25E6h at 0
and max
address
PIC16F873A OFF SUM[0000:0FFF] + (CFGW & 2FCF) 1FCF EB9D
ON (CFGW & 2FCF) + SUM_ID 4F9E 1B6C
PIC16F874A OFF SUM[0000:0FFF] + (CFGW & 2FCF) 1FCF EB9D
ON (CFGW & 2FCF) + SUM_ID 4F9E 1B6C
PIC16F876A OFF SUM[0000:1FFF] + (CFGW & 2FCF) 0FCF DB9D
ON (CFGW & 2FCF) + SUM_ID 1F9E EB6C
PIC16F877A OFF SUM[0000:1FFF] + (CFGW & 2FCF) 0FCF DB9D
ON (CFGW & 2FCF) + SUM_ID 1F9E EB6C
Legend:CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = ID locations masked by 0Fh then made into a 16-bit value with ID0 as the most significant nibble.
For example, ID0 = 01h, ID1 = 02h, ID3 = 03h, ID4 = 04h, then SUM_ID = 1234h
*Checksum = [Sum of all the individual expressions] MODULO [FFFFh]
+ = Addition
& = Bitwise AND
PIC16F87XA
DS39589C-page 16 Advance Information 2010 Microchip Technology Inc.
6.0 PROGRAM/VER IFY MODE ELECTRICAL CHARACTERISTICS
TABLE 6-1: TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
AC/DC CHARACTERISTICS
POWER SUPPLY PINS
Standard Operating Procedure (unless otherwise stated)
Operating temperature 0 TA +70°C
Operating Voltage 2.0V VDD 5.5V
Characteristics Sym Min Typ Max Units Conditions/Comments
General
VDD level for Begin Erase/Program
operations and EECON write of
program memory
VDD 2.0 —5.5 V
VDD level for Begin Erase/Program
operations and EECON write of data
memory
VDD 2.0 —5.5 V
VDD level for Bulk Erase/Write, Chip
Erase, and Begin Program operations,
of program and data memory
VDD 4.5 —5.5 V
Begin Programming Only cycle time tprog1 1 — — ms Externally Timed
Begin Erase/Programming tprog2 10 ms — — ms Internally Timed
Chip Erase cycle time tprog3 10 ms — — ms Internally Timed
High volt a ge on M C LR and
RA4/T0CKI for Test mode entry VIHH VDD + 3.5 — 13.5 V
MCLR rise time (VSS to VHH) for
Test mode entry tVHHR — — 1.0 s
(RB6, RB7) input high level VIH10.8VDD — — V Schmitt Trigger input
(RB6, RB7) input low level VIL10.2VDD — — V Schmitt Trigger input
RB<7:4> setup time before MCLR
(Test mode selection pattern setup
time)
tset0 100 — — ns
RB<7:4> hold time after MCLR (Test
mode selection pattern setup time) thld0 5 — — s
Serial Program/Verify
Data in setup ti me bef ore clocktset1 100 — — ns
Data in hold time after clockthld1 100 — — ns
Data i nput not driv en to next clock input
(delay required between
command/data or command/command)
tdly1 1.0 — — s2.0V VDD < 4.5V
100 — — ns 4.5V VDD 5.5V
Delay between clock to clock
of next command or data tdly2 1.0 — — s2.0V VDD < 4.5V
100 — — ns 4.5V VDD 5.5V
Clock to data out valid
(during read dat a) tdly3 80 — — ns
2010 Microchip Technology Inc. Advance Information DS39589C-page 17
PIC16F87XA
FIGURE 6-1: LOAD DATA FOR USER PROGRAM MEMORY COMMAND (PROGRAM/VERIFY)
FIGURE 6-2: LOAD DAT A FOR USER DATA MEMORY COMMAN D (PROGRAM/VERIFY)
FIGURE 6-3: READ DATA FROM PROGRAM MEMORY COMMAND (PROGRAM/VERIFY)
MCLR VIHH
tset0
RB6
(CLOCK)
RB7
(DATA)
RESET
tset1
thld1
tdly1
1 s min
Program/Verify Test Mode
tset1
thld1
100 ns min
1 s min
tdly2
12 3 4 56
01000X
12 34 5 15
16
strt_bit stp_bit
100 ns min
}
thld0
}
}
}
MCLR VIHH
tset0
RB6
(CLOCK)
RB7
(DATA)
RESET
tset1
thld1
tdly1
1 s min
Progr am/ Verify Test Mode
tset1
thld1
100 ns min
1 s min
tdly2
12 34 56
11000X
12 34 5 15
16
strt_bit stp_bit
100 ns min
}
thld0
}
}
}
MCLR VIHH
tset0
RB6
(CLOCK)
RB7
(DATA)
RESET
tdly1
1 s min
Program/Verify Test Mode
tset1 thld1
1 s min
tdly2
12 34 56
00100
X
12 34 515
16
100 ns min
}
}
tdly3
RB7 = input RB7 = output RB7
input
thld0
bit 0 bit 13
PIC16F87XA
DS39589C-page 18 Advance Information 2010 Microchip Technology Inc.
FIGURE 6-4: READ DATA FROM DATA MEMORY COMMAND (PROGRAM/VERIFY)
FIGURE 6-5: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)
FIGURE 6-6: BEGIN ERASE/PROGRAMING COMMAND (PROGRAM/VERIFY)
MCLR VIHH
tset0
RB6
(CLOCK)
RB7
(DATA)
RESET
tdly1
1 s min
Program/Verify Test Mode
tset1 thld1
1 s min
tdly2
12 34 56
101 0 0
X
12 34 515
16
100 ns min
}
}
tdly3
RB7 = input RB7 = output RB7
input
thld0
bit 0 bit 13
MCLR VIHH
RB6
(CLOCK)
RB7
(DATA)
RESET
tdly1
1 s m in
Program/Verify Test Mode
tset1 thld1
1 s min
tdly2
12 3 4 56
011 0X
12
100 ns min
}
}
X0
0
Next Command
MCLR VIHH
RB6
(CLOCK)
RB7
(DATA)
RESET Progr am /Verify Test Mo de
tset1 thld1
tprog2
12 3 4 56
010X
12
}
}
X0
Next Command
00
tdly1
100 ns min
2010 Microchip Technology Inc. Advance Information DS39589C-page 19
PIC16F87XA
FIGURE 6-7: BEGIN PROGRAMING ONLY COMMAND (PROGRAM/VERIFY)
FIGURE 6-8: BULK ERASE PROGRAM MEMORY COMMAND (PROGRAM/VERIFY)
FIGURE 6-9: BULK ERASE DATA MEMORY COMMAND (PROGRAM/VERIFY)
MCLR VIHH
RB6
(CLOCK)
RB7
(DATA)
RESET Program/Verify Test Mode
tset1 thld1
tprog1
12 3 4 56 12
100 ns min
}
}
10
End Programming Command
011X
00
tdly1
6
1 s min
tdly2
MCLR VIHH
RB6
(CLOCK)
RB7
(DATA)
RESET Program/Verify Test Mode
tset1
thld1
12 3 4 56
100 0X
12
100 ns min
}
}
X0
1
tdly2 Begin Erase/Programming
tdly1
Command
1 s min
MCLR VIHH
RB6
(CLOCK)
RB7
(DATA)
RESET Program/Verify Test Mode
tset1
thld1
tdly2
12 3 4 56
1100X
12
100 ns min
}
}
X0
1
tdly1
Begin Erase/Programming
Command
1 s min
PIC16F87XA
DS39589C-page 20 Advance Information 2010 Microchip Technology Inc.
FIGURE 6-10: CHIP ERASE COMMAND (PROGRAM/VERIFY)
MCLR VIHH
RB6
(CLOCK)
RB7
(DATA)
RESET Program/Verify Test Mode
tset1
thld1
tprog3
1234 56
111 1X
12
100 ns min
}
}
X0
1
Next Command
tdly1
2010 Microchip Technology Inc. Advance Information DS39589C-page 21
Information contained in this publication regarding device
applications a nd t he lik e is provided only f or your con ve nience
and may be su perseded by updates. I t is your res ponsibil ity to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC , PI Cmi cro, PI CSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor ,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE, In-Circuit Se r i a l
Programming, ICSP, Mindi, MiWi, MPAS M, MPLA B Cert ified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that i ts family of products is one of the most secure families of it s kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCU s and d sPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39589C-page 22 Advance Information 2010 Microchip Technology Inc.
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