SRAM
AS5LC1008
AS5LC1008
Rev. 1.3 03/11
Micross Components reserves the right to change products or specifi cations without notice.
1
FEATURES
• High-speed access times of 10, 12, 15 and 20 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for greater noise
immunity
• Easy memory expansion with CE\ and OE\ options
• CE\ power-down
• Fully static operation: no clock or refresh required
• TTL compatible inputs and outputs
• Single 3.3V power supply
• TSOPII in Copper Lead Frame for superior thermal
characteristics
• RoHS compliant options available
128K x 8 SRAM
High-Speed CMOS SRAM with
3.3V Revolutionary Pinout
PIN ASSIGNMENT
(Top View)
32-Pin, 400-mil
Plastic SOJ (DJ) & Plastic TSOPII (DGC & DGCR)
GENERAL DESCRIPTION
The AS5LC1008 is a very high-speed, low power,
131,072-word by 8-bit CMOS static RAM in revolutionary
pinout. The AS5LC1008 is fabricated using high-performance
CMOS technology. This highly reliable process coupled with
innovative circuit design techniques, yields higher performance
and low power consumption devices.
When CE\ is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down to 250μW (typical) with CMOS input levels.
The AS5LC1008 operates from a single 3.3V power supply
and all inputs are TTL-compatible.
OPTIONS MARKING
• Timing
10ns access -10
12ns access -12
15ns access -15
20ns access -20
• Package
Plastic SOJ (32-pin, 400-mil) DJ No. 906
Plastic TSOPII (32-pin, 400-mil) DGC1
Plastic TSOPII (RoHS Compliant) DGCR1
• Operating Temperature Ranges
-Military (-55oC to +125oC) /XT
-Industrial (-40oC to +85oC) /IT
• 2V Data Retention / Low Power L
Note 1:Contact factory on Copper Lead Frame
For more products and information
please visit our web site at
www.micross.com
PIN FUNCTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A0
A1
A2
A3
CE\
I/O 0
I/O 1
Vcc
GND
I/O 2
I/O 3
WE\
A4
A5
A6
A7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE\
I/O 7
I/O 6
GND
Vcc
I/O 5
I/O 4
A12
A11
A10
A9
A8
PIN DESCRIPTION
A0 - A16 Address Inputs
CE\ Chip Enable Input
OE\ Output Enable Input
WE\ Write Enable Input
I/O0 - I/O7 Bidirectional Ports
VCC Power
GND Ground
SRAM
AS5LC1008
AS5LC1008
Rev. 1.3 03/11
Micross Components reserves the right to change products or specifi cations without notice.
2
ABSOLUTE MAXIMUM RATINGS*
Terminal Voltage with Respect to GND (VTERM).........................................................................................-0.5V to VCC + 0.5V
Temperature Under Bias (TBIAS).........................................................................................................................-55°C to +125°C
Storage Temperature (TSTG)................................................................................................................................-65°C to +150°C
Power Dissipation (PT)...........................................................................................................................................................1.0W
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operation section of this specifi cation is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
Mode WE
\
CE
\
OE\ I/O Operation
Not Selected
(Power-down) X H X High-Z
Output Disabled H L H High-Z
Read H L L D
OUT
Write L L X D
IN
A0 - A16
VCC
GND
I/O0 - I/O7
CE\
OE\
WE\
DECODER 128K x 8
MEMORY ARRAY
I/O DATA
CIRCUIT COLUMN I/O
CONTROL
CIRCUIT
SRAM
AS5LC1008
AS5LC1008
Rev. 1.3 03/11
Micross Components reserves the right to change products or specifi cations without notice.
3
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
Output HIGH Voltage V
OH
V
CC
= Min., I
OH
= -4.0mA 2.4 --- V
Output LOW Voltage V
OL
V
CC
= Min., I
OL
= 8.0mA --- 0.4 V
Input HIGH Voltage V
IH
2.2 V
CC
+ 0.3 V
Input LOW Voltage
1
V
IL
-0.3 0.8 V
Input Leakage I
LI
GND < V
IN
< V
CC
-5 5 μA
Output Leakage I
LO
GND < V
OUT
< V
CC
;
Outputs Disabled -5 5 μA
NOTE: 1. VIL = -3.0V for pulse width less than 10ns.
POWER SUPPLY CHARACTERISTICS1
(-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V)
NOTE: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE1,2
PARAMETER SYMBOL CONDITIONS MAX UNIT
Input Capacitance CIN VIN = 0V 6pF
Input/Output Capacitance CI/O VOUT = 0V 8pF
NOTE:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1MHz, VCC = 3.3V.
PARAMETE
R
SYM CONDITIONS MIN MA
X
MIN MA
X
MIN MA
X
MIN MA
X
UNIT
VCC Dynamic Operating
Supply Current ICC
VCC = Max, CE\ = VIL,
IOUT = 0 mA, f = Max --- 105 --- 100 --- 95 --- 90 mA
ISB
VCC = Max, VIN = VIH or VIL
CE\ > VIH, f = Max --- 35 --- 30 --- 25 --- 20 mA
ISB1
VCC = Max, VIN = VIH or VIL
CE\ > VIH, f = 0 --- 20 --- 20 --- 20 --- 20 mA
CMOS Standby Current
(CMOS Inputs) ISB2
VIN > VCC - 0.2V,
or VIN < 0.2V, f = 0 --- 2 --- 2 --- 2 --- 2 mA
-10 -12 -20
TTL Standby Current
(TTL Inputs)
-15
SRAM
AS5LC1008
AS5LC1008
Rev. 1.3 03/11
Micross Components reserves the right to change products or specifi cations without notice.
4
READ CYCLE SWITCHING CHARACTERISTICS1
(-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V)
NOTES:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and C1 output loading speci-
fi ed in Figure 1.
2. Tested with the C2 load in Figure 1. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
PARAMETER UNIT
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3ns
Input and Output timing and Reference Levels 1.5V
Output Load See Figures 1 and 2
FIGURE 1 FIGURE 2
AC TEST LOADS
PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT
Read Cycle Time tRC 10 --- 12 --- 15 --- 20 --- ns
Address Access Time tAA --- 10 --- 12 --- 15 --- 20 ns
Output Hold time tOHA 2 --- 2 --- 2 --- 2 --- ns
CE\ Access Time tACE --- 10 --- 12 --- 15 --- 20 ns
OE\ Access Time tDOE --- 5 --- 6 --- 7 --- 8 ns
OE\ to Low-Z Output tLZOE
20 --- 0 --- 0 --- 0 --- ns
OE\ to High-Z Output tHZOE
205060708ns
CE\ to Low-Z Output tLZCE
22 --- 2 --- 2 --- 2 --- ns
CE\ to High-Z Output tHZCE
205060708ns
-10 -12 -20-15
30pF including
jig & scope
SRAM
AS5LC1008
AS5LC1008
Rev. 1.3 03/11
Micross Components reserves the right to change products or specifi cations without notice.
5
DATA RETENTION SWITCHING CHARACTERISTICS (Low Power “L” Version)
Symbol Parameter TestCondition Min. Typ. Max.Unit
VDR VDDforDataRetention SeeDataRetentionWaveform 2.0 Ͳ 3.6 V
IDR DataRetentionCurrent VDD=2.0V,CE\шVDDͲ0.2V Ͳ Ͳ 2mA
ISDR DataRetentionSetupTime SeeDataRetentionWaveform 0 Ͳ Ͳ ns
IRDR RecoveryTime SeeDataRetentionWaveform tRC Ͳ Ͳ ns
NOTES:
1. Typical values are measured at VDD=3.0V, TA=25oC and not 100% tested.
VDD
CE ≥ V
DD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
Data Retention Mode
DATA RETENTION SWITCHING WAVEFORM (CE\ Controlled)
SRAM
AS5LC1008
AS5LC1008
Rev. 1.3 03/11
Micross Components reserves the right to change products or specifi cations without notice.
6
READ CYCLE #11,2
READ CYCLE #21,3
NOTES:
1. WE\ is HIGH for a Read Cycle.
2. The device is continuously selected. OE\, CE\ = VIL.
3. Address is valid prior to or coincident with CE\ LOW transitions.
SRAM
AS5LC1008
AS5LC1008
Rev. 1.3 03/11
Micross Components reserves the right to change products or specifi cations without notice.
7
WRITE CYCLE SWITCHING CHARACTERISTICS1,3
(-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V)
WRITE CYCLE #11,2 (CE\ Controlled, OE\ = HIGH or LOW)
NOTES:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specifi ed
in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defi ned by the overlap of CE\ LOW and WE\ LOW. All signals must be in valid states to initiate a Write, but any one can go
inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
-10
PARAMETE
R
SYMBOL MIN MA
X
MIN MA
X
MIN MA
X
MIN MA
X
UNITS
Write Cycle Time tWC 10 --- 12 --- 15 --- 20 --- ns
CE\ to Write End tSCE 7 --- 8 --- 9 --- 10 --- ns
Address Setup Time to Write End tAW 8 --- 9 --- 10 --- 12 --- ns
Address Hold from Write End tHA 0 --- 0 --- 0 --- 0 --- ns
Address Setup Time tSA 0 --- 0 --- 0 --- 0 --- ns
WE\ Pulse Width (OE\ HIGH) tPWE1
17 --- 8 --- 9 --- 10 --- ns
WE\ Pulse Width (OE\ LOW) tPWE2
210 --- 12 --- 12 --- 15 --- ns
Data Setup to Write End tSD 5 --- 6 --- 7 --- 8 --- ns
Data Hold to Write End tHD 0 --- 0 --- 0 --- 0 --- ns
WE\ LOW to High-Z Output tHZWE
2--- 5 --- 6 --- 7 --- 8 ns
WE\ HIGH to Low-Z Output tLZWE
22 --- 2 --- 2 --- 2 --- ns
-20-12 -15
SRAM
AS5LC1008
AS5LC1008
Rev. 1.3 03/11
Micross Components reserves the right to change products or specifi cations without notice.
8
NOTES:
1. The internal write time is defi ned by the overlap of CE\ LOW and WE\ LOW. All signals must be in valid states to initiate a Write, but any one can go
inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE\ • VIH.
WRITE CYCLE #3 (WE\ Controlled, OE\ = LOW during Write Cycle)
WRITE CYCLE #21 (WE\ Controlled, OE\ = HIGH during Write Cycle)
SRAM
AS5LC1008
AS5LC1008
Rev. 1.3 03/11
Micross Components reserves the right to change products or specifi cations without notice.
9
32-Pin TSOPII (Package Designator DGC & DGCR)
MECHANICAL DEFINITION
Micross Components reserves t
h
e rig
h
t to c
h
ange pro
d
ucts or
s
9
SRAM
AS5LC1008
AS5LC1008
Rev. 1.3 03/11
Micross Components reserves the right to change products or specifi cations without notice.
10
Micross Case #906 (Package Designator DJ)
MECHANICAL DEFINITION*
* All measurements are in inches.
MIN MAX
A 0.128 0.148
A1 0.025 ---
A2 0.082 ---
B 0.015 0.020
b 0.026 0.032
C 0.007 0.013
D 0.820 0.830
E 0.435 0.445
E1 0.395 0.405
E2
e
0.370 BSC
0.050 BSC
SYMBOL MICROSS SPECIFICATIONS
SRAM
AS5LC1008
AS5LC1008
Rev. 1.3 03/11
Micross Components reserves the right to change products or specifi cations without notice.
11
ORDERING INFORMATION
*AVAILABLE PROCESSES
IT = Industrial Temperature Range -40oC to +85oC
XT = Military Temperature Range -55oC to +125oC
**OPTION DEFINITIONS
L = 2V Data Retention / Low Power
Plastic SOJ w/ Alloy 42 Lead Fram
e
Device Number Package
Type Speed
ns Options** Process
AS5LC1008 DJ -10 L
/
*
AS5LC1008 DJ -12 L
/
*
AS5LC1008 DJ -15 L
/
*
AS5LC1008 DJ -20 L
/
*
Plastic TSOPII w/ Copper Lead Frame
(
Sn/Pb Lead Finish
)
Device Number Package
Type Speed
ns Options** Process
AS5LC1008 DGC -10 L
/
*
AS5LC1008 DGC -12 L
/
*
AS5LC1008 DGC -15 L
/
*
AS5LC1008 DGC -20 L
/
*
Plastic TSOPII w/ Copper Lead Frame
(
RoHS Compliant
)
NiPdAu Lead Finish
Device Number Package
Type Speed
ns Options** Process
AS5LC1008 DGCR -10 L
/
*
AS5LC1008 DGCR -12 L
/
*
AS5LC1008 DGCR -15 L
/
*
AS5LC1008 DGCR -20 L
/
*
Note: DGC & DGCR are currently not a standard product, Contact factory
for more information.
EXAMPLE: AS5LC1008DJ-12/XT
EXAMPLE: AS5LC1008DGC-12/XT
EXAMPLE: AS5LC1008DGCR-15/IT
SRAM
AS5LC1008
AS5LC1008
Rev. 1.3 03/11
Micross Components reserves the right to change products or specifi cations without notice.
12
DOCUMENT TITLE
128K x 8 SRAM High-Speed CMOS SRAM with 3.3V Revolutionary Pinout
Rev # History Release Date Status
1.2 Added Micross Information January 2010 Release
1.3 Added TSOPII Copper Lead Frame March 2011 Release
and RoHS compliant parts, pg 1 &10,
Reduced Power Supply Currents:
Parameter Speed From (mA) To (mA)
ICC -10 160 105
ICC -12 140 100
ICC -15 130 95
ICC -20 120 90
ISB -10 45 35
ISB -12 40 30
ISB -15 35 25
ISB -20 30 20
ISB1 -10 30 20
ISB1 -12 30 20
ISB1 -15 30 20
ISB1 -20 30 20
ISB2 -10 10 2
ISB2 -12 10 2
ISB2 -15 10 2
ISB2 -20 10 2
Added “L” Versions
