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Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 1994 - Revised May 11, 1995
Using Decoupling Capacitors
Introduction
This application note describes some revised re commenda-
tions regarding the use of decoupling capacitors. The “con-
ventional” recommendation of using two different values and
two different types can, in many circumstances, cause less
than ideal operation. Simpler, more reliable designs will often
result from following the design guidelines of this note.
The Problem
Faster edges, more sensitive devices, higher clock rate s all
demand “go od” decoupling of the power supplies.
Decoupling:
The a rt and p ractice o f breaking c oupling between portions of
systems and circuits to ensure proper operation.
Bypassing:
The practice of adding a low-im pedance path t o shunt tran-
sient energy to ground at the source. Requi red for proper de-
coupling.
What used to work for lower system speeds and slower logic
may not work well when the system speed increases. The
common practice of using two different values for decoupling
can:
• Increase the RFI/EMI problems
• Re duce the reliability of operati on
• Reduce the noise tolerance
Each physical component shown on the schematic brings
with it additional electrica l compon ents determined by the de-
sign and mounting of that component into the system.
Look in
Fi g ur e 1
at th e behavior of two id eal components, a
capacitor and an inductor representing parts of the capacitor
shown in
Figure 2
. Note that without an y lead inductance or
resistance, the resulting capacitive reac tance approa ches 0Ω
with increasing frequency. Note also that th e inductive reac-
tance of the ideal induc tor, without any stray ca pacitance, a p-
pro aches infinity.
A real capacitor includes an inductor and resistor in th e form
of leads , trace s, and even ground planes i n series with it (
Fig-
ure 2)
.
Multi-layer capacitors have approximately 5 nH of parasitic
inductance when mounted on a printed circuit board. While
the component drawn on the schematic (
Figure 2)
shows a
22-nF capacitor, the system sees the 22-nF capacitor in se-
ries with a 5-nH inductor and a 30-mΩ resistor.
The impedance curve of “Real” capacitors resembles the
traces marked 22 nF and 100 pF of
Fi gur e 3 .
The shape of
these calculated curves match the curves given i n capacitor
manufacturers’ data sheets. This means that in a circuit, a
capacitor acts as a low-impedance element only over a limit-
ed ran ge of frequencies. A solution, proposed in many works,
added a second capaci tor t o bypass frequencies outside the
limited range of the single capacitor. This approach expected
that the resulting impedance curve would look like the solid
line marked “Expected” in
Figure 3
. This solution, however,
has a significant problem at “intermediate” frequencies.
These intermediate frequency problems come from the circuit
shown in
Figure 4
. The ci rcuit on the left represents the sche-
matic form of a typical decoupling arr angement, a 22-nF and
a 100-pF capacitor in par al lel.
Conventional wisdom suggests that the 100-pF should de-
coup le the high frequencies, a nd the 22-nF should decouple
Figure 1. Z vs. f for Parts of a Real Capacitor
0.01
0.10
1.00
10.00
1.00 10.00 100.00 1000.00
Frequency (MHz)
XL5nH
X
C22nF
Figure 2. The “Real” Schematic
Schematic System
22 nF
22 nF
5 n H
30 mΩ
Using Decoupling Capacitors
2
the low frequencies. However, the combination results in
some unexpected interactions. The circuit on the right in
Fig-
ure 4
shows a clearer represe ntation of the system, including
the parasitic induc tances and resistances. This picture shows
all the components necessary to create a resonant tank cir-
cuit.
Figure 5
shows a combined plot of Z vs. frequency of this
circuit. The values given for effective series resistance (ESR;
30 mΩ) and effective series inductance (ESL; 5 nH) are
achievable on real PCBs using “good” layouts and sur-
face-mounted capacitors.
The graph of
Figure 5
shows a range of frequencies where
this combin ation of two capacitors results in a higher imped-
ance than that of the larger capacitor alone. For the combina-
tion shown , this range includes approximately 15 MHz
through 175 MHz. Notice the large peak in reactance at 1 50
MHz due to resonance of the two capacitors. Any energy from
the rest of the system (ICs, clocks, and harmonics), over this
intermediate range of frequencies, will see a higher \imped-
ance than that of a single 22-nF capacitor alone. Over this
range of frequencies, the parallel combination will bypass
less of the energy to ground.
The height of the peak shown in
Figu re 5
varies inversely with
the ESR of the capacitors. As board designs and components
improve, the height of the resulting peak will actually increase
due to a reduction of the system ESR. The exact shape and
location of the parallel resonant peak will vary for each sys-
tem depending on the design of the printed circuit board
(PCB) and choice of capacitors.
Recommendations
The following recommendations can improve the resulting
designs:
• Use only one value of capacitor.
• Choose the capacitor based on the self-resonant charac-
teristi cs from the manufacturers’ data sheet to matc h the
clock rate or expected noise fre quency of the design.
• Add as many capacitors as needed for your range of fre-
quencies. As an exa mple, the capacitor shown (22 nF) has
a sel f resonant frequency of approximately 11 MHz, and a
useful (less than 1Ω) impedance range of 6 t o 40 MHz.
Use as many of these as needed to achieve the desired
level of decoupling.
• A minimum of o ne capacitor p er power pin place d as phys-
ically close to the to the power pins of the IC as possible
to reduce the parasitic impedances.
• Keep lead lengths on th e c a pacitors below 1/4″ between
the capacitor endcaps and the ground or power pins.
• Place the bypass capacitors on the same side of the PCB
as the ICs.
Figure 6
shows an example of a recommended
layout for a HOTLink Transmit ter and Receiver.
Figure 3. Expected Impedance of “Real” Capacitors
Figure 4. The “Real” Schematic
Schematic System
100 pF
5 nH
30 m Ω
22 nF 100 pF 22 nF
5 nH
30 m Ω
Using Decoupling Capacitors
3
A special note ab out
Figure 6
: in both of the layouts, only on e
connection is made to the VCC plan e. This is done so that the
noise, generated both inside the IC and external to this por-
tion of the circuit, must go through the single via to the power
plane. The additional reactance of the via helps to keep the
noise from spreading throughout the rest of the system.
HOTLink parts tolerate a fairly large amount of VCC noise.
However, to achieve the absolute “best” performance, use
these recommendations.
Figure 5. Real Z vs. f for Parallel 22-nF and 100-pF Capacitors
0.01
0.10
1.00
10.00
100.00
1.00 10.00 100.00 1000.00
100pF
22nF||100pF
22 nF
Frequency (MHz)
Figure 6. Sample Layouts
VCC Via
Ground
VCC Signals GND Via
Capacitor and Pads
CY7B923 HO T Link Transmitter CY7B933 HOTLink Receiver
Using Decoupling Capacitors
© Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no r esponsibility for the use
of any circuitry othe r than circui try embodi ed in a Cy press Semi conductor p roduct. Nor does it convey or im ply any li cense under patent or other rights. Cypress Semicondu ctor does not authori ze
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
What About Multiple Clocks?
When the design calls for multiple clock frequencies, spl it the
power plane as shown in
Figure 6
and use the correct value
of capacitor for each section, maintaining only one value per
section. An e xample of this tech nique may be fou nd in “HOT-
Link Design Considerations, Power Distribution Require-
ments for Optical Drivers. ” The isolation pro vided by the slot-
ted power plane keeps the noise of one section away from the
sensitive part s of th e other sections, and allows the separa-
tion of the capacitor values.
What About V ariable Clock Frequencies?
Bypassing ICs when the clock rate changes over a wide
range of frequencies presents the most difficult situation cov-
ered here. Fortunately, most data communications applica-
tions use only a single clock rate.
When the ra nge of operation of a single part co vers a large
range of frequencies, placing two capacitors that are within
approximately 2:1 of each other in capacitance results in a
wider low-impedance zone and allows a broad range of b y-
pass frequencies. In
Figure 7
notice th at the peak in the re-
actance still occurs, but that th e maximum impedance st ays
well below 1.5Ω and that the usable range (less than 1.5Ω)
now extends from approxi mately 3.25 MHz to 100 MHz. Use
this multiple decoupling capacitor method only when a wide
range of freque ncies must be bypa ssed around a
single
inte-
grated circuit and adequate range cannot be achieved by a
single capacitor. A gain, the capacitors must remain within a
2:1 range to prevent the reactance peak from exceed ing us e -
ful limits.
Conclusions
Application of these techniques resulted in improving the
measured optical margin of a HOTLink-based OLC (optical
link card) by about 1 dB. It simplifies the Bill of Material be-
cause only one value is used instead of two. Finally, using
only one value o f capacitor gave the be st jitter measurements
of the HOTLi nk Transmit ter.
HOTLink is a trademark of Cypress Semiconductor.
Figure 7. Real Z vs. f for Parall el 22-n F a nd 10-n F Capacitors
0.01
0.10
1.00
10.00
100.00
1.00 10.00 100.00 1000.00
10 nF
22nF 10 nF
22 nF
Frequency (MHz)
||
