S1C60N09 - Epson Company

MF1157-02

Technical Manual

CMOS 4-BIT SINGLE CHIP MICROCOMPUTER

S1C60N09 Technical Hardware

S1C60N09

NOTICE

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the Ministry of International Trade and Industry or other approval from another government agency.

The information of the product number change

Configuration of product number

Devices

Comparison table between new and previous number

S1C60 Family processors

Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,

2001 please use the new product number. For further information, please contact Epson sales

representative.

S1 C60N01 F0A01 Packing specification

Specification

Package (D: die form; F: QFP)

Model number

Model name (C: microcomputer, digital products)

Product classification (S1: semiconductor)

Development tools

S5U1 C60R08 D1 1Packing specification

Version (1: Version 1 ∗2)

Tool type (D1: Development Tool ∗1)

Corresponding model number (60R08: for S1C60R08)

Tool classification (C: microcomputer use)

Product classification

(S5U1: development tool for semiconductor products)

∗1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)

∗2: Actual versions are not written in the manuals.

Previous No.

E0C6001

E0C6002

E0C6003

E0C6004

E0C6005

E0C6006

E0C6007

E0C6008

E0C6009

E0C6011

E0C6013

E0C6014

E0C60R08

New No.

S1C60N01

S1C60N02

S1C60N03

S1C60N04

S1C60N05

S1C60N06

S1C60N07

S1C60N08

S1C60N09

S1C60N11

S1C60N13

S1C60140

S1C60R08

S1C62 Family processors

Previous No.

E0C621A

E0C6215

E0C621C

E0C6S27

E0C6S37

E0C623A

E0C623E

E0C6S32

E0C6233

E0C6235

E0C623B

E0C6244

E0C624A

E0C6S46

New No.

S1C621A0

S1C62150

S1C621C0

S1C6S2N7

S1C6S3N7

S1C6N3A0

S1C6N3E0

S1C6S3N2

S1C62N33

S1C62N35

S1C6N3B0

S1C62440

S1C624A0

S1C6S460

Previous No.

E0C6247

E0C6248

E0C6S48

E0C624C

E0C6251

E0C6256

E0C6292

E0C6262

E0C6266

E0C6274

E0C6281

E0C6282

E0C62M2

E0C62T3

New No.

S1C62470

S1C62480

S1C6S480

S1C624C0

S1C62N51

S1C62560

S1C62920

S1C62N62

S1C62660

S1C62740

S1C62N81

S1C62N82

S1C62M20

S1C62T30

Comparison table between new and previous number of development tools

Development tools for the S1C60/62 Family

Previous No.

ASM62

DEV6001

DEV6002

DEV6003

DEV6004

DEV6005

DEV6006

DEV6007

DEV6008

DEV6009

DEV6011

DEV60R08

DEV621A

DEV621C

DEV623B

DEV6244

DEV624A

DEV624C

DEV6248

DEV6247

New No.

S5U1C62000A

S5U1C60N01D

S5U1C60N02D

S5U1C60N03D

S5U1C60N04D

S5U1C60N05D

S5U1C60N06D

S5U1C60N07D

S5U1C60N08D

S5U1C60N09D

S5U1C60N11D

S5U1C60R08D

S5U1C621A0D

S5U1C621C0D

S5U1C623B0D

S5U1C62440D

S5U1C624A0D

S5U1C624C0D

S5U1C62480D

S5U1C62470D

Previous No.

DEV6262

DEV6266

DEV6274

DEV6292

DEV62M2

DEV6233

DEV6235

DEV6251

DEV6256

DEV6281

DEV6282

DEV6S27

DEV6S32

DEV6S37

EVA6008

EVA6011

EVA621AR

EVA621C

EVA6237

EVA623A

New No.

S5U1C62620D

S5U1C62660D

S5U1C62740D

S5U1C62920D

S5U1C62M20D

S5U1C62N33D

S5U1C62N35D

S5U1C62N51D

S5U1C62560D

S5U1C62N81D

S5U1C62N82D

S5U1C6S2N7D

S5U1C6S3N2D

S5U1C6S3N7D

S5U1C60N08E

S5U1C60N11E

S5U1C621A0E2

S5U1C621C0E

S5U1C62N37E

S5U1C623A0E

Previous No.

EVA623B

EVA623E

EVA6247

EVA6248

EVA6251R

EVA6256

EVA6262

EVA6266

EVA6274

EVA6281

EVA6282

EVA62M1

EVA62T3

EVA6S27

EVA6S32R

ICE62R

KIT6003

KIT6004

KIT6007

New No.

S5U1C623B0E

S5U1C623E0E

S5U1C62470E

S5U1C62480E

S5U1C62N51E1

S5U1C62N56E

S5U1C62620E

S5U1C62660E

S5U1C62740E

S5U1C62N81E

S5U1C62N82E

S5U1C62M10E

S5U1C62T30E

S5U1C6S2N7E

S5U1C6S3N2E2

S5U1C62000H

S5U1C60N03K

S5U1C60N04K

S5U1C60N07K

S1C60N09 TECHNICAL MANUAL EPSON i

CONTENTS

CHAPTER 1INTRODUCTION ____________________________________________ 1

1.1 Features......................................................................................................... 1

1.2 Blo ck Diagram .............................................................................................. 2

1.3 Pad Layout .................................................................................................... 3

1.3. 1 Pad layout d i ag ra m .................................................................................... 3

1.3.2 Pad coordinates .......................................................................................... 3

1.4 Pad Description ............................................................................................4

CHAPTER 2POWER SUPPLY AND INITIAL RESET ____________________________ 5

2.1 Power Supply ................................................................................................ 5

2.2 Initial Reset ................................................................................................... 6

2.2.1 Power-on reset circuit ................................................................................ 6

2.2.2 Reset terminal (RESET) ............................................................................. 6

2.2.3 Simultaneous high input to input ports (K00–K03) .................................. 6

2.2.4 Internal register following initialization ................................................... 7

2.3 Test Terminal (TEST) .................................................................................... 7

CHAPTER 3 CPU, ROM, RAM________________________________________ 8

3.1 CPU............................................................................................................... 8

3.2 ROM ..............................................................................................................8

3.3 RAM .............................................................................................................. 8

CHAPTER 4PERIPHERAL CIRCUITS AND OPERATION__________________________ 9

4.1 Memory Map .................................................................................................9

4.2 Oscillation Circuit .......................................................................................11

4.2.1 Crystal oscillation circuit.......................................................................... 11

4.2.2 CR oscillation circuit ................................................................................ 11

4.3 Input Ports (K00–K03) ................................................................................12

4.3.1 Configuration of input port ....................................................................... 12

4.3.2 Interrupt function ...................................................................................... 12

4.3.3 Mask option ............................................................................................... 13

4.3.4 I/O memory of input port .......................................................................... 14

4.3.5 Programming note..................................................................................... 14

4.4 Output Ports (R00–R03) ..............................................................................15

4.4.1 Configuration of output port ..................................................................... 15

4.4.2 Mask option ............................................................................................... 15

4.4.3 I/O memory of output port ........................................................................ 17

4.4.4 Programming note..................................................................................... 18

4.5 I/O Ports (P00–P03, P10–P13) ...................................................................19

4.5.1 Configuration of I/O port .......................................................................... 19

4.5.2 I/O control register and I/O mode ............................................................ 19

4.5.3 Mask option ............................................................................................... 19

4.5.4 I/O memory of I/O port ............................................................................. 20

4.5.5 Programming notes ................................................................................... 21

ii EPSON S1C60N09 TECHNICAL MANUAL

CONTENTS

4.6 LCD Driver (COM0–COM3, SEG0–SEG37) ............................................. 22

4.6.1 Configuration of LCD driver .................................................................... 22

4.6.2 Switching between dynamic and static drive............................................ 27

4.6.3 Mask option ............................................................................................... 28

4.6.4 I/O memory of LCD driver........................................................................ 29

4.6.5 Programming notes ................................................................................... 30

4.7 Clock Timer ..................................................................................................31

4.7.1 Configuration of clock timer ..................................................................... 31

4.7.2 Interrupt function ...................................................................................... 31

4.7.3 I/O memory of clock timer ........................................................................ 32

4.7.4 Programming notes ................................................................................... 33

4.8 Stopwatch Timer........................................................................................... 34

4.8.1 Configuration of stopwatch timer ............................................................. 34

4.8.2 Count-up pattern ....................................................................................... 34

4.8.3 Interrupt function ...................................................................................... 35

4.8.4 I/O memory of stopwatch timer ................................................................ 36

4.8.5 Programming notes ................................................................................... 37

4.9 Heavy Load Protection Circuit....................................................................38

4.9.1 Heavy load protection function................................................................. 38

4.9.2 I/O memory of heavy load protection circuit............................................ 38

4.9.3 Programming note..................................................................................... 38

4.10 Interrupt and HALT ..................................................................................... 39

4.10 . 1 I n t e r r u p t f a c t o rs ...................................................................................... 40

4.10.2 Specific masks for interrupt .................................................................... 40

4.10.3 Interrupt vectors ...................................................................................... 41

4.10.4 I/O memory of interrupt .......................................................................... 41

4.10.5 Programming notes ................................................................................. 42

CHAPTER 5BASIC EXTERNAL WIRING DIAGRAM ____________________________ 43

CHAPTER 6ELECTRICAL CHARACTERISTICS ________________________________ 44

6.1 Absolute Maximum Rating........................................................................... 44

6.2 Recommended Operating Conditions..........................................................44

6.3 DC Characteristics ...................................................................................... 45

6.4 Analog Circuit Characteristics and Current Consumption ........................ 46

6.5 Oscillation Characteristics.......................................................................... 50

CHAPTER 7CERAMIC PACKAGE FOR TEST SAMPLES__________________________ 51

CHAPTER 8PRECAUTIONS ON MOUNTING _________________________________ 52

CHAPTER 1: INTRODUCTION

S1C60N09 TECHNICAL MANUAL EPSON 1

CHAPTER 1INTRODUCTION

The S1C60N09 Series single-chip microcomputer features an S1C6200B CMOS 4-bit CPU as the core. It

contains a 1,536 (words) × 12 (bits) ROM, 144 (words) × 4 (bits) RAM, LCD driver, 4-bit input port (K00–

K03), 4-bit output port (R00–R03), 8-bit I/O port (P00–P03, P10–P13) and timers.

The S1C60N09 Series is configured as follows, depending on the supply voltage.

S1C60N09:3.0 V (2.6 to 3.6 V)

S1C60L09:1.5 V (1.2 to 1.8 V)

1.1 Features

Core CPU........................................... S1C6200B

Built-in oscillation circuit ............. Crystal 32.768 kHz (Typ.) or CR oscillation circuit 65 kHz (Typ.)

Instruction set .................................. 100 instructions

ROM capacity................................... 1,536 words × 12 bits

RAM capacity................................... 144 words × 4 bits

Input port .......................................... 4 bits (pull-down resistors are available by mask option)

Output port....................................... 4 bits (clock and buzzer outputs are selectable by mask option)

I/O port .............................................. 8 b i t s

LCD driver ........................................ 38 segments × 4, 3 or 2 commons

(1/4, 1/3 or 1/2 duty are selectable by mask option)

Time base counter ........................... 2 systems (clock timer and stopwatch timer) built-in

Interrupt ............................................ External: Input port interrupt 1 system

Internal: Timer interrupt 2 systems

Supply voltage ................................. 1.5 V (1.2 to 1.8 V) S1C60L09

3.0 V (2.6 to 3.6 V) S1C60N09

Current consumption (Typ.) ......... During HALT: 1.0 µA (32 kHz crystal oscillation)

During execution: 3.0 µA (32 kHz crystal oscillation)

Supply form ..................................... Die form only

CHAPTER 1: INTRODUCTION

2EPSON S1C60N09 TECHNICAL MANUAL

1.2 Block Diagram

COM0–3

SEG0–37

VDD

VL1–VL3

CA, CB

VS1

VSS

K00–K03

TEST

RESET

OSC1

OSC2

R00, R03 (BZ, BZ)∗1

R01

R02 (FOUT)∗1

∗1: Terminal specifications can be selected by mask option.

P00–P03

P10–P13

Core CPU S1C6200B

ROM

1,536 words × 12 bits System Reset

Control

Interrupt

Generator

RAM

144 words × 4 bits

Stopwatch

Timer

LCD Driver

38 SEG × 4 COM

Power

Controller

OSC

I/O Port

Clock

Timer

Input Port

Output Port

Fig. 1.2.1 S1C60N09 block diagram

CHAPTER 1: INTRODUCTION

S1C60N09 TECHNICAL MANUAL EPSON 3

1.3 Pad Layout

1.3.1 Pad layout diagram

(0, 0)

2.87mm

2.90mm

151015

Die No.

40 45 50

Fig. 1.3.1.1 Pad layout Chip thickness: 400 µm

Pad opening: 95 µm

1.3.2 Pad coordinates

Table 1.3.2.1 Pad coordinates (unit: µm)

No.

Pad name

SEG37

K03

K02

K01

K00

P13

P12

P11

P10

P03

P02

P01

P00

R02

R01

R00

R03

RESET

OSC2

OSC1

1,020

861

731

601

471

297

167

-93

-246

-376

-507

-637

-835

-969

-1,102

-1,236

-1,284

1,268

965

835

705

575

445

286

156

No.

Pad name

COM3

COM2

COM1

COM0

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

-1,284

-1,237

-1,107

-977

-795

-665

-535

-405

-275

-145

-15

115

245

375

505

635

Y26

-104

-234

-364

-494

-624

-754

-884

-1,014

-1,268

No.

–

Pad name

SEG16

SEG17

SEG18

SEG19

TEST

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

765

895

1,025

1,284

-1,268

-1,196

-1,037

-879

-749

-619

-489

-359

-229

-99

162

292

422

552

682

812

942

1,072

1,202

CHAPTER 1: INTRODUCTION

4EPSON S1C60N09 TECHNICAL MANUAL

1.4 Pad Description

Table 1.4.1 Pad description

Pad name

VDD

VSS

VS1

VL1–3

CA, CB

OSC1

OSC2

K00–03

P00–03

P10–13

R00

R03

R01

R02

SEG0–37

COM0–3

RESET

TEST

Function

Power supply terminal (+)

Power supply terminal (-)

Constant voltage output terminal

Power source for LCD

Booster capacitor connecting terminal

Crystal or CR oscillation input terminal *

Crystal or CR oscillation output terminal *

Input port terminal

I/O port terminal

Output port terminal (BZ output is selectable *)

Output port terminal

Output port terminal (FOUT output is selectable *)

LCD segment output (DC output is selectable *)

LCD common output terminal (1/4, 1/3 or 1/2 duty are selectable *)

Initial reset input terminal

Test input terminal

Pad No.

26–24

28, 27

5–2

13–10

9–6

33–52, 54–70, 1

32–29

I/O

(I)

–

I/O

∗ Can be selected by mask option

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

S1C60N09 TECHNICAL MANUAL EPSON 5

CHAPTER 2POWER SUPPLY AND INITIAL RESET

2.1 Power Supply

With a single external power supply (∗) supplied to VDD through VSS, the S1C60N09 Series generates the

necessary internal voltages (<VS1> for oscillator and internal circuits and <VL1–VL3> for driving LCD)

with the internal power supply circuit.

∗ Supply voltage: S1C60N09 ... 3.0 V S1C60L09 ... 1.5 V

The internal power supply circuit is configured according to the LCD drive voltage specification selected

by mask option. Figure 2.1.1 shows the configuration of the power supply circuit.

3.0 V

0.1µF

=1/2V

=3/2V

4.5 V LCD Panel

1/4, 1/3 or 1/2 duty, 1/3 bias

S1C60N09

and V

are shorted internally.Note:

Voltage

regulator

LCD

voltage

circuit

3.0 V

0.1µF

=1/2V

3 V LCD Panel

1/4, 1/3 or 1/2 duty, 1/2 bias

and V

are shorted internally.Note:

Voltage

regulator

LCD

voltage

circuit

1.5 V

0.1µF

=2V

=3V

4.5 V LCD Panel

1/4, 1/3 or 1/2 duty, 1/3 bias

S1C60L09

and V

are shorted internally.Note:

Voltage

regulator

LCD

voltage

circuit

1.5 V

0.1µF

=2V

3 V LCD Panel

1/4, 1/3 or 1/2 duty, 1/2 bias

and V

are shorted internally.Note:

Voltage

regulator

LCD

voltage

circuit

0.1µF

Fig. 2.1.1 Power supply configuration and external elements

Notes: • External loads cannot be driven by the output voltage of the internal power supply circuit.

• See Chapter 6, "ELECTRICAL CHARACTERISTICS", for voltage values.

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

6EPSON S1C60N09 TECHNICAL MANUAL

2.2 Initial Reset

To initialize the S1C60N09 Series circuits, an initial reset must be executed. Ther e are thr ee ways of doing this.

(1) Initial reset by the power-on reset circuit

(2) External initial reset via the RESET terminal

(3) External initial reset by simultaneous high input to K00–K03 (depending on mask option)

Figure 2.2.1 shows the configuration of the initial reset circuit.

OSC1

oscillation circuit

Power-on

reset circuit

Time authorize

circuit

OSC1

OSC2

K00

K01

K02

K03

Initial

reset

RESET

Noise

rejector

Fig. 2.2.1 Configuration of initial reset circuit

2.2.1 Power-on reset circuit

The power-on reset circuit outputs the initial reset signal at power-on until the oscillation circuit starts

oscillating.

Note: The power-on reset circuit may not work proper ly due to unstable or lower voltage input. The

following two initial reset method are recommended to generate the initial reset signal.

2.2.2 Reset terminal (RESET)

An initial reset can be executed externally by setting the reset terminal to high level. This high level must

be maintained for at least 1 sec (when oscillating frequency fosc = 32 kHz), because the initial reset circuit

contains a noise rejector circuit. When the reset terminal goes low the CPU starts operating.

2.2.3 Simultaneous high input to input ports (K00–K03)

Another way of executing an initial reset externally is to input a high signal simultaneously to the input

ports (K00–K03) selected with the mask option. The specified input port terminals must be kept high for

at least 1 sec (when oscillating frequency fosc = 32 kHz), because of the noise rejection circuit. Table

2.2.3.1 shows the combinations of input ports (K00–K03) that can be selected with the mask option.

Table 2.2.3.1 Input port combinations

A Not used

B K00*K01

C K00*K01*K02

D K00*K01*K02*K03

When, for instance, mask option D (K00*K01*K02*K03) is selected, an initial reset is executed when the

signals input to the four ports K00–K03 are all high at the same time.

Further, the time authorize circuit can be selected with the mask option. The time authorize circuit

performs initial reset, when the input time of the simultaneous high input is authorized and found to be

the same or more than the defined time (1 to 3 sec).

When this function is used, make sure that the specified ports do not go high at the same time during

normal operation.

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

S1C60N09 TECHNICAL MANUAL EPSON 7

2.2.4 Internal register following initialization

An initial reset initializes the CPU as shown in the table below.

Table 2.2.4.1 Initial values

∗ See Section 4.1, "Memory Map".

Name

Program counter step

Program counter page

New page pointer

Stack pointer

Index register X

Index register Y

General-purpose register A

General-purpose register B

Interrupt flag

Decimal flag

Zero flag

Carry flag

CPU Core

Symbol

PCS

PCP

NPP

Bit size

Initial value

00H

Undefined

Name

RAM

Display memory

Other peripheral circuits

Peripheral Circuits

Bit size

Initial value

Undefined

∗

2.3 Test Terminal (TEST)

This terminal is used when IC is inspected for shipment. During normal operation connect it to VSS or

leave it open.

CHAPTER 3: CPU, ROM, RAM

8EPSON S1C60N09 TECHNICAL MANUAL

CHAPTER 3 CPU, ROM, RAM

3.1 CPU

The S1C60N09 Series employs the S1C6200B core CPU, so that register configuration, instructions, and so

forth are virtually identical to those in other processors in the family using the S1C6200/6200A/6200B.

Refer to the "S1C6200/6200A Core CPU Manual" for details of the S1C6200B.

Note the following points with regard to the S1C60N09 Series:

(1) Since the S1C60N09 Series does not provide the SLEEP function, the SLP instruction can not be used.

(2) Because the ROM capacity is 1,536 words, 12 bits per word, bank bits are unnecessary, and PCB and

NBP are not used.

(3) The RAM page is set to 0 only, so the page part (XP, YP) of the index register that specifies addresses is

invalid.

PUSH XP POP XP LD XP,r LD r,XP

PUSH YP POP YP LD YP,r LD r,YP

3.2 ROM

The built-in ROM, a mask ROM for the program, has a capacity of 1,536 × 12-bit steps. The program area

is 6 pages (0–5), each consisting of 256 steps (00H–FFH). After an initial reset, the program start address is

set to page 1, step 00H. The interrupt vectors are allocated to page l, steps 01H–0FH.

Step 00H

Step 0FH

Step 10H

Step FFH

12 bits

Program start address

Interrupt vector area

Bank 0

Program area

Page 0

Page 1

Page 2

Page 3

Page 4

Page 5

Step 01H

Fig. 3.2.1 ROM configuration

3.3 RAM

The RAM, a data memory for storing a variety of data, has a capacity of 144 words, 4-bit words. When

programming, keep the following points in mind:

(1) Part of the data memory is used as stack area when saving subroutine return addresses and registers,

so be careful not to overlap the data area and stack area.

(2) Subroutine calls and interrupts take up three words on the stack.

(3) Data memory 000H–00FH is the memory area pointed by the register pointer (RP).

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

S1C60N09 TECHNICAL MANUAL EPSON 9

CHAPTER 4PERIPHERAL CIRCUITS AND OPERATION

Peripheral circuits (timer, I/O, and so on) of the S1C60N09 Series are memory mapped. Thus, all the

peripheral circuits can be controlled by using memory operations to access the I/O memory. The follow-

ing sections describe how the peripheral circuits operate.

4.1 Memory Map

The data memory of the S1C60N09 Series has an address space of 160 words, of which 48 words are

allocated to display memory and 16 words, to I/O memory. Figure 4.1.1 show the overall memory map

for the S1C60N09 Series, and Table 4.1.1, the memory maps for the peripheral circuits (I/O space).

Address

Page High

Low 0

RAM area

112 words × 4 bits (R/W)

RAM area

32 words × 4 bits (R/W)

Unused area

I/O memory See Table 4.1.1

Fig. 4.1.1 Memory map

Address

Page High

Low 01 2 3 4 5 6 7 8 9 A B C D EF

4 or C

5 or D

6 or E

0Display memory 48 words × 4 bits

40H–6FH = R/W

C0H–EFH = W only

Fig. 4.1.2 Display memory map

Notes: •The display memory area can be selected from between 40H–6FH and C0H–EFH by mask

option.

When 40H–6FH is selected, the display memory is assigned in the RAM area. So read/write

operation is allowed.

When C0H–EFH is selected, the display memory is assigned as a write-only memor y.

•Memory is not mounted in unused area within the memory map and in memory area not indi-

cated in this chapter. For this reason, normal operation cannot be assured for programs that

have been prepared with access to these areas.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

10 EPSON S1C60N09 TECHNICAL MANUAL

Table 4.1.1 I/O memory map

Address Comment

D3 D2

D1 D0 Name Init

∗1

073H

K03 K02 K01 K00

K03

K02

K01

K00

–

∗

–

∗

–

∗

–

∗

High

Low

Input port data (K00–K03)

071H

SWL3 SWL2 SWL1 SWL0

SWL3

SWL2

SWL1

SWL0

MSB

Stopwatch timer 1/100 sec data (BCD)

LSB

072H

SWH3 SWH2 SWH1 SWH0

SWH3

SWH2

SWH1

SWH0

MSB

Stopwatch timer 1/10 sec data (BCD)

LSB

070H

TM3 TM2 TM1 TM0

TM3

TM2

TM1

TM0

Clock timer data (2 Hz)

Clock timer data (4 Hz)

Clock timer data (8 Hz)

Clock timer data (16 Hz)

075H

EIK03 EIK02 EIK01 EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Enable

Mask

Interrupt mask register (K00–K03)

076H

HLMOD 0 EISWIT1 EISWIT0

R/W R R/W

HLMOD

∗

EISWIT1

EISWIT0

–

∗

Heavy load

–

Enable

Normal

–

Mask

Heavy load protection mode register

Unused

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

07EH

TMRST SWRUN SWRST IOC0

W R/W W R/W

TMRST

∗

SWRUN

SWRST

∗

IOC0

Reset

Run

Reset

Output

–

Stop

–

Input

Clock timer reset

Stopwatch timer Run/Stop

Stopwatch timer reset

I/O control register 0 (P00–P03)

078H

CSDC ETI2 ETI8 ETI32

R/W

CSDC

ETI2

ETI8

ETI32

Static

Enable

Dynamic

Mask

LCD drive switch

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

0FFH

0 0 0 LCDON

R R/W

∗

LCDON

–

∗

–

∗

–

∗

–

Off

Unused

LCD display On/Off control

079H

0 TI2 TI8 TI32

∗

TI2

∗

TI8

∗

TI32

∗

–

∗

–

Yes

–

Unused

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

07AH

0 IK0 SWIT1 SWIT0

∗

IK0

∗

SWIT1

∗

SWIT0

∗

–

∗

–

Yes

–

Unused

Interrupt factor flag (K00–K03)

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

07CH

R03 R02 R01 R00

R/W

R03

R02

R01

R00

High

Low

Output port (R03, BZ)

Output port (R02, FOUT)

Output port (R01)

Output port (R00, BZ)

07DH

P03 P02 P01 P00

R/W

P03

P02

P01

P00

–

∗

–

∗

–

∗

–

∗

High

Low

I/O port data (P00–P03)

Output latch is reset at initial reset

0FEH

0 0 0 IOC1

R R/W

∗

IOC1

–

∗

–

∗

–

∗

–

Output

–

Input

Unused

I/O control register 1 (P10–P13)

0FDH

P13 P12 P11 P10

R/W

P13

P12

P11

P10

–

∗

–

∗

–

∗

–

∗

High

Low

I/O port data (P10–P13)

Output latch is reset at initial reset

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

0F6H

BZFQ 0 0 0

R/W R

BZFQ

∗

–

∗

–

∗

–

∗

2 kHz

–

4 kHz

–

Buzzer frequency selection

Unused

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

S1C60N09 TECHNICAL MANUAL EPSON 11

4.2 Oscillation Circuit

The S1C60N09 Series has a built-in oscillation circuit that generates the operating clock of the CPU and

the peripheral circuit. Either crystal oscillation or CR oscillation can be selected for the oscillation circuit

by mask option.

4.2.1 Crystal oscillation circuit

The crystal oscillation circuit can be selected by mask option. The oscillation frequency (fosc) is 32.768

kHz (Typ.).

Figure 4.2.1.1 shows the configuration of the crystal oscillation circuit.

OSC2

OSC1

X'tal

GCPU

and peripheral circuits

Fig. 4.2.1.1 Configuration of crystal oscillation circuit

As Figure 4.2.1.1 indicates, the crystal oscillation circuit can be configured simply by connecting the

crystal oscillator X'tal (Typ. 32.768 kHz) between the OSC1 and OSC2 terminals and the trimmer capaci-

tor CG (5–25 pF) between the OSC1 and VDD terminals.

4.2.2 CR oscillation circuit

The CR oscillation circuit can also be selected by mask option. The oscillation frequency (fosc) is 65 kHz

(Typ.).

Figure 4.2.2.1 shows the configuration of the CR oscillation circuit.

OSC2

OSC1

CPU

and peripheral circuits

Fig. 4.2.2.1 Configuration of CR oscillation circuit

As Figure 4.2.2.1 indicates, the CR oscillation circuit can be configured simply by connecting the resistor

RCR between terminals OSC1 and OSC2 since capacity (CCR) is built-in.

See Chapter 6, "Electrical Characteristics" for RCR value.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

12 EPSON S1C60N09 TECHNICAL MANUAL

4.3 Input Ports (K00–K03)

4.3.1 Configuration of input port

The S1C60N09 Series has a 4-bit general-purpose input port. Each of the input port terminals (K00–K03)

has an internal pull-down resistor. The pull-down resistor can be selected for each bit with the mask

option.

Figure 4.3.1.1 shows the configuration of input port.

Mask option

Address

Data bus

Kxx

Interrupt

request

Fig. 4.3.1.1 Configuration of input port

Selecting "pull-down resistor enabled" with the mask option allows input from a push button, key matrix,

and so forth. When "pull-down resistor disabled" is selected, the port can be used for slide switch input

and interfacing with other LSIs.

4.3.2 Interrupt function

All four input port bits (K00–K03) provide the interrupt function. The conditions for issuing an interrupt

can be set by the software for the four bits. Also, whether to mask the interrupt function can be selected

individually for all four bits by the software. Figure 4.3.2.1 shows the configuration of K00–K03.

Data bus

Address

Interrupt mask

Kxx

Mask option

(K00–K03)

Noise

rejector Interrupt factor

flag (IK0) Interrupt

request

Address Address

Fig. 4.3.2.1 Input interrupt circuit configuration (K00–K03)

The interrupt mask registers (EIK00–EIK03) enable the interrupt mask to be selected individually for

K00–K03. An interrupt occurs when the input value which are not masked change and the interrupt

factor flag (IK0) is set to "1".

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

S1C60N09 TECHNICAL MANUAL EPSON 13

Input interrupt programming related precautions

Port K input

Factor flag set Not set

Mask register

Active status

➀

When the content of the mask register is rewritten, while the port

K input is in the active status. The input interrupt factor flag is

set at ➀.Fig. 4.3.2.2 Input interrupt timing

When using an input interrupt, if you rewrite the content of the mask register, when the value of the

input terminal which becomes the interrupt input is in the active status (input terminal = high status), the

factor flag for input interrupt may be set.

For example, a factor flag is set with the timing of ➀ shown in Figure 4.3.2.2. However, when clearing the

content of the mask register with the input terminal kept in the high status and then setting it, the factor

flag of the input interrupt is again set at the timing that has been set.

Consequently, when the input terminal is in the active status (high status), do not rewrite the mask

this case. When clearing, then setting the mask register, set the mask register, when the input terminal is

not in the active status (low status).

4.3.3 Mask option

The contents that can be selected with the input port mask option are as follows:

(1) An internal pull-down resistor can be selected for each of the four bits of the input ports (K00–K03).

Having selected "pull-down resistor disabled", take care that the input does not float. Select "pull-

down resistor enabled" for input ports that are not being used.

(2) The input interrupt circuit contains a noise rejection circuit to prevent interrupts form occurring

through noise. The mask option enables selection of the noise rejection circuit. When "use" is selected,

a maximum delay of 0.5 msec (fosc = 32 kHz) occurs from the time an interrupt condition is estab-

lished until the interrupt factor flag (IK0) is set to "1".

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

14 EPSON S1C60N09 TECHNICAL MANUAL

4.3.4 I/O memory of input port

Table 4.3.4.1 list the input port control bits and their addresses.

Table 4.3.4.1 Input port control bits

Address Comment

D3 D2

D1 D0 Name Init ∗110

073H

K03 K02 K01 K00

K03

K02

K01

K00

–

∗

–

∗

–

∗

–

∗

High

Low

Input port data (K00–K03)

075H

EIK03 EIK02 EIK01 EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Enable

Mask

Interrupt mask register (K00–K03)

07AH

0 IK0 SWIT1 SWIT0

∗

IK0

∗

SWIT1

∗

SWIT0

∗

–

∗

–

Yes

–

Unused

Interrupt factor flag (K00–K03)

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

K00–K03: Input port data (073H)

The input data of the input port terminals can be read with these registers.

When "1" is read: High level

When "0" is read: Low level

Writing: Invalid

The value read is "1" when the terminal voltage of the input port (K00–K03) goes high (VDD), and "0"

when the voltage goes low (VSS). These are read only bits, so writing cannot be done.

EIK00–EIK03: Interrupt mask registers (075H)

Masking the interrupt of the input port terminals can be done with these registers.

When "1" is written: Enable

When "0" is written: Mask

Reading: Valid

With these registers, masking of the input port bits can be done for each of the four bits.

After an initial reset, these registers are all set to "0".

IK0: Interrupt factor flag (07AH•D2)

This flag indicates the occurrence of an input interrupt.

When "1" is read: Interrupt has occurred

When "0" is read: Interrupt has not occurred

Writing: Invalid

The interrupt factor flag IK0 is associated with K00–K03. From the status of this flag, the software can

decide whether an input interrupt has occurred.

This flag is reset when the software has read it.

Reading of interrupt factor flag is available at EI, but be careful in the following cases.

If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an

interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not

be generated.

After an initial reset, this flag is set to "0".

4.3.5 Programming note

When modifying the input port from high level to low level with pull-down resistor, a delay will occur at

the fall of the waveform due to time constant of the pull-down resistor and input gate capacities. Provide

appropriate waiting time in the program when performing input port reading.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

S1C60N09 TECHNICAL MANUAL EPSON 15

4.4 Output Ports (R00–R03)

4.4.1 Configuration of output port

The S1C60N09 Series has a 4-bit general output port (R00–R03).

Output specification of the output port can be selected in a bit units with the mask option. Two kinds of

output specifications are available: complementary output and Pch open drain output. Also, the mask

option enables the output ports R00, R02 and R03 to be used as special output ports. Figure 4.4.1.1 shows

the configuration of the output port.

Data bus

Address

VDD

VSS

Rxx

Complementary

Pch open drain

Mask option

Fig. 4.4.1.1 Configuration of output port

4.4.2 Mask option

The mask option enables the following output port selection.

(1)Output specification of output port

The output specifications for the output port (R00–R03) may be set to either complementary output or

Pch open drain output for each of the four bits. However, even when Pch open drain output is

selected, a voltage exceeding the source voltage must not be applied to the output port.

(2)Special output

In addition to the regular DC output, special output can be selected for output ports R00, R02 and

R03, as shown in Table 4.4.2.1. Figure 4.4.2.1 shows the structure of output ports R00–R03.

Table 4.4.2.1 Special output

Output port

R00

R03

R02

Special output

BZ output

FOUT output

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

16 EPSON S1C60N09 TECHNICAL MANUAL

Data bus

R01

Address 07CH Mask option

R03

R00

FOUT

R02

Fig. 4.4.2.1 Structure of output ports R00–R03

BZ, BZ (R00, R03)

The output ports R00 and R03 may be set to BZ output and BZ output (BZ reverse output), respectively,

allowing for direct driving of the piezo-electric buzzer.

The BZ output is controlled by the R00 register. For the BZ output, the R00 register or the R03 register can

be selected as the control register by mask option. When the R00 register is selected, the BZ and BZ

outputs are controlled by the R00 register simultaneously.

The frequency of buzzer output may be selected by software to be either 2 kHz or 4 kHz.

Figure 4.4.2.2 shows the output waveform.

R00(R03) register

BZ output (R00 terminal)

BZ output (R03 terminal)

"0" "1" "0"

Fig. 4.4.2.2 Output waveform of BZ and BZ

Notes: •A hazard may occur when the buzzer signal is turned on or off.

•When the R00 port is set for DC output, the R03 port cannot be set for the BZ output.

FOUT (R02)

When the output port R02 is set as the FOUT output port, the R02 will output the fosc (CPU operating

clock frequency) clock or the clock that is generated by dividing the fosc clock. The clock frequency can

be selected from among 8 types by mask option.

The types of frequency which can be selected are shown in Table 4.4.2.2.

Table 4.4.2.2 FOUT clock frequency

Setting value

OSC

/16

OSC

/32

OSC

/64

OSC

/128

Clock frequency (Hz)

32,768

16,384

8,192

4,096

2,048

1,024

512

256

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

S1C60N09 TECHNICAL MANUAL EPSON 17

The FOUT output is controlled by the R02 register.

Figure 4.4.2.3 shows the output waveform.

R02 register

FOUT output (R02 terminal)

"0" "1" "0"

Fig. 4.4.2.3 Output waveform of FOUT

Note: A hazard may occur when the FOUT signal is turned on or off.

4.4.3 I/O memory of output port

Table 4.4.3.1 lists the output port control bits and their addresses.

Table 4.4.3.1 Control bits of output port

Address Comment

D3 D2

D1 D0 Name Init

∗1

07CH

R03 R02 R01 R00

R/W

R03

R02

R01

R00

High

2 kHz

–

Low

Output port (R03, BZ)

Output port (R02, FOUT)

Output port (R01)

Output port (R00, BZ)

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

0F6H

BZFQ 0 0 0

R/W R

BZFQ

∗

–

∗

–

∗

–

∗

4 kHz

–

Buzzer frequency selection

Unused

R00–R03 (when DC output is selected): Output port data (07CH)

Sets the output data for the output ports.

When "1" is written: High output

When "0" is written: Low output

Reading: Valid

The output port terminals output the data written to the corresponding registers (R00–R03) without

changing it. When "1" is written to the register, the output port terminal goes high (VDD), and when "0" is

written, the output port terminal goes low (VSS).

After an initial reset, all the registers are set to "0".

R00, R03 (when buzzer output is selected): Buzzer output control (07CH•D0, D3)

Controls the buzzer output.

When "1" is written: Buzzer output

When "0" is written: Low level (DC) output

Reading: Valid

The BZ signal is output from the R00 terminal by writing "1" to the R00 register. When "0" is written, the

R00 terminal goes low.

For the BZ signal, either "R03 control" or "R00 control" can be selected by mask option.

When "R03 control" is selected, the BZ signal is output from the R03 terminal by writing "1" to the R03

When "R00 control" is selected, the BZ and BZ signals are output simultaneously by writing "1" to the R00

After an initial reset, these registers are set to "0".

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

18 EPSON S1C60N09 TECHNICAL MANUAL

BZFQ: Buzzer frequency selection (0F6H•D3)

Selects the frequency of the buzzer signal.

When "1" is written: 2 kHz

When "0" is written: 4 kHz

Reading: Valid

When R00 and R03 ports are set to buzzer output, the frequency of the buzzer signal can be selected

using this register.

When "1" is written to this register, the frequency is set to 2 kHz and when "0" is written, it is set to 4 kHz.

After an initial reset, this register is set to "0".

R02 (when FOUT is selected): FOUT output control (07CH•D2)

Controls the FOUT (fosc clock) output.

When "1" is written: Clock output

When "0" is written: Low level (DC) output

Reading: Valid

The FOUT signal is output from the R02 terminal by writing "1" to the R02 register. When "0" is written,

the R02 terminal goes low.

After an initial reset, this register is set to "0".

4.4.4 Programming note

The buzzer (BZ, BZ) or FOUT signal may produce hazards when it is turned on or off by the control

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

S1C60N09 TECHNICAL MANUAL EPSON 19

4.5 I/O Ports (P00–P03, P10–P13)

4.5.1 Configuration of I/O port

The S1C60N09 Series has 8 bits of general-purpose I/O ports. Figure 4.5.1.1 shows the configuration of

the I/O port. Each 4-bit I/O port (P00–P03 and P10–P13) can be set to either input mode or output mode

by writing data to the I/O control register.

Address

Input

control

I/O control

(IOC)

Data bus

Pxx

Vss

Fig. 4.5.1.1 Configuration of I/O port

4.5.2 I/O control register and I/O mode

Input or output mode can be set for each 4-bit I/O port (P00–P03, P10–P13) by writing data to the I/O

control register (IOC0, IOC1).

To set the input mode, write "0" to the I/O control register. When an I/O port is set to input mode, it

becomes high impedance status and works as an input port. However, the input line is pulled down

when input data is read.

The output mode is set when "1" is written to the I/O control register. When an I/O port is set to output

mode, it works as an output port. The port terminal goes high (VDD) when the port output data is set to

"1", and goes low (VSS) when the port output data is set to "0".

After an initial reset, the I/O control registers are set to "0", and the I/O ports enter the input mode.

4.5.3 Mask option

The output specification during output mode (IOCx = "1") of the I/O port can be set with the mask option

for either complementary output or Pch open drain output. This setting can be performed for each bit of

the I/O port. However, when Pch open drain output has been selected, voltage in excess of the supply

voltage must not be applied to the port.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

20 EPSON S1C60N09 TECHNICAL MANUAL

4.5.4 I/O memory of I/O port

Table 4.5.4.1 lists the I/O port control bits and their addresses.

Table 4.5.4.1 I/O port control bits

Address Comment

D3 D2

D1 D0 Name Init ∗110

07EH

TMRST SWRUN SWRST IOC0

WR/WWR/W

TMRST

∗

SWRUN

SWRST

∗

IOC0

Reset

Run

Reset

Output

–

Stop

–

Input

Clock timer reset

Stopwatch timer Run/Stop

Stopwatch timer reset

I/O control register 0 (P00–P03)

07DH

P03 P02 P01 P00

R/W

P03

P02

P01

P00

–

∗

–

∗

–

∗

–

∗

High

Low

I/O port data (P00–P03)

Output latch is reset at initial reset

0FEH

000IOC1

RR/W

∗

IOC1

–

∗

–

∗

–

∗

–

Output

–

Input

Unused

I/O control register 1 (P10–P13)

0FDH

P13 P12 P11 P10

R/W

P13

P12

P11

P10

–

∗

–

∗

–

∗

–

∗

High

Low

I/O port data (P10–P13)

Output latch is reset at initial reset

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

P00–P03, P10–P13: I/O port data registers (07DH, 0FDH)

I/O port data can be read and output data can be set through these registers.

Writing

When "1" is written: High level

When "0" is written: Low level

When an I/O port is set to the output mode, the written data is output from the I/O port terminal. When

"1" is written as the port data, the port terminal goes high (VDD), and when "0" is written, the terminal

goes low (VSS). Data can also be written in the input mode.

ReadingWhen "1" is read: High level

When "0" is read: Low level

The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage

level being input to the port can be read; in the output mode the output voltage level can be read. When

the terminal voltage is high (VDD), the port data read is "1", and when the terminal voltage is low (VSS)

the data read is "0". Also, the built-in pull-down resistor functions during reading, so the I/O port

terminal is pulled down.

Note: When the I/O port is set to the input mode and a low-level voltage (Vss) is input, an erroneous

input results if the time constant of the capacitive load of the input line and the built-in pull-down

resistor load is greater than the read-out time. When the input data is being read, the time that the

input line is pulled down is equivalent to 0.5 cycles of the CPU system clock. Hence, the electric

potential of the terminals must settle within 0.5 cycles. If this condition cannot be met, some

measure must be devised, such as arranging a pull-down resistor externally, or performing multiple

read-outs.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

S1C60N09 TECHNICAL MANUAL EPSON 21

IOC0, IOC1: I/O control registers (07EH•D0, 0FEH•D0)

The input or output mode of the I/O port can be set with these registers.

When "1" is written: Output mode

When "0" is written: Input mode

Reading: Valid

The input or output mode of the I/O port is set in units of four bits. For instance, IOC0 sets the mode for

P00–P03 and IOC1 sets the mode for P10–P13.

Writing "1" to the I/O control register makes the corresponding I/O port enter the output mode, and

writing "0" induces the input mode.

After an initial reset, these registers are set to "0", so the I/O ports are in the input mode.

4.5.5 Programming notes

(1) When the I/O port is set to the output mode and a low-impedance load is connected to the port

terminal, the data written to the register may differ from the data read.

(2) When the I/O port is set to the input mode and a low-level voltage (Vss) is input, an erroneous input

results if the time constant of the capacitive load of the input line and the built-in pull-down resistor

load is greater than the read-out time. When the input data is being read, the time that the input line

is pulled down is equivalent to 0.5 cycles of the CPU system clock. Hence, the electric potential of the

terminals must settle within 0.5 cycles. If this condition cannot be met, some measure must be de-

vised, such as arranging a pull-down resistor externally, or performing multiple read-outs.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

22 EPSON S1C60N09 TECHNICAL MANUAL

4.6 LCD Driver (COM0–COM3, SEG0–SEG37)

4.6.1 Configuration of LCD driver

The S1C60N09 Series has four common terminals and 38 (SEG0–SEG37) segment terminals, so that an

LCD with a maximum of 152 (38 × 4) segments can be driven. The power for driving the LCD is gener-

ated by the internal circuit, so there is no need to supply power externally.

The driving method is 1/4 duty (or 1/3, 1/2 duty is selectable by mask option) dynamic drive, adopting

the four types of potential (1/3 bias), VDD, VL1, VL2 and VL3. Moreover, the 1/2 bias dynamic drive that

uses three types of potential, VDD, VL1 = VL2 and VL3, can be selected by setting the mask option (drive

duty can also be selected from 1/4, 1/3 or 1/2).

The LCD drive voltages VL1 to VL3 are generated by the internal power supply circuit as shown in Table

4.6.1.1.

Table 4.6.1.1 LCD drive voltage

Model

S1C60N09

(VSS = 3 V)

S1C60L09

(VSS = 1.5 V)

Mask option

selection

4.5 V LCD, 1/3 bias

3 V LCD, 1/2 bias

4.5 V LCD, 1/3 bias

3 V LCD, 1/2 bias

Drive voltage

VL1

1/2 VSS

VSS

VL2

VSS

1/2 VSS

2 VSS

VSS

VL3

3/2 VSS

VSS

3 VSS

2 VSS

When 1/2 bias drive option is selected, the VL1 terminal should be connected with the VL2 terminal

outside the IC. Refer to Section 2.1, "Power Supply", for details of the power supply circuit.

The frame frequency is 32 Hz for 1/4 duty and 1/2 duty, and 42.7 Hz for 1/3 duty (in the case of fosc = 32

kHz).

Figures 4.6.1.1 to 4.6.1.6 show the drive waveform for each duty and bias.

Note: "fosc" indicates the oscillation frequency of the oscillation circuit.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

S1C60N09 TECHNICAL MANUAL EPSON 23

COM0

COM1

COM2

COM3

SEG0

–SEG37

Frame frequency

Off

LCD status

COM0

COM1

COM2

COM3

SEG0–37

Fig. 4.6.1.1 Drive waveform for 1/4 duty (1/3 bias)

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

24 EPSON S1C60N09 TECHNICAL MANUAL

COM0

COM1

COM2

COM3

Off

SEG0

–SEG37

Frame frequency

LCD status

COM0

COM1

COM2

SEG0–37

Fig. 4.6.1.2 Drive waveform for 1/3 duty (1/3 bias)

COM0

COM1

COM2

COM3

Off

SEG0

–SEG37

Frame frequency

LCD status

SEG0–37

COM0

COM1

Fig. 4.6.1.3 Drive waveform for 1/2 duty (1/3 bias)

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

S1C60N09 TECHNICAL MANUAL EPSON 25

LCD lighting status

SEG

0–37

SEG0–37

COM0

COM1

COM2

COM3

COM0

COM1

COM2

COM3

-VDD

-VL1, L2

-VL3

-VDD

-VL1, L2

-VL3

Frame frequency

Off

Fig. 4.6.1.4 Drive waveform for 1/4 duty (1/2 bias)

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

26 EPSON S1C60N09 TECHNICAL MANUAL

LCD lighting status

SEG

0–37

SEG0–37

COM0

COM1

COM2

COM0

COM1

COM2

COM3

-VDD

-VL1, L2

-VL3

-VDD

-VL1, L2

-VL3

Frame frequency

Off

Fig. 4.6.1.5 Drive waveform for 1/3 duty (1/2 bias)

COM0

COM1

COM0

COM1

COM2

COM3

-V

L1, L2

-V

L1, L2

-V

LCD lighting status

SEG

0–37

SEG0–37

Frame frequency

Off

Fig. 4.6.1.6 Drive waveform for 1/2 duty (1/2 bias)

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

S1C60N09 TECHNICAL MANUAL EPSON 27

4.6.2 Switching between dynamic and static drive

The S1C60N09 Series provides software setting of the LCD static drive.

This function enables easy adjustment (cadence adjustment) of the oscillation frequency of the oscillation

circuit (crystal oscillation circuit).

The procedure for executing static drive of the LCD is as follows:

(1) Write "1" to register CSDC at address 078H•D3.

(2) Write the same value to all registers corresponding to COM0–COM3 of the display memory.

Notes: •Even when 1/3 duty is selected, COM3 is valid for static drive. However, the output frequency is

the same as for the frame frequency.

•For cadence adjustment, set the display data corresponding to COM0–COM3, so that all the

LCDs light.

Figure 4.6.2.1 shows the drive waveform for static drive.

SEG

0–37

COM

0–3

Frame frequency

LCD lighting status

COM0

COM1

COM2

COM3

SEG0–37

-VDD

-VL1

-VL2

-VL3

-VDD

-VL1

-VL2

-VL3

-VDD

-VL1

-VL2

-VL3

Off On

Fig. 4.6.2.1 LCD static drive waveform

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

28 EPSON S1C60N09 TECHNICAL MANUAL

4.6.3 Mask option

(1)Segment allocation

As shown in Figure 4.l.1, display data is decided by the data written to the display memory at address

40H–6FH or C0H–EFH.

• The mask option enables the display memory to be allocated entirely to either 40H–6FH (R/W) or

C0H–EFH (W only).

• The address and bits of the display memory can be made to correspond to the segment terminals

(SEG0–SEG37) in any combination through mask option. This simplifies design by increasing the

degree of freedom with which the liquid crystal panel can be designed.

Figure 4.6.3.1 shows an example of the relationship between the LCD segments (on the panel) and the

display memory (when 40H–6FH is selected) in the case of 1/3 duty.

aa'

ff'

ee'

dd' p'

SEG10 SEG11 SEG12

Common 0 Common 1 Common 2

06AH

06BH

06CH

06DH

Address

Data

Display data memory allocation

SEG10

SEG11

SEG12

6A, D0

(a)

6A, D1

(b)

6D, D1

(f')

6B, D1

(f)

6B, D2

(g)

6A, D2

(c)

6B, D0

(e)

6A, D3

(d)

6B, D3

(p)

Pin address allocation

Common 0 Common 1 Common 2

Fig. 4.6.3.1 Segment allocation

(2)Drive duty

According to the mask option, either 1/4, 1/3 or 1/2 duty can be selected as the LCD drive duty.

Table 4.6.3.1 shows the differences in the number of segments according to the selected duty.

Table 4.6.3.1 Differences according to selected duty

Duty

1/4

1/3

1/2

COM used

COM0–COM3

COM0–COM2

COM0–COM1

Max. number of segments

152 (38 × 4)

114 (38 × 3)

76 (38 × 2)

Frame frequency *

fOSC/1,024 (32 Hz)

fOSC/768 (42.7 Hz)

fOSC/1,024 (32 Hz)

∗ When fOSC = 32 kHz

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

S1C60N09 TECHNICAL MANUAL EPSON 29

(3)Output specification

• The segment terminals (SEG0–SEG37) are selected by mask option in pairs for either segment

signal output or DC output (VDD and VSS binary output). When DC output is selected, the data

corresponding to COM0 of each segment terminal is output.

• When DC output is selected, either complementary output or Pch open drain output can be

selected for each terminal by mask option.

Note: The terminal pairs are the combination of SEG (2

∗

n) and SEG (2

∗

n + 1) (where n is an integer from 0 to 18).

(4)Drive bias

For the drive bias, either 1/3 bias or 1/2 bias can be selected by the mask option.

4.6.4 I/O memory of LCD driver

Table 4.6.4.1 shows the control bits of the LCD driver and their addresses. Figure 4.6.4.1 shows the

display memory map.

Table 4.6.4.1 Control bits of LCD driver

Address Comment

D3 D2

D1 D0 Name Init

∗1

078H

CSDC ETI2 ETI8 ETI32

R/W

CSDC

ETI2

ETI8

ETI32

Static

Enable

Dynamic

Mask

LCD drive switch

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

0FFH

0 0 0 LCDON

RR/W

∗

LCDON

–

∗

–

∗

–

∗

–

Off

Unused

LCD display On/Off control

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

Address

Page High

Low 01 2 3 4 5 6 7 8 9 A B C D EF

4 or C

5 or D

6 or E

0Display memory 48 words × 4 bits

40H–6FH = R/W

C0H–EFH = W only

Fig. 4.6.4.1 Display memory map

LCDON: LCD display control (0FFH•D0)

Controls the LCD display.

When "1" is written: LCD displayed

When "0" is written: LCD is all off

Reading: Valid

By writing "0" to the LCDON register, all the LCD dots goes off, and when "1" is written, it returns to

normal display.

Writing "0" outputs an off waveform to the SEG terminals, and does not affect the content of the display

memory.

After an initial reset, this register is set to "1".

CSDC: LCD drive switch (078H•D3)

The LCD drive format can be selected with this switch.

When "1" is written: Static drive

When "0" is written: Dynamic drive

Reading: Valid

After an initial reset, this register is set to "0".

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

30 EPSON S1C60N09 TECHNICAL MANUAL

Display memory (40H–6FH or C0H–EFH)

The LCD segments are turned on or off according to this data.

When "1" is written: On

When "0" is written: Off

Reading: Valid for 40H–6FH

Undefined C0H–EFH

By writing data into the display memory allocated to the LCD segment (on the panel), the segment can be

turned on or off. After an initial reset, the contents of the display memory are undefined.

4.6.5 Programming notes

(1) When 40H–6FH is selected for the display memory, the memory data and the display will not match

until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the

display memory by executing initial processing.

(2) When C0H–EFH is selected for the display memory, that area becomes write-only. Rewriting the

contents with a logical operation instruction (e.g., AND, OR, etc.) which come with read-out opera-

tions is not possible. To perform bit operations, a buffer to hold the display data is required on the

RAM.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

S1C60N09 TECHNICAL MANUAL EPSON 31

4.7 Clock Timer

4.7.1 Configuration of clock timer

The S1C60N09 Series has a built-in clock timer that uses the oscillation circuit as the clock source. The

clock timer is configured as a 7-bit binary counter that counts with a 256 Hz source clock from the

divider. The high-order 4 bits of the counter (16 Hz–2 Hz) can be read by the software.

Figure 4.7.1.1 is the block diagram of the clock timer.

128 Hz–32 Hz

Data bus

2 Hz

256 Hz

Clock timer reset signal

Divider

Interrupt

request

Interrupt

control

16 Hz–2 Hz

8 Hz32 Hz

Oscillation

circuit

Fig. 4.7.1.1 Block diagram of clock timer

Normally, this clock timer is used for all kinds of timing purpose, such as clocks.

4.7.2 Interrupt function

The clock timer can generate interrupts at the falling edge of the 32 Hz, 8 Hz, and 2 Hz signals. The

software can mask any of these interrupt signals.

Figure 4.7.2.1 is the timing chart of the clock timer.

Clock timer timing chartFrequency

bits

Address

070H

D0 16 Hz

8 Hz

4 Hz

2 Hz

Occurrence of

32 Hz interrupt request

Occurrence of

8 Hz interrupt request

Occurrence of

2 Hz interrupt request

Fig. 4.7.2.1 Timing chart of the clock timer

As shown in Figure 4.7.2.1, an interrupt is generated at the falling edge of the 32 Hz, 8 Hz, and 2 Hz

signals. At this point, the corresponding interrupt factor flag (TI32, TI8, TI2) is set to "1". The interrupts

can be masked individually with the interrupt mask register (ETI32, ETI8, ETI2). However, regardless of

the interrupt mask register setting, the interrupt factor flags will be set to "1" at the falling edge of their

corresponding signal (e.g. the falling edge of the 2 Hz signal sets the 2 Hz interrupt factor flag to "1").

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

32 EPSON S1C60N09 TECHNICAL MANUAL

4.7.3 I/O memory of clock timer

Table 4.7.3.1 shows the clock timer control bits and their addresses.

Table 4.7.3.1 Control bits of clock timer

Address Comment

D3 D2

D1 D0 Name Init ∗110

070H

TM3 TM2 TM1 TM0

TM3

TM2

TM1

TM0

Clock timer data (2 Hz)

Clock timer data (4 Hz)

Clock timer data (8 Hz)

Clock timer data (16 Hz)

07EH

TMRST SWRUN SWRST IOC0

WR/WWR/W

TMRST

∗

SWRUN

SWRST

∗

IOC0

Reset

Run

Reset

Output

–

Stop

–

Input

Clock timer reset

Stopwatch timer Run/Stop

Stopwatch timer reset

I/O control register 0 (P00–P03)

078H

CSDC ETI2 ETI8 ETI32

R/W

CSDC

ETI2

ETI8

ETI32

Static

Enable

Dynamic

Mask

LCD drive switch

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

079H

0 TI2 TI8 TI32

∗

TI2

∗

TI8

∗

TI32

∗

–

∗

–

Yes

–

Unused

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

TM0–TM3: Timer data (070H)

The l6 Hz to 2 Hz timer data of the clock timer can be read from this register. These four bits are read-

only, and write operations are invalid.

After an initial reset, the timer data is initialized to "0H".

ETI32, ETI8, ETI2: Interrupt mask registers (078H•D0–D2)

These registers are used to mask the clock timer interrupt.

When "1" is written: Enabled

When "0" is written: Masked

Reading: Valid

The interrupt mask registers (ETI32, ETI8, ETI2) mask the corresponding interrupt frequencies (32 Hz, 8

Hz, 2 Hz).

At initial reset, these registers are all set to "0".

TI32, TI8, TI2: Interrupt factor flags (079H•D0–D2)

These flags indicate the status of the clock timer interrupt.

When "1" is read: Interrupt has occurred

When "0" is read: Interrupt has not occurred

Writing: Invalid

The interrupt factor flags (TI32, TI8, TI2) correspond to the clock timer interrupts (32 Hz, 8 Hz, 2 Hz). The

software can determine from these flags whether there is a clock timer interrupt. However, even if the

interrupt is masked, the flags are set to "1" at the falling edge of the signal. These flags can be reset when

the register is read by the software.

Reading of interrupt factor flags is available at EI, but be careful in the following cases.

If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an

interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not

be generated. Be very careful when interrupt factor flags are in the same address.

At initial reset, these flags are set to "0".

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

S1C60N09 TECHNICAL MANUAL EPSON 33

TMRST: Clock timer reset (07EH•D3)

This bit resets the clock timer.

When "1" is written: Clock timer reset

When "0" is written: No operation

Reading: Always "0"

The clock timer is reset by writing "1" to TMRST. The clock timer starts immediately after this. No

operation results when "0" is written to TMRST.

This bit is write-only, and so is always "0" when read.

4.7.4 Programming notes

(1) Note that the frequencies and times differ from the description in this section when the oscillation

frequency is not 32.768 kHz.

(2) When the clock timer has been reset, the interrupt factor flag (TI) may sometimes be set to "1". Conse-

quently, reset the flag by reading as necessary at reset.

(3) Reading of interrupt factor flags is available at EI, but be careful in the following cases.

If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1, an

interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will

not be generated. Be very careful when interrupt factor flags are in the same address.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

34 EPSON S1C60N09 TECHNICAL MANUAL

4.8 Stopwatch Timer

4.8.1 Configuration of stopwatch timer

The S1C60N09 Series has a built-in 1/100 sec and 1/10 sec stopwatch timer. The stopwatch timer is

configured as a two-stage, four-bit BCD timer serving as the clock source for an approximately 100 Hz

signal (obtained by approximately dividing the 256 Hz signal output from the divider). Data can be read

out four bits at a time by the software.

Figure 4.8.1.1 is the block diagram of the stopwatch timer.

SWL timer

Data bus

10 Hz,1 Hz

256 Hz

Stopwatch timer reset signal

Stopwatch timer RUN/STOP signal

Oscillation

circuit

Interrupt

request

Interrupt

control

10 Hz SWH timer

Fig. 4.8.1.1 Block diagram of stopwatch timer

The stopwatch timer can be used separately from the clock timer. In particular, digital stopwatch func-

tions can be easily realized by software.

4.8.2 Count-up pattern

The stopwatch timer is configured as two four-bit BCD timers, SWL and SWH. The SWL timer, at the

stage preceding the stopwatch timer, has an approximate l00 Hz signal as its input clock. It counts up

every 1/100 sec and generates an approximate 10 Hz signal. The SWH timer has an approximate 10 Hz

signal generated by the SWL timer for its input clock. It counts up every 1/10 sec and generates a 1 Hz

signal.

Figure 4.8.2.1 shows the count-up pattern of the stopwatch timer.

256 26

256

256 25

256

256 2

256 3

256 2

256

256 3

256

256 2

256

256 2

256

256 3

256

256 2

256

256 25

256

x 6 + x 4 = 1 (S)

0 1 2 3 4 5 6 7 8 9 0

1 Hz

signal

generation

Approximate

10 Hz

signal

generation

Approximate

10 Hz

signal

generation

SWH count value

Counting time (S)

(S)

SWL count value

Counting time (S)

SWL count value

Counting time (S)

SWH count-up pattern

SWL count-up pattern 1

SWL count-up pattern 2

Fig. 4.8.2.1 Count-up pattern of stopwatch timer

SWL generates an approximate 10 Hz signal from the 256 Hz based signal. The count-up intervals are 2/

256 sec and 3/256 sec, so that two final patterns are generated: a 25/256 sec interval and a 26/256 sec

interval. Consequently, the count-up intervals are 2/256 sec and 3/256 sec, which do not amount to an

accurate 1/100 sec. SWH counts the approximate 10 Hz signals generated by the 25/256 sec and 26/256

sec intervals in the ratio of 4:6 to generate a l Hz signal. The count-up intervals are 25/256 sec and 26/256

sec, which do not amount to an accurate 1/10 sec.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

S1C60N09 TECHNICAL MANUAL EPSON 35

4.8.3 Interrupt function

The 10 Hz (approximate 10 Hz) and 1 Hz interrupts can be generated by the overflow of the SWL and

SWH stopwatch timers, respectively. Also, software can separately mask the frequencies as described

earlier.

Figure 4.8.3.1 is the timing chart for the stopwatch timer.

Address

Stopwatch timer (SWL) timing chart

Stopwatch timer (SWH) timing chart

10 Hz interrupt request

1 Hz interrupt request

072H

(1/10 sec BCD)

071H

(1/100 sec BCD)

Fig. 4.8.3.1 Timing chart for stopwatch timer

As shown in Figure 4.8.3.1, the interrupts are generated by the overflow of the respective timers ("9"

changing to "0"). Also at this point, the corresponding interrupt factor flags (SWIT0, SWIT1) are set to "1".

The respective interrupts can be masked separately with the interrupt mask registers (EISWIT0, EISWIT1).

However, regardless of the setting of the interrupt mask registers, the interrupt factor flags are set to "1"

by the overflow of the corresponding timers.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

36 EPSON S1C60N09 TECHNICAL MANUAL

4.8.4 I/O memory of stopwatch timer

Table 4.8.4.1 shows the stopwatch timer control bits and their addresses.

Table 4.8.4.1 Control bits of stopwatch timer

Address Comment

D3 D2

D1 D0 Name Init

∗1

071H

SWL3 SWL2 SWL1 SWL0

SWL3

SWL2

SWL1

SWL0

MSB

Stopwatch timer 1/100 sec data (BCD)

LSB

072H

SWH3 SWH2 SWH1 SWH0

SWH3

SWH2

SWH1

SWH0

MSB

Stopwatch timer 1/10 sec data (BCD)

LSB

076H

HLMOD 0 EISWIT1 EISWIT0

R/W R R/W

HLMOD

∗

EISWIT1

EISWIT0

–

∗

Heavy load

–

Enable

Normal

–

Mask

Heavy load protection mode register

Unused

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

07EH

TMRST SWRUN SWRST IOC0

WR/WWR/W

TMRST

∗

SWRUN

SWRST

∗

IOC0

Reset

Run

Reset

Output

–

Stop

–

Input

Clock timer reset

Stopwatch timer Run/Stop

Stopwatch timer reset

I/O control register 0 (P00–P03)

07AH

0 IK0 SWIT1 SWIT0

∗

IK0

∗

SWIT1

∗

SWIT0

∗

–

∗

–

Yes

–

Unused

Interrupt factor flag (K00–K03)

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

SWL0–SWL3: 1/100 sec stopwatch timer (071H)

Data (BCD) of the 1/100 sec column of the stopwatch timer can be read. These four bits are read-only, and

cannot be written.

After an initial reset, the timer data is set to "0H".

SWH0–SWH3: 1/10 sec stopwatch timer (072H)

Data (BCD) of the 1/10 sec column of the stopwatch timer can be read. These four bits are read-only, and

cannot be written.

After an initial reset, the timer data is set to "0H".

EISWIT0, EISWIT1: Interrupt mask registers (076H•D0, D1)

These registers mask the stopwatch timer interrupt.

When "1" is written: Enabled

When "0" is written: Masked

Reading: Valid

The interrupt mask registers (EISWIT0, EISWIT1) are used to mask the 10 Hz and 1 Hz interrupts,

respectively.

After an initial reset, these registers are both set to "0".

SWIT0, SWIT1: Interrupt factor flags (07AH•D0, D1)

These flags indicate the status of the stopwatch timer interrupt.

When "1" is read: Interrupt has occurred

When "0" is read: Interrupt has not occurred

Writing: Invalid

The interrupt factor flags (SWIT0, SWIT1) correspond to the 10 Hz and 1 Hz interrupts, respectively. With

these flags, the software can determine whether a stopwatch timer interrupt has occurred. However,

regardless of the interrupt mask register setting, these flags are set to "1" by the timer overflow.

They are reset by reading with the software.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

S1C60N09 TECHNICAL MANUAL EPSON 37

Reading of interrupt factor flags are available at EI, but be careful in the following cases.

If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an

interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not

be generated. Be very careful when interrupt factor flags are in the same address.

After an initial reset, these flags are set to "0".

SWRST: Stopwatch timer reset (07EH•D1)

This bit resets the stopwatch timer.

When "1" is written: Stopwatch timer reset

When "0" is written: No operation

Reading: Always "0"

The stopwatch timer is reset when "1" is written to SWRST. When the stopwatch timer is reset while

running, operation restarts immediately. Also, while stopped, the reset data is maintained.

This bit is write-only, and is always "0" when read.

SWRUN: Stopwatch timer run/stop (07EH•D2)

This bit controls run/stop of the stopwatch timer.

When "1" is written: Run

When "0" is written: Stop

Reading: Valid

The stopwatch timer runs when "1" is written to SWRUN, and stops when "0" is written.

When stopped, the timer data is maintained until the timer next Run or is reset. Also, when the timer

runs after being stopped, the data that was maintained can be used to resume the count.

If the timer data is read while running, a correct read may be impossible because of the carry from the

low-order bit (SWL) to the high-order bit (SWH). This occurs if reading has extended over the SWL and

SWH bits when the carry occurs. To prevent this, read after stopping, and then continue running. Also,

the stopped duration must be within 976 µsec (256 Hz, 1/4 cycle).

At initial reset, this register is set to "0".

4.8.5 Programming notes

(1) Note that the frequencies and times differ from the description in this section when the oscillation

frequency is not 32.768 kHz.

(2) If the timer data is read while running, a correct read may be impossible because of the carry from the

low-order bit (SWL) to the high-order bit (SWH). This occurs if reading has extended over the SWL

and SWH bits when the carry occurs. To prevent this, read after stopping, and then continue running.

Also, the stopped duration must be within 976 µsec (256 Hz, 1/4 cycle).

(3) Reading of interrupt factor flags are available at EI, but be careful in the following cases.

If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an

interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will

not be generated. Be very careful when interrupt factor flags are in the same address.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Circuit)

38 EPSON S1C60N09 TECHNICAL MANUAL

4.9 Heavy Load Protection Circuit

4.9.1 Heavy load protection function

The S1C60N09 Series has a heavy load protection function for when the battery load becomes heavy and

the source voltage changes, such as when an external buzzer sounds or an external lamp lights. The state

where the heavy load protection function is in effect is called the heavy load protection mode.

The normal mode changes to the heavy load protection mode in the following case:

• When the software changes the mode to the heavy load protection mode (HLMOD = "1")

In the heavy load protection mode, the internal voltage regulator is switched to the high-stability mode

from the low current consumption mode. Consequently, more current is consumed in the heavy load

protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load

protection mode with the software.

4.9.2 I/O memory of heavy load protection circuit

Table 4.9.2.1 shows the heavy load protection circuit control bit and the address.

Table 4.9.2.1 Control bit of heavy load protection circuit

Address Comment

D3 D2

D1 D0 Name Init

∗1

076H

HLMOD 0 EISWIT1 EISWIT0

R/W R R/W

HLMOD

∗

EISWIT1

EISWIT0

–

∗

Heavy load

–

Enable

Normal

–

Mask

Heavy load protection mode register

Unused

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

HLMOD: Heavy load protection mode control (076H•D3)

Controls the heavy load protection mode.

When "1" is written: Heavy load protection mode on

When "0" is written: Heavy load protection mode off

Reading: Valid

When HLMOD is set to "1", the IC enters the heavy load protection mode.

In the heavy load protection mode, the consumed current becomes larger. Unless necessary, do not select

the heavy load protection mode with the software.

After an initial reset, this register is set to "0".

4.9.3 Programming note

In the heavy load protection mode, the consumed current becomes larger. Unless necessary, do not select

the heavy load protection mode with the software.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

S1C60N09 TECHNICAL MANUAL EPSON 39

4.10 Interrupt and HALT

The S1C60N09 Series provides the following interrupt settings, each of which is maskable.

External interrupt: Input port interrupt (one)

Internal interrupt: Timer interrupt (three)

Stopwatch interrupt (two)

To enable interrupts, the interrupt flag must be set to "1" (EI) and the necessary related interrupt mask

registers must be set to "1" (enable). When an interrupt occurs, the interrupt flag is automatically reset to

"0" (DI) and interrupts after that are inhibited.

Figure 4.10.1 shows the configuration of the interrupt circuit.

K00

EIK00

K01

EIK01

K02

EIK02

K03

EIK03

SWIT0

EISWIT0

SWIT1

EISWIT1

TI2

ETI2

TI8

ETI8

TI32

ETI32

IK0

(MSB)

(LSB)

Program counter

(low-order 4 bits)

Interrupt vector

Interrupt factor flag

Interrupt mask register

Interrupt flag

INT

(Interrupt request)

Fig. 4.10.1 Configuration of interrupt circuit

HALT mode

When the HALT instruction is executed, the CPU stops operating and enters the HALT mode. The

oscillation circuit and the peripheral circuits operate in the HALT mode. By an interrupt, the CPU exits

the HALT mode and resumes operating.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

40 EPSON S1C60N09 TECHNICAL MANUAL

4.10.1 Interrupt factors

Table 4.10.1.1 shows the factors that generate interrupt requests.

The interrupt factor flags are set to "1" depending on the corresponding interrupt factors.

The CPU is interrupted when the following two conditions occur and an interrupt factor flag is set to "1".

• The corresponding mask register is "1" (enabled)

• The interrupt flag is 1 (EI)

The interrupt factor flag is a read-only register, but can be reset to "0" when the register data is read.

At initial reset, the interrupt factor flags are reset to "0".

Note: Reading of interrupt factor flag is available at EI, but be careful in the following cases.

If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1",

an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request

will not be generated. Be very careful when interrupt factor flags are in the same address.

Table 4.10.1.1 Interrupt factors

Interrupt factor

Clock timer 2 Hz falling edge

Clock timer 8 Hz falling edge

Clock timer 32 Hz falling edge

Stopwatch timer 1 Hz falling edge

Stopwatch timer 10 Hz falling edge

Input (K00–K03) port falling edge

Interrupt factor flag

TI2 (079H•D2)

TI8 (079H•D1)

TI32 (079H•D0)

SWIT1 (07AH•D1)

SWIT0 (07AH•D0)

IK0 (07AH•D2)

4.10.2 Specific masks for interrupt

The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt

mask registers are read/write registers. The interrupts are enabled when "1" is written to them, and

masked (interrupt disabled) when "0" is written to them.

At initial reset, the interrupt mask register is set to "0".

Table 4.10.2.1 shows the correspondence between interrupt mask registers and interrupt factor flags.

Table 4.10.2.1 Interrupt mask registers and interrupt factor flags

Interrupt mask register

ETI2 (078H•D2)

ETI8 (078H•D1)

ETI32 (078H•D0)

EISWIT1 (076H•D1)

EISWIT0 (076H•D0)

EIK03* (075H•D3)

EIK02* (075H•D2)

EIK01* (075H•D1)

EIK00* (075H•D0)

Interrupt factor flag

TI2 (079H•D2)

TI8 (079H•D1)

TI32 (079H•D0)

SWIT1 (07AH•D1)

SWIT0 (07AH•D0)

IK0 (07AH•D2)

∗ There is an interrupt mask register for each input port terminal.

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

S1C60N09 TECHNICAL MANUAL EPSON 41

4.10.3 Interrupt vectors

When an interrupt request is input to the CPU, the CPU starts interrupt processing. After the program

being executed is suspended, interrupt processing is executed in the following order:

(1) The address data (value of the program counter) of the program step to be executed next is saved on

the stack (RAM).

(2) The interrupt request causes the value of the interrupt vector (page 1, 02H–0FH) to be loaded into the

program counter.

(3) The program at the specified address is executed (execution of interrupt processing routine).

Note: The processing in steps (1) and (2), above, takes 12 cycles of the CPU system clock.

Table 4.10.3.1 Interrupt vector addresses

Page

1Step

02H

04H

06H

08H

0AH

0CH

0EH

Interrupt vector

Input (K00–K03) interrupt

Clock timer interrupt

Clock timer + Input interrupt

Stopwatch timer interrupt

Stopwatch timer + Input interrupt

Stopwatch timer + Clock timer interrupt

Stopwatch timer + Clock timer + Input interrupt

4.10.4 I/O memory of interrupt

Table 4.10.4.1 shows the interrupt control bits and their addresses.

Table 4.10.4.1 Control bits of interrupt

Address Comment

D3 D2

D1 D0 Name Init

∗1

075H

EIK03 EIK02 EIK01 EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Enable

Mask

Interrupt mask register (K00–K03)

076H

HLMOD 0 EISWIT1 EISWIT0

R/W R R/W

HLMOD

∗

EISWIT1

EISWIT0

–

∗

Heavy load

–

Enable

Normal

–

Mask

Heavy load protection mode register

Unused

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

078H

CSDC ETI2 ETI8 ETI32

R/W

CSDC

ETI2

ETI8

ETI32

Static

Enable

Dynamic

Mask

LCD drive switch

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

079H

0 TI2 TI8 TI32

∗

TI2

∗

TI8

∗

TI32

∗

–

∗

–

Yes

–

Unused

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

07AH

0 IK0 SWIT1 SWIT0

∗

IK0

∗

SWIT1

∗

SWIT0

∗

–

∗

–

Yes

–

Unused

Interrupt factor flag (K00–K03)

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

ETI32, ETI8, ETI2: Interrupt mask registers (078H•D0–D2)

TI32, TI8, TI2: Interrupt factor flags (079H•D0–D2) ...See Section 4.7, "Clock Timer".

EISWIT0, EISWIT1: Interrupt mask registers (076H•D0, D1)

SWIT0, SWIT1: Interrupt factor flags (07AH•D0, D1) ...See Section 4.8, "Stopwatch Timer".

EIK00–EIK03: Interrupt mask registers (075H)

IK0: Interrupt factor flag (07AH•D2) ...See Section 4.3, "Input Ports".

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

42 EPSON S1C60N09 TECHNICAL MANUAL

4.10.5 Programming notes

(1) Restart from the HALT mode is performed by an interrupt. The return address after completion of the

interrupt processing will be the address following the HALT instruction.

(2) When an interrupt occurs, the interrupt flag will be reset by the hardware and it will become DI

status. After completion of the interrupt processing, set to the EI status through the software as

needed.

Moreover, the nesting level may be set to be programmable by setting to the EI state at the beginning

of the interrupt processing routine.

(3) The interrupt factor flags must always be reset before setting the EI status. When the interrupt mask

the interrupt factor flag.

(4) The interrupt factor flag will be reset by reading through the software. Because of this, when multiple

interrupt factor flags are to be assigned to the same address, perform the flag check after the contents

of the address has been stored in the RAM. Direct checking with the FAN instruction will cause all the

interrupt factor flag to be reset.

(5) Reading of interrupt factor flag is available at EI, but be careful in the following cases.

If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an

interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will

not be generated. Be very careful when interrupt factor flags are in the same address.

CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM

S1C60N09 TECHNICAL MANUAL EPSON 43

CHAPTER 5BASIC EXTERNAL WIRING DIAGRAM

Piezo Buzzer Single Terminal Driving

Note: The above table is simply an example, and is not guaranteed to work.

Piezo Buzzer Direct Driving

K00

K01

K02

K03

P00

P01

P02

P03

P10

P11

P12

P13

R02 (FOUT)

R03 (BZ)

R01 SEG0

SEG37

COM0

COM3

R00 (BZ)

VL1

VL2

VL3

VDD

OSC1

OSC2

VS1

RESET

TEST

VSS

Lamp Piezo

CGX

X'tal

Capacitors (C2 and C3) are connected.

Connection depends on power supply

and LCD panel specification.

Please refer to Figure 2.1.1.

S1C60N09

S1C60L09

LCD panel

I/O

X'tal

CGX

Crystal oscillator

Trimmer capacitor

Capacitor

32.768 kHz, CI = 35 kΩ

5–25 pF

0.1 µF

3.3 µF

R00 (BZ)

R03 (BZ)

RA2RA1

Piezo

S1C60N09/60L09

RA1

RA2 Protection resistor

Protection resistor 100 Ω

100 Ω

When driving the buzzer, set the IC into the heavy load

protection mode since the supply voltage changes

according to the buzzer frequency.

CHAPTER 6: ELECTRICAL CHARACTERISTICS

44 EPSON S1C60N09 TECHNICAL MANUAL

CHAPTER 6ELECTRICAL CHARACTERISTICS

6.1 Absolute Maximum Rating

S1C60N09

Item

Supply voltage

Input voltage (1)

Input voltage (2)

Operating temperature

Storage temperature

Soldering temperature / time

=0V)

Symbol

IOSC

Topr

Tstg

Tsol

Rated value

-5.5 to 0.5

- 0.3 to 0.5

-20 to 70

-65 to 150

260°C, 10sec (lead section)

Unit

°C

–

S1C60L09

Item

Supply voltage

Input voltage (1)

Input voltage (2)

Operating temperature

Storage temperature

Soldering temperature / time

=0V)

Symbol

IOSC

Topr

Tstg

Tsol

Rated value

-2.0 to 0.5

- 0.3 to 0.5

-20 to 70

-65 to 150

260°C, 10sec (lead section)

Unit

°C

–

6.2 Recommended Operating Conditions

S1C60N09

Item

Supply voltage

Oscillation frequency

Booster capacitor

Capacitor between VDD and VS1

∗1

(Ta=-20 to 70°C)

Symbol

VSS

fOSC

C3 or C4 *1

Unit

kHz

µF

Max.

-2.6

Typ.

-3.0

32.768

Min.

-3.6

0.1

Depends on the LCD specification. Please refer to Figure 2.1.1.

Condition

VDD=0V

Crystal oscillation

CR oscillation, RCR=475kΩ

S1C60L09

Item

Supply voltage

Oscillation frequency

Booster capacitor

Capacitor between VDD and VS1

∗1

(Ta=-20 to 70°C)

Symbol

VSS

fOSC

C3 or C4 *1

Unit

kHz

µF

Max.

-1.2

Typ.

-1.5

32.768

Min.

-1.8

0.1

Depends on the LCD specification. Please refer to Figure 2.1.1.

Condition

VDD=0V

Crystal oscillation

CR oscillation, RCR=475kΩ

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C60N09 TECHNICAL MANUAL EPSON 45

6.3 DC Characteristics

S1C60N09

Item

High level input voltage (1)

High level input voltage (2)

Low level input voltage (1)

Low level input voltage (2)

High level input current (1)

High level input current (2)

High level input current (3)

Low level input current

High level output current (1)

High level output current (2)

Low level output current (1)

Low level output current (2)

Common output current

Segment output current

(during LCD output)

Segment output current

(during DC output)

Unless otherwise specified:

=0V, V

=-3.0V, fosc=32.768kHz, Ta=25°C, V

–V

are internal voltage, C

–C

=0.1µF

Symbol

IH1

IH2

IL1

IL2

IH1

IH2

IH3

OH1

OH2

OL1

OL2

OH3

OL3

OH4

OL4

OH5

OL5

Unit

µA

Max.

0.8·V

0.9·V

0.5

200

-1.8

-0.9

-3

-200

Typ.Min.

0.2·V

0.1·V

-0.5

4.0

3.0

200

Condition

K00–03, P00–03, P10–13

RESET, TEST

K00–03, P00–03, P10–13

RESET, TEST

IH1

=0V, No pull-down K00–03, P00–03, P10–13

IH2

=0V, Pull-down K00–03

IH3

=0V, Pull-down P00–03, P10–13

RESET, TEST

K00–03, P00–03, P10–13

RESET, TEST

OH1

=0.1·V

R00, R03

OH2

=0.1·V

R01, R02,

P00–03, P10–13

OL1

=0.9·V

R00, R03

OL2

=0.9·V

R01, R02,

P00–03, P10–13

OH3

=-0.05V COM0–3

OL3

+0.05V

OH4

=-0.05V SEG0–37

OL4

+0.05V

OH5

=0.1·V

SEG0–37

OL5

=0.9·V

S1C60L09

Item

High level input voltage (1)

High level input voltage (2)

Low level input voltage (1)

Low level input voltage (2)

High level input current (1)

High level input current (2)

High level input current (3)

Low level input current

High level output current (1)

High level output current (2)

Low level output current (1)

Low level output current (2)

Common output current

Segment output current

(during LCD output)

Segment output current

(during DC output)

Unless otherwise specified:

VDD=0V, VSS=-1.5V, fosc=32.768kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C4=0.1µF

Symbol

VIH1

VIH2

VIL1

VIL2

IIH1

IIH2

IIH3

IIL

IOH1

IOH2

IOL1

IOL2

IOH3

IOL3

IOH4

IOL4

IOH5

IOL5

Unit

µA

Max.

0.8·VSS

0.9·V

0.5

100

-300

-150

-3

-100

Typ.Min.

0.2·VSS

0.1·V

VSS

-0.5

1400

700

100

Condition

K00–03, P00–03, P10–13

RESET, TEST

K00–03, P00–03, P10–13

RESET, TEST

VIH1=0V, No pull-down K00–03, P00–03, P10–13

VIH2=0V, Pull-down K00–03

VIH3=0V, Pull-down P00–03, P10–13

RESET, TEST

VIL=VSS K00–03, P00–03, P10–13

RESET, TEST

VOH1=0.1·VSS R00, R03

VOH2=0.1·VSS R01, R02,

P00–03, P10–13

VOL1=0.9·VSS R00, R03

VOL2=0.9·VSS R01, R02,

P00–03, P10–13

VOH3=-0.05V COM0–3

VOL3=VL3+0.05V

VOH4=-0.05V SEG0–37

VOL4=VL3+0.05V

VOH5=0.1·VSS SEG0–37

VOL5=0.9·VSS

CHAPTER 6: ELECTRICAL CHARACTERISTICS

46 EPSON S1C60N09 TECHNICAL MANUAL

6.4 Analog Circuit Characteristics and Current Consumption

S1C60N09 (Crystal oscillation)

• 4.5 V LCD panel, 1/4, 1/3, 1/2 duty, 1/3 bias (VL2 is shor ted to VSS inside the IC)

Normal mode

Item

LCD drive voltage

Current consumption

Unless otherwise specified:

VDD=0V, VSS=-3.0V, fOSC=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C4=0.1µF

Symbol

VL1

VL2

VL3

IOP

Unit

µA

Max.

1/2·VL2

×0.9

3/2·VL2

×0.9

2.5

5.0

Typ.

VSS

1.0

2.5

Min.

1/2·VL2

- 0.1

3/2·VL2

- 0.1

Condition

Connect 1 MΩ load resistor between VDD and VL1

(without panel load)

Connect 1 MΩ load resistor between VDD and VL2

(without panel load)

Connect 1 MΩ load resistor between VDD and VL3

(without panel load)

During HALT Without

During execution panel load

Heavy load protection mode

Item

LCD drive voltage

Current consumption

Unless otherwise specified:

VDD=0V, VSS=-3.0V, fOSC=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C4=0.1µF

Symbol

VL1

VL2

VL3

IOP

Unit

µA

Max.

1/2·VL2

×0.85

3/2·VL2

×0.85

5.5

10.0

Typ.

VSS

2.0

5.5

Min.

1/2·VL2

- 0.1

3/2·VL2

- 0.1

Condition

Connect 1 MΩ load resistor between VDD and VL1

(without panel load)

Connect 1 MΩ load resistor between VDD and VL2

(without panel load)

Connect 1 MΩ load resistor between VDD and VL3

(without panel load)

During HALT Without

During execution panel load

• 3 V LCD panel, 1/4, 1/3, 1/2 duty, 1/2 bias (VL3 is shor ted to VSS inside the IC and VL1 is shorted

to VL2 outside the IC)

Normal mode

Item

LCD drive voltage

Current consumption

Unless otherwise specified:

VDD=0V, VSS=-3.0V, fOSC=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C3=0.1µF

Symbol

VL1

VL2

VL3

IOP

Unit

µA

Max.

1/2·VL3

×0.9

1/2·VL3

×0.9

2.5

5.0

Typ.

VSS

1.0

2.5

Min.

1/2·VL3

- 0.1

1/2·VL3

- 0.1

Condition

Connect 1 MΩ load resistor between VDD and VL1

(without panel load)

Connect 1 MΩ load resistor between VDD and VL2

(without panel load)

Connect 1 MΩ load resistor between VDD and VL3

(without panel load)

During HALT Without

During execution panel load

Heavy load protection mode

Item

LCD drive voltage

Current consumption

Unless otherwise specified:

VDD=0V, VSS=-3.0V, fOSC=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C3=0.1µF

Symbol

VL1

VL2

VL3

IOP

Unit

µA

Max.

1/2·VL3

×0.85

1/2·VL3

×0.85

5.5

10.0

Typ.

VSS

2.0

5.5

Min.

1/2·VL3

- 0.1

1/2·VL3

- 0.1

Condition

Connect 1 MΩ load resistor between VDD and VL1

(without panel load)

Connect 1 MΩ load resistor between VDD and VL2

(without panel load)

Connect 1 MΩ load resistor between VDD and VL3

(without panel load)

During HALT Without

During execution panel load

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C60N09 TECHNICAL MANUAL EPSON 47

S1C60L09 (Crystal oscillation)

• 4.5 V LCD panel, 1/4, 1/3, 1/2 duty, 1/3 bias (VL1 is shor ted to VSS inside the IC)

Normal mode

Item

LCD drive voltage

Current consumption

Unless otherwise specified:

VDD=0V, VSS=-1.5V, fOSC=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C4=0.1µF

Symbol

VL1

VL2

VL3

IOP

Unit

µA

Max.

2·VL1

×0.9

3·VL1

×0.9

2.5

5.0

Typ.

VSS

1.0

2.5

Min.

2·VL1

- 0.1

3·VL1

- 0.1

Condition

Connect 1 MΩ load resistor between VDD and VL1

(without panel load)

Connect 1 MΩ load resistor between VDD and VL2

(without panel load)

Connect 1 MΩ load resistor between VDD and VL3

(without panel load)

During HALT Without

During execution panel load

Heavy load protection mode

Item

LCD drive voltage

Current consumption

Unless otherwise specified:

VDD=0V, VSS=-1.5V, fOSC=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C4=0.1µF

Symbol

VL1

VL2

VL3

IOP

Unit

µA

Max.

2·VL1

×0.85

3·VL1

×0.85

5.5

10.0

Typ.

VSS

2.0

5.5

Min.

2·VL1

- 0.1

3·VL1

- 0.1

Condition

Connect 1 MΩ load resistor between VDD and VL1

(without panel load)

Connect 1 MΩ load resistor between VDD and VL2

(without panel load)

Connect 1 MΩ load resistor between VDD and VL3

(without panel load)

During HALT Without

During execution panel load

• 3 V LCD panel, 1/4, 1/3, 1/2 duty, 1/2 bias (VL1 is shor ted to VSS inside the IC and VL1 is shorted

to VL2 outside the IC)

Normal mode

Item

LCD drive voltage

Current consumption

Unless otherwise specified:

VDD=0V, VSS=-1.5V, fOSC=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C3=0.1µF

Symbol

VL1

VL2

VL3

IOP

Unit

µA

Max.

2·VL1

×0.9

2.5

5.0

Typ.

VSS

1.0

2.5

Min.

2·VL1

- 0.1

Condition

Connect 1 MΩ load resistor between VDD and VL1

(without panel load)

Connect 1 MΩ load resistor between VDD and VL2

(without panel load)

Connect 1 MΩ load resistor between VDD and VL3

(without panel load)

During HALT Without

During execution panel load

Heavy load protection mode

Item

LCD drive voltage

Current consumption

Unless otherwise specified:

VDD=0V, VSS=-1.5V, fOSC=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C3=0.1µF

Symbol

VL1

VL2

VL3

IOP

Unit

µA

Max.

2·VL1

×0.85

5.5

10.0

Typ.

VSS

2.0

5.5

Min.

2·VL1

- 0.1

Condition

Connect 1 MΩ load resistor between VDD and VL1

(without panel load)

Connect 1 MΩ load resistor between VDD and VL2

(without panel load)

Connect 1 MΩ load resistor between VDD and VL3

(without panel load)

During HALT Without

During execution panel load

CHAPTER 6: ELECTRICAL CHARACTERISTICS

48 EPSON S1C60N09 TECHNICAL MANUAL

S1C60N09 (CR oscillation)

• 4.5 V LCD panel, 1/4, 1/3, 1/2 duty, 1/3 bias (VL2 is shor ted to VSS inside the IC)

Normal mode

Item

LCD drive voltage

Current consumption

Unless otherwise specified:

VDD=0V, VSS=-3.0V, fOSC=65kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C4=0.1µF, RCR=475kΩ

Symbol

VL1

VL2

VL3

IOP

Unit

µA

Max.

1/2·VL2

×0.9

3/2·VL2

×0.9

15.0

20.0

Typ.

VSS

8.0

15.0

Min.

1/2·VL2

- 0.1

3/2·VL2

- 0.1

Condition

Connect 1 MΩ load resistor between VDD and VL1

(without panel load)

Connect 1 MΩ load resistor between VDD and VL2

(without panel load)

Connect 1 MΩ load resistor between VDD and VL3

(without panel load)

During HALT Without

During execution panel load

Heavy load protection mode

Item

LCD drive voltage

Current consumption

Unless otherwise specified:

VDD=0V, VSS=-3.0V, fOSC=65kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C4=0.1µF, RCR=475kΩ

Symbol

VL1

VL2

VL3

IOP

Unit

µA

Max.

1/2·VL2

×0.85

3/2·VL2

×0.85

30.0

40.0

Typ.

VSS

16.0

30.0

Min.

1/2·VL2

- 0.1

3/2·VL2

- 0.1

Condition

Connect 1 MΩ load resistor between VDD and VL1

(without panel load)

Connect 1 MΩ load resistor between VDD and VL2

(without panel load)

Connect 1 MΩ load resistor between VDD and VL3

(without panel load)

During HALT Without

During execution panel load

• 3 V LCD panel, 1/4, 1/3, 1/2 duty, 1/2 bias (VL3 is shor ted to VSS inside the IC and VL1 is shorted

to VL2 outside the IC)

Normal mode

Item

LCD drive voltage

Current consumption

Unless otherwise specified:

VDD=0V, VSS=-3.0V, fOSC=65kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C3=0.1µF, RCR=475kΩ

Symbol

VL1

VL2

VL3

IOP

Unit

µA

Max.

1/2·VL3

×0.9

1/2·VL3

×0.9

15.0

20.0

Typ.

VSS

8.0

15.0

Min.

1/2·VL3

- 0.1

1/2·VL3

- 0.1

Condition

Connect 1 MΩ load resistor between VDD and VL1

(without panel load)

Connect 1 MΩ load resistor between VDD and VL2

(without panel load)

Connect 1 MΩ load resistor between VDD and VL3

(without panel load)

During HALT Without

During execution panel load

Heavy load protection mode

Item

LCD drive voltage

Current consumption

Unless otherwise specified:

VDD=0V, VSS=-3.0V, fOSC=65kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C3=0.1µF, RCR=475kΩ

Symbol

VL1

VL2

VL3

IOP

Unit

µA

Max.

1/2·VL3

×0.85

1/2·VL3

×0.85

30.0

40.0

Typ.

VSS

16.0

30.0

Min.

1/2·VL3

- 0.1

1/2·VL3

- 0.1

Condition

Connect 1 MΩ load resistor between VDD and VL1

(without panel load)

Connect 1 MΩ load resistor between VDD and VL2

(without panel load)

Connect 1 MΩ load resistor between VDD and VL3

(without panel load)

During HALT Without

During execution panel load

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C60N09 TECHNICAL MANUAL EPSON 49

S1C60L09 (CR oscillation)

• 4.5 V LCD panel, 1/4, 1/3, 1/2 duty, 1/3 bias (VL1 is shor ted to VSS inside the IC)

Normal mode

Item

LCD drive voltage

Current consumption

Unless otherwise specified:

VDD=0V, VSS=-1.5V, fOSC=65kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C4=0.1µF, RCR=475kΩ

Symbol

VL1

VL2

VL3

IOP

Unit

µA

Max.

2·VL1

×0.9

3·VL1

×0.9

15.0

20.0

Typ.

VSS

8.0

15.0

Min.

2·VL1

- 0.1

3·VL1

- 0.1

Condition

Connect 1 MΩ load resistor between VDD and VL1

(without panel load)

Connect 1 MΩ load resistor between VDD and VL2

(without panel load)

Connect 1 MΩ load resistor between VDD and VL3

(without panel load)

During HALT Without

During execution panel load

Heavy load protection mode

Item

LCD drive voltage

Current consumption

Unless otherwise specified:

VDD=0V, VSS=-1.5V, fOSC=65kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C4=0.1µF, RCR=475kΩ

Symbol

VL1

VL2

VL3

IOP

Unit

µA

Max.

2·VL1

×0.85

3·VL1

×0.85

30.0

40.0

Typ.

VSS

16.0

30.0

Min.

2·VL1

- 0.1

3·VL1

- 0.1

Condition

Connect 1 MΩ load resistor between VDD and VL1

(without panel load)

Connect 1 MΩ load resistor between VDD and VL2

(without panel load)

Connect 1 MΩ load resistor between VDD and VL3

(without panel load)

During HALT Without

During execution panel load

• 3 V LCD panel, 1/4, 1/3, 1/2 duty, 1/2 bias (VL1 is shor ted to VSS inside the IC and VL1 is shorted

to VL2 outside the IC)

Normal mode

Item

LCD drive voltage

Current consumption

Unless otherwise specified:

VDD=0V, VSS=-1.5V, fOSC=65kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C3=0.1µF, RCR=475kΩ

Symbol

VL1

VL2

VL3

IOP

Unit

µA

Max.

2·VL1

×0.9

15.0

20.0

Typ.

VSS

8.0

15.0

Min.

2·VL1

- 0.1

Condition

Connect 1 MΩ load resistor between VDD and VL1

(without panel load)

Connect 1 MΩ load resistor between VDD and VL2

(without panel load)

Connect 1 MΩ load resistor between VDD and VL3

(without panel load)

During HALT Without

During execution panel load

Heavy load protection mode

Item

LCD drive voltage

Current consumption

Unless otherwise specified:

VDD=0V, VSS=-1.5V, fOSC=65kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C3=0.1µF, RCR=475kΩ

Symbol

VL1

VL2

VL3

IOP

Unit

µA

Max.

2·VL1

×0.85

30.0

40.0

Typ.

VSS

16.0

30.0

Min.

2·VL1

- 0.1

Condition

Connect 1 MΩ load resistor between VDD and VL1

(without panel load)

Connect 1 MΩ load resistor between VDD and VL2

(without panel load)

Connect 1 MΩ load resistor between VDD and VL3

(without panel load)

During HALT Without

During execution panel load

CHAPTER 6: ELECTRICAL CHARACTERISTICS

50 EPSON S1C60N09 TECHNICAL MANUAL

6.5 Oscillation Characteristics

Oscillation characteristics will vary according to different conditions (elements used, board pattern). Use

the following characteristics are as reference values.

S1C60N09 Crystal Oscillation

Item

Oscillation start voltage

Oscillation stop voltage

Built-in capacitance (drain)

Frequency/voltage deviation

Frequency/IC deviation

Frequency adjustment range

Harmonic oscillation start voltage

Permitted leak resistance

Symbol

Vsta

Vstp

∂f/∂V

∂f/∂IC

∂f/∂C

hho

leak

Unit

ppm

MΩ

Max.

-3.6

Typ.

Min.

-2.6

-10

200

Condition

tsta≤5sec (V

)

tstp≤10sec (V

)

Including the parasitic capacitance inside the chip

=-2.6 to -3.6V

=5 to 25pF

)

Between OSC1 and V

, V

Unless otherwise specified:

=0V, V

=-3.0V, f

OSC

=32.768kHz, Crystal: Q13MC146, C

=25pF, C

=built-in, Ta=25°C

S1C60L09 Crystal Oscillation

Item

Oscillation start voltage

Oscillation stop voltage

Built-in capacitance (drain)

Frequency/voltage deviation

Frequency/IC deviation

Frequency adjustment range

Harmonic oscillation start voltage

Permitted leak resistance

Symbol

Vsta

Vstp

∂f/∂V

∂f/∂IC

∂f/∂C

hho

leak

Unit

ppm

MΩ

Max.

-1.8

Typ.

Min.

-1.2

-10

200

Condition

tsta≤5sec (V

)

tstp≤10sec (V

)

Including the parasitic capacitance inside the chip

=-1.2 to -1.8V

=5 to 25pF

)

Between OSC1 and V

, V

Unless otherwise specified:

=0V, V

=-1.5V, f

OSC

=32.768kHz, Crystal: Q13MC146, C

=25pF, C

=built-in, Ta=25°C

S1C60N09 CR Oscillation

Item

Oscillation frequency dispersion

Oscillation start time

Symbol

fOSC

tsta

Unit

kHz

Max.

84.5

Typ.

Min.

45.5

Condition

VSS=-2.6 to -3.6V

Unless otherwise specified:

VDD=0V, VSS=-3.0V, RCR=475kΩ, Ta=25°C

S1C60L09 CR Oscillation

Item

Oscillation frequency dispersion

Oscillation start time

Symbol

fOSC

tsta

Unit

kHz

Max.

84.5

Typ.

Min.

45.5

Condition

VSS=-1.2 to -1.8V

Unless otherwise specified:

VDD=0V, VSS=-1.5V, RCR=475kΩ, Ta=25°C

CHAPTER 7: CERAMIC PACKAGE FOR TEST SAMPLES

S1C60N09 TECHNICAL MANUAL EPSON 51

CHAPTER 7

ERAMIC

ACKAGE

FOR

EST

AMPLES

(Unit: mm)

4164

241

14.0

± 0.14

20.9

± 0.15

20.0

± 0.18

26.8

± 0.15

0.80

± 0.05

0.35

± 0.05

0.4

± 0.08

0.8

0.76

± 0.08

0.95

± 0.08

Grass

No.

Name

SEG35

N.C.

SEG36

SEG37

K03

K02

K01

K00

P13

P12

P11

P10

P03

P02

P01

P00

R02

R01

R00

No.

Name

R03

N.C.

RESET

OSC2

OSC1

COM3

COM2

COM1

COM0

SEG0

No.

Name

N.C.

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

No.

Name

N.C.

SEG19

TEST

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

N.C. : No Connection

CHAPTER 8: PRECAUTIONS ON MOUNTING

52 EPSON S1C60N09 TECHNICAL MANUAL

CHAPTER 8PRECAUTIONS ON MOUNTING

●Oscillation characteristics change depending on conditions (board pattern, components used, etc.).

In particular, when using a crystal oscillator, use the oscillator manufacturer's recommended values

for constants such as capacitance and resistance.

●Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following

points to prevent this:

(1) Components which are connected to the OSC1 and OSC2 terminals, such as oscillators, resistors

and capacitors, should be connected in the shortest line.

(2) As shown in the right hand figure, make a VDD pattern as large as

possible at circumscription of the OSC1 and OSC2 terminals and the

components connected to these terminals.

Furthermore, do not use this VDD pattern for any purpose other than

the oscillation system.

●In order to prevent unstable operation of the oscillation circuit due to

current leak between OSC1 and VSS, please keep enough distance between OSC1 and VSS or other

signals on the board pattern.

●The power-on reset signal which is input to the RESET terminal changes depending on conditions

(power rise time, components used, board pattern, etc.).

Decide the time constant of the capacitor and resistor after enough tests have been completed with the

application product.

When the built-in pull-down resistor is added to the RESET terminal by mask option, take into

consideration dispersion of the resistance for setting the constant.

●In order to prevent any occurrences of unnecessary resetting caused by noise during operating,

components such as capacitors and resistors should be connected to the RESET terminal in the

shortest line.

●Sudden power supply variation due to noise may cause malfunction. Consider the following points to

prevent this:

(1) The power supply should be connected to the VDD and VSS terminal with patterns as short and

large as possible.

(2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals

should be connected as short as possible.

VDD

VSS

Bypass capacitor connection example

VDD

VSS

(3) Components which are connected to the VS1, VL1, VL2, VL3 terminals, such as a capacitor, should

be connected in the shortest line.

OSC2

OSC1

VDD

Sample VDD pattern

CHAPTER 8: PRECAUTIONS ON MOUNTING

S1C60N09 TECHNICAL MANUAL EPSON 53

●In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do

not arrange a large current signal line near the circuits that are sensitive to noise such as the oscilla-

tion unit.

●When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line,

noise may generated by mutual interference between the signals and it may cause a malfunction.

Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the

oscillation unit.

OSC2

OSC1

VDD

Large current signal line

High-speed signal line

Prohibited pattern

●Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause

this IC to malfunction. When developing products which use this IC, consider the following precau-

tions to prevent malfunctions caused by visible radiations.

(1) Design the product and implement the IC on the board so that it is shielded from visible radiation

in actual use.

(2) The inspection process of the product needs an environment that shields the IC from visible

radiation.

(3) As well as the face of the IC, shield the back and side too.

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http://www.epson.co.jp/device/

Technical Manual

S1C60N09

EPSON Electronic Devices Website

ELECTRONIC DEVICES MARKETING DIVISION

First issue December, 1998

Printed March, 2001 in Japan A