DS28E01P-100+T&R - Hytronics

General Description

The DS28E01-100 combines 1024 bits of EEPROM with

challenge-and-response authentication security imple-

mented with the ISO/IEC 10118-3 Secure Hash

Algorithm (SHA-1). The 1024-bit EEPROM array is con-

figured as four pages of 256 bits with a 64-bit scratch-

pad to perform write operations. All memory pages can

be write protected, and one page can be put in

EPROM-emulation mode, where bits can only be

changed from a 1 to a 0 state. Each DS28E01-100 has

its own guaranteed unique 64-bit ROM registration num-

ber that is factory lasered into the chip. The DS28E01-

100 communicates over the single-contact 1-Wire®bus.

The communication follows the standard 1-Wire protocol

with the registration number acting as the node address

in the case of a multidevice 1-Wire network.

Applications

Printer Cartridge Configuration and Monitoring

Medical Sensor Authentication and Calibration

System Intellectual Property Protection

Features

♦1024 Bits of EEPROM Memory Partitioned Into

Four Pages of 256 Bits

♦On-Chip 512-Bit SHA-1 Engine to Compute 160-

Bit Message Authentication Codes (MACs) and to

Generate Secrets

♦Write Access Requires Knowledge of the Secret

and the Capability of Computing and Transmitting

a 160-Bit MAC as Authorization

♦User-Programmable Page Write Protection for

Page 0, Page 3, or All Four Pages Together

♦User-Programmable OTP EPROM Emulation Mode

for Page 1 (“Write to 0”)

♦Communicates to Host with a Single Digital

Signal at 15.3kbps or 125kbps Using 1-Wire

Protocol

♦Switchpoint Hysteresis and Filtering to Optimize

Performance in the Presence of Noise

♦Reads and Writes Over 2.8V to 5.25V Voltage

Range from -40°C to +85°C

♦6-Lead TSOC and TDFN or 2-Lead SFN Packages

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

________________________________________________________________

Maxim Integrated Products

Ordering Information

Rev: 2/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

ABRIDGED DATA SHEET

PART TEMP RANGE PIN-PACKAGE

DS28E01P-100+ -40°C to +85°C 6 TSOC

DS28E01P-100+T&R -40°C to +85°C 6 TSOC

DS28E01G-100+T&R -40°C to +85°C 2 SFN

DS28E01Q-100+T&R -40°C to +85°C6 TDFN-EP*

(2.5k pcs)

Denotes a lead(Pb)-free/RoHS-compliant package.

T&R = Tape and reel.

EP = Exposed pad.

RPUP

VCC

μC

GND

DS28E01-100

Typical Operating Circuit

1-Wire is a registered trademark of Maxim Integrated Products, Inc.

Pin Configurations appear at end of data sheet.

Note to readers: This document is an abridged version of the full data sheet. To request the full data sheet, go to

www.maxim-ic.com/DS28E01 and click on Request Full Data Sheet.

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

2 _______________________________________________________________________________________

ABRIDGED DATA SHEET

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(TA= -40°C to +85°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

IO Voltage Range to GND .......................................-0.5V to +6V

IO Sink Current ...................................................................20mA

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-55°C to +125°C

Soldering Temperature...........................Refer to the IPC/JEDEC

J-STD-020 Specification.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IO PIN: GENERAL DATA

1-Wire Pullup Voltage VPUP (Note 2) 2.8 5.25 V

1-Wire Pullup Resistance RPUP (Notes 2, 3) 0.3 2.2 k

Input Capacitance CIO (Notes 4, 5) 1000 pF

Input Load Current ILIO pin at VPUP 0.05 6.7 μA

High-to-Low Switching Threshold VTL (Notes 5, 6, 7) 0.46 VPUP -

1.8 V

Input Low Voltage VIL (Notes 2, 8) 0.5 V

Low-to-High Switching Threshold VTH (Notes 5, 6, 9) 1.0 VPUP -

1.1 V

Switching Hysteresis VHY (Notes 5, 6, 10) 0.21 1.70 V

Output Low Voltage VOL At 4mA current load (Note 11) 0.4 V

Standard speed, RPUP = 2.2k 5

Overdrive speed, RPUP = 2.2k 2

Recovery Time

(Notes 2,12) tREC Overdrive speed, directly prior to reset

pulse; RPUP = 2.2k5

μs

Standard speed 0.5 5.0

Rising-Edge Hold-Off Time

(Notes 5, 13) tREH Overdrive speed Not applicable (0) μs

Standard speed 65

Time Slot Duration

(Notes 2, 14) tSLOT Overdrive speed 8 μs

IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE

Standard speed 480 640

Reset Low Time (Note 2) tRSTL Overdrive speed 48 80

μs

Standard speed 15 60

Presence-Detect High Time tPDH Overdrive speed 2 6

μs

Standard speed 60 240

Presence-Detect Low Time tPDL Overdrive speed 8 24 μs

Standard speed 60 75

Presence-Detect Sample Time

(Notes 2, 15) tMSP Overdrive speed 6 10 μs

DS28E01-100

ELECTRICAL CHARACTERISTICS (continued)

(TA= -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IO PIN: 1-Wire WRITE

Standard speed 60 120

Overdrive speed, VPUP > 4.5V 5 15.5

Write-Zero Low Time

(Notes 2, 16, 17) tW0L

Overdrive speed 6 15.5

μs

Standard speed 1 15

Write-One Low Time

(Notes 2, 17) tW1L Overdrive speed 1 2

μs

IO PIN: 1-Wire READ

Standard speed 5 15 - 

Read Low Time

(Notes 2, 18) tRL Overdrive speed 1 2 - μs

Standard speed tRL +  15

Read Sample Time

(Notes 2, 18) tMSR Overdrive speed tRL +  2 μs

EEPROM

Programming Current IPROG (Notes 5, 19) 0.8 mA

Programming Time tPROG (Note 20) 10 ms

At +25°C 200k

Write/Erase Cycles (Endurance)

(Notes 21, 22) NCY At +85°C (worst case) 50k



Data Retention

(Notes 23, 24, 25) tDR At +85°C (worst case) 40 Years

SHA-1 ENGINE

Computation Current ILCSHA mA

Computation Time

(Notes 5, 26) tCSHA

Note 1: Specifications at TA= -40°C are guaranteed by design only and not production tested.

Note 2: System requirement.

Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.

The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more

heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.

Note 4: Maximum value represents the internal parasite capacitance when VPUP is first applied. If a 2.2kΩpullup resistor is used,

the parasite capacitance does not affect normal communications 2.5µs after VPUP has been applied.

Note 5: Guaranteed by design, characterization, and/or simulation only. Not production tested.

Note 6: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and

capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of

VTL, VTH, and VHY.

Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected.

Note 8: The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic 0 level.

Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected.

Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0.

Note 11: The I-V characteristic is linear for voltages less than 1V.

Note 12: Applies to a single device attached to a 1-Wire line.

Note 13: The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge.

Note 14: Defines maximum possible bit rate. Equal to tW0LMIN + tRECMIN.

Note 15: Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS28E01-100 present.

Minimum limit is tPDHMAX; maximum limit is tPDHMIN + tPDLMIN.

Note 16: Numbers in bold are not in compliance with legacy 1-Wire product standards. See the

Comparison Table

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

_______________________________________________________________________________________ 3

ABRIDGED DATA SHEET

Refer to the full data sheet.

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

4 _______________________________________________________________________________________

ABRIDGED DATA SHEET

Note 17: εin Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual

maximum duration for the master to pull the line low is tW1LMAX + tF- εand tW0LMAX + tF- ε, respectively.

Note 18: δin Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high

threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.

Note 19: Current drawn from IO during the EEPROM programming interval or SHA-1 computation.

Note 20:

Note 21: Write-cycle endurance is degraded as TAincreases.

Note 22: Not 100% production tested; guaranteed by reliability monitor sampling.

Note 23: Data retention is degraded as TAincreases.

Note 24: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the

data sheet limit at operating temperature range is established by reliability testing.

Note 25: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-

peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.

Note 26:

COMPARISON TABLE

LEGACY VALUES DS28E01-100 VALUES

STANDARD SPEED

(μs)

OVERDRIVE SPEED

(μs)

STANDARD SPEED

(μs)

OVERDRIVE SPEED

(μs)

PARAMETER

MIN MAX MIN MAX MIN MAX MIN MAX

tSLOT (including tREC) 61 (undefined) 7 (undefined) 65* (undefined) 8* (undefined)

tRSTL 480 (undefined) 48 80 480 640 48 80

tPDH 15 60 2 6 15 60 2 6

tPDL 60 240 8 24 60 240 8 24

tW0L 60 120 6 16 60 120 6 15.5

Intentional change; longer recovery time requirement due to modified 1-Wire front-end.

Note: Numbers in bold are not in compliance with legacy 1-Wire product standards.

ELECTRICAL CHARACTERISTICS (continued)

(TA= -40°C to +85°C.) (Note 1)

Refer to the full data sheet for this note.

DS28E01-100

Pin Description

TSOC TDFN-EP SFN NAME FUNCTION

1 3 2 GND Ground Reference

2 2 1 IO

1-Wire Bus Interface. Open-drain signal that requires an

external pullup resistor.

3, 4, 5, 6 1, 4, 5, 6 — N.C. Not Connected

— EP — EP

Exposed Pad. Solder evenly to the board’s ground plane for

proper operation. Refer to Application Note 3273: Exposed

Pads: A Brief Introduction for additional information.

Detailed Description

The DS28E01-100 combines 1024 bits of EEPROM

organized as four 256-bit pages, a 64-bit secret, a reg-

ister page, a 512-bit SHA-1 engine, and a 64-bit ROM

registration number in a single chip. Data is transferred

serially through the 1-Wire protocol, which requires only

a single data lead and a ground return. The DS28E01-

100 has an additional memory area called the scratch-

pad that acts as a buffer when writing to the memory,

the register page, or when installing a new secret. Data

is first written to the scratchpad from where it can be

read back. After the data has been verified, a Copy

Scratchpad command transfers the data to its final

memory location, provided that the DS28E01-100

receives a matching 160-bit MAC. The computation of

the MAC involves the secret and additional data stored

in the DS28E01-100 including the device’s registration

number. Only a new secret can be loaded without pro-

viding a MAC. The SHA-1 engine is also activated to

compute 160-bit MACs when performing an authenti-

cated read of a memory page and when computing a

new secret, instead of loading it. The DS28E01-100

understands a unique command “Refresh Scratchpad.”

Proper use of a refresh sequence after a Copy

Scratchpad operation reduces the number of weak bit

failures if the device is used in a touch environment

(see the

Writing with Verification

section). The refresh

sequence also provides a means to restore functionali-

ty in a device with bits in a weak state.

The device’s 64-bit ROM registration number guaran-

tees unique identification and is used to address the

device in a multidrop 1-Wire network environment,

where multiple devices reside on a common 1-Wire bus

and operate independently of each other. Applications

of the DS28E01-100 include printer cartridge configura-

tion and monitoring, medical sensor authentication and

calibration, and system intellectual property protection.

Overview

The block diagram in Figure 1 shows the relationships

between the major control and memory sections of the

DS28E01-100. The DS28E01-100 has six main data

components: 64-bit lasered ROM, 64-bit scratchpad,

four 256-bit pages of EEPROM, register page, 64-bit

secrets memory, and a 512-bit SHA-1 engine. Figure 2

shows the hierarchic structure of the 1-Wire protocol.

The bus master must first provide one of the seven ROM

function commands: Read ROM, Match ROM, Search

ROM, Skip ROM, Resume Communication, Overdrive-

Skip ROM, or Overdrive-Match ROM. Upon completion

of an Overdrive-Skip ROM or Overdrive-Match ROM

command executed at standard speed, the device

enters overdrive mode where all subsequent communi-

cation occurs at a higher speed. The protocol required

for these ROM function commands is described in

Figure 10. After a ROM function command is success-

fully executed, the memory and SHA-1 functions

become accessible and the master can provide any

one of the 9 available function commands. The function

protocols are described in Figure 8. All data is read

and written least significant bit first.

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

_______________________________________________________________________________________ 5

ABRIDGED DATA SHEET

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

6 _______________________________________________________________________________________

ABRIDGED DATA SHEET

DS28E01-100

1-Wire FUNCTION

CONTROL

1-Wire NET

PARASITE POWER

CRC-16

GENERATOR

64-BIT

LASERED ROM

64-BIT

SCRATCHPAD

512-BIT

SECURE HASH

ALGORITHM ENGINE

PAGE

SECRETS

MEMORY 64 BITS

DATA MEMORY

4 PAGES OF

256 BITS EACH

MEMORY AND

SHA-1 FUNCTION

CONTROL UNIT

Figure 1. Block Diagram

64-Bit Lasered ROM

Each DS28E01-100 contains a unique ROM registration

number that is 64 bits long. The first 8 bits are a 1-Wire

family code. The next 48 bits are a unique serial number.

The last 8 bits are a cyclic redundancy check (CRC) of

the first 56 bits. See Figure 3 for details. The 1-Wire CRC

is generated using a polynomial generator consisting of

a shift register and XOR gates as shown in Figure 4. The

polynomial is X8+ X5+ X4+ 1. Additional information

about the 1-Wire CRC is available in Application Note

27:

Understanding and Using Cyclic Redundancy

Checks with Maxim iButton

Products

The shift register bits are initialized to 0. Then, starting

with the least significant bit of the family code, one bit

at a time is shifted in. After the 8th bit of the family code

has been entered, the serial number is entered. After

the 48th bit of the serial number has been entered, the

shift register contains the CRC value. Shifting in the 8

bits of the CRC returns the shift register to all 0s.

Memory Access

The DS28E01-100 has four memory areas: data memo-

ry, secrets memory, register page with special function

registers and user bytes, and a volatile scratchpad. The

data memory is organized as four pages of 32 bytes.

Secret and scratchpad are 8 bytes each. The scratch-

pad acts as a buffer when writing to the data memory,

loading the initial secret, or when writing to the register

page.

Refer to the full data sheet for this information.

iButton is a registered trademark of Maxim Inregrated Products, Inc.

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

_______________________________________________________________________________________ 7

ABRIDGED DATA SHEET

AVAILABLE COMMANDS: DATA FIELD AFFECTED:

READ ROM

MATCH ROM

SEARCH ROM

SKIP ROM

RESUME

OVERDRIVE-SKIP ROM

OVERDRIVE-MATCH ROM

64-BIT REG. #, RC-FLAG

RC-FLAG

RC-FLAG, OD-FLAG

64-BIT REG. #, RC-FLAG, OD-FLAG

1-Wire ROM FUNCTION COMMANDS

(SEE FIGURE 10)

DEVICE-SPECIFIC MEMORY

FUNCTION COMMANDS

(SEE FIGURE 8)

COMMAND LEVEL:

DS28E01-100

Figure 2. Hierarchic Structure for 1-Wire Protocol

MSB

8-BIT

CRC CODE 48-BIT SERIAL NUMBER

MSB MSBLSB

LSB

8-BIT FAMILY CODE

MSBLSB

Figure 3. 64-Bit Lasered ROM

1ST

STAGE

2ND

STAGE

3RD

STAGE

4TH

STAGE

7TH

STAGE

8TH

STAGE

6TH

STAGE

5TH

STAGE

X0X1X2X3X4

POLYNOMIAL = X8 + X5 + X4 + 1

INPUT DATA

X5X6X7X8

Figure 4. 1-Wire CRC Generator

Refer to the full data sheet.

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

_______________________________________________________________________________________ 9

ABRIDGED DATA SHEET

Figure 6. Memory Protection Matrix

Address Registers and Transfer Status

The DS28E01-100 employs three address registers:

TA1, TA2, and E/S (Figure 7). These registers are com-

mon to many other 1-Wire devices, but operate slightly

differently with the DS28E01-100. Registers TA1 and

TA2 must be loaded with the target address to which

the data is written or from which data is read. Register

E/S is a read-only transfer-status register used to verify

data integrity with write commands. Since the scratch-

pad of the DS28E01-100 is designed to accept data in

blocks of 8 bytes only, the lower 3 bits of TA1 are

forced to 0 and the lower 3 bits of the E/S register (end-

ing offset) always read 1. This indicates that all the data

in the scratchpad is used for a subsequent copying into

main memory or secret. Bit 5 of the E/S register, called

PF or partial byte flag, is a logic 1 if the number of data

bits sent by the master is not an integer multiple of

eight or if the data in the scratchpad is not valid due to

a loss of power. A valid write to the scratchpad clears

the PF bit. Bits 3, 4, and 6 have no function; they always

read 1. The partial flag supports the master checking

the data integrity after a write command. The highest

BIT # 7 6 5 4 3 2 1 0

TARGET ADDRESS (TA1) T7 T6 T5 T4 T3 T2

(0)

TARGET ADDRESS (TA2) T15 T14 T13 T12 T11 T10 T9 T8

ENDING ADDRESS WITH

DATA STATUS (E/S)

(READ ONLY)

AA 1 PF 1 1 E2

(1)

Figure 7. Address Registers

Refer to the full data sheet.

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

10 ______________________________________________________________________________________

ABRIDGED DATA SHEET

valued bit of the E/S register, called authorization

accepted (AA), acts as a flag to indicate that the data

stored in the scratchpad has already been copied to

the target memory address. Writing data to the scratch-

pad clears this flag.

Writing with Verification

To write data to the DS28E01-100, the scratchpad must

be used as intermediate storage. First, the master

issues the Write Scratchpad command, which specifies

the desired target address and the data to be written to

the scratchpad. Note that writes to data memory must

be performed on 8-byte boundaries with the three LSBs

of the target address T[2:0] equal to 000b. Therefore, if

T[2:0] are sent with nonzero values, the device sets

these bits to 0 and uses the modified address as the

target address. The master should always send eight

complete data bytes. After the 8 bytes of data have

been transmitted, the master can elect to receive an

inverted CRC-16 of the Write Scratchpad command,

the address as sent by the master, and the data as sent

by the master. The master can compare the CRC to the

value it has calculated itself to determine if the commu-

nication was successful. After the scratchpad has been

written, the master should always perform a Read

Scratchpad to verify that the intended data was in fact

written. During a Read Scratchpad, the DS28E01-100

repeats the target address TA1 and TA2 and sends the

contents of the E/S register. The partial flag (bit 5 of the

E/S register) is set to 1 if the last data byte the

DS28E01-100 received during a Write Scratchpad or

Refresh Scratchpad command was incomplete, or if

there was a loss of power since data was last written to

the scratchpad. The authorization-accepted (AA) flag

(bit 7 of the E/S register) is normally cleared by a Write

Scratchpad or Refresh Scratchpad; therefore, if it is set

to 1, it indicates that the DS28E01-100 did not under-

stand the proceeding Write (or Refresh) Scratchpad

command. In either of these cases, the master should

rewrite the scratchpad. After the master receives the

E/S register, the scratchpad data is received. The

descriptions of Write Scratchpad and Refresh

Scratchpad provide clarification of what changes can

occur to the scratchpad data under certain conditions.

An inverted CRC of the Read Scratchpad command,

target address, E/S register, and scratchpad data fol-

lows the scratchpad data. As with the Write Scratchpad

command, this CRC can be compared to the value the

master has calculated to determine if the communica-

tion was successful. After the master has verified the

data, it can send the Copy Scratchpad to copy the

scratchpad to memory. Alternatively, the Load First

Secret or Compute Next Secret command can be

issued to change the secret. See the descriptions of

these commands for more information.

Refer to the full data sheet for this information.

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

______________________________________________________________________________________ 11

ABRIDGED DATA SHEET

Memory and SHA-1 Function

Commands

This section describes the commands and flowcharts

needed to use the memory and SHA-1 engine of the

device. Refer to the full data sheet for more information.

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

______________________________________________________________________________________ 23

ABRIDGED DATA SHEET

SHA-1 Computation Algorithm

This description of the SHA-1 computation is adapted

from the Secure Hash Standard SHA-1 document from the

National Institute of Standards and Technology (NIST).

Refer to the full data sheet for more information. bit

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

24 ______________________________________________________________________________________

ABRIDGED DATA SHEET

RPUP

VPUP

BUS MASTER

OPEN-DRAIN

PORT PIN 100Ω MOSFET

DATA

DS28E01-100 1-Wire PORT

Rx = RECEIVE

Tx = TRANSMIT

Figure 9. Hardware Configuration

1-Wire Bus System

The 1-Wire bus is a system that has a single bus master

and one or more slaves. In all instances the DS28E01-

100 is a slave device. The bus master is typically a

microcontroller. The discussion of this bus system is

broken down into three topics: hardware configuration,

transaction sequence, and 1-Wire signaling (signal

types and timing). The 1-Wire protocol defines bus

transactions in terms of the bus state during specific

time slots, which are initiated on the falling edge of

sync pulses from the bus master.

Hardware Configuration

The 1-Wire bus has only a single line by definition; it is

important that each device on the bus be able to drive

it at the appropriate time. To facilitate this, each device

attached to the 1-Wire bus must have open-drain or

three-state outputs. The 1-Wire port of the DS28E01-

100 is open drain with an internal circuit equivalent to

that shown in Figure 9.

A multidrop bus consists of a 1-Wire bus with multiple

slaves attached. The DS28E01-100 supports both a

standard and overdrive communication speed of

15.3kbps (max) and 125kbps (max), respectively. Note

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

______________________________________________________________________________________ 25

ABRIDGED DATA SHEET

that legacy 1-Wire products support a standard com-

munication speed of 16.3kbps and overdrive of

142kbps. The slightly reduced rates for the DS28E01-

100 are a result of additional recovery times, which in

turn were driven by a 1-Wire physical interface

enhancement to improve noise immunity. The value of

the pullup resistor primarily depends on the network

size and load conditions. The DS28E01-100 requires a

pullup resistor of 2.2kΩ(max) at any speed.

The idle state for the 1-Wire bus is high. If for any rea-

son a transaction needs to be suspended, the bus

must be left in the idle state if the transaction is to

resume. If this does not occur and the bus is left low for

more than 16µs (overdrive speed) or more than 120µs

(standard speed), one or more devices on the bus

could be reset.

Transaction Sequence

The protocol for accessing the DS28E01-100 through

the 1-Wire port is as follows:

• Initialization

• ROM Function Command

• Memory/SHA-1 Function Command

• Transaction/Data

Initialization

All transactions on the 1-Wire bus begin with an initial-

ization sequence. The initialization sequence consists

of a reset pulse transmitted by the bus master followed

by presence pulse(s) transmitted by the slave(s). The

presence pulse lets the bus master know that the

DS28E01-100 is on the bus and is ready to operate. For

more details, see the

1-Wire Signaling

section.

1-Wire ROM Function

Commands

Once the bus master has detected a presence, it can

issue one of the seven ROM function commands that

the DS28E01-100 supports. All ROM function com-

mands are 8 bits long. A list of these commands follows

(see the flowchart in Figure 10).

Read ROM [33h]

The Read ROM command allows the bus master to

read the DS28E01-100’s 8-bit family code, unique 48-

bit serial number, and 8-bit CRC. This command can

only be used if there is a single slave on the bus. If

more than one slave is present on the bus, a data colli-

sion occurs when all slaves try to transmit at the same

time (open drain produces a wired-AND result). The

resultant family code and 48-bit serial number result in

a mismatch of the CRC.

Match ROM [55h]

The Match ROM command, followed by a 64-bit device

registration number, allows the bus master to address a

specific DS28E01-100 on a multidrop bus. Only the

DS28E01-100 that exactly matches the 64-bit registra-

tion number responds to the subsequent memory or

SHA-1 function command. All other slaves wait for a

reset pulse. This command can be used with a single

device or multiple devices on the bus.

Search ROM [F0h]

When a system is initially brought up, the bus master

might not know the number of devices on the 1-Wire

bus or their registration numbers. By taking advantage

of the wired-AND property of the bus, the master can

use a process of elimination to identify the registration

numbers of all slave devices. For each bit of the regis-

tration number, starting with the least significant bit, the

bus master issues a triplet of time slots. On the first slot,

each slave device participating in the search outputs

the true value of its registration number bit. On the sec-

ond slot, each slave device participating in the search

outputs the complemented value of its registration num-

ber bit. On the third slot, the master writes the true

value of the bit to be selected. All slave devices that do

not match the bit written by the master stop participat-

ing in the search. If both of the read bits are zero, the

master knows that slave devices exist with both states

of the bit. By choosing which state to write, the bus

master branches in the search tree. After one complete

pass, the bus master knows the registration number of

a single device. Additional passes identify the registra-

tion numbers of the remaining devices. Refer to

Application Note 187:

1-Wire Search Algorithm

for a

detailed discussion, including an example.

Skip ROM [CCh]

This command can save time in a single-drop bus sys-

tem by allowing the bus master to access the memory

functions without providing the 64-bit registration num-

ber. If more than one slave is present on the bus and,

for example, a read command is issued following the

Skip ROM command, data collision occurs on the bus

as multiple slaves transmit simultaneously (open-drain

pulldowns produce a wired-AND result).

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

26 ______________________________________________________________________________________

ABRIDGED DATA SHEET

DS28E01-100 Tx

PRESENCE PULSE

BUS MASTER Tx

RESET PULSE

BUS MASTER Tx ROM

FUNCTION COMMAND

DS28E01-100 Tx

CRC BYTE

DS28E01-100 Tx

FAMILY CODE

(1 BYTE)

DS28E01-100 Tx

SERIAL NUMBER

(6 BYTES)

RC = 0

MASTER Tx BIT 0

RC = 0 RC = 0 RC = 0

OD = 0

33h

READ ROM

COMMAND?

N55h

MATCH ROM

COMMAND?

BIT 0 MATCH? BIT 0 MATCH?

N N

F0h

SEARCH ROM

COMMAND?

RESET PULSE?

CCh

SKIP ROM

COMMAND?

RC = 1

MASTER Tx BIT 1

MASTER Tx BIT 63

BIT 1 MATCH?

BIT 63 MATCH?

RC = 1

FROM MEMORY AND SHA-1 FUNCTION

FLOWCHART (FIGURE 8)

TO MEMORY AND SHA-1 FUNCTION

FLOWCHART (FIGURE 8)

DS28E01-100 Tx BIT 0

MASTER Tx BIT 0

BIT 1 MATCH?

BIT 63 MATCH?

DS28E01-100 Tx BIT 1

MASTER Tx BIT 1

DS28E01-100 Tx BIT 63

DS28E01-1001 Tx BIT 63

MASTER Tx BIT 63

TO FIGURE 10b

FROM FIGURE 10b

Figure 10a. ROM Functions Flowchart

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

______________________________________________________________________________________ 27

ABRIDGED DATA SHEET

RC = 0; OD = 1 RC = 0; OD = 1

BIT 0 MATCH?

RC = 1?

A5h

RESUME

COMMAND?

3Ch

OVERDRIVE-

SKIP ROM?

69h

OVERDRIVE-

MATCH ROM?

FROM FIGURE 10a

TO FIGURE 10a

MASTER Tx

RESET?

MASTER Tx

RESET?

NBIT 1 MATCH?

MASTER Tx BIT 0

MASTER Tx BIT 1

RC = 1

BIT 63 MATCH?

MASTER Tx BIT 63

Figure 10b. ROM Functions Flowchart (continued)

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

28 ______________________________________________________________________________________

ABRIDGED DATA SHEET

Resume [A5h]

To maximize the data throughput in a multidrop environ-

ment, the Resume command is available. This command

checks the status of the RC bit and, if it is set, directly

transfers control to the memory and SHA-1 function com-

mands, similar to a Skip ROM command. The only way to

set the RC bit is through successfully executing the

Match ROM, Search ROM, or Overdrive-Match ROM

command. Once the RC bit is set, the device can repeat-

edly be accessed through the Resume command.

Accessing another device on the bus clears the RC bit,

preventing two or more devices from simultaneously

responding to the Resume command.

Overdrive-Skip ROM [3Ch]

On a single-drop bus this command can save time by

allowing the bus master to access the memory func-

tions without providing the 64-bit registration number.

Unlike the normal Skip ROM command, the Overdrive-

Skip ROM command sets the DS28E01-100 into the

overdrive mode (OD = 1). All communication following

this command must occur at overdrive speed until a

reset pulse of minimum 480µs duration resets all de-

vices on the bus to standard speed (OD = 0).

When issued on a multidrop bus, this command sets all

overdrive-supporting devices into overdrive mode. To

subsequently address a specific overdrive-supporting

device, a reset pulse at overdrive speed must be

issued followed by a Match ROM or Search ROM com-

mand sequence. This speeds up the time for the

search process. If more than one slave supporting

overdrive is present on the bus and the Overdrive-Skip

ROM command is followed by a read command, data

collision occurs on the bus as multiple slaves transmit

simultaneously (open-drain pulldowns produce a wired-

AND result).

Overdrive-Match ROM [69h]

The Overdrive-Match ROM command followed by a 64-

bit registration number transmitted at overdrive speed

allows the bus master to address a specific DS28E01-

100 on a multidrop bus and to simultaneously set it in

overdrive mode. Only the DS28E01-100 that exactly

matches the 64-bit number responds to the subsequent

memory or SHA-1 function command. Slaves already in

overdrive mode from a previous Overdrive-Skip ROM or

successful Overdrive-Match ROM command remain in

overdrive mode. All overdrive-capable slaves return to

standard speed at the next reset pulse of minimum

480µs duration. The Overdrive-Match ROM command

can be used with a single device or multiple devices on

the bus.

1-Wire Signaling

The DS28E01-100 requires strict protocols to ensure

data integrity. The protocol consists of four types of

signaling on one line: reset sequence with reset pulse

and presence pulse, write-zero, write-one, and read-

data. Except for the presence pulse, the bus master

initiates all falling edges. The DS28E01-100 can com-

municate at two different speeds: standard speed and

overdrive speed. If not explicitly set into the overdrive

mode, the DS28E01-100 communicates at standard

speed. While in overdrive mode, the fast timing applies

to all waveforms.

To get from idle to active, the voltage on the 1-Wire line

needs to fall from VPUP below the threshold VTL. To get

from active to idle, the voltage needs to rise from

VILMAX past the threshold VTH. The time it takes for the

voltage to make this rise is seen in Figure 11 as ε, and

its duration depends on the pullup resistor (RPUP) used

and the capacitance of the 1-Wire network attached.

The voltage VILMAX is relevant for the DS28E01-100

when determining a logical level, not triggering any

events.

Figure 11 shows the initialization sequence required to

begin any communication with the DS28E01-100. A

reset pulse followed by a presence pulse indicates that

the DS28E01-100 is ready to receive data, given the

correct ROM and memory and SHA-1 function com-

mand. If the bus master uses slew-rate control on the

falling edge, it must pull down the line for tRSTL + tFto

compensate for the edge. A tRSTL duration of 480µs or

longer exits the overdrive mode, returning the device to

standard speed. If the DS28E01-100 is in overdrive

mode and tRSTL is no longer than 80µs, the device

remains in overdrive mode. If the device is in overdrive

mode and tRSTL is

between

80µs and 480µs, the device

resets, but the communication speed is undetermined.

After the bus master has released the line it goes into

receive mode. Now the 1-Wire bus is pulled to VPUP

through the pullup resistor or, in the case of a DS2482-

x00 or DS2480B driver, through active circuitry. When

the threshold VTH is crossed, the DS28E01-100 waits

for tPDH and then transmits a presence pulse by pulling

the line low for tPDL. To detect a presence pulse, the

master must test the logical state of the 1-Wire line at

tMSP.

The tRSTH window must be at least the sum of tPDHMAX,

tPDLMAX, and tRECMIN. Immediately after tRSTH is

expired, the DS28E01-100 is ready for data communi-

cation. In a mixed population network, tRSTH should be

extended to minimum 480µs at standard speed and

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

______________________________________________________________________________________ 29

ABRIDGED DATA SHEET

48µs at overdrive speed to accommodate other 1-Wire

devices.

Read/Write Time Slots

Data communication with the DS28E01-100 takes place

in time slots that carry a single bit each. Write time slots

transport data from bus master to slave. Read time

slots transfer data from slave to master. Figure 12 illus-

trates the definitions of the write and read time slots.

All communication begins with the master pulling the

data line low. As the voltage on the 1-Wire line falls

below the threshold VTL, the DS28E01-100 starts its

internal timing generator that determines when the data

line is sampled during a write time slot and how long

data is valid during a read time slot.

Master-to-Slave

For a write-one time slot, the voltage on the data line

must have crossed the VTH threshold before the write-

one low time tW1LMAX is expired. For a write-zero time

slot, the voltage on the data line must stay below the

VTH threshold until the write-zero low time tW0LMIN is

expired. For the most reliable communication, the volt-

age on the data line should not exceed VILMAX during

the entire tW0L or tW1L window. After the VTH threshold

has been crossed, the DS28E01-100 needs a recovery

time tREC before it is ready for the next time slot.

Slave-to-Master

A read-data time slot begins like a write-one time slot.

The voltage on the data line must remain below VTL

until the read low time tRL is expired. During the tRL

window, when responding with a 0, the DS28E01-100

starts pulling the data line low; its internal timing gener-

ator determines when this pulldown ends and the volt-

age starts rising again. When responding with a 1, the

DS28E01-100 does not hold the data line low at all, and

the voltage starts rising as soon as tRL is over.

The sum of tRL + δ(rise time) on one side and the inter-

nal timing generator of the DS28E01-100 on the other

side define the master sampling window (tMSRMIN to

tMSRMAX), in which the master must perform a read

from the data line. For the most reliable communication,

tRL should be as short as permissible, and the master

should read close to but no later than tMSRMAX. After

reading from the data line, the master must wait until

tSLOT is expired. This guarantees sufficient recovery

time tREC for the DS28E01-100 to get ready for the next

time slot. Note that tREC specified herein applies only to

a single DS28E01-100 attached to a 1-Wire line. For

multidevice configurations, tREC must be extended to

accommodate the additional 1-Wire device input

capacitance. Alternatively, an interface that performs

active pullup during the 1-Wire recovery time such as

the DS2482-x00 or DS2480B 1-Wire drivers can be

used.

RESISTOR MASTER DS28E01-100

tRSTL tPDL

tRSTH

tPDH

MASTER Tx "RESET PULSE" MASTER Rx "PRESENCE PULSE"

VPUP

VIHMASTER

VTH

VTL

VILMAX

tREC

tMSP

Figure 11. Initialization Procedure: Reset and Presence Pulse

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

30 ______________________________________________________________________________________

ABRIDGED DATA SHEET

RESISTOR MASTER

RESISTOR MASTER DS28E01-100

VPUP

VIHMASTER

VTH

VTL

VILMAX

VPUP

VIHMASTER

VTH

VTL

VILMAX

VPUP

VIHMASTER

VTH

VTL

VILMAX

tSLOT

tW1L

tREC

tSLOT

tW0L

tREC

MASTER

SAMPLING

WINDOW

tRL

tMSR

WRITE-ONE TIME SLOT

WRITE-ZERO TIME SLOT

READ-DATA TIME SLOT

Figure 12. Read/Write Timing Diagrams

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

______________________________________________________________________________________ 31

ABRIDGED DATA SHEET

Improved Network Behavior

(Switchpoint Hysteresis)

In a 1-Wire environment, line termination is possible

only during transients controlled by the bus master

(1-Wire driver). 1-Wire networks, therefore, are suscep-

tible to noise of various origins. Depending on the phys-

ical size and topology of the network, reflections from

end points and branch points can add up or cancel

each other to some extent. Such reflections are visible

as glitches or ringing on the 1-Wire communication line.

Noise coupled onto the 1-Wire line from external

sources can also result in signal glitching. A glitch dur-

ing the rising edge of a time slot can cause a slave

device to lose synchronization with the master and,

consequently, result in a Search ROM command com-

ing to a dead end or cause a device-specific function

command to abort. For better performance in network

applications, the DS28E01-100 uses a new 1-Wire front-

end, which makes it less sensitive to noise.

The DS28E01-100’s 1-Wire front-end differs from tradi-

tional slave devices in three characteristics.

1) There is additional lowpass filtering in the circuit that

detects the falling edge at the beginning of a time

slot. This reduces the sensitivity to high-frequency

noise. This additional filtering does not apply at over-

drive speed.

2) There is a hysteresis at the low-to-high switching

threshold VTH. If a negative glitch crosses VTH but

does not go below VTH - VHY, it is not recognized

(Figure 13, Case A). The hysteresis is effective at

any 1-Wire speed.

3) There is a time window specified by the rising edge

hold-off time tREH during which glitches are ignored,

even if they extend below the VTH - VHY threshold

(Figure 13, Case B, tGL < tREH). Deep voltage droops

or glitches that appear late after crossing the VTH

threshold and extend beyond the tREH window can-

not be filtered out and are taken as the beginning of a

new time slot (Figure 13, Case C, tGL ≥tREH).

Devices that have the parameters VHY and tREH speci-

fied in their electrical characteristics use the improved

1-Wire front-end.

CRC Generation

The DS28E01-100 uses two different types of CRCs.

One CRC is an 8-bit type that is computed at the factory

and is stored in the most significant byte of the 64-bit

registration number. The bus master can compute a

CRC value from the first 56 bits of the 64-bit registration

number and compare it to the value read from the

DS28E01-100 to determine if the registration number

has been received error-free. The equivalent polynomial

function of this CRC is X8+ X5+ X4+ 1. This 8-bit CRC

is received in the true (noninverted) form.

The other CRC is a 16-bit type, which is used for error

detection with memory and SHA-1 commands. For

details, refer to the full data sheet.

VPUP

VTH VHY

tREH

tGL

tREH

tGL

CASE A CASE CCASE B

Figure 13. Noise Suppression Scheme

DS28E01-100

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

______________________________________________________________________________________ 35

ABRIDGED DATA SHEET

TOP VIEW

N.C.

GND

N.C.

TSOC

DS28E01-100

SFN

(6mm × 6mm × 0.9mm)

BOTTOM VIEW

NOTE: THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL

CONTACT APPLICATIONS ONLY, NOT FOR SOLDERING. FOR MORE

INFORMATION, REFER TO APPLICATION NOTE 4132: ATTACHMENT

METHODS FOR THE ELECTRO-MECHANICAL SFN PACKAGE.

IO GND

SIDE VIEW

16N.C. N.C.

25IO N.C.

34GND N.C.

TDFN-EP

(3mm × 3mm)

TOP VIEW

DS28E01-100

2801

ymrrF

*EP

*EXPOSED PAD

Pin Configurations

USER DIRECTION OF FEED

LEADS FACE UP IN ORIENTATION SHOWN ABOVE.

SFN Package Orientation on Tape and Reel

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

6 TSOC —21-0382

2 SFN —21-0390

6 TDFN-EP T633+2 21-0137

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.