AM186EM/AM188EM - Advanced Micro Devices

Am186EM and Am188EM

Microcontrollers

User’s Manual

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Table of Contents v
TABLE OF CONTENTS
PREFACE INTRODUCTION AND OVERVIEW
DESIGN PHILOSOPHY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
PURPOSE OF THIS MANUAL  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
INTENDED AUDIENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
USER’S MANUAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
AMD DOCUMENTATION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xx
E86 Family xx
CHAPTER 1 FEATURES AND PERFORMANCE
1 KEY FEATURES AND BENEFITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
2 DISTINCTIVE CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2
3 APPLICATION CONSIDERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
3.1 Clock Generation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
3.2 Memory Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
3.3 Serial Communications Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
4 THIRD-PARTY DEVELOPMENT SUPPORT PRODUCTS  . . . . . . . . . . .1-6
CHAPTER 2 PROGRAMMING
1 REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
1.1 Processor Status Flags Register  . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2 MEMORY ORGANIZATION AND ADDRESS GENERATION . . . . . . . . .2-3
3 I/O SPACE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
4 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
5 SEGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
6 DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
CHAPTER 3 SYSTEM OVERVIEW
1 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
1.1 Pins That Are Used by Emulators   . . . . . . . . . . . . . . . . . . . . . . .3-15
2 BUS OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
3 BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19
3.1 Nonmultiplexed Address Bus  . . . . . . . . . . . . . . . . . . . . . . . . . . .3 -19
3.2 Byte Write Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 -19
3.3 Pseudo Static RAM (PSRAM) Support . . . . . . . . . . . . . . . . . . . .3-19
4 CLOCK AND POWER MANAGEMENT UNIT  . . . . . . . . . . . . . . . . . . . .3-20
4.1 Phase-Locked Loop (PLL)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-20
4.2 Crystal-Driven Clock Source   . . . . . . . . . . . . . . . . . . . . . . . . . . .3-20
4.3 External Source Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22
4.4 System Clocks  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22
4.5 Power-Save Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22
CHAPTER 4 PERIPHERAL CONTROL BLOCK
1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
1.1 Peripheral Control Block Relocation Register 
(RELREG, Offset FEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
1.2 Reset Configuration Register (RESCON, Offset F6h). . . . . . . . . .4-5
1.3 Processor Release Level Register (PRL, Offset F4h). . . . . . . . . .4-6
1.4 Power-Save Control Register (PDCON, Offset F0h). . . . . . . . . . .4-7
2 INITIALIZATION AND PROCESSOR RESET . . . . . . . . . . . . . . . . . . . . .4-8

Table of Contents
vi
CHAPTER 5 CHIP SELECT UNIT
1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
2 CHIP SELECT TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
3 READY AND WAIT-STATE PROGRAMMING . . . . . . . . . . . . . . . . . . . . .5-2
4 CHIP SELECT OVERLAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
5 CHIP SELECT REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
5.1 Upper Memory Chip Select Register (UMCS, Offset A0h) . . . . . .5-4
5.2 Low Memory Chip Select Register (LMCS, Offset A2h) . . . . . . . .5-6
5.3 Midrange Memory Chip Select Register (MMCS, Offset A6h)  . . .5-8
5.4 PCS and MCS Auxiliary Register (MPCS, Offset A8h) . . . . . . . .5-10
5.5 Peripheral Chip Select Register (PACS, Offset A4h) . . . . . . . . .5-12
CHAPTER 6 REFRESH CONTROL UNIT
1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
1.1 Memory Partition Register (MDRAM, Offset E0h)  . . . . . . . . . . . .6-1
1.2 Clock Prescaler Register (CDRAM, Offset E2h) . . . . . . . . . . . . . .6-2
1.3 Enable RCU Register (EDRAM, Offset E4h)  . . . . . . . . . . . . . . . .6-2
CHAPTER 7 INTERRUPT CONTROL UNIT
1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1
1.1 Definitions of Interrupt Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1
1.2 Interrupt Conditions and Sequence. . . . . . . . . . . . . . . . . . . . . . . .7-4
1.3 Interrupt Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5
1.4 Software Exceptions, Traps, and NMI. . . . . . . . . . . . . . . . . . . . . .7-6
1.5 Interrupt Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7
1.6 Interrupt Controller Reset Conditions . . . . . . . . . . . . . . . . . . . . . .7-8
2 MASTER MODE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
2.1 Fully Nested Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
2.2 Cascade Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-10
2.3 Special Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-11
2.4 Operation in a Polled Environment . . . . . . . . . . . . . . . . . . . . . . .7-11
2.5 End-of-Interrupt Write to the EOI Register  . . . . . . . . . . . . . . . . .7-11
3 MASTER MODE INTERRUPT CONTROLLER REGISTERS  . . . . . . . .7-12
3.1 INT0 and INT1 Control Registers 
(I0CON, Offset 38h, I1CON, Offset 3Ah) (Master Mode) . . . . . .7-13
3.2 INT2 and INT3 Control Registers 
(I2CON, Offset 3Ch, I3CON, Offset 3Eh) (Master Mode) . . . . . .7-15
3.3 INT4 Control Register (I4CON, Offset 40h) (Master Mode)  . . . .7-16
3.4 Timer and DMA Interrupt Control Registers
(TCUCON, Offset 32h, DMA0CON, Offset 34h, DMA1CON,
Offset 36h) (Master Mode)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-17
3.5 Watchdog Timer Interrupt Control Register (WDCON, 
Offset 42h) (Master Mode)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
3.6 Serial Port Interrupt Control Register (SPICON, Offset 44h)
(Master Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-19
3.7 Interrupt Status Register (INTSTS, Offset 30h)
(Master Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20
3.8 Interrupt Request Register (REQST, Offset 2Eh)
(Master Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-21
3.9 In-Service Register (INSERV, Offset 2Ch)
(Master Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-22
3.10 Priority Mask Register (PRIMSK, Offset 2Ah) (Master Mode). . .7-23
3.11 Interrupt Mask Register (IMASK, Offset 28h) (Master Mode) . . .7-24
3.12 Poll Status Register (POLLST, Offset 26h) (Master Mode). . . . .7-25
3.13 Poll Register (POLL, Offset 24h) (Master Mode). . . . . . . . . . . . .7-26
3.14 End-of-Interrupt Register (EOI, Offset 22h) (Master Mode)  . . . .7-27
4 SLAVE MODE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-28

Table of Contents vii
7.4.1 Slave Mode Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . .7-28
7.4.2 Slave Mode Interrupt Controller Registers  . . . . . . . . . . . . . . . . .7-28
7.4.3 Timer and DMA Interrupt Control Registers
(T0INTCON, Offset 32h, T1INTCON, Offset 38h, T2INTCON, Offset 
3Ah, DMA0CON, Offset 34h, DMA1CON, Offset 36h)
(Slave Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-29
7.4.4 Interrupt Status Register (INTSTS, Offset 30h) (Slave Mode)  . .7-30
7.4.5 Interrupt Request Register (REQST, Offset 2Eh) (Slave Mode).7-31
7.4.6 In-Service Register (INSERV, Offset 2Ch) (Slave Mode) . . . . . .7-32
7.4.7 Priority Mask Register (PRIMSK, Offset 2Ah) (Slave Mode). . . .7-33
7.4.8 Interrupt Mask Register (IMASK, Offset 28h) (Slave Mode) . . . .7-34
7.4.9 Specific End-of-Interrupt Register (EOI, Offset 22h) 
(Slave Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-35
7.4.10 Interrupt Vector Register (INTVEC, Offset 20h) (Slave Mode) . .7-36
CHAPTER 8 TIMER CONTROL UNIT
8.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
8.2 PROGRAMMABLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
8.2.1 Timer Operating Frequency  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2
8.2.2 Timer 0 and Timer 1 Mode and Control Registers 
(T0CON, Offset 56h, T1CON, Offset 5Eh) . . . . . . . . . . . . . . . . . .8-3
8.2.3 Timer 2 Mode and Control Register (T2CON, Offset 66h) . . . . . .8-5
8.2.4 Timer Count Registers 
(T0CNT, Offset 50h, T1CNT, Offset 58h, T2CNT, Offset 60h) . . .8-6
8.2.5 Timer Maxcount Compare Registers 
(T0CMPA, Offset 52h, T0CMPB, Offset 54h, T1CMPA, Offset 5Ah, 
T1CMPB, Offset 5Ch, T2CMPA, Offset 62h)  . . . . . . . . . . . . . . . .8-7
CHAPTER 9 DMA CONTROLLER
9.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
9.2 DMA OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
9.3 PROGRAMMABLE DMA REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . .9-2
9.3.1 DMA Control Registers (D0CON, Offset CAh, D1CON, 
Offset DAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
9.3.2 DMA Transfer Count Registers (D0TC, Offset C8h, D1TC, 
Offset D8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5
9.3.3 DMA Destination Address High Register
(High Order Bits) (D0DSTH, Offset C6h, D1DSTH, Offset D6h). .9-6
9.3.4 DMA Destination Address Low Register (Low Order Bits) 
(D0DSTL, Offset C4h, D1DSTL, Offset D4h) . . . . . . . . . . . . . . . .9-7
9.3.5 DMA Source Address High Register (High Order Bits) 
(D0SRCH, Offset C2h, D1SRCH, Offset D2h) . . . . . . . . . . . . . . .9-8
9.3.6 DMA Source Address Low Register (Low Order Bits) 
(D0SRCL, Offset C0h, D1SRCL, Offset D0h) . . . . . . . . . . . . . . . .9-9
9.4 DMA REQUESTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10
9.4.1 Synchronization Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-11
9.4.2 DMA Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-12
9.4.3 DMA Priority  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-12
9.4.4 DMA Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-12
9.4.5 DMA Channels on Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-13
CHAPTER 10 ASYNCHRONOUS SERIAL PORT
10.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
10.2 PROGRAMMABLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
10.2.1 Serial Port Control Register (SPCT, Offset 80h). . . . . . . . . . . . .10-2
10.2.2 Serial Port Status Register (SPSTS, Offset 82h)  . . . . . . . . . . . .10-4
10.2.3 Serial Port Transmit Data Register (SPTD, Offset 84h) . . . . . . .10-5
10.2.4 Serial Port Receive Data Register (SPRD, Offset 86h). . . . . . . .10-6
10.2.5 Serial Port Baud Rate Divisor Register (SPBAUD, Offset 88h). .10-7

Table of Contents
viii
CHAPTER 11 SYNCHRONOUS SERIAL INTERFACE
1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
1.1 Four-Pin Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2
2 PROGRAMMABLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2
2.1 Synchronous Serial Status Register (SSS, Offset 10h). . . . . . . .11-3
2.2 Synchronous Serial Control Register (SSC, Offset 12h). . . . . . .11-4
2.3 Synchronous Serial Transmit 1 Register (SSD1, Offset 14h)
Synchronous Serial Transmit 0 Register (SSD0, Offset 16h) . . .11-5
2.4 Synchronous Serial Receive Register (SSR, Offset 18h) . . . . . .11-6
3 SSI PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-7
CHAPTER 12 PROGRAMMABLE I/O PINS
1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1
2 PIO MODE REGISTERS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-3
2.1 PIO Mode 1 Register (PIOMODE1, Offset 76h) . . . . . . . . . . . . .12-3
2.2 PIO Mode 0 Register (PIOMODE0, Offset 70h) . . . . . . . . . . . . .12-3
3 PIO DIRECTION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-4
3.1 PIO Direction 1 Register (PDIR1, Offset 78h)  . . . . . . . . . . . . . .12-4
3.2 PIO Direction 0 Register (PDIR0, Offset 72h)  . . . . . . . . . . . . . .12-4
4 PIO DATA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5
4.1 PIO Data Register 1 (PDATA1, Offset 7Ah) . . . . . . . . . . . . . . . .12-5
4.2 PIO Data Register 0 (PDATA0, Offset 74h)  . . . . . . . . . . . . . . . .12-5
5 OPEN-DRAIN OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5
APPENDIX A REGISTER SUMMARY

Table of Contents ix

LIST OF FIGURES

Figure 1-1 Am186ES Microcontroller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4

Figure 1-2 Am188ES Microcontroller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5

Figure 1-3 Basic Functional System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6

Figure 2-1 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2

Figure 2-2 Processor Status Flags Register (F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2

Figure 2-3 Physical Address Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4

Figure 2-4 Memory and I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4

Figure 2-5 Supported Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9

Figure 3-1 Am186ES Microcontroller Address Bus—Normal Read and Write Operation.3-21

Figure 3-2 Am186ES Microcontroller—Read and Write with Address Bus

Disable In Effect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-21

Figure 3-3 Am188ES Microcontroller Address Bus—Normal Read

and Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22

Figure 3-4 Am188ES Microcontroller—Read and Write with Address

Bus Disable In Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22

Figure 3-5 Oscillator Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-26

Figure 3-6 Clock Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-27

Figure 4-1 Peripheral Control Block Relocation Register . . . . . . . . . . . . . . . . . . . . . . . . . .4-3

Figure 4-2 Reset Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4

Figure 4-3 Processor Release Level Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5

Figure 4-4 Auxiliary Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6

Figure 4-5 System Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7

Figure 5-1 Upper Memory Chip Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4

Figure 5-2 Low Memory Chip Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6

Figure 5-3 Midrange Memory Chip Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8

Figure 5-4 PCS and MCS Auxiliary Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10

Figure 5-5 Peripheral Chip Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12

Figure 6-1 Memory Partition Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1

Figure 6-2 Clock Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2

Figure 6-3 Enable RCU Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2

Figure 6-4 Watchdog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3

Figure 7-1 External Interrupt Acknowledge Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8

Figure 7-2 Fully Nested (Direct) Mode Interrupt Controller Connections . . . . . . . . . . . . .7-10

Figure 7-3 Cascade Mode Interrupt Controller Connections. . . . . . . . . . . . . . . . . . . . . . .7-11

Figure 7-4 INT0 and INT1 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-14

Figure 7-5 INT2 and INT3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-15

Figure 7-6 INT4 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-16

Figure 7-7 Timer/DMA Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-17

Figure 7-8 Serial Port 0/1 Interrupt Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18

Figure 7-9 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-19

Figure 7-10 Interrupt Request Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20

Figure 7-11 Interrupt In-Service Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-22

Figure 7-12 Priority Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-23

Figure 7-13 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-24

Figure 7-14 Poll Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-25

Figure 7-15 Poll Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-26

Figure 7-16 Example EOI Assembly Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-27

Figure 7-17 End-of-Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-27

Figure 7-18 Timer and DMA Interrupt Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .7-29

Figure 7-19 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-30

Figure 7-20 Interrupt Request Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-31

Figure 7-21 Interrupt In-Service Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-32

Figure 7-22 Priority Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-33

Figure 7-23 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-34

Figure 7-24 Specific End-of-Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-35

Figure 7-25 Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-36

Figure 8-1 Typical Waveform Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1

Table of Contents

Figure 8-1 Timer 0 and Timer 1 Mode and Control Registers. . . . . . . . . . . . . . . . . . . . . . .8-3

Figure 8-2 Timer 2 Mode and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5

Figure 8-3 Timer Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6

Figure 8-4 Timer Maxcount Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7

Figure 9-1 DMA Unit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2

Figure 9-2 DMA Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3

Figure 9-3 DMA Transfer Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6

Figure 9-4 DMA Destination Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7

Figure 9-5 DMA Destination Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8

Figure 9-6 DMA Source Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9

Figure 9-7 DMA Source Address Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10

Figure 9-8 Source-Synchronized DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-12

Figure 9-9 Destination Synchronized DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-13

Figure 10-10 DCE/DTE Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2

Figure 10-11 CTS/RTR Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3

Figure 10-1 Serial Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5

Figure 10-2 Serial Port 0/1 Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-9

Figure 10-3 Serial Port 0/1 Transmit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-11

Figure 10-4 Serial Port Receive 0/1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-12

Figure 10-5 Serial Port 0/1 Baud Rate Divisor Registers . . . . . . . . . . . . . . . . . . . . . . . . .10-14

Figure 11-1 Programmable I/O Pin Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1

Figure 11-3 PIO Mode 0 Register (PIOMODE0, offset 70h) . . . . . . . . . . . . . . . . . . . . . . . .11-3

Figure 11-2 PIO Mode 1 Register (PIOMODE1, offset 76h) . . . . . . . . . . . . . . . . . . . . . . . .11-3

Figure 11-4 PIO Direction 1 Register (PDIR1, offset 78h) . . . . . . . . . . . . . . . . . . . . . . . . .11-4

Figure 11-5 PIO Direction 0 Register (PDIR0, offset 72h) . . . . . . . . . . . . . . . . . . . . . . . . .11-4

Figure 11-6 PIO Data 1 Register (PDATA1, offset 7Ah) . . . . . . . . . . . . . . . . . . . . . . . . . .11-5

Figure 11-7 PIO Data 0 Register (PDATA0, offset 74h). . . . . . . . . . . . . . . . . . . . . . . . . . .11-5

Figure A-1 Internal Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-4

Table of Contents xi

LIST OF TABLES

Table 2-1 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5

Table 2-2 Segment Register Selection Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8

Table 2-3 Memory Addressing Mode Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10

Table 3-1 Numeric PIO Pin Designations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13

Table 3-2 Alphabetic PIO Pin Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14

Table 3-3 Programming Am186ES Microcontroller Bus Width . . . . . . . . . . . . . . . . . . . .3-24

Table 4-1 Peripheral Control Block Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2

Table 4-2 Processor Release Level (PRL) Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5

Table 4-3 Initial Register State After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9

Table 5-1 Chip Select Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

Table 5-2 UMCS Block Size Programming Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4

Table 5-3 LMCS Block Size Programming Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6

Table 5-4 MCS Block Size Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10

Table 5-5 PCS Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13

Table 5-6 PCS3–PCS0 Wait-State Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13

Table 6-7 Watchdog Timer COUNT Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4

Table 6-8 Watchdog Timer Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4

Table 7-1 Am186ES and Am188ES Microcontroller Interrupt Types. . . . . . . . . . . . . . . . .7-4

Table 7-2 Interrupt Controller Registers in Master Mode . . . . . . . . . . . . . . . . . . . . . . . . .7-13

Table 7-3 Priority Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18

Table 7-4 Priority Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-23

Table 7-5 Interrupt Controller Registers in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . .7-28

Table 7-6 Priority Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-33

Table 8-1 Timer Control Unit Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2

Table 9-1 DMA Controller Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1

Table 9-2 Synchronization Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4

Table 9-3 Maximum DMA Transfer Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-11

Table 10-4 Serial Port External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2

Table 10-1 Asynchronous Serial Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .10-4

Table 10-2 DMA Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5

Table 10-3 Serial Port MODE Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-7

Table 10-4 Common Baud Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-13

Table 11-1 PIO Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2

Table 11-2 PIO Mode and PIO Direction Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-3

Table A-1 Internal Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1

Table of Contents

xii

Introduction and Overview xiii

PREFACE

INTRODUCTION AND OVERVIEW

DESIGN PHILOSOPHY

AMD’s Am186 and Am188 family of microcontrollers is based on the architecture of the

original 8086 and 8088 microcontrolle rs, and currently includes the 80C186, 80C188,

80L186, 80L188 , Am186™EM, Am188™EM, Am186EMLV, Am188EMLV, Am186ES,

Am188ES, Am186ESLV, Am188ESLV, Am186ER, and Am188ER microcontrollers. The

Am186EM and Am188EM microcontrollers provide a natural migration path for 80C186/

188 designs that need performance and cost enhancements.

The Am186EM and Am188EM microcontrollers provide a low-cost, high-performance solution

for e mbedde d syst em des igne rs who wan t to use the x 86 arc hitec ture. By int egra ting mu ltip le

funct ional block s with th e CPU, t he Am18 6EM and Am188 EM microc ontr oller s elimi nate t he

need for off-chip system-interface logic. It is possible to implement a fully functional system with

ROM and RAM, serial interfaces, and custom I/O capability without additional system-interface

logic.

The Am186EM and Am188EM microcontroll ers can operate at frequencies up t o 40 MHz.

The microcontrollers include an on-board PLL so that the input clock can be on e-to-one

with the internal processor cloc k. The Am186 EM and Am188EM microcontroller s are

availabl e in versions operating a t 20, 25, 33, and 40 MHz.

PURPOSE OF THIS MANUAL

This manual describes the technical features and programming interface of the Am186EM

and Am188EM microcontrollers. The complete instruction set is documented in the

Am186

and Am188 Family Instr uction Set Manual,

order #21267.

INTENDED AUDIENCE

This manual is intended f o r computer hardware and software engi neers and system

architects who are designing or are considering designing systems based on the Am186EM

and Am188EM microcontrollers.

USER’S MANUAL OVERVIEW

This manual contains information on the Am186EM and Am188EM microcontrollers and

is essential for sy stem architects and design engi neers. Additional inf ormation is availabl e

in the form of data sheets, application notes, and other documentation that is provided with

software products and hardware-development tools.

The information in this manual is organized into 12 chapters and 1 appendix.

nChapter 1 introduces the features and performance aspects of the Am186EM and

Am188EM microcontrollers.

nChapter 2 describes the programmer’s model of the Am186 and Am188 family

microcontrollers, including an instruction set overview and register model.

nChapter 3 provides an overview of the system interfaces, along with cl ocking

features.

Introduction and Overview

xiv

nChapter 4 provides a description of the peripheral control block along with power

management and reset configuration.

nChapter 5 provides a description of the chip select unit.

nChapter 6 provides a description of the refresh control unit.

nChapter 7 provides a description of the on-chip interrupt controller.

nChapter 8 describes the timer control uni t.

nChapter 9 describes the DMA controller.

nChapter 10 describes the asynchronous serial port.

nChapter 11 describes the synchronous serial i nterface.

nChapter 12 describes the programmable I/O pins.

nAppendix A includes a complete summary of peripheral registers and fields.

For complete information on the Am186EM and Am188EM microcontroller pin lists, timing,

thermal characteristics, and physical dimensions, please refer to the

Am186EM/EMLV and

Am188EM/EMLV Microcontrollers Data Sheet

(orde r# 19168 ).

AMD DOCUMENTATION

E86 Family

ORDER NO. DOCUMENT TI TLE

19168 Am186EM/EMLV and Am1 88EM/ EMLV Microc ontrol lers Data Sh eet

Hardwa re doc ument atio n: pin d escr ipti ons, f uncti onal de scri pti ons, abs olu te

maximum ratings, operating ranges, switching characteristics and waveforms,

connec tion d iagra ms and pin outs , and pac kage phy sical dimensio ns.

21267 Am186 and Am188 Family Inst ruct ion Set Ma nual

Provides a detailed description and examples for each instruction included in the

Am186 and Am188 Fa mily Instru ction Set.

19255 FusionE86SM Catalo g

Provi des in for matio n on too ls tha t spe ed an E86 famil y embed ded pr oduct t o

market. Includes pro ducts from exp ert supplie rs of embedded development so-

lutions.

2007 1 E86 Fa mily Sup port Tools Brief

Lists available E86 family software and hardware development tools, as well as

contact information for suppliers.

21058 FusionE86 Dev elop ment Tool s Refe rence CD

Provi des a si ngle-so urce multi media to ol for cus tomer eva luatio n of AMD pr od-

ucts, as well as Fusion partner tools and technologies that support the E86 family

of mi crocontr ollers an d microp rocess ors. Techn ical do cumentati on for the E86

family is included on the CD in PDF format.

To order literatur e, contact the nearest AMD sales o ffi c e o r c a l l 8 0 0 -222 - 9 3 2 3 ( i n t h e U . S .

and Ca nada) or dire ct dia l from a ny lo catio n 512- 602-56 51.

Literature is also available in postscript and PDF formats on the AMD web site. To access the

AMD home page, go to http://www.amd.com. To download documents and software, ftp to

ftp.amd.com and log on as anonymous using your E-mail address as a password. Or via

your web browser, go to ftp://ftp.am d.com.

Features and Performance 1-1

CHAPTER

1FEATURES AND PERFORMANCE

Compared to the 80C186/188 microcontrollers, the Am186™EM and Am188™EM

microcontrollers enable desi gners to increase performance and functionality, while

reducing the cost, size, and pow er consumption of embedded systems. The Am186EM

and Am188EM microcontrollers are cost-effective, enhanced versions of the AMD 80C186/

188 devices.

The Am186EM and Am188EM microcontrollers are the ideal upgrade for 80C186/188

design s requi ring 80C186/188-compatibilit y, increased performance, serial

communications, and a glueless bus inte rface. Developed exclusively for the embedded

marketplace, t he Am186EM and Am188EM microcontrollers increase the perfor mance of

existing 80C186/188 syste ms while decr easing their cost.

Because the Am186EM and Am188EM microcontrollers integrate on-chip peripherals and

offer up to twice the performance of an 80C186/188, they are ideal upgrade solutions for

customers requiring more integration and performance than their present x86 solution

delivers.

1.1 KEY FEATURES AND BENEFITS

The Am186EM and Am188EM microcontrollers extend the AMD family of microcontrollers

based on the industry-standard x86 architecture. The Am186EM and Am188EM

microcontrollers deliver higher performance and more integration than the 80C186/188

core microcontrollers. Upgrading to the Am186EM or Am188EM microcontrollers is

attractive for the following reasons:

nMinimized total system cost—The new periph erals and on-c hip syst em-inter face l ogic

reduc e the cost of exis ting 80C186 designs .

nx86 software compatibility—80C186/188-compatible and upward-compatible with the

AMD E86 family.

nEnhanced performance—The Am186EM and Am188EM microcontrollers can provide

increased performance over 80C186/188 systems, and the nonmultiplexed address bus

offers faster, unbuffered access to memory.

nNo wait-state operation—At 40 MHz with 70-ns memories.

nEnhanced functionality—The new and enhanced on-chip peripherals of the Am186EM

and Am188EM microcontrollers include an asynchronous serial port, a watchdog timer

interrupt, an additional interrupt pin, a high-speed synchronous serial interface, a PSRAM

controller, a 16-bit Reset Configuration register, enhanced chip-select functionality, 32

programmable I/Os, and additional interrupt signals.

The Am 186EM and Am18 8EM micr ocontr olle rs are p art of the AMD E86 f amily of embedd ed

microcontrollers and microprocessors based on the x86 architecture. The 16-bit members of the

E86 fami ly, re ferr ed to thr oughou t this manual a s the A m186 and Am188 fami ly, in clude t he

80C186, 80C18 8, 80L186 , 80L188, Am186EMLV, Am188EMLV, Am186ES, Am188ES,

Am186ESLV, Am188ESL V, Am186ER, and Am188ER microcontrollers.

Features and Performance

1-2

The Am186EM and Am188EM microcontrollers are designed to meet the most common

requirement s of embedded products developed for the office automation, mass storage,

communicatio ns, and genera l embedded markets. Appl ica tions inc lude disk drives, hand-

held term inals, fax machines, terminals, printers, photocopi ers, feature phones, cellula r

phones, PBXs, multiplexer s, modems, and i ndustrial contr ols .

1.2 DISTINCTIVE CHARACTERISTICS

A block diagram of each micr ocontroller is shown in Figure 1-1 and Figure 1-2. The

Am186EM microcontroll er uses a 16-bit ext ernal bus, while the Am188EM microcontroller

has an 8-bit external bus.

The Am186EM and Am188EM microcontrollers provide the following features:

nHigh performance:

— 20-, 25-, 33-, and 40-MHz operating frequencies

— Support for zero wait-state operation at 40 MHz with 70-ns memory

— 1-Mbyte memory address space and 64-Kbyte I/O space

nNew features remove the r equirement fo r a 2x c lock input and provide faster acces s to

memory:

— Phase-locked loop (PLL) all o ws processor to op erate at the clock input frequency

— Nonmultipl exed address bus

nNew integrated peripherals increase functionalit y wh ile reducing system cost:

— 32 programmable I/O (PIO ) pins

— Asynchronous serial port allows full-duplex, 7-bit or 8-bit data tr ansfers

— Pseudo-static RAM (PSRAM) controller includes auto refresh capability

— Reset Configuration register

— Synchronous serial interface allows high-speed, half-dupl ex, bidirectional data

transfer to and from application-specific integrated circuits (ASICs)

— Addition al external interrupts

nFamiliar 80C 186 peripherals:

— Two independent DMA channels

— Programmable interrupt controller with five external interrupts

— Three programmable 16-bit timers

— Timer 1 can be configured to provide a watchdog timer interrupt

— Programmable memory and peripheral chip-s elect logic

— Programmable wa it-state generator

— Power-save mode

nSoftware-compatible with the 80C186/188 microcontroller

nWidely available native development tools, applications, and system software

nAvailable in the following packages :

— 100-pin, thin quad flat pack (TQFP)

— 100-pin, plastic quad flat pack (PQFP)

Features and Performance 1-3

Figu r e 1-1 Am1 86 EM Micr ocontroller Blo ck Diagram

Note:

* All PIO signals are shared with other physical pins. See the pin descriptions in Chapter 3 and Table

3-1 on page 3-9 for information on shared functions.

S2–S0

Interrupt

Control Unit

Timer Control

Unit DMA

Unit

Bus

Interface

Unit

Execution

Unit Chip-Select

Unit

Clock and

Power

Managem ent

Unit

Control

Registers

16-Bit Count

Registers

Max Count A

Registers 16-Bit Count

Registers

20-Bit Destination

Pointers

20-Bit Source

Pointers

Control

Registers

Control

Registers

Control

Registers

01 (WDT)2 0 1

Max Count B

Registers

Refresh

Control

Unit

Control

Registers Control

Registers

CLKOUTB

CLKOUTA INT4

INT3/INTA1/IRQ

INT2/INTA0

INT1/SELECT

INT0 TMROUT0 TMROUT1

DRQ0 DRQ1

VCC

GND

TMRIN0 TMRIN1

ARDY

SRDY

DT/R

DEN

HOLD

HLDA

Asynchronous

Serial Port

Synchronous Serial

Interface

TXD

RXD

SCLK SDATA

SDEN0 SDEN1

NMI

A19–A0

AD15–AD0

ALE

BHE/ADEN

WLB

WHB

RES

LCS/ONCE0

MCS2–MCS0

PCS6/A2

PCS3–PCS0

PCS5/A1

UCS/ONCE1

Control

Registers

PSRAM

Control

Unit

MCS3/RFSH

PIO

Unit PIO31–

PIO0*

Control

Registers

S6/

UZI

CLKDIV2

Features and Performance

1-4

Figu r e 1-2 Am1 88 EM Micr ocontroller Blo ck Diagram

Note:

* All PIO signals are shared with other physical pins. See the pin descriptions in Chapter 3 and Table

3-1 on page 3-9 for information on shared functions.

S2–S0

Interrupt

Control Unit

Timer Control

Unit DMA

Unit

Bus

Interface

Unit

Execution

Unit Chip-Select

Unit

Clock and

Power

Management

Unit

Control

Registers

16-Bit Coun t

Registers

Max Count A

Registers 16-Bit Count

Registers

20-Bit Destination

Pointers

20-Bit Source

Pointers

Control

Registers

Control

Registers

Control

Registers

01 (WDT)2 0 1

Max Count B

Registers

Refresh

Control

Unit

Control

Registers Control

Registers

CLKOUTB

CLKOUTA INT4

INT3/INTA1/IRQ

INT2/INTA0

INT1/SELECT

INT0 TMROUT0 TMROUT1

DRQ0 DRQ1

VCC

GND

TMRIN0 TMRIN1

ARDY

SRDY

DT/R

DEN

HOLD

HLDA

Asynchronous

Serial Port

Synchronous Serial

Interface

TXD

RXD

SCLK SDATA

SDEN0 SDEN1

NMI

S6/

A19–A0

AD7–AD0

ALE

RES

LCS/ONCE0

MCS2–MCS0

PCS6/A2

PCS3–PCS0

PCS5/A1

UCS/ONCE1

UZI

Control

Registers

PSRAM

Control

Unit

MCS3/RFSH

PIO

Unit PIO31–

PIO0*

Control

Registers

AO15–AO8

RFSH2/ADEN

CLKDIV2

Features and Performance 1-5

1.3 APPLICATION CONSIDERAT IONS

The integration enhancements of the Am186EM and Am188EM microcontrollers provide

a high-performance, low-system-cost solution for 16-bit embedded microcontroller designs.

The nonmultiplexed address bus (A19–A0) eliminates system-interface logic for memory

device s, while the multipl exed address/dat a bus maintains the val ue of existing customer-

specific peripherals and circ uits within the upgraded design.

The nonmultiplexed address bus is available in addition to th e 80C186 and 80C188

microcont rolle rs’ multipl exed address/d ata bus (AD15–AD0). The two buses can operate

simultaneously or the AD15–AD0 bus can be configured to operate only during the data

phase of a bus cycle. See the BHE/ADEN and RFSH2/ ADEN pin desc ription s in Chapt er 3,

and see secti on 5.5. 1 and se ction 5. 5.2 fo r addit ional info rmati on regar ding t he AD15–AD 0

addre ss enabl ing and disa bling.

Figure 1- 3 illust rate s a fun cti onal sy stem de sig n tha t uses t he integ rated per ipheral se t to

achieve high per formance with reduced system cost.

Figure 1-3 Basic Functional System Design

1.3.1 Clo ck Generation

The integrated PLL clock-generation circuitry of the Am186EM and Am188EM

microcontrollers allows the use of a

times-one

crysta l freq uency. The desi gn in Fi gure 1- 3

achi eves 40- MHz CPU op erati on with a 40 -MHz c rystal .

The integrated PLL lowers system cost by reducing the cost of the crystal and reduces

electromechanical interference (EMI) in the system.

RS-232 Level

Converter

TXD

RXD

LCS

UCS

WHB

WLB

Address

Data

Address

Data

AD15–AD0

A19–A0

Flash PROM

Static RAM

Serial Port

Am186EM

Microcontroller

40-MHz

Crystal

Features and Performance

1-6

1.3.2 Memory Interface

The integrated memory controller logic of the Am186EM and Am188EM microcontrollers

provides a direct address bus interface to memory devices. The use of an external address

latch controlled by the address latch enable (ALE) signal is not required.

Individual byte write-enable signals are provided to eliminate the need for external high/

low-byte, write-enable circuitry. The maximum bank size programmable for the memory

chip-sel ect signals i s inc reased to 512 Kby tes to facilitat e the use of high-densit y memory

devices.

Improved memory timing specifications enabl es the use of no-wait-stat e memories with

70-ns acce ss ti mes at 40-MHz CPU operation. This reduces overall system cost

significantly by allowing the use of commonly available memory devices.

Figure 1-3 illust rates an Am186EM microcontroller- based SRAM configuration. The

memory interf ace requires the foll owing:

nThe processor A19–A0 bus connects to the memory address inputs .

nThe AD bus connects directly to the data inputs/outputs.

nThe chip selects connect to the memory chip-select inputs.

Read operations require th at the RD output connects to the SRAM Output Enable (OE) inpu t

pins . Write op erati ons req uire t hat th e byte wri te enabl es conn ect to the SRA M Write Enabl e

(WE) input pin s.

The design uses 2-Mbit (256-Kbyte) memory technology to full y populate the available

address space. Two Flash PROM devices provide 512 Kbytes of nonvolatile program

storage, and two static RAM devices provide 512 Kbytes of variable storage area.

1.3.3 Serial Communi cations Port

The integrated universal asynchronous receiver/transmitter (UART) controller in the

Am186EM and Am188EM microcontrollers eliminates the need for external logic to

implement a communications interface. The integrated UART generates the serial clock

from the CPU clock so that no external time-base oscillator is requir ed.

Figure 1-3 shows a minimal implementation of an RS-232 console or modem

communications port. The RS-232 to CMOS voltage-level converter is required for the

proper electri cal interface with the exter nal device.

The Am186EM and Am188EM microcontrollers also include a synchronous serial interface.

For more information, see Chapte r 11.

1.4 THIRD-PARTY DEVELOPMENT SUPPORT PRODUCTS

The FusionE86 Progra m of Par tners hips for Applica tion Solut ions p rovid es the custo mer w ith

an arr ay of produc ts de signed to meet criti cal t ime-t o-marke t nee ds. P roduct s and s oluti ons

avai lable from the AMD Fu sio nE86 part ners i nclud e emulat ors, hardwar e and sof tware

debugg ers, bo ard-l evel p rodu cts, and s oftwar e devel opment t ools, among o thers.

In additi on, mature development tools and applications for the x86 platform are widely

availabl e in the general marketplace.

Programming 2-1

CHAPTER

2PROGRAMMING

All members of the Am186 and Am188 family of microco ntrollers, including the Am186EM

and Am188EM, contain the same basic set of regi sters, instructions, and addressing

modes, and are compatibl e with the original indust ry-standard 186/188 parts.

2.1 REGISTER SET

The base ar chitect ure of the Am186EM a nd Am188EM micro control lers has 14 regi sters,

as shown in Figure 2-1. These registers are grouped into the following categories:

nGeneral Registe rs—Eight 16-bit gener al purpose regi sters can be used f or arithmeti c

and logical operands. Four of these (AX, BX, CX, and DX) can be used as 16-bit registers

or split i nto pairs of separat e 8-bit registers ( AH, AL, BH, BL, CH, CL, DH, and DL). The

Destination Index (DI) and Source Index (SI) general-purpose registers are used for

data movement and string i nstruc tions. The Base Point er (BP) and St ack Pointer (SP)

general-purpose registers are used for the stack segment and point to the bottom and

top of the stack, respectively.

—Base and Index Registers—Four of the general-purpose registers (BP, BX, DI, and

SI) can also be used to determine offset addres ses of operands in memory. These

registers can contain base addresses or indexes to particular locations within a

segment. The addressing mode selects the specific registers for operand and address

calculations.

—Stack Pointer Register—All stack operations (POP, POPA, POPF, PUSH, PUSHA,

PUSHF) utilize the stack pointer. The Stack Pointer register is always offset from the

Stack Segment (SS) register, and no segment override is allo wed.

nSegment Registers—Four 16-bit specia l-purpose regist ers (CS, DS, ES, and SS)

select, at any given time, the segments of memory that are immediat ely addressable

for code (CS), dat a (DS and ES), and stack (SS) memory. (For usage, refe r to sect io n

2.2.)

nStatus and Control Registers—Two 16-bit special-purpose registers record or alter certain

as pect s of th e pro cessor state —the Instr ucti on Poin ter ( IP) r egist er cont ains t he of fset

addre ss of the ne xt sequ entia l inst ruct ion to b e exec uted and th e Proces sor S tatus Flags

(FLA GS) reg ister contai ns s tatus and con trol flag bits (see Fi gure 2-1 and Fi gur e 2-2).

Note that the Am186EM and Am188EM microcontrollers have additional on-chip peripheral

registe rs, which are exter nal to the processor. These e xternal register s are not accessi ble

by the instruction set. However, because the processor treats these peri pheral registers

like memory, instructions that have operands that access memory can also access

peripheral registers. The above processor registers, as well as the additional on-chip

peripheral registers, are described in the chapte rs that follow.

Programming

2-2

Figu r e 2-1 Regi st er Se t

2.1.1 Processor Status Fl ags Register

The 16-b it processor Status Flags register (Figure 2-2) r ecords specific characteristics of

the result of logical and arithmetic instructions (bits 0, 2, 4, 6, 7, and 11) and cont rols the

operation of the microcontroller within a given operating mode (bits 8, 9, and 10).

After an i nstruction i s executed, t he value o f the flags may be s et (to 1), cleared /reset (se t

to 0), unchanged, or undefined. The term

undefined

means that t he flag value p rio r to th e

execution of the instruction is not preserved, and the value of the flag after the instruction is

execut ed cann ot be p redic ted.

Figure 2-2 Processor Status Flags Register (F)

Bits 15–12—Reserved

Bit 11: Overflow Flag (OF)—Set if the signed result cannot be expressed within the number

of bits in the destination operand, cleared other wise.

Bit 10: Direction Flag (DF)—Causes string instructions to auto-decrement the appropriate

index regis ters when set. Clearing DF causes auto-increment.

Byte

Addressable

(8-Bit

Name s

Shown)

Loop/Shift/Repeat/Count

Base Registe rs

Code Segment

Data Segment

Stack Segmen t

Extra Segment

Processor Status Flags

Instruction Pointer

General

Registers Status and Control

Registers

Segment Registers

15 0

7 0 7 0

15 0

FLAGS

16-Bit

Functions

Index Registers

Stack Pointer

Multiply/Divide

I/O Instructions

Base Pointer

Source Index

Destin ati on Ind ex

16-Bit

15 70

ResCF

Reserved

Res

OFDF

Programming 2-3

Bit 9: Interrupt-Enable Flag (IF)—When set, enables maskable interrupts to cause the

CPU to transfer cont rol to a loc ation specified by an interrupt vector.

Bit 8: Trace Flag (TF)—When set , a trace interrupt occurs after instructions execute. TF

is cl eared by th e trace interr upt after t he processor st atus flags are pushed onto t he stack.

The trace serv ice routine ca n continue t racing by poppi ng the fl ags back with an interr upt

retu rn (IRET) instruction.

Bit 7: Si gn Flag (SF)—Set equal to h igh-order bit of result (0 if 0 or positive, 1 if negative).

Bit 6: Zero Flag (ZF) —Set if result is 0; cleared otherwise.

Bit 5: Reserved

Bit 4: Auxil iary Carry (AF) —Set on carry from or borr ow to the low-order 4 bits of the AL

general-purpose register; cleared otherwise.

Bit 3: Reserved

Bit 2: Parity Flag (PF)—Set if lo w-order 8 bits of resul t cont ain an even number of 1 bit s;

cleared otherwi se.

Bit 1: Reserved

Bit 0: Carry Flag (CF)—Set on high-order bit carry or borrow; cleared otherwise.

2.2 MEMORY ORGANIZATION AND ADDRESS GENERATION

Memory is organized in sets of segments. Each segment is a linear contiguous sequence

of 64K (216) 8-bit bytes. Memory is addressed using a two-component address that consists

of a 16-bit segment value and a 16-bit offset. The offset is the number of bytes from the

beginning of the segment (the segment address), to the data or instruction that is being

accessed.

The processor forms the physical address of the target location by taking the segment

address, shi fting it to the left 4 bits (multiplying by 16), and adding this to the 16-bit offs et.

The result is the 20-bit address of the target data or instruction. This allows for a 1-Mbyte

physi cal address size.

For example, if the segment register is loaded with 12A4h and the offset is 0022h, the

resulta n t address is 12A62h (see Figure 2-3). To find the result:

1. The segment register contains 12A4h.

2. The segment register is shifted 4 places and is now 12A40h.

3. The offset is 0022h.

4. The shifted segment address (12A40h) is added to the offset (00022h) to get 12A62h.

5. This address is placed on the pins of th e con tr o ller.

All instructions that address operands in memory mu st specify (implicitly or explicitly) a 16-

bit segment value and a 16-bit offset value. The 16-bit segment values are contained in one

of f our internal segment reg isters (CS, DS, ES, and SS). See “Addr essing Modes” on page

2-10 for more infor mation on calculat ing the o ffset val ue. See “Segments” on page 2-8 for

more information on CS, DS, ES, and SS.

In addi tion to memory space, all Am1 86 and Am188 fami ly processor s provide 64K of I/O space

(see Figure 2-4).

Programming

2-4

Figure 2-3 Physical Address Generation

2.3 I/O SPACE

The I/O space consists of 64K 8-bit or 32K 16-bit ports. The IN and OUT instructions address

the I/O space wit h either a n 8-bit port address spec ified in the instruction, or a 16-bit port

address in the DX register. Eight-bit port addresses are zero-extended so that A15–A8 are

Low. I/O port addresses 00F8h through 00FFh are reserved. The Am186EM and Am188EM

microcontrollers provide specific instructions for addressing I/O space.

Figu r e 2-4 Memor y an d I/ O Space

2.4 INSTRUCTION SET

Each member of the Am186 and Am188 family of microcontrollers, including the Am186EM

and Am188EM, share the standard 186 in str uction set. An instr uction can re fer ence from

zero to several operands. An operand can reside in a regist er, in the instruction itsel f, or in

memory. Specific operand addressing modes are discussed on page 2-10.

Table 2-1 lis ts t he instructions for the Am1 86EM and Am188EM microcontrollers in

alphabetical order. The Am186 and Am188 Family Instruction Set Manual, PID #21076,

provides det ailed informa ti on on the for mat and function of the following instructions.

1 2 A 4 0

0 0 0 2 2

1 2 A 6 2

1 2 A 4

0 0 2 2

Segment

Base Logical

Address

Shift

Left

4 Bits

Physical Address

To Memor

15 0

19 0

15 0

Offset

Memory

Space

I/O

Space

64K

Programming 2-5

Table 2-1 Instruction Set

Mnemonic Instruction Name

AAA ASCII adjust for addition

AAD ASCII adjust for division

AAM ASCII adjust for multiplication

AAS ASCII adjust for subtraction

ADC Add byte or word with carry

ADD Add byte or word

AND Logical AND byte or word

BOUND Detects values outside prescribed range

CALL Call procedure

CBW Convert byte to word

CLC Clear carry flag

CLD Clear direction flag

CLI Clear interrupt-enable flag

CMC Complement carry flag

CMP Compare byte or word

CMPS Compare byte or word string

CWD Convert word to doubleword

DAA Decimal adjust for addition

DAS Decimal adjust for subtraction

DEC Decrement byte or word by 1

DIV Divide byte or word unsigned

ENTER Format stack for procedure entry

ESC Escape to extension processor

HLT Halt until interrupt or reset

IDIV Integer divide byte or word

IMUL Integer multiply byte or word

IN Input byte or word

INC Increment byte or word by 1

INS Input bytes or word string

INT Interrupt

INTO Interrupt if overflow

IRET Interrupt return

JA/JNBE Jump if above/not below or equal

JAE/JNB Jump if above or equal/not bel ow

Programming

2-6

JB/JNAE Jump if below/not above or equal

JBE/JNA Jump if below or equal/not above

JC Jump if carry

JCXZ Jump if register CX = 0

JE/JZ Jump if equal/zero

JG/JNLE Jump if greater/not less or equal

JGE/JNL Jump if greater or equal/not les s

JL/JNGE Jump if less/not greater or equal

JLE/JNG Jump if less or equal/not greater

JMP Jump

JNC Jump if not carry

JNE/JNZ Jump if not equal/not zero

JNO Jump if not overflow

JNP/JPO Jump if not parity/parity odd

JNS Jump if not sign

JO Jump if overflow

JP/JPE Jump if parity/parity even

JS Jump if sign

LAHF Load AH register from flags

LDS Load pointer using DS

LEA Load effective address

LEAVE Restore stack for procedure exit

LES Load pointer using ES

LOCK Lock bus during next instruction

LODS Load byte or word string

LOOP Loop

LOOPE/

LOOPZ Loop if equal/zero

LOOPNE/

LOOPNZ Loop if not equal/not zero

MOV Move byte or word

MOVS Move byte or word string

MUL Multiply byte or word unsigned

NEG Negate byte or word

NOP No operation

NOT Logical NOT byte or word

Mnemonic Instruction Name

Programming 2-7

OR Logical Inclusive OR byte or word

OUT Output byte or word

POP Pop word off stack

POPA Pop all general register off stack

POPF Pop flags off stack

PUSH Push word onto stack

PUSHA Push all general registers onto stack

PUSHF Push flags onto stack

RCL Rotate left through carry byte or word

RCR Rotate right through carry byte or word

REP Repeat

REPE/REPZ Repeat while equal/zer o

REPNE/

REPNZ Repeat while not equal/not zero

RET0 Return from procedure

ROL Rotate left byte or word

ROR Rotate right byte or word

SAHF Store AH register in flags SF, ZF, AF, PF, and CF

SAL Shift left arithmetic byte or word

SAR Shift right arithmetic byte or word

SBB Subtract byte or word with borrow

SCAS Scan byte or word string

SHL Shift left logical byte or word

SHR Shift right logical byte or word

STC Set carry flag

STD Set direction flag

STI Set interrupt-enable flag

STOS Store byte or word string

SUB Subtract byte or word

TEST Test (Logical AND, flags only set) byte or word

XCHG Exchange byte or word

XLAT Translate byte

XOR Logical exclusive OR byte or word

Mnemonic Instruction Name

Programming

2-8

2.5 SEGMENTS

The Am186EM and Am188EM use four segment registers:

1. Data Segment (DS): The processor assumes that all accesses to the program’s

variables are from the 64K space pointed to by the DS register. The data segment holds

data, operands, etc.

2. Code Segment (CS): This 64K space is the default location for all instructions. All code

must be executed from the code segment.

3. Stack Segment (SS): The processor uses the SS register to perform operations that

involve the st ack, such as pushes a nd pops. The stack seg ment i s used for t emporary

space.

4. Extra Segment (ES): Usually this segmen t is used for large string operations and for

large data str u ctures. Certain string instructions assume the extra segment as the

segment port ion of the address. The extra segment is also used (by using segment

override) as a spare data segment.

When a segment i s not defined for a data movement instruc tion, it’s assumed t o be a data

segment. An instr u ction prefix can be used to over ride the segment register. For speed

and compact instruction encoding, the segment registe r used for physical address

generation is implied by the addressing mode used (see Table 2-1).

Table 2-1 Segme nt Register Selectio n Rules

2.6 DATA TYPES

The Am186EM and Am188EM microcontroll ers directly support the following data types:

nInteger—A signed binary numeric value cont ained in an 8-bit byte or a 16-bit word. All

operations assume a two’s complement representation.

nOrdinal—An unsig ned binary numeric va lue contained in an 8-bit byt e or a 16-bit word .

nDouble Word—A signed binary numeri c value contained in two sequential 16-bit

addresses, or in a DX::AX register pair.

nQuad Word—A signed binary numeri c value contained in four sequential 1 6-bit

addresses.

nBCD—An unpacked byte repres entation of the decimal digits 0–9.

nASCII—A byte repr esentati on of alp hanumeric and c ontro l char acters using the ASCII

standard of char acter representat ion.

nPacked BCD—A packed byte representation of two decimal digits (0–9). One digit is

stored in each nibble (4 bits) of the byte.

Memory Reference

Needed Segment Register

Used Implicit Segment Selection Rule

Local Data Data (DS) All data references

Instructions C ode (CS) Instructions (in cluding i mmediat e data)

Stack Stack (SS) All stack pushes a nd pops

Any memory refere nces that use the BP register

External Data (Glob al) Extra (ES) All string instruction references that use the DI register

as an index

Programming 2-9

nString—A c ontiguous sequ ence of bytes or words. A stri ng can contain from 1 b yte up

to 64 K b y t e .

nPointer—A 16-bit or 32-bi t quantity, compos ed of a 16-bit offset component or a 16-bit

segment base component plus a 16-bi t offset component.

In general, indi vidual data elements must fi t within defined segment limits. Figure 2-5

graphically represents the data types supported by the Am186EM and Am188EM

microcontrollers.

Figure 2-5 Supported Data Types

7 0

Signed

Byte

Magnitude

7 0

MSB

Unsigned

Byte

Signed

Word

Magnitude

MSB

+1 0

Magnitude

MSB

+3 +2 +1 0

Signed

Quad

Word

Magnitude

MSB

63 48 47 32 31 1615 0

Unsigned

Word

Magnitude

MSB

+1 0

7 0 7 0 7 0

+N +1 0

. . .

7 0 7 0 7 0

+N +1 0

. . .

7 0 7 0 7 0

+N +1 0

. . .

Binary

Coded

Decimal

(BCD) BCD

Digit N BCD

Digit 1 BCD

Digit 0

ASCII

CharacterNASCII

Character1ASCII

Character0

ASCII

Most Significant

Digit Least

Significant Digit

Packed

BCD

7 0 7 0

+N +1 0

. . .

Byte/WordN Byte/Word1 Byte/Word0

String

+3 +2 +1 0

Segment Base Offset

Pointer

31 1615 0

015

+3 +2 +1+6 +5 +4 +0+7

1514 8 7 0

Signed

Double

Word

Sign Bit

Programming

2-10

2.7 ADDRESSING MODES

The Am186EM and Am188EM microcontrollers use eight categories of addressing modes

to specify operands. Two addressing modes are pro vid ed for inst ruct ions that operate on

operand in a memory segment.

nRegister Operand Mode—The operand is located in one of the 8- or 16-bit registers.

nImmediate Operand Mode—The operand is included in the instruction.

Memory Operands

A memory-operand address consists of two 16-bit components: a segment value and an

offset. The s egment value is supplied by a 16-bit segment register either i mplicitly chosen

by the add ressing mode or explicitly chosen by a segment override prefix. The offset, als o

called the effective address, is calculated by summing any combi nation of the following

three address elements:

1. Displacement—an 8-bit or 16-b it imme diate value co ntai ned in the i nstru ctio n

2. Base—conte nts o f eit her the BX or BP ba se re giste rs

3. Index—cont ents of eith er the SI or DI ind ex regi sters

Any carry from the 16-bit addition is ign ored. Eight-bit displace ments ar e sign-ext ended to

16-bit val ues.

Combinations of the above thr ee address elements define the following six memory

addressing modes (see Table 2-2):

1. Direct Mode—Th e operan d offs et is co ntained in th e instr uctio n as an 8 - or 16-bi t

displacement element.

2. Register Indirect Mode—Th e oper and off set is i n one o f the re gister s BP, BX , DI, or SI .

3. Based Mode—The operand offset is the sum of an 8- or 16-bit displacement and the contents

of a bas e reg ister (BX or BP ).

4. Indexed Mode—The ope rand offset i s the su m of an 8- o r 16-bit displ acement and the

contents of an index register (DI or SI).

5. Based Indexed Mode—The o perand o ffset is the sum of th e conten ts of a b ase regis ter

(BP or BX) and an index register (DI or SI).

6. Based Indexed Mode with Displacement—The op erand of fset i s the sum of a base

regi ste r’s co ntents , an in dex r egist er’s c ontent s, and an 8-bi t or 16 -bit disp lacemen t.

Table 2-2 Memory Addressing Mode Examples

Addressing Mode Example

Direct mov ax, ds:4

Based mov ax, [bx]4

Indexed mov ax, [si]4

Based Indexed mov ax, [si][bx]

Based Indexed with Displacement mov ax, [si][bx]4

System Ov erv iew 3-1

CHAPTER

3SYSTEM OVERVIEW

This chapter contains descriptions of the Am186EM and Am188EM microcontroller pins,

the bus interf ace unit, the clock and power management unit, and power-save operation.

3.1 PIN DESCRIPTIONS

Pin Terminology

The followi ng terms are used to describe the pins:

Input—An input-only pin.

Output—An output-only pin.

Input/Output—A pin that can be either input or output.

Synchronous—Synchronous inputs must meet setup and hold times in relation to

CLKOUTA. Synchronous outputs are synchronous to CLKOUTA.

Asynchronous—Inputs or outputs that are asynchronous to CLKOUTA.

A19–A0 Address Bus (output, three-state, synchr onous)

The A19–A0 pins supply nonm ultiplexed memory or I/O addresses to

the syst em one-half of a CLKOUTA period e arlier than the mult iplexed

address and data bus (AD15–AD0 on the Am186EM or AO15–AO8 and

AD7–AD0 on the Am188EM). During a bus hold or reset condition, the

address bus is in a high- impedance state.

AD7–AD0 Address and Data Bus

(input/ output, three-state, synchronous, level-sensitive)

These time-multiplexed pins supply partial memory or I/O addresses,

as well as data, to the syst em. This b us supplies the l ow-order 8 bits of

an addre ss to the system du ring the first period of a bus c ycle (t1), and

it supplies data to the system during the remaining periods of that cycle

(t2, t3, and t4).

The address phase of these pins can be disabled. See the ADEN

descript ion with the BHE/ADEN pin. When WLB is not asser ted, these

pins are three-stated during t2, t3, and t4.

During a bus hold or reset condition, the address and data bus is in a

high-impedance state.

During a power-on res et, the addre ss and da ta bus pins (AD15–AD0

for the Am186EM, AO15–AO8 and AD7–AD0 for the Am188EM) can

also be us ed to load sy ste m configur at ion in for mation i nto the i nternal

Reset Configuration register.

System Ov erv iew

3-2

AD15–AD8 Address and Data Bus, Am186EM Microcontroller Only

(input/ output, three-state, synchronous, level-sensitive)

AD15–AD8—These time-multiplexed pins supply partial memory or

I/O addresses, as well as data, to the system. This bus supplies an

address to the syst em during the first period of a bus cycle (t1), and it

supplies dat a to the syst em duri ng the remaini ng perio ds of t hat cycle

(t2, t3, and t4).

The address phase of these pins can be disabled. See the ADEN

descript io n with the BHE/ADEN pin. When WHB is not asserted, these

pins are three-stated during t2, t3, and t4.

During a bus hold or reset condition, the address and data bus is in a

high-impeda nce state. Dur ing a power-on re set, th e address and data

bus pins (AD15–AD0 for the Am186EM, AO15–AO8 and AD7–AD0 for

the Am188EM) can also be used to lo ad system configuration

informat ion into the internal Reset Configur ation register .

AO15–AO8 Address-Only Bus, Am188EM Microcontroller Only

(output, three-stat e, synchronous, level-sensitive)

AO15–AO8—The address-only bus (AO15–AO8) contains valid high-

order address bits from bus cycles t1–t4. These outputs are floa ted

during a bus hold or reset.

On the Am188EM microcontroller, AO15–AO8 combine with AD7–AD0

to form a complete multiplexed address bus while AD7–AD0 is the 8-bit

data bus.

The address phase of these pins can be disabled during t1. See the

ADEN description with the BHE/ADEN pin.

During a power-on res et on the Am188EM microcon trol ler, th e AO15–

AO8 and AD7–AD0 pins can also be used to load system configuration

informat ion into an internal register for l ater use.

ALE Address Latch Enable (output, synchronous)

ALE—This pin indicates to the system th at an address appears on the

address and data bus (AD15–AD0 for the Am186EM or AO15–AO8

and AD7–AD0 for t he Am188EM). The address is guar anteed valid on

the trailing edge of ALE.

ARDY Asynchronous Ready (input, asynchronous, lev e l-sensitive)

This pin indicat e s to the microco n troller that the addressed memory

space or I/O device will complete a data transfer. The ARDY pin accepts

a rising edge that is asynchronous to CLKOUTA and is active High. The

falling edge of ARDY must be synchronized to CLKOUTA. To always

assert t he ready conditi on to the micr ocontroll er, tie ARDY High. I f the

system does not use ARDY, tie the pin Low to yield control to SRDY.

System Ov erv iew 3-3

BHE/ADEN Bus High Enable, Am186EM Microcontroller Only

(three-state, output, synchronous)

Address Enable, Am186EM Microcontroller Only

(input, internal pullup)

BHE—During a memory access, this pin and the least signifi cant

address bit (AD0 and A0) indicate to the system which bytes of the data

bus (upper, lower, or both) participate in a bus cycle. The BHE/ADEN

and AD0 pins are encoded as shown in the following table.

BHE is asserted during t1 and remains asserted through t3 and tW. BHE

does not need to be latched. BHE fl oats during bus hold and reset.

On the Am186EM microcontroller, WLB and WHB implement the

functionality of BHE and AD 0 for high and l ow byte wr ite enab les.

BHE/ADEN also signals DRAM refresh cycles when using the

multiplexed address and data (AD) bus. A refresh cyc le is indicat ed

when both BHE/ADEN and AD0 are High. During r efresh cycles, the A

bus and the AD bus are not guaranteed to provide the same address

during the addr ess phase of the AD bus cycle. For this reason, the A0

signal cann ot be used in pl ace of the AD0 signal to determine refresh

cycles. PSRAM refreshes also provide an additional RFSH s ignal (see

the MCS3/RFSH pin descripti on).

ADEN—If BHE/ADEN is held High or left floating during power-on reset,

the address po rtion of the AD bus (AD15–AD0) is enab led or di sabled

during LCS and UCS bus cycles based on the DA bit in the Upper

Memory Chip Select (UMCS) and Low Memory Chip Select (LMCS)

registers. If the DA bit is set, the memory address i s accessed on the

A19–A0 pins. This mode of operation reduces power consumption.

If BHE/ADEN is held Low on power-on reset, the AD bus always drives

both addresses and data. The pin is sa mpled one crystal clock cycle

after the rising edge of RES.

See section 5.5.1 and se ction 5.5.2 for addit ional information on

enabling and disabling th e AD bus during the address phase of a bus

cycle.

CLKOUTA Clock Output A (output, synchronous)

This pin supplies the internal clock to the system. Depending on the

value of the Power-Save Control (PDCON) register, CLKOUTA

operates at either the crystal input frequency (X1), the power-save

frequency, or is three-stated. CLKOUTA remains active during reset

and bus hold conditions.

BHE AD0 Type of Bus Cycle

0 0 Word Transfer

0 1 High Byte Transfer (Bits 15–8)

1 0 Low Byte Transfer (Bits 7–0)

1 1 Refresh

System Ov erv iew

3-4

CLKOUTB Clock Output B (output, synchronous)

This pin supplies an additional clock t o the system. Depending on the

value of the Power-Save Control (PDCON) register, CLKOUTB

operates at either the crystal input frequency (X1), the power-save

frequency, or is three-stated. CLKOUTB remains active during reset

and bus hold conditions.

DEN Data Enable (output, three-state, synchronous)

This pin supplies an output enable to an external data-bus transceiver.

DEN is asserted during memory, I/O, and interrupt acknowledge cycles.

DEN is deasserted when DT/R changes state. DEN floats during a bus

hold or reset condition.

DRQ1–DRQ0 DMA Requests (i nput, synchronous, level-sensitive)

These pins indicate to the m icrocontroller that an external device is

ready for DMA channel 1 or 0 t o perfor m a transf er. DRQ1–DRQ0 ar e

level tr iggered and internally synchroni zed.

The DRQ signals are not latched and must remain active until serviced.

DT/R Data Transmit or Receive (output, three-state, synchronous)

This pi n indicates which direction data should f low through an external

data-bus transceiver. When DT/R is asserted High, the microcontroller

transmit s da ta. When this pin is deasserted Low, the micr ocontroller

receives dat a. DT/R floats during a bus hold or re set condition.

GND Ground

These pins connect the system ground to the micr ocontroller.

HLDA Bus Hold Acknowledge (output, synchronous)

This pin is asserted High to ind icate to an external bus master that the

microcontroller has relinquished control of the local bus. When an

external bus master requests control of the local bus (by asserting

HOLD), the microcont roller completes the bus cycle in progress an d

then relinquishes control of the bus to the external bus master by

asserti ng HLDA and floating DEN, RD, WR, S2–S0, AD15–AD 0, S6,

A19–A0, BHE, WHB, WLB, and DT/R, and then driving the chip selects

UCS, LCS, MC S3–MCS0, PCS6–PCS5, and PCS3–PCS0 High.

When the external bus master has finished using the local bus, it

indicate s this to the microcontr oller by deasserting HOLD. The

microcontroller resp onds by deasserting HLDA.

If the microcont roller requires access t o the bus ( i.e., for refresh), it wil l

deassert HLDA bef ore the external bus master deasserts HOLD. The

external bus master must be abl e to deassert HOLD and allow the

microcontroller access to the bus.

HOLD Bus Hold Request (input, synchronous, level-sensitive)

This pin indicat e s to the microco n troller that an external bus master

needs contr ol of the lo cal bus. For more information, see the HLDA pin

description.

The Am186EM and Am188EM microcontrollers’ HOLD latency time,

that is , the t ime between HOLD request and HOLD acknowl edge, is a

function of the activity occurring in the processor when the HOLD

System Ov erv iew 3-5

request is r eceived. A HOLD reques t is second onl y to DRAM ref resh

requests in pri ority of activit y requests received by the process or. This

implies that if a HOLD request is received just as a DMA transfer begins,

the HOLD latency can be as great as 4 bus cycles. This occurs if a DMA

word transfer operation is taking place (Am186EM microcontroller only)

from an odd address to an odd address. This is a total of 16 clock cycles

or more if wait states are required. In addition, if locked transfers are

performed, the HOLD latency time is increased by the length of the

locked transfer.

INT0 Maskable Interrupt Request 0 (input, asynchronous)

This pin indicat e s to the microco n troller that an interrupt reque st has

occurred. If the INT0 pin is not masked, the microcontroller transfers

program execution to the location specified by the INT0 vector in the

microcontroller interrupt vector table. Interrupt requests are

synchronized internally, and can be edge-triggered or level-triggered.

To guarantee the interrupt is recognized, the device issuing the request

must continue asserting INT0 until the request is acknowledged.

INT1/SELECT Maskable Int errupt Request 1 (input, asynchronous)

Slave Select (input, asynchronous)

INT1—This pin indicates to the microcontroller that an interrupt request

has occurred. If the INT1 pin is not masked, the microcontroller transfers

program execution to the location specified by the INT1 vector in the

microcontroller interrupt vector table. Interrupt requests are synchro-

nized int ernally, and can b e edge-tri ggered or lev el-tr iggered. T o guar-

antee the inter rupt is recognized, the device issui ng the request must

continue asser ting INT1 until the re quest is acknowledged.

SELECT—When the microcontroll er inter rupt cont rol unit is operat ing

as a slave to an external master interrupt controller, this pin indicates

to the microcontroller that an interrupt type appears on the address and

data bus. The INT0 pin must ind icate to the microcontroller that an

interr upt has occurred before the SELECT pin indicates to the

microcontroller that the int errupt type appear s on the bus.

INT2/INTA0 Maskable Interrupt Request 2 (input, asynchronous)

Interrupt Acknow ledge 0 (output, synchronous)

INT2—This pin indicates to the microcontroller that an interrupt request

has occurred. If the INT2 pin is not masked, the microcontroller transfers

program execution to the location specified by the INT2 vector in the

microcontroller interrupt vector table. Interrupt requests are

synchronized internally, and can be edge-triggered or level-triggered.

To guarantee the interrupt is recognized, the device issuing the request

must conti nue asserting INT2 unt il the requ est is acknowl edged. INT2

becomes INTA0 when INT0 is configured in cascade mode.

INTA0—When the mic rocontr oller inte rrupt cont rol uni t is operati ng in

cascade mode, this pin indicates to the system that the microcontroller

needs an inte rrupt type to process the interrupt reques t on INT0. The

peripheral issuing the interrupt request must provide the microcontroller

with the corr esponding interrupt type.

System Ov erv iew

3-6

INT3/INTA1/IRQ Maskable Interrupt Request 3 (input, asynchronous)

Interrupt Acknow ledge 1 (output, synchronous)

Slave Interrupt Request (output, synchronous)

INT3—This pin indicates to the microcontroller that an interrupt request

has occurred. If the INT3 pin is not masked, the microcontroller then

transfers program execution to the location specified by the INT3 vector

in the microcontroller interrupt vector table. Inter rupt requests are

synchronized internally, and they can be edge-triggered or level-

triggered. To guarantee the inte rrupt is recogni zed, the device issuin g

the request must continue asserting INT3 until the request is

acknowledged. INT3 becomes INTA1 when INT1 is configured in

cascade mode.

INTA1—When the mic rocontr oller inte rrupt cont rol uni t is operati ng in

cascade mode, this pin indicates to the system that the microcontroller

needs an inte rrupt type to process the interrupt reques t on INT1. The

peripheral issuing the interrupt request must provide the microcontroller

with the corr esponding interrupt type.

IRQ—When the microcont roll er inter rupt contr ol unit is operat ing as a

slave to an external master interrupt contr oller, this pin lets the

microcontroller issue an interrupt request to the external master

interrupt controller.

INT4 Maskable Interrupt Request 4 (input, asynchronous)

This pin indicat e s to the microco n troller that an interrupt reque st has

occurred. If the INT4 pin is not masked, the microcontroller then

transfers program execution to the location specified by the INT4 vector

in the microcontroller interrupt vector table. Inter rupt requests are

synchronized internally, and they can be edge-triggered or level-

triggered. To guarantee the inte rrupt is recogni zed, the device issuin g

the request must continue asserting INT4 until the request is

acknowledged.

LCS/ONCE0 Lower Memory Chip Select (output, synchronous, inte rnal pull up)

ONCE Mode Request 0 (input)

LCS—This pin indicates to the system that a memory access is in

progress to the lower memory bl ock. The base address and si ze of the

lower memory bl ock are pr ogrammable up to 512 Kby tes. LCS is hel d

High during a bus hold condition.

ONCE0—During reset this pin and UCS/ONCE1 indicate to the

microcontroller the mode in which it shou ld operate. ONCE0 and

ONCE1 are sampled on the rising edge of RES. If both pins are asserted

Low, the microcontroller enters ONCE mode; otherwise, it operates

normally.

In ONCE mode, all pins assume a high-impedance state and remain in

that state until a subsequent reset occurs. To guarantee that the

microcontrol le r does not inadvertently ent er ONCE mode, ONCE0 has

a weak internal pullup resistor that is active only during a reset.

System Ov erv iew 3-7

MCS3/RFSH Midrange Memory Chip Select 3

(output, synchronous, internal pullup)

Automatic Refresh (output, synchronous)

MCS3—This pin indicates to the system that a memory access is in

progress t o the fourth region of the midran ge memory block. The base

address and size of the midrange memory block are programmable.

MCS3 is held High during a bus hold condition. In addition, this pin has

a weak internal pullup resistor that is active during reset.

RFSH—This pin provides a signal timed for auto refresh to PSRAM

devices. It is only enabled to function as a refresh pulse when the

PSRAM mode bit is set in the LMCS register. An active Low pulse is

generated f or 1.5 clock cycles wit h an adequate dea sser tion peri od t o

ensure overall auto refresh cycle time is met.

MCS2–MCS0 Midrange Memory Chip Selects

(output, synchronous, internal pullup)

These pins indi cate to the system that a memory access is in progr ess

to the corresponding region of the midr ange memory block. The base

address and size of the midrange memory block are programmable.

MCS2–MCS0 are held High during a bus hold condition. In addition,

they have weak inter nal pullup resistors that are active during a reset.

NMI Nonmaskable Interrupt (input, synchronous, edge-sensitive)

This pin indicat e s to the microco n troller that an interrupt reque st has

occurred. The NMI signal is the highest priority hardware interrupt and,

unlike the INT4 –INT0 pins, cannot be masked. The microcontroller

always transfers program execution to the location specified by the

nonmaskable interrupt vector in the microcontroller interrupt vector

table when NMI is asserted.

Although NMI is the highest priority interrupt source, it does not

participate in the priority resolution process of the maskable interrupts.

There is no bit associated with NMI in the interrupt in-service or interrupt

request r egisters. This means that a new NMI request can int errupt an

executing NMI interrupt service routine. As with all hardware interrupts,

the IF (interrupt flag) is cleared when the processor takes the interrupt,

disabling the maskable interrupt sources. However, if maskable

interrupts are re-enabled by software in the NMI interrupt service

routine, via t he STI inst ruction for example, the fact tha t an NMI is

currentl y in service will not have any effect on the priority reso lution of

maskable interrupt requests. For this reason, it is strongly advised that

the interr upt servi ce routine for NMI does not enable the maskable

interrupts.

An NMI transition from Low to High is latched and synchronized

internal ly, and it initi ates the interrupt at the nex t instruct ion boundary.

To guarantee that the interrupt is recognized, the NMI pin must be

asserted for at least one CLKOUTA period.

PCS3–PCS0 Peripheral Chip Selects (output, synchronous)

These pins indi cate to the system that a memory access is in progr ess

to the corres ponding region of the peripheral memory block (either I/O

or memory address space). The base address of the peripheral memory

block is programmable. PCS3–PCS0 are held High during a bus hold

System Ov erv iew

3-8

or reset condition. Unlike the UCS and LCS chip selects, the PCS

outputs assert with the multiplexed AD address bus.

Note: PCS4 is not available on the Am186EM and Am188EM micro-

controllers. Note also that each peripheral chip select asserts over a

256-byte address range, which is twice the address range covered by

peripheral chip selects in the 80C186 and 80C188 microcontrollers.

PCS5/A1 Peripheral Chip Select 5 (output, synchronous)

Latched Address Bit 1 (output, synchr onous)

PCS5—This pin indicates to the system that a memory access is in

progress to th e sixth region of th e peripheral memory block (ei ther I/O

or memory address space). The base address of the peripheral memory

block is programmable. PCS5 is held Hig h during a bus hold or reset

conditi on. It is also hel d High duri ng reset.

Note: Unlike the UCS and LCS chip selects, the PC S outputs assert

with the multiplexed AD address bus. Note also that each peripheral

chip select asserts over a 256-byte address range, which is twice the

address range covered by peripheral chip selects in the 80C186 and

80C188 microcontrollers.

A1—When the EX bit i n the MCS and PCS Auxiliary regi ster is 0, thi s

pin suppli es an intern ally latched address bi t 1 to the system. During a

bus hold condition, A1 retains its prev iously latched value.

PCS6/A2 Peripheral Chip Select 6 (output, synchronous)

Latched Address Bit 2 (output, synchr onous)

PCS6—This pin indicates to the system that a memory access is in

progress to the sevent h region of the peripher al memory block (ei ther

I/O or memory address space) . The base address of the peripheral

memory block is programmable. PCS6 is held High duri ng a bus hold

or reset condition.

Note: Unlike the UCS and LCS chip selects, the PC S outputs assert

with the multiplexed AD address bus. Note also that each peripheral

chip select asserts over a 256-byte address range, which is twice the

address range covered by peripheral chip selects in the original 80C186

and 80C188 microcontrollers.

A2—When the EX bit i n the MCS and PCS Auxiliary regi ster is 0, thi s

pin suppli es an intern ally latched address bi t 2 to the system. During a

bus hold condition, A2 retains its prev iously latched value.

PIO31–PIO0 (Shared)

Programmable I/ O Pins (in put/output , asynchr onous, open- drain)

The Am186EM and Am188EM microcontrollers provide 32 individually

programmable I/O pins. The pins that are multiplexed with PIO31–PIO0

are listed in Table 3-1 and Table 3- 2. Each PIO can be programmed

with the following attribut es: PIO function (enabl ed/disabled), directi on

(input/output), and weak pullup or pulldown. See Chapter 12 for the PIO

control registers.

After power-on reset, the PIO pins default to various configurations. The

column titled

Power-On Reset State

in Table 3-1 and Table 3-2 lists the

defaults for the PIOs. The syst em initializati on code mus t reconfigure

any PIOs as required.

System Ov erv iew 3-9

The A19–A17 address pins default to normal operation on power-on

reset, allowi ng the processor to correct ly begin fetching instructi ons at

the boot address FFFF0h. The DT/R, DEN, and SRDY pins also default

to normal operation on power-on reset.

Table 3-1 PIO Pin Assignments—Numeric Listing

Notes:

1. These pins are used by emulators. (Emulators also use

S2–S0

RES

, NMI, CLKOUTA,

BHE

ALE, AD15–AD0, and A16–A0.

2. These pins revert to normal operation if

BHE/ADEN

(Am186EM) or

RFSH2/ADEN

(Am188E M)

is held Low during power-on reset.

3. When used as a PIO, input with pullup option available.

4. When used as a PIO, input with pulldown option available.

PIO No. Associated Pin Power-On Reset Status

0 TMRIN1 Input with pullup

1 TMROUT1 Input with pulldown

2PCS

6/A2 Input with pullup

3PCS

5/A1 Input with pullup

4DT/R Normal opera tio n(3)

5DEN Normal opera tio n(3)

6 SRDY Normal operatio n(4)

7(1) A17 Normal operatio n(3)

8(1) A18 Normal operatio n(3)

9(1) A19 Normal operatio n(3)

10 TMROUT0 Input with pulldown

11 TMRIN0 Input with pullup

12 DRQ0 Input with pullup

13 DRQ1 Input with pullup

14 MCS0 Input with pullup

15 MCS1 Input with pullup

16 PCS0 Input with pullup

17 PCS1 Input with pullup

18 PCS2 Input with pullup

19 PCS3 Input with pullup

20 SCLK Input with pullup

21 SDATA Input with pullup

22 SDEN0 Input with pulldown

23 SDEN1 Input with pulldown

24 MCS2 Input with pullup

25 MCS3/RFSH Input with pullup

26(1,2) UZI Input with pullup

27 TXD Input with pullup

28 RXD Input with pullup

29(1,2) S6/CLKDIV2 Input with pullup

30 INT4 Input with pullup

31 INT2 Input with pullup

System Ov erv iew

3-10

Table 3-2 PIO Pin Assignments—Alphabetic Listing

Notes:

1. These pins are used by emulators. (Emulators also use

S2–S0

RES

, NMI, CLKOUTA,

BHE

ALE, AD15–AD0, and A16–A0.

2. These pins revert to normal operation if

BHE/ADEN

(Am186EM) or

RFSH2/ADEN

(Am188E M)

is held Low during power-on reset.

3. When used as a PIO, input with pullup option available.

4. When used as a PIO, input with pulldown option available.

Associated Pin PIO No. Power-On Reset Status

A17(1) 7Normal operation(3)

A18(1) 8Normal operation(3)

A19(1) 9Normal operation(3)

DEN 5Normal operation(3)

DRQ0 12 Input with pullup

DRQ1 13 Input with pullup

DT/R 4Normal operation(3)

INT2 31 Input with pullup

INT4 30 Input with pullup

MCS0 14 Input with pullup

MCS1 15 Input with pullup

MCS2 24 Input with pullup

MCS3/RFSH 25 Input with pullup

PCS0 16 Input with pullup

PCS1 17 Input with pullup

PCS2 18 Input with pullup

PCS3 19 Input with pullup

PCS5/A1 3 Input with pullup

PCS6/A2 2 Input with pullup

RXD 28 Input with pullup

S6/CLKDIV2(1,2) 29 Input with pullup

SCLK 20 Input with pullup

SDATA 21 Input with pullup

SDEN0 22 Input with pulldown

SDEN1 23 Input with pulldown

SRDY 6Normal operation(4)

TMRIN0 11 Input with pullup

TMRIN1 0 Input with pullup

TMROUT0 10 Input with pulldown

TMROUT1 1 Input with pulldown

TXD 27 Input with pullup

UZI(1,2) 26 Input with pullup

System Ov erv iew 3-11

RD Read Strobe (output, s ynchronous, three-state)

RD—This pin indicates to the system that the microcontroller is

performi ng a memory or I/O read cycl e. RD is guaranteed not to be

asserted before the address and data bus is floated during the address-

to-data transition. RD floats during a bus hold condition.

RES Reset (input, asynchronous, level-sensitive)

This pin causes the microcontroller to perform a reset. When RES is

asserted, the microcontroller immediately terminates its present

activi ty, cle ars its internal logic, and CPU control is tr ansferred to the

reset address FFFF0h. RES must be held Low for at least 1 ms. The

asserti on of RES can be asynchronou s to CLKOUTA because RES is

synchronized internally. For proper initialization, VCC must be within

specifications, and CLKOUTA must be stable f or mor e than four

CLKOUTA periods during which RES is asser ted. The micr ocontroll er

begins fetching instructions approximately 6.5 CLKOUTA periods after

RES is deasserted. This input is provided with a Schmitt tr igger to

facili tate power-on RES generation via an RC network.

RFSH2/ADEN Refresh 2 (three-state, output, synchronous)

Address Enable (input, internal pull up)

RFSH2—Available on the Am188EM microcontroller only, RFSH2/

ADEN is asserted Low to signify a DRAM refresh bus cycle. The use

of RFSH2/ADEN to signal a refresh is not valid when PSRAM mode is

selected. Instead, the MCS3/RFSH signal is prov ided to the PSRAM.

ADEN—If RFSH2/ADEN is held High or left floating on power-on reset,

the AD bus ( AO15–AO8 and AD7–AD0) is e nabled or disabl ed duri ng

the address portion of LCS and UCS bus c ycles based on the DA bit in

the LMCS and UMCS registers. If the DA bit is set, the memory address

is accessed on the A19–A0 pins. This mode of operation reduces power

consumption. There is a weak internal pullup resistor on RFSH2/ADEN,

so no external pul lup is required.

If RFSH2/ADEN is held Low on po wer-on rese t, the AD bus dr ives both

addre sses and dat a. The pi n i s sample d one cr ystal cloc k cycle after the

rising edge of RES. RFSH2/ADEN is t hree-stated dur ing bus holds a nd

ONCE mode.

See section 5.5.1 and se ction 5.5.2 for addit ional information on

enabling and disabling th e AD bus during the address phase of a bus

cycle.

RXD Receive Data (input, asynchronous)

This pin supplies asynchronous serial receive data to the

microcontroller UART.

S2–S0 Bus Cycle Status (output , three-state, synchronous)

These pins i ndicate to the sys tem the type of bus cycle i n progress. S2

can be used as a logical memory or I/O indicator, and S1 can be used

as a data transmit or receive indicator. S2–S0 float during bus hold and

hold acknowledge condi tions. The S2–S0 pins are encoded as shown

in the following table.

System Ov erv iew

3-12

S6/CLKDIV2 Bus Cycle Status Bit 6 (output, synchronous)

Clock Divide by 2 (input, internal pullup)

S6—During the second and remaining periods of a cycle (t2, t3, and t4),

this pin is asserted High to indicate a DMA-initiated bus cycle. Duri ng

a bus hold or reset condition, S6 floats.

CLKDIV2—If S6/CLKDIV2 is held Low during power-on reset, the chip

enters clock divide-by- 2 mode where the processor clock i s derived by

dividing t he ex ternal clock inpu t b y 2. I f thi s mode is sel ected, the PLL

is disabl ed. The pin is sampled on the rising edge of RES .

If S6 is to be used as PIO29 in input mode, the device driving PIO29

must not drive the pin Low during power-on reset. S6/PIO29 defaults

to a PIO input with pullup, so the pin does not need to be driven High

externally.

SCLK Serial Clock (out put, synchronous, three-state)

This pin supplies the synchronous serial interface (SSI) clock to a slave

device, allowing transmit and receive operations to be synchronized

between the microcontroller and the slav e. SCLK is derived from the

microcontroller internal clock and then divided by 2 , 4, 8, or 16,

depending on register settings. An access to any of the SSR or SSD

registers activates SCLK for eight SCLK cycles (see Figure 11-5 and

Figure 11-6 on page 11-8). When SCLK is inactiv e, it is held High by

the microcont roller.

SDATA Serial Data (input/output, synchronous)

This pin transmits and receives synchronous serial interface (SSI) data

to and from a slave device. When SDATA is inactive, a weak keeper

holds the last value of SDATA on the pin.

SDEN1–SDEN0 Serial Data Enables (output, synchronous)

These pins enable data tr ansfers on ports 1 and 0 of the synchronous

serial interface (SSI). The microcontroller asserts either SDEN1 or

SDEN0 at the beginning of a transfer and deasserts it after the transfer

is complete. When SDEN1–SDEN0 are inactive, they are held Low by

the microcont roller.

S2 S1 S0 Bus Cycle

000Interrupt acknowledge

001Read data from I/O

0 1 0 Write data to I/O

0 1 1 Halt

1 0 0 Instruction fetch

1 0 1 Read data from memory

110Write data to memory

111None (passive)

System Ov erv iew 3-13

SRDY Synchronous Ready (input, synchronous, level-sensitive)

This pin indicat e s to the microco n troller that the addressed memory

space or I/O device will complete a data transfer. The SRDY pin accepts

an active -High input sync hronized to CLKOUTA. Using SRDY instead

of ARDY allows a relax ed system t iming because of th e elimination of

the one-half clock period requi red to inter nally sync hronize ARDY. To

always assert the ready condition to the microcontroller, tie SRDY High.

If the system does not use SRDY, tie the pin Low to yield control to

ARDY.

TMRIN0 Timer Input 0 (input, synchronous, edge-sensitive)

This pin supplies a clock or control signal to the internal microcontroller

timer 0. After internally synchronizi ng a L ow-to-High transition on

TMRIN0, the microcontroller increments the timer. TMRIN0 must be

tied High if not being used.

TMRIN1 Timer Input 1 (input, synchronous, edge-sensitive)

This pin supplies a clock or control signal to the internal microcontroller

timer 1. After internally synchronizi ng a L ow-to-High transition on

TMRIN1, the microcontroller increments the timer. TMRIN1 must be

tied High if not being used.

TMROUT0 Timer Output 0 (output, synchronous)

This pin supplies to the system either a single pulse or a continuous

waveform with a programmable duty cycle. TMROUT0 is floated during

a bus hold or reset.

TMROUT1 Timer Output 1 (output, synchronous)

This pin supplies to the system either a single pulse or a continuous

waveform with a programmable duty cycle. It can also be programmed

as a watchdog timer. TMROUT1 is floated during a bus hold or reset.

TXD Transmit Data (output, asynchronous)

This pin supplies asynchronous serial transmit d ata from the

microcontroller UART to the system.

UCS/ONCE1 Upper Memory Chip Select (output , synchronous)

ONCE Mode Request 1 (input, internal pullup)

UCS—This pin indicates to the system that a memory access is in

progress to the upper memory block. The base address and size of the

upper memory bl ock are programmable up to 512 Kbytes. UCS is held

High during a bus hold condition.

After power-on reset, UCS is asserted because the processor b egins

executing at FFFF0h and the default configuration for the UCS chip

select is 64 Kbytes from F0000h to FFFFFh. See section 5.5.1.

ONCE1—During reset this pin and ONCE0 indicate to the

microcontroller the mode in which it shou ld operate. ONCE0 and

ONCE1 are sampled on the rising edge of RES. If both pins are asserted

Low, the microcontroller enters ONCE mode; otherwise, it operates

normally. In ONCE mode, all pins assume a high-impedance state and

remain in that state until a subsequent re set occurs. To guarantee that

the microcontr oller doe s not inadverten tly enter ONCE mode, ONCE1

has a weak internal pullup resistor that is active only during a reset.

System Ov erv iew

3-14

UZI Upper Zero Indicate (output, synchronous)

This pi n lets the designer determine whether an access to the i nterrupt

vector table is in progress by ORing it wit h bits 15–10 of the address

and data bus (AD15–AD10 on the Am186EM and AO15–AO10 on the

Am188EM). UZI is the logical OR o f t he inverted A19–A16 bits, and it

asserts in the first period of a bus cycle and is held throughout the cycle.

This pin should be allowed to float or should be pull ed High at reset. If

this pin is Low at the negation of reset, the Am186EM and Am188EM

microcontrollers will enter a reserved clock test mode.

VCC Power Supply (input)

These pins supply power (+5 V) to the microcontroller.

WHB Write High Byte, Am186EM Micro controller Only

(output, three-stat e, synchronous)

This pin and WLB indicate to the system which bytes of the data bus

(upper, l ower, or both) parti cip ate in a wri te cycl e. In 80C186 desi gns,

this information is provided by BHE, the least-significant address bit

(AD0), and by WR. However, by using WHB and WLB, the standard

system-interface logic and external address latch that were required

are eliminated.

WHB is asserted with AD15–AD8. WHB is the logical OR of BHE and

WR. This pi n floats during reset.

WLB/WB Write Low Byte, Am186EM Microcontroll er Only

(output, three-stat e, synchronous)

Write Byte, Am188EM Microcontroller Only

(output, three-stat e, synchronous)

WLB—This pin and WHB indicate to the system which bytes of the data

bus (upper, lower, or both) participate in a write cycle. In 80C186

design s, this information is provided by BHE, the least-significant

address bit (AD0), and by WR. However, by using WHB and WLB, the

standard syst em interface logic and external address latch that were

required are eliminat ed.

WLB is asserted with AD7–AD0. WLB is the logical OR of AD0 and WR.

This pin floats during reset.

WB—On the Am188EM microcontroller, this pin indicates a write to the

bus. WB uses the same early timing as the nonmultiplexed address

bus. WB is assoc iated wit h AD7–AD0. This pin floats dur ing reset. WB

is the logical OR of WHB and WLB, which are not present on the

Am188EM microcontroller.

WR Write Strobe (output, synchronous)

WR—This pin indic ates to th e system that the data on t he bus is to be

writte n to a memory or I/O device. WR floats during a bus hold or reset

condition.

System Ov erv iew 3-15

X1 Crystal Input (input)

This pin and the X2 pin provide connections for a fundamental mode

or third-overtone parallel-resonant crystal used by the internal oscillator

circuit. To provide the microcontroller with an external clock source,

connect the source to the X1 pin and leave the X2 pin unconnected.

X2 Crystal Output (output)

This pin and the X1 pin provide connections for a fundamental mode

or third-overtone parallel-resonant crystal used by the internal oscillator

circuit. To provide the microcontroller with an external clock source,

leave the X2 pin unconnected and connect the source to the X1 pin.

3.1.1 Pins That Are Used by Emulators

The following pins are used by emulators: A19–A0, AO15–AO8, AD7–AD0, ALE, BHE/

ADEN (on the Am186EM), CLKOUTA, RFSH2/ADEN (on the Am188EM), RD, S2–S0, S6/

CLKDIV2, and UZI.

Emulators require that S6/CLKDIV2 and UZI be configured in their normal functionality,

that is, as S6 and UZI.

If BHE/ADEN (on the Am186EM) or RFSH2/ADEN (on the Am188EM) is held Low during

the ri sing edge of RES, S6 and UZI ar e confi gured in th eir normal func tional it y, i nstead of

as PIOs, at reset.

System Ov erv iew

3-16

3.2 BUS OPERATION

The industry-standard 80C 186 and 80C188 microcontrollers use a multiplexed address

and data (AD) bus. The address is present on the AD bus only during the t1 clo ck pha se.

The Am186EM and Am188EM microcontrollers continue to provide the multiplexed AD bus and,

in add ition, provi de a no nmultipl exed ad dress ( A) bus. The A bu s provide s an ad dress t o the

system for the complete bus cycle (t1–t4).

For systems wher e power consumption is a concern, it is possible to disable the address

from being driven on the AD bus on t he Am186EM microcontroller and on the AD and AO

buses on the Am188EM microcontroller during the normal address portion of the bus cycle

for accesse s to UCS and/or LCS address sp aces. In this mode, t he affected bus is placed

in a high impedance state during the address portion of the bus cycle. This feature is enabled

through the DA bits in the UMCS and LMCS registers. When address disable is in effect,

the number of signals that assert on the bus during all normal bu s cycles to the associated

address space is reduced, thus decreasing power consumption, reducing processor

switching noise, and preventing bus contention with memory devices and peripherals when

operating at high clock rates. On the Am188EM microcontroller, the address is driven on

A015–A08 during the data portion of the bus cycle, regardless of the setting of the DA bits.

If the ADEN pin is pulled Low during processor reset, the value of the DA bits in the UMCS and

LMCS reg ister s is igno red a nd the add ress i s driven on the AD bu s for al l acce sses, thus

preserving the industry-standard 80C186 and 80C188 microcontrollers’ multiplexed address bus

and p rovid ing sup port f or ex isting emula tion t ool s.

Figure 3-1 on page 3-17 shows the affected signals during a normal read or write operation

for an Am186EM microcontroller. The address and data will be multiplexed onto the AD bus.

Figure 3-2 on page 3-17 shows an Am186EM microcontroller bus cycle when address bus

disable is in effect. This results in the AD bus operating in a nonmultiplexed data-only mode.

The A bus will provide the address during a read or write operation.

Figure 3-3 on page 3-18 shows the affected signals during a normal read or write operation

for an Am188EM microcon troller. The multiplexed address/ data mode is compatible with

80C188 microc ontrollers and might be used to take advant age of existing logic or

peripherals.

Figure 3-4 on page 3-18 shows an Am188EM microcontroller bus cycle when address bus

disable is in effect. The address and data are not multiplexed. The AD7–AD0 signals will

have only data on the bus, while the A bus will have the address during a read or write

operation. The AO bus will also have the address during t2–t4.

System Ov erv iew 3-17

Figur e 3-1 Am186EM Microcontroller Address Bus—Normal Read and Write Operation

Figur e 3-2 Am1 86 EM Mi crocontroller— Read and Write with Add r ess Bus Disa ble In Ef fe ct

CLKOUTA

t1t2t3t4

AD15–AD0

(Read) Data

AD15–AD0

(Write)

LCS or UCS

Address

DataAddress

Address

Phase Data

Phase

A19–A0 Address

MCSx, PCSx

CLKOUTA

t1t2t3t4

AD15–AD0

(Write) Data

LCS, UCS

AD15–AD8

(Read)

AD7–AD0

(Read)

Address

Phase

Data

Phase

Data

A19–A0 Address

System Ov erv iew

3-18

Figur e 3-3 Am188EM Microcontroller Address Bus—Normal Read and Write Operation

Figure 3-4 Am188EM Microcontroller—Read and Write with Address Bus Disable In Effect

CLKOUTA

t1t2t3t4

AD7–AD0

(Read) Data

AO15–AO8

(Rea d or Write)

AD7–AD0

(Write)

Address

DataAddress

Address

Phase Data

Phase

A19–A0 Address

LCS or UCS

MCSx, PCSx

CLKOUTA

t1t2t3t4

AD7–AD0

(Read) Data

Address

AO15–AO8

LCS, UCS

AD7–AD0

(Write) Data

Address

Phase Data

Phase

A19–A0 Address

System Ov erv iew 3-19

3.3 BUS INTERFACE UNIT

The bus interf ace unit controls all access es to external peri pherals and memory devices.

External accesses include those to memory d evices, as well as those to memory- mapped

and I/O-mapped peripherals and the peripheral control block. The Am186EM and

Am188EM microcontrollers provide an enhanced bus interface unit with the following

features:

nA nonmultiplexed address bus

nSeparate byte write enables for high and low bytes in the Am186EM microcontroller

nPseudo-Static RAM (PSRAM) support

The standard 80C186 multip lexed address and data bus requires system-int erface logic

and an external address latch. On the Am186EM and Am188EM microcontrollers, new

byte write enables, PSRAM control logic, and a new nonmultiplexed address bus can reduce

design costs by eliminating external logic.

Timing diagrams for the operations described in this chapter appear in the

Am186EM/EMLV

and Am188EM/EMLV Microcontrollers Data Sheet

, order# 19168.

3.3.1 Nonmultiple xed Addr ess Bus

The nonmultiplexed address bus (A19–A0) is valid one-half CLKOUTA cycle in advance

of the addres s on th e AD bus. When used i n conjunct ion wit h th e modified UCS and LCS

outputs and the byt e write enable si gnals, the A19–A0 bu s pr ovides a seamles s inter fa ce

to SRAM, PSRAM, and Flash/EPROM memory systems.

3.3.2 Byte Write Enables

The Am186EM microcontr oller provides two si gnals that act as byt e write enables—WHB

(Write High Byte, AD15–AD8) and WLB (Write Low Byte, AD7–AD0). WHB is th e logical

OR of BHE and WR (WHB is Low when both BHE and WR are Low). WLB is the logical

OR of AD0 and WR (WLB is Low when both AD0 and WR are both Low).

The Am188EM microcontroller provides one signal for byte write enables—WB (Write Byte).

WB is the lo gic a l OR o f WH B and WLB, which are not present on the Am188EM

microcontroller.

The byte write enables are driven in conjunction with the demultiplexed address bus as

required f or the write timing requirements of common SRAMs.

3.3.3 Pseudo Static RAM (PSRAM) Support

The Am186EM and Am188EM microcontroll ers support the use of PSRAM devices in low

memory chip select (LCS) space only. When PSRAM mode is enabled, the timing for the

LCS signal is modified by the chip select control unit to provide a CS precharge per iod

during PSRAM accesses. The 40-MHz timing of the Am186EM microcontro ll er is

appropria te to allow 70-ns PSRAM to run with one wait state. PSRAM mode is enabled

through a b it in t he Low Memory Chip Sel ect (LMCS) reg ister. ( See section 5 .5.2 on page

5-6.) The PSRAM feature is disab led on CPU reset.

In additi on to the LCS ti ming changes for PSRAM precharge, the PSRAM devices also

require per iodic refresh of all i nte rnal row addr esses to r etai n th eir data. Although r efresh

of PSRAM can be accomplished several ways, the Am186EM and Am188EM

microcontrollers implement auto refresh only. The microcontroller generates a refresh

signal, RFSH, to the PSRAM devices when PSRAM mode is enabled. No refresh address

is required by the PSRAM when using the auto refresh mechanism . The RFSH signal is

multiplexed with the MCS3 signal pin. When PSRAM mode is enabl ed, MCS3 is not

available for use as a chip select signal.

System Ov erv iew

3-20

The refresh control unit must be programmed before accessing PSRAM in LCS space. The

refresh counter in the Clock Prescaler (CDRAM) register must be configured with the

required r efresh inter val value. The ending address of LCS space and the ready and wait-

state generation in the LMCS register must also be programmed.

The refresh count er reload value in the CDRAM register should not be set to less than 18

(12h) in order to provi de time for processor cycles within refresh . In PSRAM mode, th e

refresh address counter must be set to 0000h to prevent another chip select from asserting.

LCS is held High during a refresh cycle. The A19–A0 bus is not used during refresh cycles.

The LMCS register must be configured to external Ready ignored (R2=1) with one wait

state (R1–R0=01 b), and the PSRAM mod e enable bit (PSE) must b e set to 1. See section

5.5.2 on page 5-6.

3.4 CLOCK AND POWER MANAGEMENT UNIT

The clock and power management unit of the Am186EM and Am188EM microcontrollers

includes a phase- locked loop (PLL) and a second programmable system clock output

(CLKOUTB).

3.4.1 Phase-Locked Loop (PLL)

In a traditional 80C186/188 design, the crystal frequency is twice that of the desired internal

clock. Because of the inter nal PLL on the Am186EM and Am188EM microcontrol lers, the

internal clock genera ted by the microcon tr oller (CLKOUTA) is the same frequency as the

crystal. The PLL takes the crystal inputs (X1 and X2) and generates a 45/55% (worst case)

duty cycle intermediate system clock of the same frequency. This feature removes the need

for an ex ternal 2x os cillat or, thereby reducing sy stem cost. The PLL is r eset duri ng power-

on reset by an on-chip power-on reset (POR) circuit.

3.4. 2 Cryst a l-Drive n Clock Sour ce

The inte rnal oscillator ci rcuit of the microcontroller is desi gned to function with a parallel

resonant fundamental or third overtone crystal. Because of the PLL, t he crysta l fr equency

is equal to the processor fr equency. Replacement of a cryst al with an LC or RC equiv alent

is not recommended.

The X1 and X2 signals are connected to an internal inverting amplif ier (oscillator) which

provides, along with the external feedback loading, the necessary phase shift (Figure 3-5).

In such a positi ve feedback circuit, the inverti ng ampli fier has an output signal (X2) 180

degrees out of phase of t he input s ignal (X1) . The exter nal f eedbac k network provi des an

additio nal 180-degree phase shift. In an ideal system, the input to X1 wil l have 360 or z ero

degrees of phase shift.

The external feedback network is designed to be as close as possible to ideal. If the

feedback network is not providing necessary phase shift, negative feedback will dampen

the output of the amplifier and negatively affect the operation of the clock generator. Values

for the loading on X1 and X2 must be chosen to provide the necessar y phase shift and

crystal operation.

System Ov erv iew 3-21

3.4.2 .1 Sele ct ing a Crystal

When selecti ng a crystal, the load capac itance should always be specified (CL). This value

can cause variance in the oscillation frequency from the desired specified value (resonance).

The lo ad cap acitanc e and t he loadin g of the feedb ack net work hav e the fo llowi ng rel ation ship:

where CS is the str ay capacit ance of the circuit. Pla cing the crys tal and CL in series across the

inverting amplifier and tuning these values (C1, C2) allows the crystal to oscillate at resonance.

This relati onship is true f or bot h fundame ntal an d thir d-ove rtone o perati on. Fina lly, there is a

relationship between C1 and C2. To enhance the oscillation of the inverting amplifier, these values

need to be offset with the larger load on the output (X2). Equal values of these loads tend to

balance the poles of the inverting amplifier.

The characteristics of the inverting amplifier set limits on the following parameter s for

crystals:

ESR (Equivalent Series Resistance)....................80 ohm Max

D rive Level ........ ...... ......................... ...... ..................1 mW Max

The recommended range of values for C1 and C2 are as fol lows:

C1...............................................................................15 pF ± 20%

C2...............................................................................22 pF ± 20%

The specif ic values f or C1 and C2 must be determine d by the designer and are depe ndent on

the ch arac teri stic s of the chose n cryst al and b oard desi gn.

Figure 3-5 Oscillator Configurations

(C1 ⋅ C2)

CL = (C1 + C2)+ CS

Crystal

Am186EM/

200 pF

Note 1

b. Crystal Configuration

a. Inverting Amplifier Configuration

C1C2

Crystal

Microcontroller

Am188EM

Note 1: Use for Third Overtone Mode

XTAL Frequency L1 Value (Max

20 MHz 12

20%

25 MHz 8.2

20%

33 MHz 4.7

20%

40 MHz 3.0

20%

System Ov erv iew

3-22

3.4.3 External Source Cl ock

Alternat ely, the inter nal oscillator can be dr iven from an exter nal clock source. This source

should be connected to the input of the i nverting amplifier (X1) with the output (X2) not

connected.

3.4.4 System Clocks

Figure 3-6 shows the organization of the clocks. The 80C186 microcontroller system clock

has been renamed CLKOUTA. CLKOUTB is provided as an additional output.

Figure 3-6 Clock Organization

CLKOUTA and CLKOUTB operate at either the processor frequency or the PLL frequency.

The output drivers for both clocks are individually programmable for drive enable or disable.

The second c lock output (CLKOUTB) l ets one clock ru n at the PLL f requency and another

clock run at the power-save frequency. Individual drive enable bits allow selective enabling

of just one or both of these clock outputs.

3.4.5 Power-Save Operation

The power-save mode reduces power consumption and heat dissipation, which can reduce

power supply costs and size in all systems and extend battery life in portable systems. In

power-save mo de, operation of the CPU and internal peripherals continues at a slower

clock fr equency. When an inter rupt occurs, the mi crocontrol ler automati cally returns t o its

normal operating frequency on the inte rnal clock’s next ris ing edge of t3.

Note: Power-save operation requires that clock-dependent devices be reprogrammed for

clock frequency changes. Software drivers must be aware of clock frequency.

PLL

Power-Save

Divisor

(/2 to /128)

Mux

CLKOUTA

CLKOUTB

Drive

Enable

X1, X2

Processor In ternal Clock

Time

Delay

6 ± 2.5ns

Mux

Drive

Enable

Peripheral Control Block 4-1

CHAPTER

4PERIPHERAL CONTROL BLOCK

4.1 OVERVIEW

The Am186EM and Am188EM microcontroller integrated peripherals are controlled by

16-bit read/write registers. The peripheral registers are contained within an internal 256-

byte control block—the peripheral control block. Registers are physically located in the

periphera l devices th ey control, but they a re addressed as a singl e 256-byte block. Figu re

4-1 shows a map of the peripheral control block registers.

Code that is intended to execute on the Am188EM microcontroller should perform all writes

to the PCB registers as byte wri tes. These writes will transfer 16 bits of data to the PCB

results in the value of ax bein g writ ten to the port addr ess in dx. Reads to the PCB should be

done as word reads. Code written in this manner will run correctly on the Am188EM

microc on tr olle r a nd o n the A m1 86 EM micr oc on tr oller. Unaligned reads and writes to the PCB

result in unpredictable behavior on both the Am186EM and Am188EM microcontrollers.

The peripheral control block can be mapped into either memory or I/O space. The base

address of the control block must be on an even 256-byte boundary (i.e., the lower eight

bits of the base address are 00h). Internal logic recognizes control block addresses and

responds to bus cycles. During bus cycles to internal registers, the bus controller signals

the operati on external ly (i.e., t he RD, WR, st atus, addres s, and data l ines are dri ven as in

a normal bus cycle), but t he data bus, SRDY, and ARDY are ignored.

At reset, the Peripher al Control Block Relocat ion register i s set to 20FFh, which maps the

control block to start at FF00h in I/O space. An offset map of the 256-byte peripheral control

description of the Peripheral Control Block Relocation (RELREG) register.

Peripheral Control Block

4-2

Figure 4-1 Peripheral Control Block Register Map

Chapter 4

Chapter 6

Chapter 9

Chapter 5

Chapter 10

PCS and MCS Auxiliary Register

Memory Partition Register

PDCON Register

Reset Configuration Register

Peripheral Control Block Relocation RegisterFE Register Name

Changed from 80C186

microcontroller.

Note: Gaps in offs et address es

indicate reserved registers.

Offset

(Hexadecimal)

Clock Presca ler Regi ste r

Enable RCU Regi ster

DMA 1 Control Register

DMA 1 Transfer Count Register

DMA 1 Destination Address Low Register

DMA 1 Source Address High Register

DMA 1 Source Address Low Register

DMA 0 Control Register

DMA 0 Transfer Count Register

DMA 0 Destination Address High Register

DMA 0 Destination Address Low Register

DMA 0 Source Address Low Register

DMA 0 Source Address High Register

Midrange Memory Chip Select Register

Peripheral Chip Select Register

Low Me mo ry Ch ip Select Register

Upper Memory Chip Select Register

80 Serial Port Status Register

84 Serial Port Receive Register

Processor Release Level Register

DMA 1 Destination Address High Register

Serial Port Baud Rate Divisor Register

Serial Port Transmit Register

Serial Port Control Register

Peripheral Control Block 4-3

Chapter 12

Chapter 8

Chapter 7

Chapter 11

Offset

(Hexadecimal)

INT2 Control Register

INT1 Control Regi ster

INT0 Control Register

DMA 1 Interrupt Control Register

DMA 0 Interrupt Contro l Regis ter

Timer Interrupt Control Register

Interrupt Status Register

Interrupt Request Register

In-service Register

Priority Mask Register

Interrupt Mask Register

Poll Status Register

Poll Regi ste r

End-of-Interrupt Register

Interrupt Vector Register

12 Synchronous Serial Transmit 1 Register

PIO Mode 0 Register

Changed from 80C186

microcontroller.

Note: Gaps in offs et addresses

indicate reserved registers.

Timer 2 Mode/Control Register

Timer 2 Maxcount Compare A Register

Timer 2 Count Register

Timer 1 Mode/Control Register

Timer 1 Maxcount Compare B Register

Timer 1 Maxcount Compare A Register

Timer 1 Count Register

Timer 0 Mode/Control Register

Timer 0 Maxcount Compare B Register

Timer 0 Maxcount Compare A Register

Timer 0 Count Register

INT3 Control Register

PIO Data 1 Register

PIO Direction 1 Register

PIO Mode 1 Register

PIO Data 0 Register

PIO Direction 0 Register

Serial Port Interrupt Control Register

Watchdog Timer Control Register

INT4 Control Register

Synchronous Serial Receive Register

Synchronous Serial Transmit 0 Register

Synchronous Serial Enable Register

Synchronous Serial Status Register

Peripheral Control Block

4-4

4.1.1 Peripheral Control Block Relocation Register (RELREG, Offset FEh)

The peripheral control block is mapped int o eit her memory or I/O space by programming

the Peri pheral Control Block Relocation (RELREG) register (see Figure 4-2). This register

is a 16-bit register at offset FEh from the control block base address. The RELREG register

provides the upper 12 bits of the base address of the control block. The control block is

effectively an internal chip select range.

Other chip selects can overlap the control block only if they are programmed to zero wait

states and ignore external re ady. If the control register bl ock is mapped into I/ O space, the

upper fo ur bits of the base address must be programmed as 0000b (since I/O addresses

are only 16 bits wide).

In additi on to providing relocation information for the control block, the RELREG register

contains a bit that places the interrupt controller into either slave m ode or master mode.

At reset, the RELREG register is set to 20FFh, which m aps the control block to start at

FF00h in I/O space. An offset map of the 256-byte peripheral control register block is shown

in Figure 4-1.

Figure 4-2 Peripheral Control Block Relocation Register (RELREG, offset FEh)

The value of the RELREG register is 20FFh at reset.

Bit 15: Reserved

Bit 14: Slave/Master (S/M)—Configures the interrupt contr o ller for slave mod e when set

to 1 and for master mode when set to 0.

Bit 13: Reserved

Bit 12: Memory/IO Space (M/IO)—When set to 1, the peripheral control block (PCB) is

located in memory space. When set to 0, the PCB is located in I/O space.

Bits 11–0: Relocation Address Bits (R19–R8)—R19–R8 define the upper address bits

of the PCB base address. The lower eight bits (R7–R0) default to 00h. R19–R16 are ignored

when the PCB is mapped to I/O space.

15 70

Res

S/M

R19–R8

Res

M/IO

Peripheral Control Block 4-5

4.1.2 Reset Configuration Register (RESC ON, Offset F6h)

The Reset Configuration (RESCON) register (see Figure 4-3) in the peripheral control block

latches system-configuration information that is presented to the processor on the address/

data bus (AD15–AD0 for the Am186EM or AO15–AO8 and AD7–AD1 for t he Am188EM)

during the rising edge of reset. The interpretation of this information is system-specific. The

processor does not impose any predetermined interpretation, but simply provides a means

for communicating this information to software.

When the RES input is ass erted Low, the contents of the address/data bus are writ ten into

the RESCON register. The system can place configuration information on the address/data

bus using weak external pullup or pulldown resi stors, or using an external driver tha t is

enabled during reset. The processor does not drive the address/data bus during reset.

For example, the RESCON register could be used to provide the software with the position

of a conf iguratio n switch in the sy stem. Using we ak external pullu p and pulldown resistors

on the address and data bus, the system could provide the microcontroller with a value

corresponding to the positi on of a jumper dur ing a reset.

Figur e 4-3 Rese t Configuration Regist er (R ES CO N , off set F6 h)

On reset, the RESCON register is set to the value fou nd on AD15–AD0.

Bits 15–0: Reset Configuration (RC)—There is a one-to-one correspond ence between

address/data bus signals during the reset and th e Reset Configuration registe r’ s bits. On

the Am186EM microcontroller, AD15 corresponds to bit 15 of the Reset Configuration

15, and AD7 corresponds to bi t 7. Once RES is deasserted, the RESCON register holds

its value. This value can be read by softwar e to determine the configuration informati on.

The contents of the RESCON register are read-only and remain valid until the next

processor reset.

15 70

Peripheral Control Block

4-6

4.1.3 Processor Release Level Register (PRL, Offset F4h)

The Processor Release Level (PRL) register (Figure 4-4) is a read-only register that

specifi e s the processor version.

Figure 4-4 Processor Re lease Level Register (PRL, offset F4h)

The values of the PRL register are listed in Table 4-1.

Bits 15–8: Processor Release Level (PRL)—This field is an 8-bit, read-only identification

number that speci fi es the processor release level. The values of the PRL field for the

Am186EM and Am188EM microcontr ollers are shown in Tabl e 4-1. Each rel ease level is

numbered one highe r than the previous level.

Bits 7–0: Reserved

Table 4- 1 Processor Re lease Lev el (PRL) Val ues

PRL Value Processor Relea se Level

01h C

02h D

03h E

04h F

15 70

Reserved

PRL

Peripheral Control Block 4-7

4.1.4 Power-Save Control Regi ster (PDCON, Offset F0h)

Figure 4-5 Power-Save Control Register (PDCON, offset F0h)

The value of the PDCON register is 0000h at reset.

Bit 15: Enable Power-Save Mode (PSEN)—When set to 1, enables Power-Save mode

and divides the internal operating clock by the value in F2–F0. PSEN is automatically

cleared when an external interrupt, including those generated by on-chip peripheral

devices, occurs. T he value of the PSEN bit is not restored by the execution of an IRET

instruction. Soft ware interrupts (INT instruction) and exceptions do not clear the PSEN bit,

and interrupt service routines for these conditions should do so if desired. This bit is 0 after

processor reset.

Bits 14–12: Reserved—Read back as 0.

Bit 11: CLKOUTB Output Frequency (CBF)—When set to 1, CLKOUTB follows the crystal

input (PLL) frequenc y. When set to 0, CLKOUTB follows the internal processor frequency

(after the clock divisor). Set to 0 on reset.

CLKOUTB can be used as a full-speed clock source in power-save mode.

Bit 10: CLKOUTB Drive Disable (CBD)—When set to 1, CBD three-states the clock output

driver fo r CLKOUTB. When set to 0, CLKOUTB is driven as an output. Set to 0 on reset.

Bit 9: CLKOUTA Output Frequency (CAF)—When set to 1, CLKOUTA follows the crystal

input (PLL) frequenc y. When set to 0, CLKOUTA follows the internal processor frequency

(after the clock divisor). Set to 0 on reset.

CLKOUTA can be used as a full-speed clock source in power-save mode.

Bit 8: CLKOUTA Drive Disable (CAD)—When set to 1, CAD three-states the clock output

driver fo r CLKOUTA. When set to 0, CLKOUTA is driven as an output. Set to 0 on reset.

Bits 7–3: Reserved—Read back as 0.

Bits 2–0: Clock Divisor Select (F2–F0)—Controls the division factor when Power-Save

mode is enabled. Allowable values are as follows:

F2 F1 F0 Divider Factor

000 Divide by 1 (20)

001 Divide by 2 (21)

010 Divide by 4 (22)

011 Divide by 8 (23)

100 Divide by 16 (24)

101 Divide by 32 (25)

110 Divide by 64 (26)

111 Divide by 128 (27)

15 70

000 00000

CBDCAF

CAD

F1 F0

PSEN CBF

Peripheral Control Block

4-8

4.2 INITIALIZATION AND PROCESSOR RESET

Processor ini tial izat ion or start up is acco mplished by drivi ng the RES input pin Low. RES

must be Low during power-up to ensure proper device initialization. RES forces the

Am186EM and Am188EM microcontrollers to terminate all execution and local bus activity.

No instruction or bus activity occurs as long as RES is active.

After RES is dea sserted and an internal processing interval elapses, the microcontroller

begins execution with the instruction at physical location FFFF0h. RES also sets some

registers to predefined values as shown in Tabl e 4-2.

Peripheral Control Block 4-9

Table 4-2 Initial Register State After Reset

Note:

Registers not listed in this table are undefined at reset.

Reset Comments

Processor Status Flags F F002h Interrupts disabled

Instruction Pointer IP 0000h

Code Segment CS FFFFh Boot address is FFFF0h

Data Segment DS 0000h DS = ES = SS = 0000h

Extra Segmen t ES 0000h

Stack Segm ent SS 0000h

Processor Release Level PRL XXxxh PRL XX = Revision (lower half-word is undefined)

Peripheral Control Block

Relocation RELREG 20FFh Peripheral control block located at FF00h in I/O space and

interrupt controller in master mode

Memory Partition MDRAM 0000h Ref r esh base ad dres s is 000 00h

Enable RCU EDRAM 0000h Refresh disabled, counter = 0

Upper Memory Chip Select UMCS F03Bh UCS active for 64K from F0000h to FFFFFh, 3 wait states,

external Ready signal required

Low Memory Chip Select LMCS Undefined

Serial Port Control SPCT 0000h

Serial port interrupts disabled, no loopback, no break,

BRKVAL low, no parity, word length = 7, 1 stop bit,

transmitter and receiver disabled

PIO Direction 1 PIODIR1 FFFFh

PIO Mode 1 PIOMODE1 0000h

PIO Direction 0 PIODIR0 FC0Fh

PIO Mode 0 PIOMODE0 0000h

Serial Port Interrupt Control SPICON 001Fh Serial port interrupt masked, priority 7

Watchdog Timer Interrupt Control WDCON 000Fh Watchdog timer interrupt masked, priority 7

INT4 Control I4CON 000Fh Int4 interrupt masked, edge-triggered, priority 7

INT3 Control I3CON 000Fh Int3 interrupt masked, edge-triggered, priority 7

INT2 Control I2CON 000Fh Int2 interrupt masked, edge-triggered, priority 7

INT1 Control I1CON 000Fh Int1 interrupt masked, edge-triggered, priority 7

INT0 Control I0CON 000Fh Int0 interrupt masked, edge-triggered, priority 7

DMA1 Interrupt Control DMA1CON 000Fh DMA1 interrupts masked, edge-triggered, priority 7

DMA0 Interrupt Control DMA0CON 000Fh DMA0 interrupts masked, edge-triggered, priority 7

Timer Interrupt Control TCUCON 000Fh Timer interrupts masked, edge-triggered, priority 7

In-Service INSERV 0000h No interrup ts are in-s erv ic e

Priority Mask PRIMSK 0007h Allow all interrupts based on priority

Interrupt Mask IMASK 07FDh All interrupts masked (off)

Synchronous Serial Control SSC 0000h SCLK = 1/2 CLKOUTA, no data enabled

Synchronous Serial Status SSS 0000h Synchronous serial port not busy, no errors, no transmit or

receive completed.

DMA 1 Control D1CON FFF9h

DMA 0 Control D0CON FFF9h

Peripheral Control Block

4-10

Chip Select Unit 5-1

CHAPTER

5CHIP SELECT UNIT

5.1 OVERVIEW

The Am186EM and Am188EM micr ocontrollers cont ain logic that provides programmabl e

chip select generation for both memories and peripherals. In addition, the logic can be

programmed to provide ready or wait-state generation and latched address bits A1 and A2.

The chip select lines are active for al l memory and I/O cycles in their programmed areas,

whether they are generated by the CPU or by the integrated DMA unit.

The Am186EM and Am188EM microcontrollers provide six chip select outputs for use with

memory devices and six more for use with peripherals in either memory space or I/O space.

The six memory chip selects can be used to address three memory ranges. Each peripheral

chip select addresses a 256-byte block offset from a programmable base address (see

section 4.1.1 on page 4-4).

The chip selects are programmed through the use of five 16-bit peripheral registers (Table

5-1). The UMCS register, offset A0h, is used to program the Upper Memory Chip Select

(UCS). The LMCS register , offset A2h, is used to progr am the Lower Memory Chip Select

(LCS). The Midrange Memory Chip Selects (MCS3–MCS0) are programmed thr ough the

use of two r egisters—the Midran ge Memory Chip Select (MMCS) r egister, o ffset A6h and

the PCS and MCS Auxiliary (MPCS) register, offset A8h. In addition to its use in configuring

the MCS chip selects , the MPCS register and t he PACS reg ister are us ed to pr ogram the

Peripheral Chip Selects (PCS6–PCS5 and PCS3–PCS0).

Note: The PCS4 chip select is not implemented on the Am186EM and Am188EM

microcontrollers.

Table 5-1 Chip Select Register Summar y

Note:

A read or write will enable a chip select register .

Offset Register

Mnemonic Regi ster Na me Affected Pins Comments

A0h UMCS Upper Memory Chip Select UCS Ending address is fixed at FFFFFh

A2h LMCS Lower Memory Chip Select LCS Starting address is fixed at 00000h

A4h PACS Peripheral Chip Select PCS6–PCS5

PCS3–PCS0 Block size is fixed at 256 bytes

A6h MMCS Midrange Chip Sele ct MCS3–MCS0 Starting address and block size are

programmable

A8h MPCS PCS and MCS Auxiliary PCS6–PCS5

PCS3–PCS0

MCS3–MCS0

Affects both PCS and MCS

chip selects

Chip Select Unit

5-2

Except for the UCS chip select, which is active on reset as discussed in section 5.5.1, chip

selects ar e not activated until the assoc iated registers have been accessed. (An access is

any read or write operation.) For this reason, the chip select registers should not be read

by the processor ini ti a lization code until after they have been written with valid data. The

LCS chip select is activated when the LMCS register is accessed, the MCS chip selects

are activated after both the MMCS and MPCS registers have been accessed, and the PCS

chip select s are activated after both the PACS and MPCS registers have been accessed.

5.2 CHIP SELECT TIMING

The timing for the UCS and LCS outputs has been modified from the 80C186 and 80C188

microcont rollers. These ou tputs now assert in conj unction with th e demultiplexed addr ess

bus (A19–A0) for normal memory timing. To make these outputs available earlier in the

bus cycle, the number of programmable memory si ze selections has been reduced.

The MCS3–MCS0 and PCS ch ip selects assert with the AD bus.

5.3 READY AND WAIT-STATE PROGRAMMING

The Am186EM and Am188EM microcontrollers can be programmed to sense a ready signal

for each of the peripher al or memory chip select lines. The ready signal can be either the

ARDY or SRDY signal. Each chip select cont rol register (UMCS, LMCS, MMCS, PACS,

and MPCS) contains a single-bit field, R2, that determines whether the external ready signal

is required or ignored. When R2 is set to 1, external r eady is ignored. When R2 is set to 0,

external ready is required.

The number of wait states to be inserted for each access to a periphe ral or memory region

is programmable. Zero wait st ates to 15 wait states can be inserted for the PCS3–PCS0

peripheral chip selects. Zero wait states to three wait st ates can be inserted for all other

chip sele cts.

Each of the chip select control registers, other than the PACS register (UMCS, LMCS,

MMCS, and MPCS), contain s a two-bit f ield, R1–R0, whose value det ermines the number

of wait states from none to three to be inserted. A value of 00b in this field specifies no

inserted wait states. A value of 11b specifies three inserted wait states.

The PCS3–PCS0 peri pheral chip selec ts can be programmed for up to 15 wait sta tes. The

PACS register uses bits R3 and R1–R0 for the addit ional wait stat es.

When external ready is required (R2 is set to 0), internally programmed wait states will

always complet e before external ready can terminat e or extend a bus cycle. For example,

if the internal wait states are set to insert two wait states (R1–R0 = 10b), the processor

samples the external ready pin during the fi rst wait cycle. If external ready is asserted at

that time, the access completes after six cycles (four cycles plus two wait states). If external

ready is not asserted during the first wait state, the access is extended until ready is

asserted, which is followed by one more wait state followed by t4.

5.4 CHIP SELECT OVERLAP

Although progr amming the vari ous chip selects on the Am186EM microcontroller so that

multiple chip select signals are asserted for the same physical address is not recommended,

it may be unavoidable in some systems. In such systems, the chip selects whose assertions

overlap must have the same configuration for ready (external ready required or not required)

and the number of wait states to be inserted into the cycle by the pr ocessor.

The peripheral control block (PCB) is accessed using internal signals. These internal signals

functio n as chip selects con figured wit h zero wait states and n o external r eady. Therefor e,

the PCB can be programmed to addresses that overlap external chip select signals if those

external chip selects are programmed to zero wait stat es with no external ready require d.

Chip Select Unit 5-3

When overlapping an additional chip select with either the LCS or UCS chip selects, it must

be noted that setting the Disable Address (DA) bit in the LMCS or UMCS register will disable

the address from being driven on the AD bus for all accesses for which the associated chip

select is asserted, including any accesses for which multiple chip selects assert.

The MCS and PCS chip select pins can be configured as either chip selects (norma l

functio n) or as PIO i nputs or output s. It shou ld be note d; howe ver, that the r eady and wai t

state generation logic for these chip selects is in effect, regardless of their configurations

as chip selects or PIOs. This means that if these chip selects are enabled (by a read or

write to the MMCS and MPCS registers for the MCS chip selects, or by a read or write to

the PACS and MPCS registers for the PCS chip selects), the ready and wait stat e

programming for these signals must agree with the programming for any other chip selects

with which their assertion would overlap if they were configured as chip selects.

Although the PCS4 signal is not available on an external pin, the ready and wait state logic

for this signal still exists internal to the part. For this reason, the PCS 4 address space must

follow the rules for overlapping chip selects. The ready and wait-state logic for PCS6–PCS5

is disabled when these signals are configured as address bits A2–A1.

Failure to configure overlapping chip selects with the same ready and wait state

requirements may cause the processor to hang with the appear ance of waiting for a ready

signal. This behavior may occur even in a system in which ready is always asserted (ARDY

or SRDY tied High).

Configuring PCS in I/O space with LCS or any other chip select configured for memory

address 0 is not considered overlapping of the chip selects. Overlapping chip selects refers

to confi gurations where more than one chip select asserts for the same physical address.

5.5 CHIP SELECT REGISTERS

The following sections describe the chip select registers.

Chip Select Unit

5-4

5.5.1 Upper Memory Chip Select Register (UMCS, Offset A0h)

The Am186EM and Am188EM microcontrollers provide the UCS chip select pin for the top

of memory. On reset, the microcontroller begins fetching and executing instructions starting

at memory locat ion FFFF0h, so upper memory i s usually used as i nstr ucti on memory. To

facilitate this usage, UCS defaults to active on reset with a default memory range of 64

Kbytes from F0000h to FFFFFh, external ready required, and three wait states automatically

inserted.

The UCS memory range always ends at FFFFFh. The lower boundar y is programmable.

The Upper Memory Chip Select is conf igured through the UMCS register (Figure 5-1).

Figure 5-1 Upper Memory Chip Select Register (UMCS, offset A0h)

The value of the UMCS register at reset is F03Bh.

Bit 15: Reserved—Set to 1.

Bits 14–12: Lower Boundary (LB2–L B0)—The LB2–LB0 bits define the lower bound of

the memory accessed through the UCS chip selects. The number of programmable bits

has been reduced from eight bi ts in the 80C186 and 80C188 microcontrol lers to three bit s

in the Am186EM and Am188EM microcontrollers.

The Am186EM and Am188EM microcontro llers provide an additional block size of 512K,

which i s not avai lable on the 8 0C186 and 8 0C188 microcont rollers. Table 5- 2 outli nes the

possible configurations and differences with the 80C186 and 80C188 microcontrollers.

Table 5-2 UMCS Bloc k Size Programming Values

Memory

Block

Size Starting

Address LB2–LB0 Comments

64K F0000h 111b Default

128K E0000h 110b

256K C0000h 100b

512K 80000h 000b Not available on the 80C186 or 80C188 microcontroller

15 70

LB2–LB0

10000

R1–R0

A19

111

R2DA

Chip Select Unit 5-5

Bits 11–8: Reserved

Bit 7: Disable Addre ss (DA)—The DA bit enables or disables th e AD15–AD0 bus during

the address phase of a bus cycle when UCS is asserted. If DA is set to 1, AD15–AD0 is

not driven during the address phase of a bus cycle when UCS is asserted. If DA is set to

0, AD15–AD0 is driven duri ng the address phase of a bus cycle. Disabling AD15–AD0

reduces power consumption. DA defaults to 0 at power-on reset.

Note: On the Am188EM microcontroller, the AO15–AO8 address pins are driven during

the data phase of the bus cycles, even when the DA bit is set to 1 in either the UMCS or

LMCS register.

If BHE/ADEN (on the Am186EM) or RFSH2/ADEN (on the Am188EM) is held Low on the

rising edge of RES, then AD15– A D0 is always driven regardless of the DA setting. This

configures AD15–AD0 to be enabled regardless of the setting of DA.

If BHE/ADEN (on the Am186EM) or RFSH2/ADEN (on the Am188EM) is High on the rising

edge of RES, then DA in the Upper Memory Chip Select (UMCS) regi ster and DA in the

Lower Memory Chip Select (LMCS) regi ster control the AD15–AD0 disabl ing.

See the description s of the BHE/ADEN and RFSH2/ADEN pins in Chapter 3.

Bits 6: Reserved—Set to 0.

Bits 5–3: Reserved—Set to 1.

Bit 2: Ready Mode (R2)—The R2 bit is used to configure the ready mode for the UCS chip

select. If R2 is set to 0, external ready is required. If R2 is set to 1, external ready is ignored.

In each case, the processor also uses the value of the R1–R0 bits to determine the number

of wait states to insert. R2 defaults to 0 at reset.

Bits 1–0: Wait-State Value (R1–R0)—The value of R1–R0 determines the number of wait

states inserted into an access to the UCS memory area. From zero to three wait states can

be inserted (R1–R0 = 00b to 11b). R1–R0 default to 11b at reset.

Chip Select Unit

5-6

5.5.2 Low Memory Chip Select Register (LMCS, Offset A2h)

The Am186EM and Am188EM microcontrollers provide the LCS chip select pi n for the

bottom of memory. Since the interrupt vector table is located at 00000h at the bottom of

memory, the LCS pin has been provided to facil itate this usage. The LCS pin is not acti ve

on reset, but any read or write access to the LMCS register activates this pin.

The Low Memory Chip Select is confi gured through the LMCS register (see Fi gure 5-2).

Figure 5-2 Low Memory Chip Select Register (LMCS, offset A2h)

The value of the LMCS register at reset is undefined.

Bit 15: Reserved—Set to 0.

Bits 14–12: Upper Boundary (UB2–UB0)—The UB2–UB0 bits define the upper bound of

the memory access ed through the LCS chip select. Because of the timing requir ements of

the LCS output and the nonmultiplexed address bus, the number of programmable memory

sizes for t he LMCS register is reduced compar ed to the 80C186 and 80C188

microcontrol le rs. Consequen tly, the number of programmable bits has been reduced from

eight bits in the 80C186 and 80C188 microcontrollers to three bits in the Am186EM and

Am188EM microcontrollers.

The Am186EM and Am188EM mi croc ontroller s have a b lock si ze of 512 Kbytes, which is

not availa ble on the 80C186 and 80C188 microcontroll ers. Table 5-3 outlines the possi ble

configur ations and the differences between the 80C186 and 80C188 microcontrollers and

the Am186EM and Am188EM microcontrollers.

Table 5-3 LMCS Block Size Programming Values

Memory

Block

Size Ending

Address UB2–UB0 Comments

64K 0FFFFh 000b

128K 1FFFFh 001b

256K 3FFFFh 011b

512K 7FFFFh 111b Not available on the 80C186 and 80C188 microcontrollers

15 70

UB2–UB0

111

PSE

11 1

A19

R1–R0

Chip Select Unit 5-7

Bits 11–8: Reserved—Set to 1.

Bit 7: Disable Addre ss (DA)—The DA bit enables or disables th e AD15–AD0 bus during

the address phase of a bus cycle when LCS is asserted. If DA is set to 1, AD15–AD0 is

not driven during the address phase of a bus cycle when LCS is asserted. If DA is set to

0, AD15–AD0 is driven duri ng the address phase of a bus cycle. Disabling AD15–AD0

reduces power consumption.

Note: On the Am188EM microcontroller, the AO15–AO8 address pins are driven during

the data phase of the bus cycles, even when the DA bit is set to 1 in either the Upper

Memory Chip S elect register (UMCS) or the Low Memory Chip Select register (LMCS).

If BHE/ADEN (on the Am186EM) or RFSH2/ADEN (on the Am188EM) is held Low on the

rising edge of RES, then AD15– A D0 is always driven regardless of the DA setting. This

configures AD15–AD0 to be enabled regardless of the setting of DA.

If BHE/ADEN (on the Am186EM) or RFSH2/ADEN (on the Am188EM) is High on the rising

edge of RES, then the DA bit in the UMCS register and the DA bit in the LMCS register

control the AD15–AD0 disabling.

See the description s of the BHE/ADEN and RFSH2/ADEN pins in Chapter 3.

Bit 6: PSRAM Mode Enable (PSE)—The PSE bit is used to enable PSRAM support for

the LCS chip select memory space. Wh en PSE is set to 1, PSRAM support is enabl ed.

When PSE is set to 0, PSRAM support is disabled. The refresh control unit registers

EDRAM, MDRAM, and CDRAM, must be confi gured for auto refresh before PSRAM

support is enabl ed.

Bits 5–3: Reserved—Set to 1.

Bit 2: Ready Mode (R2)—The R2 bit is used to configure the ready mode for the LCS chip

select. If R2 is set to 0, external ready is required. If R2 is set to 1, external ready is ignored.

In each case, the processor also uses the value of the R1–R0 bits to determine the number

of wait states to insert.

Bits 1–0: Wait-State Value (R1–R0)—The value of R1–R0 determines the number of wait

states inserted into an access to the LCS memory area. From zero to three wait states can

be inserted (R1–R0 =00b to 11b).

Chip Select Unit

5-8

5.5.3 Midrange Memory Chip Select Regi ster ( MMCS, Offset A6h)

The Am186EM and Am188EM microcontrollers provide four chip select pins, MCS3–MCS0,

for use withi n a user-locatable memory block. The base address of the memory block can

be located anywhere within the 1-Mbyte memory address space, ex clusive of the areas

associated with the UCS and LCS chip selects (and, if they are m apped to memory, the

address range of the Periphera l Chip Sele cts, PCS6–PCS5 and PCS3–PCS0). The MCS

address ra nge can over lap the PCS address range if the PCS chip sele cts are mapped to

I/O space.

The Midrange Memory Chip Selects are programmed through two registers. The Midrange

Memory Chip Select (MMCS) register (see Figure 5-3) determines the base address and

the ready condi tion and wait states of the memory bloc k accessed through th e MCS pins.

The PCS and MCS Auxiliary (MPCS) register is used to configure the block size. The

MCS3–MCS0 pins are not active on reset. Both the MMCS and MPCS registers must be

accessed with a read or wri te to activate these chip selects.

Unlike the UCS and LCS chip selects, the MCS3–MCS0 outputs assert with the multiplexed

AD address bus (AD15–AD0 or AO1 5–AO8 and AD7–AD0) rather than the earlier timing

of the A19– A0 bus. The A19–A0 bus can still be used f or address selec tion, but the t iming

is delayed for a half cycle later than tha t for UCS and L CS.

The Midrange Memory Chip Selects are configured by the MMCS register (Fig ure 5-3).

Figure 5-3 Midrange Memory Chip Select Register (MMCS, offset A6h)

The value of the MMCS register at reset is undefined.

Bits 15–9: Base Addre ss (BA19–BA13)—The base address of the memory block t hat is

addressed by the MCS chip select pins i s determined by the value of BA19–BA13. These

bits correspond to bits A19–A13 of the 20-bit memory address. Bits A12–A0 of the base

address are always 0.

The base address can be set to any integer multiple of t he size of the memory block size

selected in the MPCS register. For example, if the midrange block is 32 Kbytes, the block

could be located at 10000h or 18000h but not at 14000h.

The base address of the midrange chi p selects can be set t o 00000h only if the LCS chi p

select is not active. This is due to the fact that the LCS base address is defined to be

address 00000h and chip select address ranges are not allowed to overlap. Because of

the additional restriction that the base address must be a multiple of the block size, a 512K

MMCS block size can only be used when located at address 00000h, and the LCS chip

selects must not be active in this case. Use of the MCS chip selects to access low memory

allows the timing of these accesses to follow the AD address bus rather than the A address

bus. Locati ng a 512K MMCS block at 80000h always confli cts with the range of the UCS

chip select and is not allowed.

15 70

BA19–BA13 1 1 1111

R1–R0

Chip Select Unit 5-9

Bits 8–3: Reserved—Set to 1.

Bit 2: Ready Mode (R2)—The R2 bit is used to configure the ready mode for the MCS

chip selects . I f R2 is set to 0, ext er nal ready is req uir ed. If R2 is set t o 1, exte rnal r eady is

ignored. In each case, t he processor also uses the value of the R1–R0 bits to determine

the number of wait sta tes to insert.

Bits 1–0: Wait-State Value (R1–R0)—The value of R1–R0 determines the number of wait

states inserted into an access to the MCS memory area. From zero to three wait st ates

can be inserted (R1–R0 = 00b to 11b).

Chip Select Unit

5-10

5.5.4 PCS and MCS Auxiliary Register (MPCS, Offset A8h)

The PCS and MCS Auxiliary (MPCS) register (see Figure 5-4) differs from the other chip

select control registers in that it contains fields that pertain to more than one type of chip

select. The MPCS r egister fields prov ide program informati on for MCS3–MCS0 as well as

PCS6–PCS5 and PCS3–PCS0.

In additi on to its function as a chip select control register, the MPCS register contains a

field that configures the PCS6–PCS5 pins as either chip selects or as alternate sources for

the A2 and A1 address bits . When programmed to provide addr ess bits A1 and A2, PCS6–

PCS5 cannot be used as peripheral chip selects. These outputs can be used to provide

latched address bits for A2 and A1.

On reset, PCS 6–PCS5 are not active. If PCS 6–PCS5 are configured as address pins, an

access to th e MPCS re gister cau ses the pin s to ac tivat e. No corre sponding a ccess to the

PACS register is requi red to acti vate the PCS6–PCS5 pins as addresses.

Figur e 5-4 PCS and MCS Auxiliary Register (MPCS, off set A8h )

The value of the MPCS register at reset is undefined.

Bit 15: Reserved—Set to 1.

Bits 14–8: MCS Block Size (M6–M0)—This field deter m ines the total block size for the

MCS3–MCS0 chip selec ts. Each individua l chip select is act ive for one quarter of the total

block size. The size of the m emory block defined is shown in Table 5-4.

Only one of the M6–M0 bits can be set at any time. If more t han one of the M6–M0 bi ts is

set, unpredictable operation of the MCS lines occu rs.

Table 5-4 MCS Block Size Programming

Total Block

Size Individual

Select Size M6–M0

8K 2K 0000001b

16K 4K 0000010b

32K 8K 0000100b

64K 16K 0001000b

128K 32K 0010000b

256K 64K 0100000b

512K 128K 1000000b

15 70

M6–M0

1111

R1–R0

Chip Select Unit 5-11

Bit 7: Pin Selector (EX)—This bit determines whether the PCS6–PCS5 pins are configured

as chip selects or as alternate outputs for A2–A1. When this bit is set to 1, PCS6–PCS5

are configured as peripheral chip select pins. When EX is set to 0, PCS5 becomes address

bit A1 and PCS6 becomes address bit A2.

Bit 6: Memory/ I/O Space Selector (MS)—This bi t dete rmines whether the PCS pins are

active du ring memory bus c ycles or I /O bus cycles . When MS is set to 1, t he PCS out puts

are acti ve for memory bus cycl es. When MS is set to 0, the PCS outputs ar e active f or I/O

bus cycles.

Bits 5–3: Reserved—Set to 1.

Bit 2: Ready Mode (R2)—This bit applies only to the PCS6–PCS5 chip selects. If R2 is

set to 0, external ready is required. If R2 is set to 1, external ready is ignored. In each case,

the processor also uses the value of the R1–R0 bits to determine the number of wait states

to insert.

Bits 1–0: Wait-State Value (R1–R0)—These bits apply only to the PCS6–PCS5 chip

selects. The value of R1–R0 determines the number of wait states i nserted into an access

to the PCS memory or I/O area. From zero to three wait states can be inserted

(R1–R0 = 00b to 11b).

Chip Select Unit

5-12

5.5.5 Periphe ral Chip Select Regi ster (PACS, Offset A4h)

Unlike the UCS and LCS chip sele cts, the PCS output s assert with the same t iming as the

multiplexed AD address bus. Also, each peripheral chip select asserts over a 256-byte

address range, which is twi ce the address range covered by peripheral chi p selects in the

80C186 and 80C188 microcontrollers.

The Am186EM and Am188EM microcontrollers provide six chip selects, PCS6–PCS5 and

PCS3–PCS0, for use within a user-locatable memory or I/O block. (PCS4 is not

implemented on the Am186EM and Am 188EM microcontrollers.) The base address of the

memory block can be located anywhere within the 1-Mbyte memory address space,

exclusi ve of the areas ass o ciated with the UCS, LCS, and MCS chip selects, or they can

be configured to access the 64-Kbyte I/O space.

The Periph eral Chip Sel ects ar e programmed t hro ugh two regi sters —the Per iphera l Chip

Select (PACS) register and the PCS and MCS Auxiliary (MPCS) register. The Peripheral

Chip Select (PACS) register (Figure 5-5) determines the base address, the ready condition,

and the wait states for the PCS3–PCS0 outputs.

The PCS and MCS Auxiliary (MPCS) register ( see Figure 5-4) contains bits that conf igure

the PCS6–PCS5 pins as either chip sel ect s or address pi ns A1 and A2. When the PCS 6–

PCS5 pins are chip selects, the MPCS register also determines whet her PCS chip selects

are active duri ng memory or I/O bus cycles and specif ies the ready and wait states for the

PCS6–PCS5 outputs.

The PCS pins are not active on reset. Both the PACS and MPCS registers must be accessed

with a read or write to activa te the PCS pins as chip selects.

PCS6–PCS5 can be configured and activated as address pins by writing only the MPCS

PCS3–PCS0 can be configured for zero wait states t o 15 wait states. PCS6–PCS5 ca n be

configur ed for zero wait states to three wait states.

Figur e 5-5 Peripheral Chip Select Register (PACS, offset A4 h)

The value of the PACS register at reset is undefined.

Bits 15–7: Base Address (BA19–BA11)—The base address of the peripheral chip select

block is defined by BA19–BA11 of the PACS register. BA19–BA11 correspond to bits

19–11 of the 20-bit programmable base address of the peripheral chip se lect block. Bit 6

of the PACS register corresponds to bit 10 of the base address in the 80C186 and 80C188

microcontrollers, and is not implemented. Thus, code previously written for the 80C186

microcontroller in which bit 6 was set with a meaningful value would not produce the address

expected on the Am186EM.

When the PCS chip selects are mapped to I/ O space, BA19–16 must be programmed to

0000b because the I/O address bus is only 16-bits wide.

15 70

BA19–BA11 1 11

R1–R0

Chip Select Unit 5-13

Table 5-5 PCS Address Ranges

Bits 6–4: Reserved—Set to 1.

Bit 3: Wait -State Valu e (R3)—If thi s bit i s set to 0, the number of wait st ates from zero t o

three is enc oded in the R1–R0 bits. In this case, R1–R0 encodes from zero (00b) to three

(11b) wait states.

When R3 is set to 1, the four possible values of R1–R0 encode four additi onal wait-state

values as follows: 00b = 5 wait states, 01b = 7 wait states, 10b = 9 wait states, and

11b = 15 wait states. Table 5-6 shows the wait-state encoding.

Table 5-6 PCS3–PCS0 Wait- Stat e E nco di ng

Bit 2: Ready Mode (R2)—The R2 bit is used to configure the ready mode for the PCS3–

PCS0 chip selects. If R2 is set to 0, external ready is required. External ready is ignored

when R2 is set t o 1. In each case, the processor a lso uses the value of the R3 and R1–R0

bits to determine the number of wait stat es to insert. The ready mode for PCS6–PCS5 is

configured through the MPCS register.

Bits 1–0: Wait-State Value (R1–R0)—The value of R3 and R1–R0 determines the number

of wait states inserted into a PCS3–PCS0 access. Up to 15 wait states can be inserted.

See the discussi on of bit 3 (R3) for the wait-state encodi ng o f R1–R0.

From zero to three wait states for the PCS6–PCS5 outputs are programmed through the

R1–R0 bits in the MPCS register.

PCS Line Range

Low High

PCS0 Base Address Base Address+255

PCS1 Base Address+256 Base Address+511

PCS2 Base Address+512 Base Address+767

PCS3 Base Address+768 Base Address+1023

Reserved N/A N/A

PCS5 Base Address+1280 Base Address+1535

PCS6 Base Address+1536 Base Address+1791

R3 R1 R0 Wait States

0 0 0 0

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 5

1 0 1 7

1 1 0 9

111 15

Chip Select Unit

5-14

Refresh Control Unit 6-1

CHAPTER

6REFRESH CONTROL UNIT

6.1 OVERVIEW

The Refresh Control Un it (RCU) automatically generates refresh bus cycles. After a

programmable period of t ime, the RCU generates a memory read request to the bus

interf ace unit. The RCU is fixed to three wait states for the PSRAM auto ref resh mode.

The Refresh Control Unit operates off the processor internal clock. If the power-save mode

is in effec t, the Refresh Control Uni t must be reprogrammed to reflect the new clock rate.

If the HLDA pin is active when a refresh request is generated (indicating a bus hold

conditi on), then the microcontroller deactivates t he HLDA pin in order to perf orm a refresh

cycle. The c ircuit external bu s master must remove the HOLD signal for at least one cl ock

to allow the refresh cycle to execute.

6.1.1 Memory Partitio n Register (MDRAM, Offset E0h)

Figure 6-1 Memory Partition Register (MDRAM, offset E0h)

The MDRAM register is set to 0000h on reset.

Bits 15–9: Refresh Base (M6–M0)—Upper bits corr esponding to address bits A19–A13

of the 20-bit memory refr esh address. Since these bit s are available only on the AD bus,

the AD bit must not be set in the LMCS register if the refresh control unit is used. When

using PSRAM mode, M6–M0 must be programmed to 0000000b.

These bits are cl eared to 0 at reset.

Bits 8–0: Reserved—Read back as 0.

15 70

M6–M0

RA19 RA13

000000000

Refresh Control Unit

6-2

6.1.2 Clock Pres caler Register (CDRAM, Offset E2h)

Figure 6-2 Clock Prescaler Register (CDRAM, offset E2h)

The CDRAM register is undefined on reset.

Bits 15–9: Reserved—Read back as 0.

Bits 8–0: Refresh Counter Reload Value (RC8–RC0)—Contains the value of the desired

clock count in terval between refre sh cycles. The counter value should not be set to less

than 18 (12h), oth e rwise there would never be sufficient bus cycles available fo r the

processor to execute code.

In powe r-save mode, the ref resh counter value must be adjusted to take into account the

reduced processor clock rate.

6.1.3 Enable RCU Register (EDRAM, Offset E4h)

Figure 6-3 Enable RCU Register (EDRAM, offset E4h)

The EDRAM register is set to 0000h on reset.

Bit 15: Enable RCU (E)—Enables the refr esh counter unit when set to 1. Clearing the E

bit at any time clears t he ref resh count er an d stops ref resh reques ts, but it does not res et

the refres h address. Set to 0 on reset .

Bits 14–9: Reserved—Read back as 0.

Bits 8–0: Refre sh Count (T8–T0)—This r ead-only fi eld contai ns the pr esent val ue o f the

down counter which tr iggers refresh requests.

15 70

000000 RC8–RC0

15 70

00000 T8–T0

Interrupt Control Unit 7-1

CHAPTER

7INTERRUPT CONTROL UNIT

7.1 OVERVIEW

The Am186EM and Am188EM microcontroll ers can receive interrupt requests from a

variety of sources, both internal and external. The internal interrupt controller arranges

these requests by priority and presents them one at a time to the CPU.

There are six external interrupt sources on the Am186EM and Am188EM microcontrollers—

five mask able interrupt p ins (I NT4–INT0) and the non-mask able interrupt ( NMI) pin. There

are six internal interrupt sources that are not connected to external pins—three timers, two

DMA channels, and the asynchronous serial port.

The Am186EM and Am188EM microcontrollers provide three interrupts that are not present

on the 80C 186 and 80C188 microcontrollers:

nINT4, an additi onal external interrupt pin that operates like the INT3–INT0 pins

nAn internal watchdog ti mer interrupt

nAn internal interrupt from the serial port

The INT4–INT0 interrupt request pins can be used as direct interrupt requests. If more

inputs are needed, INT3–INT0 can also be cascaded with an 82C59A-compatible external

interr upt control device. An external inter rupt controll er can be used as the sys tem master

by program ming the internal interrupt controller to operate in slave mode. In all cases,

nesting can be enabled that allows high priority interrupts to interrupt lower-priority interrupt

service routines.

7.1.1 Definitions of Interrupt Terms

The following definitions cover some of the terminology that is used in describing the

functio nality of the interrupt controller. Table 7-1 contai ns information regarding the

reserved interrupts.

7.1.1.1 Interrupt Type

An 8-bit interrupt type identifies each of the 256 possible interrupts.

Software exceptions, internal peripherals, and non-cascaded external interrupts supply the

interrupt type through the internal interrupt controller.

Cascaded external interrupts and slave-mode external interrupts get the interrupt type from

the external interrupt controller by means of interrupt acknowledge cycles on the bus.

Interrupt Control Unit

7-2

7.1.1.2 Interrupt Vector Table

The interrupt vector table is a memory area of 1 Kbyte beginning at address 00000h that

holds up to 256 four-byte a ddress pointers con taining the addre ss for the inter rupt service

routine f or each possible interrupt type. For each interru pt, an 8-bit inte rrupt type identifi es

the appropriate interrupt vector table entry.

Interrupts 00h to 1Fh are reserved. See Table 7-1.

The processor calculates the index to the interrupt vector table by shifting the interrupt type

left 2 bits (mult iplying by 4).

7.1.1.3 Maskable and Non-Maskable Interrupts

Interrupt types 08h through 1Fh are maskable. Of these, only 08h through 14h are actually

in use (se e Table 7-1 ). The maskable int errupts ar e enabled and d isabled by t he interrup t

enable flag (IF) in the processor status flags, but the INT command can execute any interrupt

regardless of the setting of IF.

Interrupt types 00h through 07h and all software interrupt s (the INT ins truction) are non-

maskable. The non-maskable interr upts are not affected by the setting of the IF flag.

The Am186EM and Am188EM microcontrollers provide two methods for masking and

unmaskin g the maskable i nterr upt source s. Each interr upt sourc e has an interru pt contr ol

If the Inte rrupt Mask register is written while interr upts are enabled, it is possible that an

interr upt could occur while the register is in an undefined state. This can cause interrupts

to be accepted even though they were masked both before and after the write to the Interrupt

Mask register. Therefore, the Interrupt Mask register should only be written when interrupts

are disabled. Mask bits in the individual interr upt control registers can be written while

interr upts are enabl ed, and there will be no erroneous interrupt operation.

7.1.1.4 Interrupt Enabl e Flag (IF)

The interrupt enable flag (IF) is part of the processor status flags (see section 2.1.1 on page

2-2). I f IF is set to 1, maskable i nterrupts are enabl ed and can cause processor i nterrupts.

(Individual maskable interrupts can still be disabled by means of the mask bit in each control

If IF is set to 0, all maskable interrupts are disabled.

The IF flag doe s not affect the NMI or software exception interrupts (int errupt types 00h to

07h), and it does not affect the execution of any interrupt through the INT instruction.

7.1.1.5 Interrupt Mask Bit

Each of the interrupt control registers for the maskable interrupts contains a mask bit (MSK).

If MSK is set to 1 for a particular interrupt, that interrupt is disabled regardless of the IF

setting.

7.1.1.6 Interrupt Priority

The column titled

Overall Priority

in Table 7-1 shows the fundamental priority breakdown

for the interrupts at power-on reset. The non-maskable interrupts 00h through 07h are

always prioritized ahead of the maskable interrupts.

The maskable interrupts can be reprioritized by reconfiguring the PR2–PR0 bits in the

interrupt control registers. The PR2–PR0 bits in all the maskable interrupts are set to priority

level 7 at power-on reset.

Interrupt Control Unit 7-3

7.1.1.7 Software Interrupts

Software interrupts can be initiated by the INT instruction. Any of the 256 possible interrupts

can be ini tiated by t he INT instruct ion. INT 21h causes an inter rupt to the vec tor located at

00084h in the inter rupt vector table. INT FFh causes an interrupt to the vector located at

003FCh in the interrupt vector table. Software interrupts are not maskab le and are not

affected by the setting of the IF flag.

7.1.1.8 Software Exceptions

A software exception interrupt occurs when an instruction causes an interrupt due to some

conditi on in the process or. Interrupt types 00h, 01h, 03h, 04h, 05h, 06h, and 07h are

software exc eption interrup ts. Software exceptions ar e not maskable and are not affec ted

by the setting of the IF flag.

Table 7-1 Am186EM and Am188EM Microcontroller Interrupt Types

Notes:

1. Interrupts generated as a result of an instruction execution.

2. Trace is performed in the same manner as 80C186 and 80C188.

3. An ESC opcode causes a trap. This is part of the 80C186 and 80C188 co-processor interface, which is not

supported on the Am186EM.

4. All three timers constitute one source of request to the interrupt controller. As such, they share the same priority

level with respect to other interrupt sources. However, the timers have a defined priority order among themselves

(2A>2B>2C).

5. The interrupt types of these sources are programmable in slave mode.

6. Not available in slave mode.

Interrupt Name Interrupt

Type Vector Table

Address EOI

Type Overall

Priority Related

Instructions Notes

Divide Error Exception 00h 00h N/A 1 DIV, IDIV 1

Trace Inter rupt 01h 04h N/A 1A All 2

Non-Maskable Interrupt (NMI) 02h 08h N/A 1B

Breakpoint Interrupt 03h 0Ch N/A 1 INT 3 1

INTO Detected Overflow Exception 04h 10h N/A 1 INTO 1

Array Bounds Exception 05h 14h N/A 1 BOUND 1

Unused Opcode Exception 06h 18h N/A 1 Undefined

Opcodes 1

ESC Opcode Exception 07h 1Ch N/A 1 ESC Opcodes 1, 3

Timer 0 Interrupt 08h 20h 08 2A 4, 5

Timer 1 Interrupt 12h 48h 08 2B 4, 5

Timer 2 Interrupt 13h 4Ch 08 2C 4, 5

Reserved for AMD Use 09h

DMA 0 Interrupt 0Ah 28h 0A 3 5

DMA 1 Interrupt 0Bh 2Ch 0B 4 5

INT0 Interrupt 0Ch 30h 0C 5

INT1 Interrupt 0Dh 34h 0D 6

INT2 Interrupt 0Eh 38h 0E 7

INT3 Interrupt 0Fh 3Ch 0F 8

INT4 Interrupt 10h 40h 10 9 6

Watchdog Timer Interrupt 11h 44h 11 9 6

Asynchronous Serial Port Interrupt 14h 50h 14 9 6

Reserved for AMD Use 15h–1Fh

Interrupt Control Unit

7-4

7.1.2 Interrupt Conditions and Sequence

Interrupts are generally serviced as follows.

7.1.2.1 Non-Maskable Interrupts

Non-maskable int errupts—the trace interrupt, the NMI interrupt, and soft ware interrupts

[both user -defined (INT) and software exc eptions]—are se rviced regardless of t he setting

of the interrupt enable flag (IF) in the pr ocessor status flags.

7.1. 2.2 Maskable Ha r dwa r e Interrupts

In order for maskabl e hardware interrupt requests to be serviced, the IF flag must be set

by the STI instruction, and the mask bit associated with each interrupt must be reset.

7.1.2.3 The Interrupt Request

When an interrupt is r equested, the interna l interrupt controll er verifies that the in terrupt is

enabled and that t here are no higher priori ty interrupt request s being serviced or pending.

If the interrupt request is granted, the interrupt controller uses the interrupt type (see Table

7-1) to access a vector from the interrupt vector table.

Each interrupt type has a four-byte vector available in the interrupt vector table. The interrupt

vector table is located in the 1024 bytes from 00000h to 003FFh. Each four-byte vector

consists of a 16-bit offset (IP) value and a 16-bit segment (CS) value. The 8-bit interrupt

type is shifted left 2 bit positions (multiplied by 4) to generate the index into the interrupt

vector table.

7.1.2.4 Interrupt Servic ing

A vali d interrupt trans fers execution to a new program location based on the vector in the

interr upt vector t able. The next instruct ion address ( CS:IP) and the processor status fl ags

are pushed onto the stack.

The inter rupt enable flag (IF) is clea red after the proce ssor status flags are pushed on t he

stack, dis abling maskable interrupts during the interrupt service routine (ISR).

The segment:offset values from the interrupt vector table are loaded into the code segment

(CS) and the instruction pointer (IP), and execution of the ISR begins.

7.1.2.5 Returning from the Interrupt

The interrupt return (IRET) instruction pops the processor status flags and the return

address off the stack. Program execution resumes at the point where the interrupt occurred.

The interrupt enable flag (IF) is rest ored by the IRET instruction along with the rest of the

processor status flags. If the IF flag was set before the interrupt was serviced, inte rrupts

are re-enabl ed when the IRET is executed. If there are valid interrupts pending when the

IRET is executed, the instruction at the retu rn address is not executed. Instead, the new

interrupt is serviced immediately.

If an ISR intends t o permanently modify the v alue of any of the saved flags, it must modify

the copy of the Process or Status Flags register that was pushed onto th e stack.

Interrupt Control Unit 7-5

7.1.3 Interrupt Priority

Table 7-1 shows t he predefi ned typ es and overa ll pr ior ity stru cture for t he Am186EM and

Am188EM microcontrollers. Non-maskable interrupts (interrupt types 0–7) are always

higher priority than maskable interrupts. Maskable interrupts have a programmable priority

that can override the default priorities relative to one another.

The levels of interrupt priorit y a re as follows:

nInte rrupt priority for non-mask able interrupts and software interrupts

nInterrupt priority for maskable hardware interrupts

7.1.3.1 Non-Maskable Interrupts and Software Interrupt Priority

The non-maskable int errupts from 00h to 07h and software int errupts (INT instruction )

always take pr iority over the maskable har dware interr upts. Withi n the non-maskable and

software interrupts, the trace interrupt has the highest priority, followed by the NMI interrupt,

followed by th e remaining non-maskable and soft ware interrupts.

After the trace interrupt and the NMI interrupt, the remaining software exceptions are

mutually exc lusive and can only occur one at a time, so there is no furt her priority

breakdown.

7.1.3.2 Maskable Hardware Interrupt Priority

Beginning with interrupt type 8 (the Timer 0 interrupt), the maskable hardware interrupts

have both an overall priority (see Table 7-1) and a programmable priori ty. The

programmable priority is the primary priority for maskable hardware interrupts. The overall

priority is the secondary prior ity for maskable hardware interrupts.

Since all maskable interrupts are set to a programmable priorit y of seven on reset , the

overall priority of the interrupts determines the priority in which each interrupt is granted by

the interrupt controller until programmable priorities are changed by reconfiguring the

control registers.

The overall priority levels shown in Table 7-1 are not the same as the programmable priority

level that is associated with each maskable hardware interrupt. Each of the maskable

hardware interrupts has a programmable priority from zero to seven, with zero being the

highest pri ority (see Table 7-3 on page 7-14).

For example, if the INT4–INT0 inter rupts are all ch anged to programmable pri ority six and

no other programmable priorities are changed from the reset value of seven, then the INT4–

INT0 interrupts take precedence over all other maskable interrupts. (Within INT4–INT0,

INT0 takes precedence over INT1, and INT1 takes precedence over INT2, etc., because

of the underlying hierarchy of the overall priority.)

Interrupt Control Unit

7-6

7.1.4 Software Exceptions, Traps, and NMI

The following predefined interrupts cannot be masked by programming.

7.1.4.1 Divide Error Exception (Interrupt Type 00h)

Generated when a DIV or I DIV inst ructi on qu otient cannot be ex pressed i n th e number of

destination bits.

7.1.4.2 Trace Interrupt (Interrupt Type 01h)

If the trac e flag (TF) in the Processor Status flags register is set, the trace interrupt is

generated aft er most instructions. This inter rupt allows programs to execute i n single-step

mode. The interr upt is not generated after pref ix instructions like REP, instr uctions that

modify segment registers like POP DS, or the WAIT instruction.

Taking the trace interrupt clears the TF bit after the processor status flags are pushed onto

the stack. The IRET instruction at the end of the single step interrupt service routine restores

the processor status flags (and the TF bit) and trans fers control to the next instruction to

be traced.

Trace mode is initiated by pushing the processor status flags onto the stack, setting the TF

flag on the stack, and then popping the flags .

7.1.4.3 Non-Maskable Interrupt—NMI (Interrupt Type 02h)

The NMI pin provides an external interrupt source that is serviced regardless of the state

of the IF (int errupt enable flag) bit . No external interrupt acknowledge sequence is

performed for an NMI interrupt (see section 7.1.5). A typical use of NMI is to activate a

power failure routine.

7.1.4.4 Breakpoint Interrupt (Interrupt Type 03h)

An interrupt caused by the 1-byte version of the INT instruction (INT3).

7.1.4.5 INTO Detected Overflow Exception (Interrupt Type 04h)

Generated by an INTO instruction if the OF bit is set in the Processor Status Flags (FLAGS)

7.1.4 .6 Array BOUNDS Exceptio n (Interrupt Type 05h)

Generated by a BOUND instruction if the array index is outside the array bounds. The array

bounds are located in memory at a location indicated by one of the instruction operands.

The other operand indicates the value of the index to be checked.

7.1.4.7 Unused Opcode Exception (Interrupt Type 06h)

Generated if execution is attempted on undefined opcodes.

7.1. 4.8 ESC Opcode Ex ception (Inte r r up t Type 07h)

Generated i f execution of ESC opcodes ( D8h–DFh) is attempte d. The microcontrol lers do

not check the escape opcode trap bit. The return address of this exception points to the

ESC instruct ion that caused the exception . If a segment override prefix preceded the ESC

instruction, the return address points to the segment override prefix.

Note: All numeric coprocessor opcodes cause a trap. The Am186EM and Am188EM

microcontrollers do not support the num eric coprocessor interface.

Interrupt Control Unit 7-7

7.1.5 Interrupt Acknowledge

Interrupts can be acknowledged in two different ways—the internal interrupt controller can

provide t he int errupt type or an extern al i nterr upt control ler can pr ovide t he inte rr upt type.

The processor requires the interrupt type as an ind ex into the interrupt vector table.

When the internal interrupt controller is supplying the interrupt type, no bus cycles are

generated. The only external i ndication that an i nterrupt is bei ng serviced is t he processor

reading the interrupt vector table.

When an external interrupt controller is supplying the interrupt type, the processor

generates two interrupt acknowledge bus cycles (see Figure 7 -1) . The interrupt type is

written to the AD7–AD0 lines by the external interrupt controller during the second bus cycle.

Interrupt acknowledge bus cycles have the following characteristics:

nThe two interr upt acknowledge cycles are internal ly locked. (There is no LOCK pin on

the Am186EM and Am188EM microcontrollers.)

nTwo idle states are always inserted between the two cycles.

nWait states are inser ted if READY is not retur ned to the processor.

Figure 7-1 External Interrupt Acknowledge Bus Cycles

Notes:

1. ALE is active for each INTA cycle.

2. RD is inactive.

T1 T2 T3 T4 T1 T2 T3 T4

S0–S2

INTA

Internal lock

Ti Ti

Interrupt

Acknowledge Interrupt

Acknowledge

AD7–AD0 Interrupt

Type

Interrupt Control Unit

7-8

7.1.6 Interrupt Controller Reset Conditions

On reset, the interrupt controller performs the following nine actions:

1. All special fully neste d mode (SFNM) bits are reset, implying full y ne sted mode.

2. All priori ty (PR) bits in the various control registers are set to 1. This places all sources

at the lowe st priority (level 7).

3. All level-t ri ggered mode (LTM) bits are reset to 0, result ing in edge-t riggered mode.

4. All interrupt in-service bit s are reset to 0.

5. All interrupt request bits are reset to 0.

6. All mask (MSK) bits are set to 1. All interrupts are masked.

7. All cascade (C) bit s are reset to 0 (non-cascade).

8. The interrupt priority mask is set to 7, allowing interrupts of all prio rities.

9. The interrupt controller is initialized to master mode.

Interrupt Control Unit 7-9

7.2 MASTER MODE OPERATION

This section describes master mode operation of the internal interrupt controller. See

section 7.4 on page 7-28 for a descr iption of slave mode operation.

Six pins are provided for external interrupt sources. One of these pins is NMI, the non-

maskable in terrupt. NMI is g enerally used f or unusual events li ke power failure. The other

five pins can be configured in any of the following ways:

nFully nested mode—five interrupt lines with inter nally-generated interrupt types

nCascade mode one—an interrupt line and interrupt acknowledge line pair with externally-

generated interrupt types, plus three interrupt input lines with internally-generated types

nCascade mode two—two pairs of interrupt and interrupt acknowledge lines with

externally-generated int errupt types, and one interrupt input line (INT4) with in ternally-

generated type

The basic modes of operation of the interrupt controller in master mode ar e similar to the

82C59A. The interrupt cont roller responds identically to internal interrupts in all three

modes, the difference is only in the interpretation of function o f the five external interrupt

pins. The interrupt controller is set into one of these modes by programming the correct

bits in the INT0 and INT1 control register s. The modes of interrupt controller operat ion are

fully nested mo de, cascade mode, special fully nest ed mod e , and polled mode.

7.2.1 Fully Nested Mode

In fully nested mode, five pins are used as direct interrupt requests as in Figure 7-2. The

interrupt types for these five inputs are generated internally. An in-service bit is provided

for every interrupt source. If a lower-priority device requests an interrupt while the in-service

bit (IS) is set for a higher priority interrupt, no interrupt is generated by the interrupt controller.

In additi on, if another inter rupt request occur s from the same interr upt source while the in -

service b it is set, no inte rrupt is generated by th e int errupt cont ro ller. This al lo ws inter rup t

service routines operating with interrupts enabled to be suspended only by interrupts of

equal or higher priority than the in-service interrupt.

When an interr upt service routine is completed, the proper IS bit must be reset by writing

the interrupt type t o the EOI register. This is required to allow subs equent interrupts from

this interrupt source and to allow servicing of lower-priority interrupts. A write to the EOI

from interrupt instruction.

Figur e 7-2 Ful ly Nested (Direct) Mode Int er rupt Con troller C onnections

Am186EM

or Am188EM

Microcontroller

INT1

INT3

Interrupt Source

INT2

INT0

INT4 Interrupt Source

Interrupt Control Unit

7-10

7.2.2 Cascade M ode

The Am186EM and Am188EM microcontrollers have five interrupt pins, two of which (INT2

and INT3) have dual functions. In fully nested mode, the five pins are used as direct interrupt

inputs and the cor responding interrupt types are generated internally. In cascade mode,

four of the five pins can be configured into interrupt input and dedicated acknowledge signal

pairs. INT0 can be configured with interrupt acknowledge INTA0 (INT2). INT1 can be

configured with interrupt acknowledge INTA1 (INT3).

External sour ces in cascade mode use exter nally gen erated interrupt types. When an

interrupt is acknowledged, two INTA cycles are initiated and the type is read into the

microcontroller on the second cycle (see section 7.1.5 on page 7-7). The capability to interface

to on e or t wo ex terna l 82C59 A progr ammable in terru pt con trol lers i s prov ided w hen t he in puts

are co nfigu red in c ascade mo de.

Figure 7-3 shows the interconnection for cascade mode. INT0 is an interrupt input interfaced

to one 82C59A, and INT2/INTA0 serves as the dedicated interrupt acknowledge signal to that

peripheral. INT1 and INT3/INTA1 are als o inte rface d to an 82C59A . Each inter rup t and

acknowledge pair can be selectively placed in the cascade or non-cascade mode by

programming the proper value into the INT0 and INT1 control registers. The dedicated

acknow ledge s igna ls elimin ate the need f or ext ernal lo gic to generat e INTA and device select

signals.

Cascade mode provides the capability to serve up to 128 external interrupt sources through

the use of external master and slave 82C59As. Three levels of priority are created, requiring

priori ty resolution in the microcontrol ler interrupt controller, the master 82C59As, and the

slave 82C59As. If an external interrupt is ser viced, one IS bit is set at each of these levels.

When the interr upt service routine is completed, up to three end-of-i nterrupt (EOI) register

writes must be issued by the program.

Figure 7-3 Cascade Mode Interrupt Controller Connections

Am186EM

or Am188EM

Microcontroller

82C59A

INT0 VCC

82C59A

VCC

INT1

82C59A

Interrupt Sources

INTA0

INTA1

INT4

Interrupt Control Unit 7-11

7.2.3 Special Fully Nested Mode

Speciall y fully ne sted mode is entered by setting the SFNM bit in the INT0 o r INT1 cont rol

registers. (See section 7.3.1 on page 7-13. ) It enables complete nesting with external

82C59A masters or multiple interrupts from the same ext ernal interrupt pin when not in

cascade mode. In this case, the ISRs must be re-entrant.

In full y nested mode, an interru pt request from an inter rupt source is not recogni zed when

the in-service bit for t hat source is set. In this case, if more tha n one interrupt source is

connected to an exter nal interrupt controller, all of the interrupts go through the same

Am186EM or Am188EM microcontroller interrupt request pin. As a result, if the external

interr upt controlle r receives a higher -priority i nterrupt, i ts interrupt i s not recognized by the

microcontroller until the in-service bit is reset.

In special full y nested mode, the microcontroller’s int errupt controller al lows the processor

to take inter rupts from an external pin regardless of the state of the in-service bit for an

interr upt source in order to allow multiple interr upts from a single pin . An in- service bit

continues t o be set, however, to inhibit interrupts from other lower-priority Am186EM or

Am188EM microcontroller interrupt sources.

In specia l fully nested mode with cascade mode, when a write is issued to th e EOI r egister

at the end of the inter rupt service rout ine, software polli ng of the IS register in the ext ernal

master 82C59A must determine if there is more than one IS bit set. If so , the IS bit in the

microcontroller remains acti ve and the next ISR is entered.

7.2.4 Opera tion in a Polled Envi ronment

To allow reading of t he Poll register informati on without setting the indicated in-servi ce bit,

the Am186EM and Am188EM microcontrollers provide a Poll Status register (Figure 7-15)

in addition to the Poll re gister. Poll register information is duplicat ed in the Poll Status

bit. These regis ters are located in two adjacent memory locations in the peripher al control

block.

The interrupt controller can be used in polled mode if int e rrupts are not desir ed. Wh en

polli ng, int err upts are di sabled and s oft ware poll s the int err upt cont roll er as requi red . The

interr upt controller is polled by reading the Poll Status register (Figure 7-15). Bi t 15 in the

Poll Status regi ster indicates to the processor th at an int e rrupt of high enough priori ty is

requesting service. Bits 4–0 indicate to the processor the interrupt type of the highest priority

source requesting service. After determining that an interrupt is pending, software reads

the Poll register (rather than the Poll Status register), which causes the in-service bit of the

highest priority source to be set.

7.2.5 End-of-Interrupt Write to the EOI Register

A program must write to the EOI register to reset the in-service (IS) bit when an interrupt

service routine is completed. There are two types of writes to the EOI register—specific

EOI and non-specific EOI (see secti on 7.3.14 on page 7-27).

Non-specific EOI does not specify which IS bit is to be reset. Instead, the interrupt controller

automatically resets the IS bit of the highest priority source with an active servi ce routine.

Specific EOI require s the progr am to se nd the int errupt t ype to th e inte rrupt con trolle r to indic ate

the source IS bit that is to be reset. Specific reset is applicable when interrupt nesting is possible

or when t he highest pr iority IS bit that was set does not be long to t he service rou tine in pr ogress.

Interrupt Control Unit

7-12

7.3 MASTER MODE INTERRUPT CONTROLLER REGISTERS

The inter rupt controller registers for master mode are shown in Ta ble 7-2. All the registers

can be read and written unless otherwise specified.

Registers can be redefined in slave mode. See section 7.4 on page 7-28 for detailed

information regarding slave mode register usage. On reset, the microcontroller is in master

mode. Bit 14 of the relocation register (see Figure 4-2) must be set to initiate slave mode

operation.

Table 7- 2 Interrupt Con troller R egisters in Master Mode

Offset Register

Mnemonic Register Name Associated

Pins Comments

3Ah I1CON INT1 Control INT1

38h I0CON INT0 Control INT0

3Eh I3CON INT3 Control INT3

3Ch I2CON INT2 Control INT2

40h I4CON INT4 Control INT4

36h DMA1CON DMA1 Interrupt Control DRQ1

34h DMA0CON DMA0 Interrupt Control DRQ0

32h TCUCON Timer Interrupt Control TMRIN1

TMRIN0

TMROUT1

TMROUT0

42h WDCON Watchdog Timer Interrupt Control

44h SPICON Serial Port Interrupt Control TXD, R X D

30h INTSTS Interrupt Status

2Eh REQST Interrupt Request INT4–INT0

DRQ1–DRQ0 Read-only register

2Ch INSERV In-Service INT4–INT0

DRQ1–DRQ0

2Ah PRIMSK Priority Mask

28h IMASK Interrupt Mask INT4–INT0

DRQ1–DRQ0

26h POLLST Poll Status Read-only register

24h POLL Poll Read-only register

22h EOI End of Interrupt Write-only register

Interrupt Control Unit 7-13

7.3.1 INT0 and INT1 Contr ol Register s

(I0CON, Offset 38h, I1CON, Offset 3Ah)

(Master Mode)

The INT0 interrupt is assigned to interrupt type 0Ch. The INT1 interrupt is assigned to

interr upt type 0Dh.

When cascade mode is enabled for INT0 by setting the C bit of I0CON to 1, the INT2 pin

becomes INTA0, t he interrupt acknowledge for INT0 .

When cascade mode is enabled for INT1 by setting the C bit of I1CON to 1, the INT3 pin

becomes INTA1, t he interrupt acknowledge for INT1 .

Figure 7-4 INT0 and INT1 Control Registers (I0CON, I1CON, offsets 38h and 3Ah)

The value of I0CON and I1CON at reset is 000Fh.

Bits 15–7: Reserved—Set to 0.

Bit 6: Speci al Fully Nested Mode (SFNM)—When set to 1, enables special fully nested

mode.

Bit 5: Cascade Mode (C)—When set to 1, this bit enables cascade mode.

Bit 4: Level-Tr iggered Mode (LTM)—T his bit determines whether the microcont roller

interprets an INT0 or INT1 interrupt request as edge- or level-sensitive. A 1 in this bit

configures INT0 or INT1 as an active High, level-sensitive interrupt. A 0 in this bit configures

INT0 or INT1 as a Low-to-High, edge-triggered interrupt. In either case, INT0 or INT1 must

remain High unti l they are acknowledged.

Bit 3: Mask (MSK)—This bit determines whether the INT0 or INT1 signal can cause an

interr upt. A 1 in thi s bit masks this i nterr upt source, pr eventing INT0 or I NT1 from causing

an interrupt. A 0 in this bit enables INT0 or INT1 interrupts.

This bit is duplicated in the Interrupt Mask register. See the Interrupt Mask register in section

7.3.11 on page 7-24.

Bits 2–0: Priority Level (PR2–PR0)— This field determines the priority of INT0 or INT1

relati ve to the other interrupt signals, as shown in Table 7-3 on page 7-14.

15 70

Reserved

PR2

PR1

PR0

MSK

LTM

SFNM

Interrupt Control Unit

7-14

Table 7-3 Priority Level

Priority PR2–PR0

(High) 0 0 0 0b

1 0 0 1b

2 0 1 0b

3 0 1 1b

4 1 0 0b

5 1 0 1b

6 1 1 0b

(Low) 7 1 1 1b

Interrupt Control Unit 7-15

7.3.2 INT2 and INT3 Contr ol Register s

(I2CON, Offset 3Ch, I3CON, Offset 3Eh)

(Master Mode)

The INT2 interr upt is assigned to interrupt type OEh. The INT3 interrupt is assi gned to

interr upt type 0Fh.

The INT2 and INT3 pins can be configured as interrupt acknowledge pins INTA0 and INTA1

when cascade mode is implemented.

Figur e 7-5 INT2 and INT3 Control Registers (I2CON, I3CON, off sets 3Ch and 3Eh)

The value of I2CON and I3CON at reset is 000Fh.

Bits 15–5: Reserved—Set to 0.

Bit 4: Level-Tr iggered Mode (LTM)—T his bit determines whether the microcont roller

interprets an INT2 or INT3 interrupt request as edge- or level-sensitive. A 1 in this bit

configures INT2 or INT3 as an active High, level-sensitive interrupt. A 0 in this bit configures

INT2 or INT3 as a Low-to-High, edge-triggered interrupt. In either case, INT2 or INT3 must

remain High unti l they are acknowledged.

Bit 3: Mask (MSK)—This bit determines whether the INT2 or INT3 signal can cause an

interr upt. A 1 in thi s bit masks this i nterr upt source, pr eventing INT2 or I NT3 from causing

an interrupt. A 0 in this bit enables INT2 or INT3 interrupts.

This bit is duplicated in the Interrupt Mask register. See the Interrupt Mask register in section

7.3.11 on page 7-24.

Bits 2–0: Priority Level (PR2–PR0)— This field determines the priority of INT2 or INT3

relati ve to the other interrupt signals, as shown in Table 7-3 on page 7-14.

15 70

Reserved

PR2

PR1 PR0

MSK

LTM

Interrupt Control Unit

7-16

7.3.3 INT4 Control Register (I4CON, Offset 40h)

(Master Mode)

The Am186EM and Am188EM microcontrollers provide INT4, an additional external

interr upt pin. This input behaves like INT3–INT0 on the 80C186/188 microcontroller with

the exception that INT4 is only intended for use as a nested-mode interrupt source.

This interrupt is assigned to interrupt type 10h. The Interrupt 4 Control register (see Figure

7-6) controls the operation of the INT4 signal.

Figure 7-6 INT4 Control Register (I4CON, offset 40h)

The value of I4CON at reset is 000Fh.

Bits 15–5: Reserved—Set to 0.

Bit 4: Level-Tr iggered Mode (LTM)—T his bit determines whether the microcont roller

interprets an INT4 interrupt request as edge- or level-sensitive. A 1 in this bit configures

INT4 as an active High, level-sensitive interrupt. A 0 in this bit configures INT4 as a Low-

to-High, edge-triggered interrupt. In either case, INT4 must remain High until it is

acknowledged.

Bit 3: Mask (MSK)—This bit determ ines whether the INT4 signal can cause an interrupt.

A 1 in this bit masks this interrupt source, prevent ing INT4 from causing an int e rrupt. A 0

in this bit enables INT4 inte rrupts.

This bit is duplicated in the Interrupt Mask register. See the Interrupt Mask register in section

7.3.11 on page 7-24.

Bits 2–0: Priority (PR)—This field det ermines the priority of INT4 r e lative to the other

interr upt signals, as shown in Table 7-3 on page 7-14.

15 70

MSK

LTM

Reserved

PR2

PR1

PR0

Interrupt Control Unit 7-17

7.3.4 Timer and DMA In terrupt Control Register s

(TCUCON, Offset 32h, DMA0CON, Offset 34h, DMA1CON,

Offset 36h)

(Master Mode)

The three t imer int errupts ar e assigned to inter rupt type 08 h, 12h, and 13h. All three timer

interr upts are configured through TCUCON, offset 32h. The DMA0 interrupt is assigned t o

interr upt type 0Ah. The DMA1 interrupt is assigned to int errupt type 0 Bh .

Figure 7-7 Timer/DMA Interrupt Control Registers (TCUCON, DMA0CON, DMA1CON,

offsets 32h, 34h, and 36h)

The value of TCUCON, DMA0CON, and DMA1CON a t reset is 000Fh.

Bits 15–4: Reserved—Set to 0.

Bit 3: Inter rupt Mask (MSK)—This bit determines whether t he corresponding signal can

generate an interrupt. A 1 masks this interrupt source. A 0 enables the corresponding

interrupt.

This bit is duplicated in the Interrupt Mask register. See the Interrupt Mask register in section

7.3.11 on page 7-24.

Bits 2–0: Pri ority Leve l (PR2–PR0)—Sets the pri ority le vel for its corresp onding sourc e.

See Table 7-3 on page 7-14.

15 70

000 000 000000

PR2

PR1

PR0

MSK

Interrupt Control Unit

7-18

7.3.5 Watchdog Timer Interrupt Control Regi ster (W DCON, Offset 42h)

(Master Mode)

The Am186EM and Am188EM microcontroll ers provide an additional on-chip interrupt

source, the watchdog timer. This timer is constructed from existing 80C186 microcontroller

pins. It is implemented by connecting the TMROUT1 output to an additional internal interrupt

to creat e the watchdog t imer interrupt. This i nterrupt is assigned to i nterrupt ty pe 11h. The

control register format is shown in Figur e 7-8.

The systems programmer should program the timer (s ee section 8.2.2 on page 8-3) and

then program the interrupt pin.

Figure 7-8 Watchdog Timer Interrupt Control Register (WDCON, offset 42h)

The value of WDCON at reset is 000Fh.

Bits 15–5: Reserved—Set to 0.

Bit 4: Reserved—

Must

be set to 0 to ensure proper operation of the Am186EM and

Am188EM microcontrollers.

Bit 3: Mask (MSK)—This bit determines whether the watchdog timer can cause an interrupt.

A 1 in this bit masks t hi s inter rupt sour ce, prev enting t he watchdog t imer fr om causing an

interr upt. A 0 in this bit enabl es watchdog timer interrupts.

This bit is duplicated in the Interrupt Mask register. See the Interrupt Mask register in section

7.3.11 on page 7-24.

Bits 2–0: Priority (PR)—This field det ermines the priority of the watchdog timer relative

to the other interrupt signals, as shown in Table 7-3 on page 7-14.

15 70

Reserved

MSK

PR2PR1PR0

Interrupt Control Unit 7-19

7.3.6 Serial Port Interrupt Control Register (SPICON, Offset 44h)

(Master Mode)

The Serial Port Int errupt Control regist er controls the operation of the asynchronous serial

port interrupt source (SPI, bit 10 in the Interrupt Request register). This interrupt is assigned

to interrupt type 14h. The control register format is shown in Figure 7-9.

Figure 7-9 Serial Port Interrupt Control Register (SPICON, of fset 44h)

The value of SPICON at reset is 001Fh.

Bits 15–5: Reserved—Set to 0.

Bit 4: Reserved—Set to 1.

Bit 3: Mask (MSK)—This bi t determin es whether the ser ial p ort can cause an i nterrupt . A

1 in this bit masks this interrupt source, preventing the serial port from causing an interrupt.

A 0 in this bit enabl es serial port interrupts.

This bit is duplicated in the Interrupt Mask register. See the Interrupt Mask register in section

7.3.11 on page 7-24.

Bits 2–0: Pri ority (PR2–PR0)— T h is f ie l d d et e r mi n e s the priority of the serial port relative to

the other interrupt signals. After a reset, the priority is 7. See Table 7-3 on page 7-14.

15 70

MSK

Res

Reserved 1

PR2

PR1

PR0

Interrupt Control Unit

7-20

7.3.7 Interrupt Status Register (INTSTS, Offset 30h)

(Master Mode)

The Interrupt Status (INTSTS) regi ster indicates the interrupt request stat us of the three

timers.

Figure 7-10 Interrupt Stat us Register (INTSTS, offset 30h)

Bit 15: DMA Halt (DHLT)—When set to 1, halts any DMA activity. This pin is automatically

set to 1 when non-maskable interrupts occur and is reset when an IRET instruction is

executed. Ti me-c riti cal sof twar e, su ch as inter ru pt handler s, can modif y th is b it dir ectly to

inhibit DMA transfers. Because of the function of this register as an interrupt request register

for the ti mers, the DHLT bit should not be modified by software wh en ti mer interrupts are

enabled.

Bits 14–3: Reserved

Bits 2–0: Timer Int errupt Request (TMR2–TMR0)—When set to 1, these bits indi cate

that the corresponding timer has an inter rupt request pending. (Note that the timer TMR

bit in the REQST register is the OR of these timer interr upt requests.)

15 70

Reserved

TMR2

TMR1

TMR0

DHLT

Interrupt Control Unit 7-21

7.3.8 Interrupt Request Register (REQST, Offset 2Eh)

(Master Mode)

The hardware inter rupt sources have interrupt request bits inside the interrupt controll er.

A read from thi s register yields the status o f these bits. The Inter rupt Request regi ster is a

read-only register. The format of the REQST register is shown in Figure 7-11.

The Am186EM and Am188EM microcontroll ers define th ree new bits to report t he state of

INT4, the Watchdog Timer , and the asynchronous serial port.

For int ernal interrupts (SPI, WD, D1, D0, and TMR), the c orresponding bit i s set to 1 when

the device reques ts an interrupt. The bit is reset durin g the int ernally generated interrupt

acknowledge.

For INT4–INT0 ex ter nal int errupt s, the c orr esponding bi t (I 4–I0) r eflect s the cur rent val ue

of the exter nal signal. The device must hold this signal High unti l the interrupt is serviced.

Generally the interrupt service routine signals the exte rnal device to remove the interrupt

request.

Figur e 7-1 1 Inter r up t Requ est R egister (REQST, offs et 2Eh)

The REQST register is undefined on reset.

Bits 15–11: Reserved

Bit 10: Serial Port Int errupt Request (SPI)—This bit indicates the inter rupt state of the

serial port. If enabled, the SPI bit is the logical OR of all possible serial port interrupt sources

(THRE, RDR, BRKI, FER, PER, and OER status bits ).

Bit 9: Watchdog Timer Interrupt Request (WD)—When this bit is set to 1, the Watchdog

Timer has an inter rupt pending.

Bits 8–4: Interrupt Requests (I4–I0)—When set to 1, the corresponding INT pin has an

interr upt pending (i.e., when INT0 is pending, I0 is set). These bit s reflect the status of the

external pin.

Bits 3–2: DMA Channel Interr upt Request (D1– D0)—When set to 1, the corr esponding

DMA channel has an interrupt pending.

Bit 1: Reserved

Bit 0: Timer Interrupt Request (TMR)—This bit indicates the state of the timer interrupts.

This bit is the l ogical OR of the t imer int errupt req uests. When se t to a 1, thi s bit i ndicat es

that the timer control unit has an interrupt pending.

The Interrupt Status register indicates the specific timer that is requesting an interrupt. See

section 7.3.7.

15 70

Reserved

ResTMRD0

SPI

Interrupt Control Unit

7-22

7.3.9 In-Service Register (INSERV, Offset 2Ch)

(Master Mode)

The Am186EM and Am188EM microcontrollers define three new bits to report the in-service

state of INT4, the Vir tual Wat chdog Timer, and the asynchronous serial port. The form at

of the modifi ed In-Service register is shown in Figure 7-12.

The bits in the INSERV register are set by the i nterrupt controller when the interrupt is

taken. Each bit in the register is cleared by wri ting the correspondi ng interrupt type to the

End-of-I nterrupt (EOI) register. See Table 7-1 on page 7-3.

When an in-servi ce bit i s set, the mi croc ontrol ler will not generate an i nterru pt re quest for

the associat ed source, preventing an interrupt from interrupting itself if interr upts are

enabled in the ISR. Special fully nested mode allows the INT1–INT0 requests to circumvent

this restriction for the INT0 and INT1 sources.

Figure 7-12 In-Service Register (INSERV, offset 2Ch)

The INSERV register is set to 0000h on reset.

Bits 15–11: Reserved

Bit 10: Serial Port Interrupt In-Service (SPI)—This bit indicates the in-service state of

the asynchronous serial port.

Bit 9: Watchdog Timer Interrupt In-Service (WD)—This bit indicates the in-service state

of the Watchdog Timer.

Bits 8–4: Interrupt In-Service (I 4–I0)—These bits indicat e the in-service state of the

corresponding INT pin.

Bits 3–2: DMA Channel Interrupt In-Service (D1–D0)—These bits indicate the in-service

stat e of the corre spondi ng DMA cha nnel.

Bit 1: Reserved

Bit 0: Timer Interrupt In-Service (TMR)—This bit indicates the state of the in-service timer

interrupts. This bit is the logical OR of all the timer interrupt status bits. When set to a 1,

this bit indicates that the corresponding timer interrupt status bit is in-service.

15 70

Reserved

ResTMRD0

SPI

Interrupt Control Unit 7-23

7.3.10 Priority Mask Register (PRIMSK, Offset 2Ah)

(Master Mode)

The Priori ty Mask (PRIMSK) register provides the value that determines the minimum

priori ty level at which maskable in terru pts can generate an interrupt.

Figure 7-13 Priority Mask Register (PRIMSK, offset 2Ah)

The value of PRIMSK at reset is 0007h.

Bits 15–3: Reserved—Set to 0.

Bits 2–0: Priority Field Mask (PRM2–PRM0)—This field determines the minimum priority

that is required i n order for a mask able interrupt source to generate an interrupt. Mas kable

interr upts with programmable pri ority values th at are numeric ally higher than thi s field are

masked. The possible values are zero (000b) to seven (111b).

A value of seven (111b) allows all interrupt sources that are not maske d to generate

interrupts. A value of five (101b) allows only unmasked interrupt sources with a

programmable prio rity of zero to five (000b to 101b) to generate interrupts.

Table 7-4 Priority Level

Priority PR2–PR0

(High) 0 0 0 0b

1 0 0 1b

2 0 1 0b

3 0 1 1b

4 1 0 0b

5 1 0 1b

6 1 1 0b

(Low) 7 1 1 1b

15 70

000 000 000

000

PRM2

PRM1

PRM0

Interrupt Control Unit

7-24

7.3.1 1 Interrupt Mask Register (IMASK, Offset 28h)

(Master Mode)

The Am186EM and Am188EM microcontroll ers define three new bits to report the mask

state of the INT4 Control, Watchdog Timer Interrupt Control, and Serial Port Interrupt

Control registers.

The Interrupt Mask (IMASK) register is a read/write register. Programming a bit in the IMASK

registe r has the e ff ect of pr ogramming t he MSK bit i n th e assoc iated con trol r egist er. The

format of the IMASK register is shown in Figure 7-14.

Do not write to the interrupt mask register while interrupts are enabled. To modify mask

bits while interrupts are enabled, use the individual interrupt control registers.

Figur e 7-14 Interrupt Mask Register (IMASK, offset 28h)

The IMASK register i s set to 07FDh on reset.

Bits 15–11: Reserved

Bit 10: Serial Port Int errupt Mask (SPI)— When set to 1, this bit indicates that the

asynchronous serial port interrupt is masked.

Bit 9: Virtual Wat chdog Timer Interrupt Mask (WD)—When set to 1, this bit indica tes

that the Watchdog Timer interrupt is masked.

Bits 8–4: Interrupt Mask (I4–I0)—When set to 1, an I4–I0 bit indicates that the

corresponding interrupt is masked.

Bits 3–2: DMA Channel Interrupt Masks (D1–D0)—When set to 1, a D1–D0 bit indicates

that the corresponding DMA channel interrupt is masked.

Bit 1: Reserved

Bit 0: Timer Interrupt Mask (TMR)—When set to 1, this bit indicates that interrupt requests

from the timer contr ol unit are masked.

15 70

Reserved

ResTMR

SPI

Interrupt Control Unit 7-25

7.3.12 Poll Status Registe r (POLLST, Offset 26h)

(Master Mode)

The Poll Status (POLLST) register mirrors the current state of the Poll register. The POLLST

is read, the current interrupt is acknowledged and the next interrupt takes its place in the

Poll register.

Figure 7-15 Poll Status Register (POLLST, o ffset 26h)

Bit 15: Inter rupt Request (IREQ)—Set t o 1 if an inter ru pt is pendi ng. When thi s bit is set

to 1, the S4–S0 fiel d contains valid data.

Bits 14–5: Reserved—Set to 0.

Bits 4–0: Poll Status (S4–S0)—Indic ates the inte rrupt type of t he highest priority p ending

interrupt.

15 70

S4–S0

IREQ

Reserved

Interrupt Control Unit

7-26

7.3.13 Poll Register (POLL, Offset 24h)

(Master Mode)

When the Poll regi ster is read, t he current interrupt is acknowledged and the next interrupt

takes its place in the Poll register.

The Poll Status register mirrors the current state of the Poll register, but the Poll Status

Figure 7-16 Poll Register (POLL, offset 24h)

Bit 15: Inter rupt Request (IREQ)—Set t o 1 if an inter ru pt is pendi ng. When thi s bit is set

to 1, the S4–S0 fiel d contains valid data.

Bits 14–5: Reserved—Set to 0.

Bits 4–0: Poll Status (S4–S0)—Indic ates the inte rrupt type of t he highest priority p ending

interrupt. Reading the Poll register acknowledges the highest priority pending interrupt and

enables the next interrupt to advance into the register.

Although the IS bit is set, the interrupt service routine does not begin execution

automatically. The applicati on software must execute the appropriate ISR.

15 70

S4–S0

IREQ

Reserved

Interrupt Control Unit 7-27

7.3.14 End-of- Interrupt Register (EOI, Offse t 22h)

(Master Mode)

The End-of-Interrupt (EOI) register is a write-only register. Th e in-service flags in the In-

Service register (see section 7. 3.9 on page 7 -22) are reset by writing to the EOI register.

Before execut ing the IRET instr uction that ends an int errupt service ro utine (ISR), t he ISR

should write to the EOI register to reset the IS bit for the interrupt.

The specifi c EOI reset is th e most secure met hod to use for resetting IS bits. Figure 7-17

shows example code for a speci fic EOI res et. See Table 7-1 on page 7-3 for specif ic EOI

values.

Figure 7-17 Example EOI Assembly Code

Figur e 7-1 8 End-o f- Interrupt Regi ster (E O I, offset 22h)

Bit 15: Non-Specific EOI (NSPEC)—The NSPEC bit determines the type of EOI command.

When written as a 1, NSPEC indicates non-specific EOI. When written as a 0, NSPEC

indicates the specific EOI interrupt type in S4–S0.

Bits 14–5: Reserved

Bits 4–0: Source EOI Type (S4–S0)—Specifies the EOI type of the interrupt that is

currently being processed. See Table 7-1 on page 7-3.

...

... ;ISR code

...

mov dx, EOI_ADDR

exit: mov ax,int_type ;load the interrupt type in ax

out dx,ax ;write the interrupt type to EOI

popa

iret ;return from interrupt

15 70

S4–S0

NSPEC

Reserved

Interrupt Control Unit

7-28

7.4 SLAVE MODE OPERA TI ON

When slave mode is used, the microcont roller’s inte rnal interru p t controller is used as a

slave controller to an external master interrupt controller. The internal interrupts are

monitored by t he internal i nterrupt cont roller, wh ile the exter nal controll er functions as the

system master interrupt controller.

On reset, the microcontroller is in master mode. To activate slave mode operation, bit 14

of the relocat ion register must be set ( see Figur e 4-2 on page 4 -4) .

Because of pin l imitations caused by the need to interf ace to an external 82C59A master,

the internal interrupt controller does not accept external inputs. However, there are enough

interrupt controller inputs (internally) to dedicate one to each timer. In slave mode, each

timer interrupt sou rce has its own mask bit, IS bit, and control word.

The INT4, watchdog ti mer, and serial port int errupts are not availabl e in sl ave mode . In

slave mode, each peripheral must be assigned a unique priorit y to ensure pro per inter rupt

control ler operation. The prog rammer must assign correc t priorit ies and initial ize interrupt

control registers before enabl ing inter rupts.

7.4.1 Slave Mode Interrupt Nesting

Slave mode operati on all ows ne sting of interrupt requests. When an interrupt is

acknowledged, the priority logic masks off all priority levels except those with equal or higher

priority.

7.4.2 Slave Mode Interrupt Contro ller Registers

The Interr upt Controller Regist ers for slave mode are sh own in Table 7-5. All registers can

be read and written, unless specified otherwise.

Table 7-5 Interrupt Controller Registers in Slave Mode

Offset Register

Mnemonic Register Name Affect ed Pin s Comments

3Ah T2INTCON Timer 2 Interrupt Control Interrupt Type XXXXX101

38h T1INTCON Timer 1 Interrupt Control TMRIN1

TMROUT1 Interrupt Type XXXXX100

36h DMA1CON DMA 1 Interrupt Control Interrupt Type XXXXX011

34h DMA0CON DMA 0 Interrupt Control Interrupt Type XXXXX010

32h T0INTCON Timer 0 Interrupt Control TMRIN0

TMROUT0 Interrupt Type XXXXX000

30h INTSTS Interrupt Status

2Eh REQST Interrupt Request Read Only

2Ch INSERV In-Service Read Only

2Ah PRIMSK Priority Mask

28h IMASK Interrupt Mask

22h EOI Specific EOI Write Only

20h INTVEC Interrupt Vector

Interrupt Control Unit 7-29

7.4.3 Timer and DMA In terrupt Control Register s

(T0INTCON, Offset 32h, T1INTCON, Offset 38h, T2INTCON, Offset

3Ah, DMA0CON, Offset 34h, DMA1CON, Offset 36h)

(Slave Mode)

In slave mode, there ar e thr ee sepa rate regis ters f or the thr ee t imers. I n master mode, a ll

three timers are masked and prioritized in one register, TCUCON.

In slave mode, the two DMA control registers retain their functionality and addressing from

master mode.

Figure 7-19 Timer and DMA Interrupt Control Registers

(T0INTCO N, T1INTCON, T2INTCON, DMA0CON, DMA1CON,

offsets 32h, 38h, 3Ah, 34h, and 36h)

These regist ers are set to 000Fh on reset .

Bits 15–4: Reserved—Set to 0.

Bit 3: Mask (MSK)—This bit determines whether the interrupt source can cause an

interr upt. A 1 in t his bit masks the interrupt source , prev enting the source from causi ng an

interrupt. A 0 in t his bit enabl es interrupts from the source.

This bit is duplicated in the Interrupt Mask register. See the Interrupt Mask register in section

7.4.8 on page 7-34.

Bits 2–0: Priority Level (PR2–PR0)— This field determines the priority of the interrupt

source relative to the other in terrupt signals, as shown in Table 7-3 on page 7-14.

15 70

PR2PR1PR0

MSK

Reserved

Interrupt Control Unit

7-30

7.4.4 Interrupt Status Register (INTSTS, Offset 30h)

(Slave Mode)

The Interrupt Status regist er controls DMA activi ty when non-maskable interrupts occur

and indicates the current interrupt status of the three timers.

Figure 7-20 Interrupt Stat us Register (INTSTS, offset 30h)

The INTSTS register is set to 0000h on reset.

Bit 15: DMA Halt (DHLT)—When set to 1, halts an y DMA activity. Automat ically set to 1

when non-maskable int errupts occur and reset when an IRET instr u ction is executed.

Bits 14–3: Reserved

Bits 2–0: Timer Int errupt Request (TMR2–TMR0)—When set to 1, indicates the

corr espondi ng ti mer has an interr upt req uest pen ding.

15 70

Reserved

TMR2

TMR1

TMR0

DHLT

Interrupt Control Unit 7-31

7.4.5 Interrupt Request Register (REQST, Offset 2Eh)

(Slave Mode)

The internal interrupt sources have interrupt request bits inside the interrupt controller. A

read from this regi ster yields the status of these bits. The Int errupt Request register is a

read-only register. The format of the Interrupt Request register is shown in Figure 7-21.

For internal interrupts (D1, D0, TMR2, TMR1, and TMR0), the corresponding bit is set to

1 when the device requests an interrupt. The bit i s reset d uring the internal ly generated

interr upt acknowledge.

Figur e 7-2 1 Inter r up t Requ est R egister (REQST, offs et 2Eh)

The REQST register is set to 0000h on reset .

Bits 15–6: Reserved

Bits 5–4: Timer 2/Timer 1 Interrupt Request (TMR2–TMR1)—When set to 1, these bit s

indicate the state of any interrupt requests from the associated timer.

Bits 3–2: DMA Channel Interrupt Request (D1–D0)—When set to 1, D1–D0 indicate that

the corresponding DMA channel has an interrupt p ending.

Bit 1: Reserved

Bit 0: Timer 0 Interrupt Request (TMR0)—When set to 1, this bit indicates the state of

an interrupt request from Timer 0.

15 70

Reserved

TMR1

TMR2 Res

TMR0

Interrupt Control Unit

7-32

7.4.6 In-Service Register (INSERV, Offset 2Ch)

(Slave Mode)

The format of the In-Service register is shown in Figure 7-22. The bits in the In-Service

are cleared by writing to the End-of-I nterrupt (EOI) register.

Figure 7-22 In-Service Register (INSERV, offset 2Ch)

The INSERV register is set to 0000h on reset.

Bits 15–6: Reserved

Bits 5–4: Timer 2/Timer 1 Interrupt In-Service (TMR2–TMR1)—When set to 1, these bits

indicate that the corresponding timer interrupt is currently being serviced.

Bits 3–2: DMA Channel Interrupt In-Service (D1–D0)—When set to 1, the corresponding

DMA channel is currently being serviced.

Bit 1: Reserved

Bit 0: Timer 0 Interrupt In-Service (TMR0)—When set to 1, this bit indicates Timer 0 is

currently being serviced.

15 70

Reserved

TMR1

TMR2 Res

TMR0

Interrupt Control Unit 7-33

7.4.7 Priority Mask Register (PRIMSK, Offset 2Ah)

(Slave Mode)

The format of the Prior ity Mask register is shown i n Figure 7-23. The Priority Mask r egister

provides the value that determines the minimum priority level at which maskable interrupts

can generate an interrupt.

Figure 7-23 Priority Mask Register (PRIMSK, offset 2Ah)

The value of the PRIMSK register at reset is 0007h.

Bits 15–3: Reserved

Bits 2–0: Priority Field Mask (PRM2–PRM0)—This field determines the minimum priority

which is required i n order for a maskable interrupt source to generate an interrupt.

A value of seven (111b) allows all interrupt sources that are not maske d to generate

interrupts. A value of five (101b) allows only unmasked interrupt sources with a

programmable prio rity of zero to five (000b to 101b) to generate interrupts.

Table 7-6 Priority Level

Priority PR2–PR0

(High) 0 0 0 0b

1 0 0 1b

2 0 1 0b

3 0 1 1b

4 1 0 0b

5 1 0 1b

6 1 1 0b

(Low) 7 1 1 1b

15 70

PRM0

PRM2

PRM1

Reserved

Interrupt Control Unit

7-34

7.4.8 Interrupt Mask Register (IMASK, Offset 28h)

(Slave Mode)

The format of the Interrupt Mask register is shown in Figure 7-24. The Interrupt Mask register

is a read/write r egister. Programming a bit in the Inter rupt Mask regi ster has the effect of

programming the MSK bit in the associated control regi ster.

Figur e 7-24 Interrupt Mask Register (IMASK, offset 28h)

The IMASK register i s set to 003Dh on reset.

Bits 15–6: Reserved

Bits 5–4: Timer 2/Timer 1 Interr upt Mask (TMR2–TMR1)—These bits indi cate the s tate

of the mask bit of the Timer Interrupt Control register and when set to a 1, indicate which

source has its interrupt requests masked.

Bits 3–2: DMA Channel Interr upt Mask (D1–D0)—These bits indicate the state of the

mask bits of the corresponding DMA control register.

Bit 1: Reserved

Bit 0: Timer 0 I nterrupt Mask (TMR0)—Thi s bit i ndica tes the st ate of t he mask bi t of the

Timer Interrupt Co ntrol register and when set to a 1, indicates Timer 0 has its interrupt

request masked.

15 70

Reserved

TMR1

TMR2 Res

TMR0

Interrupt Control Unit 7-35

7.4.9 Specific End-of- I nterr upt Register (EOI, Offset 22h)

(Slave Mode)

In slave mode, a write to the EOI reg ister reset s an in-serv ice bit of a specific prio rity. The

user suppli es a three-bit priori ty-level value that poi nts to an in-service bit to be res et. The

command is executed by writing the cor re ct value in the Specific EOI register at offs et 22h.

Figur e 7-2 5 Spec ific End-of-Interru pt R egi st er (EOI, offset 22h)

The EOI register is undefined on reset.

Bits 15–3: Reserved—Write as 0.

Bits 2–0: Interrupt Type (L2–L0)—Encoded value indicating the priority of the IS (interrupt

service) bit to be reset. Writes to these bits cause an EOI to be issued for the interrupt type

in slave mode. Write-only register.

15 70

000 000 0000 L2–L0

000

Interrupt Control Unit

7-36

7.4.1 0 Interrupt Vector Re gister (INTVEC, Offset 20h)

(Slave Mode)

Vector generation in slave mode is exactly like that of an 8259A or 82C59A slave. The

interr upt controller generates an 8-bit interrupt type that the CPU shifts left two bits

(multiplies by four) to generate an offset into the interrupt vector table.

Figure 7-26 Interrupt Vector Register (INTVEC, offset 20h)

The INTVEC register is undefined on reset.

Bits 15–8: Reserved—Read as 0.

Bits 7–3: Interrupt Type (T4–T0)—Sets the five most significant bits of the interrupt types

for th e i nternal int err upt ty pe. The int err upt cont ro ller itsel f pr ovides the lower t hr ee bits of

the int errupt type, as dete rmined by the pr io rity level of t he i nterr upt request . See Table 7-

5 on page 7-15.

Bits 2–0: Reserved—Read as 0.

15 70

000 000 000

T4–T0

Timer Control Unit 8-1

CHAPTER

8TIMER CONTROL UNIT

8.1 OVERVIEW

There are three 16-bit p rogrammable timers in the Am186EM and Am188EM

microcontrollers. Timers 0 and 1 are highly versatile and are each connected to two external

pins (each one has an input and an output). These two timers can be used to count or time

external events, or they can be used to generate nonrepetitive or variable-duty-cycle

waveforms. Timer 1 can also be configured as a watchdog timer.

The watch dog timer provides a mechanism for detect ing software crashes or hangs. The

TMROUT1 output is internally connected to the watchdog timer interrupt. Software

developers must first program the TIMER1 Mode/Control, Count, and Max Count registers,

and then program t he Watchdog Timer I nterru pt Cont rol regi ster ( see Figur e 7-8 on page

7-18). The TIMER1 Count register must be reloaded at intervals less than the TIMER1 max

count to assure the watchdog interrupt is not taken. If the code crashes or hangs, the

TIMER1 countdown can cause a watchdog interrupt.

Timer 2 i s not connected to any external p ins. It can b e used for real-t ime coding and ti me-

delay applications. It can also be used as a prescale to timer 0 and timer 1 or as a DMA

request source.

8.2 PROGRAMMABLE REGISTERS

The timers ar e controll ed by eleven 16-bi t registe rs (see Table 8-1) t hat are locat ed in the

peripheral control block.

Table 8-1 Timer C ontrol Unit Register Summary

The timer-coun t registers contain the current value of a timer. The timer-count registers

can be read or written at any time, regardless of whether the corresponding timer is running.

The microcont roller increments the value of a t imer-count register each time a timer eve nt

occurs.

Offset from

PCB Register

Mnemonic Register Name

56h T0CON Timer 0 Mode/Control

5Eh T1CON Timer 1 Mode/Control

66h T2CON Timer 2 Mode/Control

50h T0CNT Timer 0 Count

58h T1CNT Timer 1 Count

60h T2CNT Timer 2 Count

52h T0CMPA Timer 0 Maxcount Compare A

54h T0CMPB Timer 0 Maxcount Compare B

5Ah T1CMPA Timer 1 Maxcount Compare A

5Ch T0CMPB Timer 1 Maxcount Compare B

62h T2CMPA Timer 2 Maxcount Compare A

Timer Control Unit

8-2

Each timer also has a corresponding maximum-count regi ster that defines the maximum

value for the timer. When the timer reaches the maximum valu e, it resets to 0 during the

same clock cycl e. (The value in the ti mer-count registe r never equals the maximum-count

the pri mary and secondary maximum-count registers l ets the t imer alte rnate between t wo

maximum values.

If the timer is programmed to use only the primary maximum-count register, the timer output

pin swit ches Low fo r one clock cycle, the clock c ycle after t he maximum value i s reached.

If the timer is programmed to use both of its maximum-count registers, the output pin creates

a waveform by indicat ing which maximum-count register is currently in control. The duty

cycle and freque ncy of the wavefor m depend on the values in the alternating maximum-

count re gisters.

8.2.1 Timer Operating Frequenc y

Each timer is servic ed on every fourth c lock cycle. Therefore, a timer can operate at a

maximum speed of one-quarter of the internal clock frequency. A timer can be clocked

external ly at the same maximum frequency of one-fourth of the internal clock frequency.

However, because of internal synchronization and pipelining of the timer circuitry, the timer

output takes up to six clock cycles to respond to the clock or gate input.

The timers are run by the processor’s internal clock. If power-save mode is in effect, the

timers operate at the reduced power-sav e cloc k rate.

Timer Control Unit 8-3

8.2.2 Timer 0 and Timer 1 Mode and Control Registers

(T0CON, Offset 56h, T1CON, Offset 5Eh)

These regist ers control the functionality of timer 0 and timer 1. See Figure 8- 1.

Figure 8-1 Timer 0 and Timer 1 Mode and Control Registers (T0CON, T1CON,

offset s 56h and 5Eh)

The value of T0CON and T1CON at reset is 0000h.

Bit 15: Enable Bit (EN)—When set to 1, the timer i s enabled. When set to 0 , the timer is

inhibited from counting. This bit can only be written with the INH bit set at the same time.

Bit 14: Inhibit Bit (INH)—Allows selective updating of enable (EN) bit. When set to 1 during

a write, EN can also be modified. When set to 0 duri ng a writ e, writes to EN are ignored.

This bit is not stored and is al ways read as 0.

Bit 13: Interrupt Bit (INT)—When set to 1, an interrupt request is generated when the

count regi ster equals a maximum count. If th e timer is configured in dua l maxcount mode,

an interrupt is generated each t ime t he count reaches maxcount A or max count B. When

INT is set to 0, the ti mer will n o t issue interrupt requests. If the enable bit is cleared aft e r

an interrupt request has been generated but befor e the pending interrupt is serv iced, the

interr upt request will still be present.

Bit 12: Register in Use Bit (RIU)—When the Maxcount Compare A register is being used

for comparison to the timer count value, this bit is set to 0. When the Maxcount Compa re

B register is being used, this bit is set to 1.

Bits 11–6: Reserved—Set to 0.

Bit 5: Maximum Count Bit (MC)—The MC bit is set to 1 when the timer reaches a maximum

count. In dual maxcount mode, the bit is set each t ime eit her Maxcount Compare A or B

can be used to monit or ti mer st atus thr ough sof tware pol ling inst ead of through i nterr upts .

Bit 4: Retrigger Bit (RTG) —Det ermines the control function prov ided by the timer input

pin. When set to 1, a 0 to 1 edge trans ition on TMRIN0 or TMRIN1 resets the count. When

set to 0, a High input enables counting a nd a Low input holds the timer val ue. This bit is

ignored when external clocking (EXT=1) is selected.

Bit 3: Pr escaler Bi t (P)—When se t t o 1, t he timer is pr esca led by t imer 2. When set t o 0,

the timer counts up every fourth CLKOUT period. This bit is ignored when external clocking

is enabled (EXT=1).

15 70

EN INT

INH RIU

EXT

RTG ALT

CONT

00000

Timer Control Unit

8-4

Bit 2: External Clock Bit (EXT)— When set to 1, an external clock is used. When set to

0, the internal clock is used.

Bit 1: Alternate Compare Bit (ALT)—When set to 1, the timer counts to maxcount compare

A, then resets the count register to 0. Then the timer counts to maxcount compare B, resets

the count register to zero, and starts over with maxc ount compare A.

If ALT is clear, the timer c ounts to maxcount compare A and then resets the count register

to zero and start s counting again against maxcount compare A. In this case, maxcount

compare B is not used.

Bit 0: Continuous Mode Bit (CONT)—When set to 1, CONT causes the associated timer

to run in the normal cont inuous mode.

When CONT is set to 0, EN is cleared after each timer count sequence and the timer clears

and then halts on reaching the maximum count. If CONT=0 and ALT=1, the timer counts

to the maxcount compare A register value and resets, then it counts to the B register value

and resets and halts.

Timer Control Unit 8-5

8.2.3 Timer 2 Mode and Control Regist er

(T2CON, Offset 66h)

This register controls the functionalit y of timer 2. See Figure 8-2.

Figure 8-2 Timer 2 Mode and Control Register (T2CON, offset 66h)

The value of T2CON at reset is 0000h.

Bit 15: Enable Bit (EN)—When EN is set to 1, the timer is enabled. When set to 0, the

timer is i nhibited from count ing. Do not write to this bit unl ess the INH bit is set to 1 dur ing

the same write.

Bit 14: Inhibi t Bit (INH)—Allows selecti ve updating of enable (EN) bi t. When INH is set to

1 during a write, EN can be modified on the same write. When INH is set to 0 during a write,

writes to EN are igno red. This bi t is not stored and is al ways read as 0.

Bit 13: Interr upt Bit (INT)—When INT is set to 1, an interr upt request is generated when

the count register equals a maximum count. When INT is set to 0 , t he timer will not issue

interr upt requests. If the EN enable bit is cleared after an int e rrupt request has been

generated, but before the pending interrupt is serviced, the interrupt request remains active.

Bits 12–6: Reserved—Set to 0.

Bit 5: Maximum Count Bit (MC)—The MC bit is set to 1 when the time r reaches its

maximum count. This bi t is set regardless of the timer interrupt -enable bit. The MC bit can

be used to monitor timer status through software polling instead of through interrupts.

Bits 4–1: Reserved—Set to 0.

Bit 0: Continuous Mode Bit (CONT)—When CONT is set to 1, it causes the associated

timer to run continuously. When se t to 0, EN is cleared aft er each timer count sequence

and the timer halts on reachi ng the maximum count.

15 70

EN INT

INH

MC CONT

0000000000

Timer Control Unit

8-6

8.2.4 Timer Count Registers

(T0CNT, Offset 50h, T1CNT, Offset 58 h, T2CNT, Offset 60h)

These registe rs can be incremented by one every four inter nal processo r cloc ks. Timer 0

and timer 1 can also be configured to increment based on the TMRIN0 and TMRIN1 external

signals, or they can be prescaled by timer 2. See Figure 8-3.

The count registers are compared to maximum count registers and various actions are

triggered based on reaching a maximum count.

Figure 8-3 Timer Count Registers (T0CNT, T1CNT, T2CNT, offsets 50h, 58h, and 60h)

The value of these registers at reset is undefined.

Bits 15–0: Timer Count Value (TC15–TC0)—This register contains the current count of

the associat ed timer. The count is incr emen ted every fourth processor clock in internal

clocked mode, or each time the timer 2 maxcount is reached if prescaled by t imer 2. Timer

0 and timer 1 can be configured for ext ernal cl ocking based on the TMRIN0 and TMRIN1

signals.

15 70

TC15–TC0

Timer Control Unit 8-7

8.2.5 Timer Maxcount Compare Registers

(T0CMPA , O ffset 52h, T0CMPB, Offset 54h, T1CM PA, Offset 5Ah,

T1CMPB, Offset 5Ch, T2CMPA, Offset 62h)

These regist ers serve as comparators for t heir associ ated count registers. Time r 0 and

timer 1 each have two maximum count compare registers. See Figure 8-4.

Timer 0 and timer 1 can be config ured to count and compar e to r egiste r A and t hen count

and compare to register B. Using this method, the TMROUT0 or TMROUT1 signals can

be used to generate waveforms of various duty cycles.

Timer 2 has one compare register, T2CMPA.

If a maximum count compare register is set to 0000h, the timer associated with that compare

clock, a time r configured this way interrupts every 6.5536 ms.

Figure 8-4 Timer Maxcount Compare Registers

(T0CMPA, T0CMPB, T1CMPA, T1CMPB, T2CMPA,

offsets 52h, 54h, 5Ah, 5Ch, and 62h)

The value of these registers at reset is undefined.

Bits 15–0: Timer Compare Value (TC15–TC0)—This register contains the maximum

value a timer wil l count to bef ore resetting its count register to 0.

15 70

TC15–TC0

Timer Control Unit

8-8

DMA Controller 9-1

CHAPTER

9DMA CONTROLLER

9.1 OVERVIEW

Direct memory access (DMA) permits transfer of data between memory and peripherals

without CPU involvement. The DMA unit in the Am186EM and Am188EM microcontrollers

provides two high-s peed DMA channels. Da ta t ra ns fe rs c an oc cu r be tw ee n m em o ry an d I / O

spaces (e.g., memory to I/O) or within the same space (e.g., memory-to-memory or I/O-to-I/O).

Either bytes or words can be transferred to or from even or odd addresses on the Am186EM.

(The Am188E M micr ocontrol ler does not suppor t wor d tr ansfer s.) Two bus cy cles (a mi nimum

of eight clocks) are necessary for each data transfer.

Each channel accepts a DM A request from one of two sources: the channel request pin

(DRQ1–DRQ0) or Timer 2. The two DMA channels can be programmed with different

priorities to resolve simultaneous DMA requests, and transfers on one channel can interrupt

the other channel.

9.2 DMA OPERATION

The format of the DMA control block is shown in Table 9-1. Six regi sters in the peripheral

control block define the operation of each channel. The DMA regist ers consi st of a 20-bi t

source address (2 registers), a 20 -bit destination address (2 regi sters), a 16-bit transfer

count register, and a 16-bit control register.

Table 9-1 DMA Controller Register Summary

The DMA transfer count register (DTC) specifies the number of DM A transfers to be

performed. Up to 64 Kbytes or 64 Kwords can be transferred with automatic termination.

The DMA control registers define the channel operations (see Figure 9-1). All registers

can be modified or altered during any DMA activity. Any changes made to these registers

are r eflected immediat ely in DMA operati on.

Offset from

PCB Register

Mnemonic Register Name

CAh D0CON DMA 0 Control

DAh D1CON DMA 1 Control

C8h D0TC DMA 0 Transfer Count

D8h D1TC DMA 1 Transfer Count

C6h D0DSTH DMA 0 Destination Address High

D6h D1DSTH DMA 1 Destination Address High

C4h D0DSTL DMA 0 Destination Address Low

D4h D1DSTL DMA 1 Destination Address Low

C2h D0SRCH DMA 0 Source Ad dr es s High

D2h D1SRCH DMA 1 Source Ad dr es s High

C0h D0SRCL DMA 0 Sour ce Ad dres s Low

D0h D1SRCL DMA 1 Sour ce Ad dres s Low

DMA Controller

9-2

Figure 9-1 DM A Unit Block Diagram

9.3 PROGRAMMABLE DMA REGISTERS

The sections on the following pages describe the control registers that are used to configure

and operate the two DMA channels.

Source Address Ch. 1

Source Address Ch. 0

20-bit Adder/Subtractor

DMA

Control

Logic

Request

Selection

Logic

Adder Control

Logic

Channel Control Register 1

Channel Control Register 0

DRQ1

DRQ0

Internal Address/Data Bus

Timer Request

Interrupt

Request

Transfer Counter Ch. 1

Destination Address Ch. 1

Destination Address Ch. 0

Transfer Counter Ch. 0

DMA Controller 9-3

9.3.1 DMA Control Registers (D0CON, Offset CAh, D1CON, Offset DAh)

The DMA control regi sters (s ee Figur e 9-2) determi ne the mode of operati on for the DMA

channels. These registers specify the foll owing options:

nWhether the destination address is memory or I/O space

nWhether the d estination address i s incremented, decremented, or maintained constant

after each transfer

nWhether the source address is memory or I/O space

nWhether the source address is incremented, decremented, or maintained constant after

each transfer

nIf DMA activity ceases after a programmed number of DMA cycles

nIf an interrupt is generated after the last transfer

nThe mode of synchronization

nThe relative priority of one DMA channel with respect to the other DMA channel

nWhether timer 2 DMA requests are enabled or disabled

nWhether bytes or words are transferre d

The DMA channel control registers can be changed while the channel is operating. Any

changes made during DMA operations affect the current DMA tr ansfer.

Figure 9-2 DMA Control Registers (D0CON, D1CON, offsets CAh and DAh)

The value of D0CON and D1CON at reset is FFF9h.

Bit 15: Destination Address Space Select (DM/IO)—Selects memory or I/O space for

the destination address. When DM/IO is set to 1, the destination address is in memory

space. When set to 0, the destination address is in I/O space.

Bit 14: Destination Decrement (DDEC)—When DDEC is set to 1, the destination address

is autom atically decremented after each transfer. The address decrements by 1 or 2,

depending on the byte/word bit (B/W, bit 0). The address remains constant if the increment

and decrement bits are set to the same value (00b or 11b).

Bit 13: Destination Increment (DINC)—When DINC is set to 1, the destination address

is automati cally incremented after each transfer. The address increments by 1 or 2,

depending on the byte/word bit (B/W, bit 0). The address remains constant if the increment

and decrement bits are set to the same value (00b or 11b).

Bit 12: Source Address Space Select (SM/IO)—When SM/IO is set to 1, the source

address is in memory space. When set to 0, the source address is in I/O space.

15 70

DM/IO

DINC

DDECSM/IO

SINC

SDEC B/W

CHG

Res

TCINTSYN P

TDRQ

DMA Controller

9-4

Bit 11: Source Decrement (SDEC)—When SDEC is set to 1, the source address is

automatically decremented after each transfer. The addr ess decrements by 1 or 2

depending on the byte/word bit (B/W, bit 0). The address remains constant if the increment

and decrement bits are set to the same value (00b or 11b).

Bit 10: Source Increment (SINC)—When SINC is set to 1, the source address is

automatically incremented after each transfer. The address increments by 1 or 2 depending

on the byte/word bit (B/W, bit 0). The address remai ns constant if the increment and

decrement bits are set to the same value (00b or 11b).

Bit 9: Terminal Count (TC)—The DMA decrements the transfer count for each DMA

transfer. When TC is set to 1, source or destination synchronized DMA transfers terminate

when the count r eaches 0. When TC is set to 0, sour ce or dest ina tion syn chron ized DMA

transfer s do n ot terminate when the count reaches 0. Unsynchronized DMA transfers

always terminate when the count reaches 0, regardless of the setting of this bit.

Bit 8: Interrupt (INT)—When INT is set to 1, the DMA channel generates an interrupt

request on completion of the transfer count . The TC bit must also be set to generate an

interrupt.

Bits 7–6: Synchronizati on Type (SYN1–SYN0)—The SYN1–SYN0 bits select channel

synchronization as shown in Table 9-2. For more information on DMA synchronization, see

section 9.4 on page 9-10.

Table 9-2 Synchronization Type

Bit 5: Relati ve Priority (P)—When P is set to 1, i t selects high priorit y for this channel

relative to the other channel during simultaneous transfers.

Bit 4: Timer Enable/ Disable Request (TDRQ)—When TDRQ is set to 1, it enables DMA

requests fr om timer 2. When set to 0, TDRQ disables DMA reque sts from timer 2.

Bit 3: Reserved

Bit 2: Change Start Bit (CHG)—This bit must be set to 1 during a write to allow modification

of the ST bit. When CHG is set to 0 during a write, ST is not altered when writing the control

word.

Bit 1: Start/Stop DMA Channel (ST)—The DMA channel is started when the start bit is

set to 1. This bit can be modifi ed only when the CHG bit is set to a 1 during the same

Bit 0: Byte/Word Select (B/W)—On the Am186EM microcont roller, when B/W is set to 1,

word transfers are selected. When B/W is set to 0, byte transfers are selected. Word

transfer s are not support ed on the Am18 8EM microcontroller.

SYN1 SYN0 Sync Type

0 0 Unsynchronized

0 1 Source Synch

1 0 Destination Synch

1 1 Reserved

DMA Controller 9-5

9.3.2 DMA Transfer Count Register s (D0TC, Offse t C8 h, D1TC,

Offset D8h)

Each DMA channel maintains a 16-bit DMA Transfer Count register (DTC). This register

is decremented af ter every DMA cycle, regardless of the state of the TC bit in the DMA

Control regi ster. However, if the TC bit in the DMA control word is set or i f unsync hronized

transfer s are programmed, DMA activity terminates when the Transfer Count register

reaches 0.

Figur e 9-3 DMA Tra nsf er Count R egi st er s (D0 T C, D1T C, offsets C 8h an d D8h)

The value of D0TC and D1TC at reset is undefined.

Bits 15–0: DMA Transfer Count (TC15–TC0)—Contains the transfer count for a DMA

channel. Value is decreme nted by 1 aft e r each transfer.

15 70

TC15–TC0

DMA Controller

9-6

9.3.3 DMA Destination Address High Register

(High Order Bits) (D0DSTH, Offset C6h, D1DSTH, Offset D6h)

Each DMA channel maintains a 20-bit destination and a 20-bit source register. Each register

takes up two full 16-bit registers (the high register and the low register) in the per ipheral

control block. For each DMA channel to be used, all four registers must be initialized. These

registers can be individuall y incr emented or decremented after each transf er. If word

transfers are performed, the address is incremented or decremented by 2 after each

transfer . If byte transfers are performed, the address is i ncremented or decremented by 1.

Each register can point into either memory or I/O space. The user must program the upper

four bits to 0000 b in order to address the nor mal 64K I/O space. Since the DMA channels

can perform transfer s to or from odd addresses, there is no restriction on values for the

destination and source address regi sters. Higher transfer rates can be achi eved on the

Am186EM microcontroller if all word transfers are performed to or from even addresses so

that accesses occur in singl e, 16-bit bus cycles.

Figure 9-4 DMA Destination Address High Register (D0DSTH, D1DSTH, offsets C6h and D6h)

The value of D0DSTH and D1DSTH at reset is undefined.

Bits 15–4: Reserved

Bits 3–0: DMA Destination Address High (DDA19–DDA16)—These bits are driven onto

A19–A16 during the write phase of a DMA transfer.

15 70

Reserved

DDA19–DDA16

DMA Controller 9-7

9.3.4 DMA Destination Address Low Register

(Low Order Bits) (D0DSTL, Offset C4h, D1DSTL, Offset D4h)

Figure 9-5 shows the DMA Destination Address Low register. The sixteen bits of this register

are combined wit h the four bits of the DMA Destination Address High register ( see Figure

9-4) to produce a 20-bit destination address.

Figur e 9-5 DMA Destin ation Addre ss Low Regi ster (D0 DSTL, D1DST L, offse ts C4h and D 4h)

The value of D0DSTL and D1DSTL at reset is undefined.

Bits 15–0: DMA Destination Address Low (DDA15–DDA0)—These bits are dr iven onto

A15–A0 during the write phase of a DMA transfer.

15 70

DDA15–DDA0

DMA Controller

9-8

9.3.5 DMA Source Address High Register

(High Order Bits) (D0SRCH, Offset C2h, D1SRCH, Offset D2h )