S-8550/8551 Series
www.sii-ic.com
STEP-DOWN, BUILT-IN FET, SYNCHRONOUS
RECTIFICATION, PWM CONTROL SWITCHING REGULATORS
© Seiko Instruments Inc., 2007-2010 Rev.4.0_00
Seiko Instruments Inc. 1
The S-8550/8551 Series is a CMOS synchronous rectification step-down switching regulator which mainly consists of a
reference voltage circuit, an oscillator, an error amplifier, a phase compensation circuit, a PWM controller, an under
voltage lockout circuit (UVLO) , a current limit circuit, an d a po wer MOS FET. The oscillation frequency is h igh at 1.2 MHz,
so a high efficiency, la rge out put curr ent, step-down switching regu lator c an be a chi eved by using sm all external p arts.
The built-in synchr onous rectification circ uit makes achieving hi gh efficiency easier compared with conventional step-down
switching regulators. A ceramic capacitor can be used as an output capacitor. High-density mounting is supported by
adopting packages sm al l SOT -23-5 and s u per-sm all an d thin S NT -8A.
The S-8550 and S-85 51 Seri e s are offer ed accordi ng to diff erent p in confi gurat io n.
Features
• Oscillation frequenc y : 1.2 MHz
• Input voltage range : 2.0 V to 5.5 V
• Output voltage range : Arbitrarily settable by external output voltage setting resistor
• Output current : 600 mA
• Reference voltage : 0.6 V ±2.0%
• Efficiency : 92%
• Soft-start function : 1 ms typ.
• Shutdown function : Shutdown current consumption : 1.0 μA m a x.
• Built-in current limit circuit
• Pch power MOS FET on-res istance : 0.4 Ω typ.
• Nch power MOS FET on-resistanc e : 0.3 Ω typ.
• Constant continuous mo de oper ati on (no li ght lo ad m ode)
• Lead-free, Sn 100%, halogen-free*1
*1. Refer to “ Product Name Structure” for details.
Applications
• Mobile devices, such as mobile phones, Bluetooth devices, wireless devices, digital audio players, digital still
cameras, portable DVD playe rs, and porta ble CD pla yers
Packages
• SOT-23-5
• SNT-8A
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICAT ION
,
PWM CONTROL SWITCHING REGULATORS
S-8550/8551 Series Rev.4.0_00
2 Seiko Instruments Inc.
Block Diagram
1. SOT-23-5
L
ON/OFF
V
IN
+
−
+
−
C
IN
FB
VIN
CONT
VSS
C
FB
R
FB1
R
FB2
V
OUT
C
OUT
*1
*1
Reference
voltage PWM comparator
PWM control
circuit
UVLO
circuit
ON/OFF
circuit
IC internal
power supply
Current limit
circuit
Error amplifier
T
r
i
angu
l
ar wave
generation
circuit
*1. Parasitic diode
Figure 1
2. SNT-8A
L
ON/OFF
V
IN
+
−
+
−
C
IN
FB
VIN
CONT
PVSS
C
FB
R
FB1
R
FB2
V
OUT
C
OUT
*1
*1
Reference
voltage PWM compar ator
PWM control
circuit
UVLO
circuit
ON/OFF
circuit
IC internal
power supply
Current limit
circuit
Error amplifier
T
r
i
angu
l
ar wave
generation
circuit
VSS
*1. Parasitic diode
Figure 2
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICATION
,
PWM CONTROL SWITCHING REGULATORS
Rev.4.0_00 S-8550/8551 Series
Seiko Instruments Inc. 3
Product Name Structure
1. Product name
S-855 x A A − xxxx x
Pin configuration setting*2
0 : Pin configuration 1 (SOT-23-5), Pin configuration 3 (SNT-8A)
1 : Pin configuration 2 (SOT-23-5)
Package name (abbreviation) and packing specification*1
M5T1 : SOT-23-5, tape
I8T1 : SNT-8A, tape
Oscillation frequency
A : 1.2 MHz
Environmental code
U : Lead-free (Sn 100%), halogen-free
G : Lead-free (for details, please contact our sales office)
*1. Refer to t he t ape sp ecif ic ati o ns at t he end o f t his book.
*2. Refer to Table 1 to Table 3 of “ Pin Configurations”.
2. Packages
Drawing Code
Package Name Package Tape Reel Land
SOT-23-5 MP005-A-P-SD MP005-A-C-SD MP005-A-R-SD ⎯
SNT-8A PH008-A-P-SD PH008-A-C-SD PH008-A-R-SD PH008-A-L-SD
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICAT ION
,
PWM CONTROL SWITCHING REGULATORS
S-8550/8551 Series Rev.4.0_00
4 Seiko Instruments Inc.
Pin Configurations
Table 1 S-8550 Series (SOT-23-5, Pin Configuration 1)
Pin No. Symbol Description
1 VIN IC power supply p in
2 VSS GND pin
3
ON/OFF Shutdown pin
“H” : Po wer on (normal o per ation)
“L” : Po wer off (standby)
4 FB Output voltage feedback p in
5 CONT External inductor con necti on pin
SOT-23-5
Top view
5 4
3 2 1
Figure 3
Table 2 S-8551 Series (SOT-23-5, Pin Configuration 2)
Pin No. Symbol Description
1
ON/OFF Shutdown pin
“H” : Po wer on (normal o per ation)
“L” : Po wer off (standby)
2 VSS GND pin
3 CONT External inductor con necti on pin
4 VIN IC power supply p in
5 FB Output voltage feedback p in
Table 3 S-8550 Series (SNT-8A, Pin Configuration 3)
Pin No. Symbol Description
1 FB Output voltage feedback p in
2 NC*1 No connection
3 VSS*2 Small signal GND Pin
4 OFFON/ Shutdown pin
“H”：Power on (normal operation)
“L”：Power off (standby)
5 VIN IC power supply p in
1
2
3
4
SNT-8A
Top vi e w
8
7
6
5
6
PVSS*2 Power GND pin
Figure 4 7 NC*1 No connection
8 CONT External inductor con necti on pin
*1. The NC pin is electrical l y open.
The NC pin can be c onnecte d to VIN, VSS or PVSS.
*2. Connect VSS and PVSS to GND.
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICATION
,
PWM CONTROL SWITCHING REGULATORS
Rev.4.0_00 S-8550/8551 Series
Seiko Instruments Inc. 5
Absolute Maximum Ratings
Table 4 Absolute Maximum Ratings
(Unless otherwise specified: T a = 25°C, VSS = 0 V)
Parameter Symbol Absolute Maximum Rating Unit
VIN pin voltage VIN V
SS − 0.3 to VSS + 6.0 V
FB pin voltage VFB V
SS − 0.3 to VIN + 0.3 V
CONT pin voltage VCONT V
SS − 0.3 to VIN + 0.3 V
ON/OFF pin voltage VON/OFF V
SS − 0.3 to VIN + 0.3 V
CONT pin current ICONT 1300 mA
SOT-23-5 600*1 mW
Power
dissipation SNT-8A PD 450*1 mW
Operating temperature Topr −40 to +85 °C
Storage temperature Tstg −40 to +125 °C
*1. When mounte d on printed circuit board
[Mounted board]
(1) Board size: 114.3 mm × 76.2 mm × t1.6 mm
(2) Board name: JEDEC STANDAR D51-7
Caution 1. The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
2. Since this IC has a built-in power MOS FET, make sure that dissip ation of the power MOS FET
does not exceed th e allow able p ow er dissipatio n of the pack age. (Refer to Fig ure 5.)
Generally, dissipation of a switching regulator can be calculated by the following equation.
Dissipation = (100 (%) − efficiency (%)) / efficiency (%) × output voltage × load current
The greater part of dissipation depends on the built-in power MOS FET, however, dissipation
of the inductor is also included.
In addition, since power dissipation of the package also changes according to a mounting
board or a mounting state, fully check them using an actually mounted mode.
0
400
0
Power dissipation (PD) [mW]
Ambient temperature (Ta) [°C]
200
500
300
100
600
700
50 100 150
SNT-8A
SOT-23-5
Figure 5 Power Dissipation of Package (Mounted on Board)
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICAT ION
,
PWM CONTROL SWITCHING REGULATORS
S-8550/8551 Series Rev.4.0_00
6 Seiko Instruments Inc.
Electrical Characteristics
Table 5 Electrical Characteristics
(
Unless otherwise specified: V
IN
=
3.6 V, V
OUT
=
1.8 V (the conditions in
Table 6
), Ta
=
+25
°
C
)
Parameter Symbol Conditions Min. Typ. Max. Unit
Test
Circuit
Operating input voltag e VIN ⎯ 2.0 ⎯ 5.5 V 2
Output voltage range*1 VOUT V
IN = VOUT(S) + 0.4 V to 5.5 V 1.1 ⎯ 4.0 V 2
FB voltage VFB V
IN = VOUT(S) + 0.4 V to 5.5 V 0.588 0.6 0.612 V 2
FB voltage temperature
coefficient ΔVFB
ΔTa
Ta = −40°C to +85°C ⎯ ±100 ⎯ ppm/°C 2
FB pin input current IFB V
IN = 2.0 V to 5.5 V, FB pin −0.1 ⎯ +0.1 μA 1
Current consumption
during shutdown ISSS VIN = 2.0 V to 5.5 V,
VON/OFF = 0 V ⎯ ⎯ 1.0 μA 1
Current consumption 1 I SS1 fosc = 1.2 MHz, no ext ernal p art s,
VFB = VFB(S) × 1.1 V ⎯ 200 400 μA 1
RPFET I
CONT = 100 mA ⎯ 0.4 0.6 Power MOS FET
on-resistance RNFET I
CONT = −100 mA ⎯ 0.3 0.5 Ω 1
Power MOS FET
leakage current ILSW VIN = 2.0 V to 5.5 V,
VON/OFF = 0 V, VCONT = 0 or 3.6 V ⎯ ±0.01 ±0.5 μA 1
Limit current ILIM ⎯ 800 1000 1200 mA 1
Oscillation frequenc y fosc ⎯ 1.02 1.2 1.38 MHz 2
Soft-start time tSS Time required to reac h 90 % of
VOUT(S) 0.7 1.0 1.3 ms 2
High level inpu t voltag e VSH V
IN = 2.0 V to 5.5 V, ON/OFF pin 0.9 ⎯ ⎯ V 2
Low level input voltag e VSL V
IN = 2.0 V to 5.5 V, ON/OFF pin ⎯ ⎯ 0.3 V 2
High level input current ISH V
IN = 2.0 V to 5.5 V, ON/OFF pin −0.1 ⎯ 0.1 μA 1
Low level input current ISL V
IN = 2.0 V to 5.5 V, ON/OFF pin −0.1 ⎯ 0.1 μA 1
UVLO detection voltage
VUVLO ⎯ 1.4 1.6 1.78 V 2
*1. V
OUT(S) is the output voltage set value, and V OUT is the t yp. value of the actual output voltage.
V
OUT(S) can be set depending on the r atio between the VFB valu e and o utput voltag e set resistors (RFB1, RFB2).
For details, ref er to “ External Parts Selectio n”.
External Parts When Measuring Electrical Characteristics
Table 6 External Parts
Element Name Symbol Constant Manufacturer Part Number
Inductor L 3.3 μH Taiyo Yuden Co., Ltd. NR4018T3R3M
Input capacitor CIN 4.7 μF TDK Corporation C3216X7R1E475K
Output capacitor COUT 10 μF TDK Corporation C3216X7R1C106K
Output voltage set resistor 1 RFB1 36 kΩ Rohm Co., Ltd. MCR03 Series 3602
Output voltage set resistor 2 RFB2 18 kΩ Rohm Co., Ltd. MCR03 Series 1802
Phase compensation capacitor CFB 68 pF Murata Manufacturin g Co., Lt d. GRM1882C1H680J
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICATION
,
PWM CONTROL SWITCHING REGULATORS
Rev.4.0_00 S-8550/8551 Series
Seiko Instruments Inc. 7
Test Circuits
1.
S-8550/8551Series
ON/OFF
A
↓
C
IN
CONT
FB
VSS
VIN
PVSS
*1
*1. PVSS pin is unavaila ble f or the S-855 0/855 1 ser ies with SOT -23-5.
Figure 6
2.
L
S-8550/8551Series
ON/OFF
C
IN
CONT
FB
VSS
VIN
V
V↓I
OUT
V
OUT
C
FB
C
OUT
R
FB1
R
FB2
PVSS
*1
*1. PVSS pin is unavaila ble f or the S-855 0/855 1 ser ies with SOT -23-5.
Figure 7
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICAT ION
,
PWM CONTROL SWITCHING REGULATORS
S-8550/8551 Series Rev.4.0_00
8 Seiko Instruments Inc.
Operation
1. Synchronous rectification PWM control step-down switching regulator
1.1 Synchronous rectification
The synchronous rectification method lowers voltage drop to greatly reduce power dissipation since an Nch
power MOS FET, having resistance m uch lo wer than conventi onal switching regulators, is used.
In conventional switching regulators, current flows in the diode connect ed between the GND and CONT pins
when the Pch power MOS FET is off. The forward drop voltage (Vf) of such diodes is large, between 0.3 V
to 0.7 V, so the power dissipation used to b e very large. S ynchronous r ectification ultr a-low resistance Nch
transistors repeat on and off, in synchronization with the operation of the Pch driver, in the reverse cycle of
the Pch driver. Moreover, the built-in P and N through prevention circuit helps much reduction of power
consumption during oper atio n .
1.2 PWM control
The S-8550/8551 Ser ies is a switching regul ator using a pulse width modu lation method (PWM) and featur es
low current consumption.
In conventional PWM control switching regulators, pulses are skipped when the output load current is low,
causing a fluctuation in the ripple frequency of the output voltage, resulting in an increase in the ripple
voltage.
In the S-8550/8551 Series, the s witching frequency does not change, although the puls e width changes from
0% to 100% corresponding to each load current. The ripple voltage generated from switching can thus be
removed easily usin g a filt er beca use the s witchi ng frequ enc y is c onstant.
2. Soft-start function
The soft-start circuit built in the S-8550/8551 Series controls the rush current and the overshoot of the output
voltage when po wering on, t he ON/OFF pi n is switched fr om the “ L” level to the “ H” level, or th e UVLO operation
is released. A reference voltage adjustme nt method is adopt ed as th e soft-start meth od.
3. Shutdown pin
This pin stops or starts step-up op erations.
Switching the shutdown pin to the “L” level stops operation of all the internal circuits and reduces the current
consumption significantly. DO NOT use the shutdown pin in a floating state because it is not pulled up or
pulled down internally. DO NOT apply voltage of between 0.3 V and 0.9 V to the shutdown pin because
applying such a voltage increases the current consumption. If the shutdown pin is not used, connect it to the
VIN pin.
Table 7
Shutdown Pin CR Oscillation Circuit Output Voltage
“H” Operates Set value
“L” Stops Hi-Z
VIN
ON/OFF
VSS
Figure 8
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICATION
,
PWM CONTROL SWITCHING REGULATORS
Rev.4.0_00 S-8550/8551 Series
Seiko Instruments Inc. 9
4. Current limit circuit
A current limit circuit is built in the S-8 550/8551 S eries.
The current limit circuit monitors the c urrent that flows in the Pch power MOS FET and limits curre nt in order to
prevent thermal destruction of the IC due to an o verl oad or magnetic sa turation of the induct or.
When a current exceeding the current limit detection value flows in the Pch power MOS FET, the current limit
circuit operates and turns off the Pch power MOS FET since the current limit detection until one clock of the
oscillator ends. The Pch power MOS FET is turned on in the next clock and the current limit circuit resumes
current detection operation. If the value of the current that flows in the Pch power MOS FET remains the
current limit detection value or more, the current limit circu it functions again and the same oper ation is repeate d.
Once the value of the current that flows in the Pch power MOS FET is lowered up to the specified value, the
normal operation stat us restores. A slight overs hoot is generated i n the output voltag e when the current l imit is
released.
The current limit detection value is fixed to 1 A (typ.) in the IC. If the time taken for the current limit to be
detected is shorter than th e time required for the current limit circuit i n the IC to detect, the current value that is
actually limited increases. Generally, the voltage difference between the VIN and VOUT pins is large, the
current limit detection st atus is reach ed faster and the c urr ent val ue incre ases.
5. 100% duty cycle
The S-8550/8551 Series operates up to the maximum duty cycle at 100%. Even when the input voltage is
lowered up to the outp ut voltage valu e set using t he ex ternal output v oltage setting r esistor, the Pch po wer MOS
FET is kept on and current can be supplied to the loa d. The outp ut voltage at this time is the input voltage from
which the voltage drop due to the direct resistance of the inductor a nd the on-resistance of th e Pch power MOS
FET are subtracted.
6. UVLO function
The S-8550/8551 Series includes a UVLO (under-voltage lockout) circuit to prevent the IC from malfunctioning
due to a transient status when power is app lied or a momentary drop of the supply voltage. When UVLO is in
the detection state, the Pch and Nch power MOS FETs stop switching operation, and the CONT pin become
Hi-Z. Once the S-8550/8551 is in the UVLO detection status, the soft-start function is reset, but the soft-start
operates by the rel eas ing op erati on of UVL O after that.
Note that the other internal cir cuits op erat e n ormall y and that the status is different from the po wer-off status.
The hysteresis width is set for the UVLO cir cuit to prevent a malfunction due to a noise that is generated in the
input voltage. A voltage about 150 mV (typ .) higher than the UVLO dete ction volta ge is the rel ease vo ltag e.
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICAT ION
,
PWM CONTROL SWITCHING REGULATORS
S-8550/8551 Series Rev.4.0_00
10 Seiko Instruments Inc.
Operation Principle
The S-8550/8551 Series is a step-down synchronous rectification switching regulator based on constant PWM
control. Figure 9 shows the basic circuit diagram.
A step-down switching regulator starts current supply by the input voltage (VIN) when the Pch power MOS FET is
turned on and holds energy in the inductor at the same time. When the Pch power MOS FET is turned off, the
current held in the inductor is released. The released current flows in the smoothing circuit, with the energy loss
held minimum, supplies the output voltage (VOUT) lower than VIN. VOUT is kept constant by controlling the
switching frequenc y (fosc) and ON time (ton). With the PWM control method, VOUT is made constant by controlling
the ON time with fOSC unchanged.
L
Control
circuit
Pch power MOS FET
Nch po wer MO S F ET
V
IN
V
OUT
C
OUT
I
1
I
2
Figure 9 Basic Circuit Drawing of Step-down Switching Regulator
1. Continuous mode
The following explains how the current flows to the inductor when the step-down operation is constant and
stable.
When the Pch power MOS FET is turned on, current I1 flows in the direction shown by the arrow in Figure 9,
and energy is stored in the inductor (L). When the output capacitor (COUT) is charged, supply of the output
current (IOUT) is started at the same time. The inductor curre nt (IL) gradually increases in proportion to the ON
time (tON) of the Pch power MOS FET as shown in Figure 10 (changes from IL min. to IL max.). When the Pch
power MOS FET is turned of f, the Nch power MOS FET is turne d on and IL tries to hold IL max. Consequently,
current I2 flows in the direction shown by the arrow in Figure 9. As a result, IL gradually decreases and
reaches IL min. when the OFF time (tOFF) has elapsed. When tOFF has elapsed, the Nch power MOS FET is
turned off and the next cycle i s enter ed. The above sequ ence is r epe ated.
As explained in the above, the continuous mode refers to the operation in the current cycle in which IL linearly
changes from IL min. to IL max. Ev en if IL min. is less than 0 A, IL min. keeps flo wing (backflo w current flows).
ton toff
T = 1/fOSC
IL
IL max.
IL min.
t
Figure 10 Continuous Mode (Current Cycle of Inductor Current (IL))
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICATION
,
PWM CONTROL SWITCHING REGULATORS
Rev.4.0_00 S-8550/8551 Series
Seiko Instruments Inc. 11
2. Backflow current
The S-8550/8551 Ser ies performs PWM synchronous rect ification even if IL min. is less than 0 A, so a backflo w
current is generated in VIN and the backflow current becomes maximum when no load is applied (see Figure
11). Use the following equation to calculate the maximum backflow current value, which should be taken into
consideration when designi ng.
Duty (IOUT = 0) = VOUT / VIN
Example : VIN = 3.6 V, VOUT = 1.8 V …… Duty = 50%
ΔIL = ΔV / L × ton = (VIN − VOUT) × Duty / (L × fOSC)
Example : VIN = 3.6 V, VOUT = 1.8 V, fOSC = 1.2 MHz, L = 3.3 μH …… ΔIL = 227 mA
I
L max. = ΔIL / 2 = 113.5 mA, IL min. = −ΔIL / 2 = −113.5 mA
The current value waveform of the inductor is a tr iangular wave, of which the maximum value is I L max. and the
minimum value is IL min. (negative value), and the negative value (the portion marked by diagonal lines in
Figure 11) backflows when no load is applie d (see Figure 11).
If about 113.5 mA of IOUT flows in the above conditions, the minimum value (IL min.) of the triangular wave is
made 0 mA and no backflo w current flo ws.
When an input capacit or (CIN) is connected, the backfl ow current is absorbed by CIN, thus reduci ng the backflow
current to flow in the power supply. Be sure to connect an input capacitor to reduce backflow current to the
power supply (see Figure 12).
The above presents the conditions required to prevent backflow current from flowing, which is only a guideline.
Perform sufficient confirmatio n using an act ual ap plic ation.
Inductor current with no load Inductor current when load is a
current of 113.5 mA
Backflow
current
−113.5 mA
113.5 mA
IL min.
IL max.
ΔIL
IL
0 mA Backflow current = 0 mA
0 mA
I
OUT
113.5 mA
I
OUT
227 mA
IL min.
IL max.
ΔIL
IL
Figure 11 Example of Conditions to Prevent Backflow Current from Flowing
VOUT
VIN
CONT
Backflow current
Inductor
current IL
CIN
VIN
Figure 12 Backflow Current
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICAT ION
,
PWM CONTROL SWITCHING REGULATORS
S-8550/8551 Series Rev.4.0_00
12 Seiko Instruments Inc.
External Parts Selection
1. Inductor
The inductanc e (L value) has a strong i nflue nce on the m a xim um output current (IOUT) and efficiency (η).
The peak current (IPK) incr eases by decreasing L and t he stability of the circuit impr oves and IOUT increases. If
L is decreased further, the current driv e ca pabi lit y of the external transistor is insufficient and IOUT decreases.
If the L value is increased, the loss due to IPK of the power MOS FET decreases and the efficiency becomes
maximum at a certain L value. Further increasing L decreases the efficiency due to the increased loss of the
DC resistance of the induct or.
The recommended L val ue for the S-8550/8551 Series is 3. 3 μH.
When selecting an inductor, note the allowable current of the inductor. If a current exceeding this allowable
current flows through the inductor, mag netic saturati on o ccurs, substantially lo wering the effici ency.
Therefore, select an inductor so that IPK does not exceed the allowable current. IPK is expressed by the
following equations in the disc onti nuous mo de an d cont inuo us mode.
2 × f
OSC
× L × V
IN
I
PK
= I
OUT
+ V
OUT
× (V
IN
− V
OUT
)
fOSC = Oscillation frequency
Table 8 Typical Inductors
Manufacturer Part Number L Value DC
Resistance Rated Current Dimensions
(L × W × H) [mm]
NR4018T3R3M 3.3 μH 0.07 Ω max. 1.23 A max. 4.0 × 4.0 × 1.8
Taiyo Yuden Co., Ltd.
NR3012T3R3M 3.3 μH 0.1 Ω max. 0.91 A max. 3.0 × 3.0 × 1.2
CDRH3D16/HP-3R3 3.3 μH 0.085 Ω max. 1.40 A max. 4.0 × 4.0 × 1.8
Sumida Corporation
CDRH2D11/HP-3R3 3.3 μH 0.173 Ω max. 0.9 A max. 3.2 × 3.2 × 1.2
VLF4012AT-3R3M 3.3 μH 0.12 Ω max. 1.3 A max. 3.7 × 3.5 × 1.2
TDK Corporation
VLF3010AT-3R3M 3.3 μH 0.17 Ω max. 0.87 A max. 2.6 × 2.8 × 1.0
MIP3226D3R3M 3.3 μH 0.104 Ω max. 1.2 A max. 3.2 × 2.6 × 1.0
FDK Corporation
MIPS2520D3R3M 3.3 μH 0.156 Ω max. 1.0 A max. 2.5 × 2.0 × 1.0
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICATION
,
PWM CONTROL SWITCHING REGULATORS
Rev.4.0_00 S-8550/8551 Series
Seiko Instruments Inc. 13
2. Capacitors (CIN, COUT)
A ceramic capacitor can be used for the input (CIN) and output (COUT) sides. CIN lowers the power supply
impedance and aver ages the input curre nt to impr ove effic iency. Select CIN accordi ng t o the im pe dan ce of the
power supply to be used. The recomme nded ca pac itanc e is 4.7 μF for the S-855 0/855 1 Series when a general
lithium ion rechargeabl e batt ery is us ed.
Select as COUT a capacitor with large capacitance and small ESR for smoothing the ripple voltage. The
optimum capacitor selection depends on the L value, capacitance value, wiring, and application (output load).
Select COUT after sufficient evaluation under actual use c onditions.
3. Output voltage setting resistors (RFB1, RFB2), capacitor for phase compensation (CFB)
With the S-8550/8551 Series, VOUT can be set to any value by external divider resistors. Connect the divider
resistors across the VOUT and VSS pi ns. Because VFB = 0.6 V typ., VOUT can be calculated by this equ ation.
VOUT = (RFB1 + RFB2)
R
FB2 × 0.6
Connect divider resistors RFB1 and RFB2 as close to the IC to minimize eff ects from of noise. If noise does have
an effect, adjust the values of RFB1 and RFB2 so that RFB1 + RFB2 < 100 kΩ.
CFB connected in paral lel with RFB1 is a capacitor for ph as e comp ensatio n.
By setting the zero point (the phase fee dback) by adding capacitor CFB t o output voltage setting resistor RFB1 in
parallel, the feedback loop g ains the phase margin. As a result, the stabi lity can be obtained. In pr inciple, to use
the portion how much the phase has feed back by the zero point effectively, define CFB referring to the following
equation.
CFB ≅ 1
2 × π × RFB1 × 70 kHz
This equation i s the refer enc e.
The followings are expl anatio n regard ing th e proper s ettin g.
To use the port ion ho w much the phase has feed back by the z ero point effectivel y, set R FB1 and CFB so that the
zero point goes into the high er frequenc y than the pole fre quenc y of L and COUT. The following equations are the
pole frequency of L and COUT and the zero point frequenc y b y CFB and RFB1.
fpole ≅ 1
2 × π × L × COUT
fzero ≅ 1
2 × π × RFB1 × CFB
The transient response can be improved by setting the zero point frequency in the range of lower frequency.
However, since the gain bec omes higher in the rang e of h igh frequency, the total phase of feedback loop d elays
180° or more by setting the zero point frequenc y in the sign ificantly lower range. As a result, the gain cannot b e
0 dB or lower in the frequenc y range thus the operati on might be unstable. Determi ne the proper valu e after the
sufficient evaluation under the actual con dition.
The typical constants by our evaluation are in Table 9.
Table 9 Constant for External Parts
VOUT(s) [V] RFB1 [kΩ] RFB2 [kΩ] CFB [pF] L [μH]*1 C
OUT [μF]*1
1.1 36 43 56 3.3 10
1.8 36 18 68 3.3 10
3.3 36 8 120 3.3 10
4.0 51 9 100 3.3 10
*1. The recommend ed parts in Table 6
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICAT ION
,
PWM CONTROL SWITCHING REGULATORS
S-8550/8551 Series Rev.4.0_00
14 Seiko Instruments Inc.
Standard Circuit
1. SOT-23-5
L
ON/OFF
V
IN
+
−
+
−
C
IN
FB
VIN
CONT
VSS
C
FB
R
FB1
R
FB2
V
OUT
C
OUT
*1
*1
4.7
μ
F
3.3
μ
H
36 k
Ω
18 k
Ω
10
μ
F
68 pF
1.0
μ
F
Reference
voltage PWM comparat or
PWM control
circuit
UVLO circuit
ON/OFF
circuit
IC internal
power supply
Current limit
circuit
Error amplifier
Ground point
T r iangular wave
generation
circuit
*1. Parasitic diode
Figure 13
2. SNT-8A
L
ON/OFF
V
IN
+
−
+
−
C
IN
FB
VIN
CONT
VSS
C
FB
R
FB1
R
FB2
V
OUT
C
OUT
*1
*1
4.7
μ
F
3.3
μ
H
36 k
Ω
18 k
Ω
10
μ
F
68 pF
1.0
μ
F
Reference
voltage PWM comp arato r
PWM control
circuit
UVLO circ u it
ON/OFF
circuit
IC internal
power supply
Current limit
circuit
Error amplifier
Ground point
T r iangular wave
generation
circuit
PVSS
*1. Parasitic diode
Figure 14
Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough
evaluation using an actual application to set the constants.
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICATION
,
PWM CONTROL SWITCHING REGULATORS
Rev.4.0_00 S-8550/8551 Series
Seiko Instruments Inc. 15
Precaution
• Mount external capacitors, di odes, and inductors as clo se as poss ible to t he IC, an d make a o ne-p oint ground ing.
• Characteristics ripple voltage and spike noise occur in IC containing switching regulators. Moreover rush current
flows at the time of a power supply injection. Because these largely depend on the inductor, the capacitor and
impedance of po wer suppl y used, fully ch e ck them using an act ual ly mounte d model.
• The 1.0 μF capacitance connected bet ween the VIN and VSS pins is a bypass capacitor. It stabilizes the power
supply in the IC when application is used with a heavy load, and thus effectively works for stable switching
regulator operatio n. Allocate the bypass capac itor as c lo se to the IC as possibl e, prior itized over oth er parts.
• Although the IC contains a static electricity protection circuit, static electricity or voltage that exceeds the limit of
the protection circuit shou ld not be app lied.
• The power dissipation of the IC greatly varies depending on the size and material of the board to be connected.
Perform sufficient evaluatio n usin g an actu al ap plic ation b ef ore desig ning.
• Seiko Instruments Inc. assumes no responsibility for the way in which this IC is used on products created using
this IC or for the specifications of that product, nor does Seiko Instruments Inc. assume any responsibility for any
infringement of patents or copyrights b y products that inclu de this IC eit her in Japan or in other c ountr ies.
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICAT ION
,
PWM CONTROL SWITCHING REGULATORS
S-8550/8551 Series Rev.4.0_00
16 Seiko Instruments Inc.
Characteristics (Typical Data)
1. Example of Major Pow er Supply Dependence Characteristics (Ta = 25°C)
1. 1 Current con sum ption 1 (I
SS1
) vs. Input voltage (V
IN
)
1. 2 Current consumption during shutdown (I
SSS
) vs. Input voltage (V
IN
)
2.0 4.0 5.0 5.5
I
SS1
[μA]
500
400
300
200
100
0
V
IN
[V]
2.5 3.0 3.5 4.5
2.0 4.0 5.0 5.5
I
SSS
[μA]
1.0
0.8
0.6
0.4
0.2
0
V
IN
[V]
2.5 3.0 3.5 4.5
1. 3 Oscillation frequency (f
osc
) vs. Input voltage (V
IN
)
1. 4 Soft-start time (tSS) vs. Input voltage (VIN)
2.0 4.0 5.0 5.5
f
OSC
[MHz]
1.38
1.30
1.18
1.10
1.02
V
IN
[V]
2.5 3.0 3.5 4.5
1.06
1.14
1.22
1.26
1.34
2.0 4.0 5.0 5.5
t
SS
[ms]
1.3
1.1
1.0
0.9
0.7
V
IN
[V]
2.5 3.0 3.5 4.5
0.8
1.2
1. 5 Power MOS FET on-resistance (R
FET
) vs. Inp ut voltag e (V
IN
)
1. 6 Power MOS FET leakage current (I
LSW
) vs. Inp ut voltag e (V
IN
)
2.0 4.0 5.0 5.5
R
FET
[Ω]
0.8
0.6
0.5
0.4
0.2
V
IN
[V]
2.5 3.0 3.5 4.5
0.3
0.7
Nch
Pch
2.0 4.0 5.0 5.5
I
LSW
[μA]
0.5
0.1
0
−0.1
−0.5
V
IN
[V]
2.5 3.0 3.5 4.5
−0.4
0.4
Nch
Pch
0.2
0.3
−0.2
−0.3
1. 7 ON/ OFF pin in put volt a ge“ H” (V
SH
) vs. Input voltage (V
IN
)
1. 8 ON/OF F pin in put voltage“L” ( V
SL
) vs. Input voltage (V
IN
)
2.0 4.0 5.0 5.5
V
SH
[V]
0.9
0.6
0.3
V
IN
[V]
2.5 3.0 3.5 4.5
0.7
0.8
0.5
0.4
2.0 4.0 5.0 5.5
V
SL
[V]
0.9
0.6
0.3
V
IN
[V]
2.5 3.0 3.5 4.5
0.7
0.8
0.5
0.4
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICATION
,
PWM CONTROL SWITCHING REGULATORS
Rev.4.0_00 S-8550/8551 Series
Seiko Instruments Inc. 17
1. 9 FB voltage (VFB) vs. Input voltage (VIN)
2.0 4.0 5.0 5.5
V
FB
[mV]
612
600
588
V
IN
[V]
2.5 3.0 3.5 4.5
604
608
596
592
2. Example of Major Temperature Characteristics (Ta = −40 to 85°C)
2. 1 Current con sum ption 1 (I
SS1
) vs. Temperatu re (Ta)
2. 2 Current consumption during shutdown (I
SSS
) vs. Temperature (Ta)
−40 75 85
I
SS1
[
μA
]
500
0
−25 0 25 50
300
400
200
100
Ta [°C]
VIN = 5.5 V
VIN = 3.6 V
VIN = 2.0 V
−40 75 85
I
SSS
[
μA
]
1.0
0
−25 0 25 50
0.6
0.8
0.4
0.2
Ta [°C]
VIN = 5.5 V
VIN = 3.6 V
VIN = 2.0 V
2. 3 Oscillation frequency (f
osc
) vs. Temperature (Ta)
2. 4 Soft-start time (tSS) vs. Temperature (Ta)
−40 75 85
fOSC
[MHz]
1.32
1.08
−25 0 25 50
1.28
1.20
1.16
Ta [°C]
V
IN
= 5.5 V
V
IN
= 3.6 V
V
IN
= 2.0 V
1.12
1.24
−40 75 85
tSS
[ms]
1.3
0.7
−25 0 25 50
1.1
1.0
0.9
Ta [°C]
V
IN
= 5.5 V
V
IN
= 3.6 V
V
IN
= 2.0 V
0.8
1.2
2. 5 Power MOS FET on-resistance (R
FET
) vs. Tem pe ratu re (T a)
2. 6 Power MOS FET leakage current (I
LSW
) vs. Tem pe ratu re (T a)
−40 75 85
R
FET
[Ω]
0.8
0.2
−25 0 25 50
Ta [°C]
VIN = 5.5 V
VIN = 3.6 V
VIN = 2.0 V
VIN = 5.5 V
VIN = 3.6 V
VIN = 2.0 V
Pch Nch
0.6
0.5
0.4
0.3
0.7
−40 75 85
I
LSW
[μA]
0.5
−0.5 −25 0 25 50
Ta [°C]
VIN = 5.5 V
VIN = 5.5 V
Pch
Nch
0.1
0
−0.1
−0.4
0.4
0.2
0.3
−0.2
−0.3
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICAT ION
,
PWM CONTROL SWITCHING REGULATORS
S-8550/8551 Series Rev.4.0_00
18 Seiko Instruments Inc.
2. 7 ON/ OFF pin in put volt a ge“ H” (V
SH
) vs. Tempe r atu r e (Ta)
2. 8 ON/OF F pin in put voltage“L” ( V
SL
) vs. Temp e r atu r e (Ta)
−40 75 85
VSH
[V]
0.9
0.3 −25 0 25 50
Ta [°C]
0.6
0.7
0.8
0.5
0.4
V
IN
= 3.6 V
V
IN
= 5.5 V
V
IN
= 2.0 V
−40 75 85
VSL
[V]
0.9
0.3 −25 0 25 50
Ta [°C]
0.6
0.7
0.8
0.5
0.4
V
IN
= 5.5 V
V
IN
= 3.6 V
V
IN
= 2.0 V
2. 9 UVLO detection voltage (V
UVLO
) vs. Temperature (Ta)
2. 10 FB voltage (VFB) vs. Temperatur e (Ta)
−40 75 85
V
UVLO
[V]
1.80
1.40 −25 0 25 50
Ta [°C]
1.60
1.70
1.75
1.55
1.45
1.50
1.65
−40 75 85
V
FB
[mV]
612
588 −25 0 25 50
Ta [°C]
600
604
608
596
592
VIN = 5.5 V
VIN = 3.6 V
VIN = 2.0 V
3. Examples of Transient Response Characteristics
(Unless otherwise specified, the used parts are ones shown in
Extern al Part s Wh en Me asu ri ng Ele ct ric al Cha rac teri st ics
.)
3. 1 Powering ON (VOUT = 1.8 V, VIN = 0 V → 3.6 V, Ta = 25°C)
(1) IOUT = 1 mA (2) IOUT = 600 m A
−0.2 0.6 1.0 1.6
V
IN
, V
OUT
[V]
4
3
1
0
−1
t [ms]
I
L
[A]
0.6
0.2
0.4
−0.2
0
0 0.2 0.4 0.8
V
OUT
V
IN
I
L
2
1.2 1.4
−0.2 0.6 1.0 1.6
VIN, VOUT [V]
4
3
1
0
−1
t [ms]
IL [A]
1.5
0.5
1.0
−0.5
0
0 0.2 0.4 0.8
2
1.2 1.4
V
OUT
V
IN
I
L
3. 2 Shutdown pin response (VOUT = 1.8 V, VIN = 3.6 V, VON/OFF = 0 V → 3.6 V, Ta = 25°C)
(1) IOUT = 1 mA (2) IOUT = 600 mA
−0.2 0.6 1.0 1.6
V
ON/OFF
, V
OUT
[V]
4
3
1
0
−1
t [ms]
I
L
[A]
0.6
0.2
0.4
−0.2
0
0 0.2 0.4 0.8
2
1.2 1.4
V
OUT
V
ON/OFF
I
L
−0.2 0.6 1.0 1.6
VON/OFF, VOUT [V]
4
3
1
0
−1
t [ms]
IL [A]
1.5
0.5
1.0
−0.5
0
0 0.2 0.4 0.8
2
1.2 1.4
V
OUT
V
ON/OFF
I
L
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICATION
,
PWM CONTROL SWITCHING REGULATORS
Rev.4.0_00 S-8550/8551 Series
Seiko Instruments Inc. 19
3. 3 Power supply fluctuations (VOUT = 1.8 V, Ta = 25°C)
(1) IOUT = 1 mA, VIN = 2.6 V → 3.6 V → 2.6 V (2) IOUT = 60 0 m A, VIN = 2.6 V → 3.6 V → 2.6 V
−0.1 0.3 0.5 0.7
V
OUT
[V]
2.2
2.0
1.8
1.6
1.4
t [ms]
V
IN
[V]
3.5
2.5
1.5
0.5
4.5
0 0.1 0.2 0.4 0.6
V
OUT
V
IN
−0.1 0.3 0.5 0.7
VOUT [V]
2.2
2.0
1.8
1.6
1.4
t [ms]
VIN [V]
3.5
2.5
1.5
0.5
4.5
0 0.1 0.2 0.4 0.6
V
OUT
V
IN
3. 4 Load fluctuations (VOUT = 1.8 V, VIN = 3.6 V, Ta = 25°C)
(1) IOUT = 0.1 mA → 100 mA → 0.1 m A (2) IOUT = 0.1 mA → 300 mA → 0.1 mA
−0.1 0.3 0.5 0.7
V
OUT
[V]
1.90
1.85
1.80
1.75
1.70
t [ms]
I
OUT
[mA]
200
100
0
−100
400
0 0.1 0.2 0.4 0.6
V
OUT
I
OUT
300
−0.1 0.3 0.5 0.7
VOUT [V]
1.90
1.85
1.80
1.75
1.70
t [ms]
IOUT [mA]
200
100
0
−100
400
0 0.1 0.2 0.4 0.6
300
V
OUT
I
OUT
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICAT ION
,
PWM CONTROL SWITCHING REGULATORS
S-8550/8551 Series Rev.4.0_00
20 Seiko Instruments Inc.
Reference Data
1. Reference data for external parts
Properties of External Parts
Element Name Product Name Manufacture Characteristics
Inductor NR4018T3R3M
Taiyo Yuden Co., Ltd 3.3 μH, DCRMAX = 0.07 Ω, IMAX = 1.23 A
Input capacitor C3216X7R1E475K TDK Corporation 4.7 μF
Output capacitor C3216X7R1C106K TDK Corporation 10 μF
Caution The values of the external p arts are b ased on the mate rials provided by each man u facture r. Ho wever,
consider the characteristics of the original materials when using the above products.
2. Output current (I
OUT
) vs. Efficiency (
η
) Characteristics and Output current (I
OUT
) vs. Outp ut v ol tag e ( V
OUT
) Characteristics
2. 1 VOUT = 1.1 V (RFB1 = 36 kΩ, RFB2 = 43 kΩ)
(1) Output current (IOUT) vs. Efficiency (η) (2) Output current (IOUT) vs. Output voltage (VOUT)
0 1000
η [%]
100
01 10 100
I
OUT
[mA]
50
70
80
30
10
20
40
60
90 VIN = 2.0 V
VIN = 3.6 V
VIN = 5.5 V
0 1000
VOUT [V]
1.3
0.9 1 10 100
I
OUT
[mA]
1.1
1.2
1.0
VIN = 5.5 V
VIN = 3.6 V
VIN = 2.0 V
2. 2 VOUT = 1.8 V (RFB1 = 36 kΩ, RFB2 = 18 kΩ)
(1) Output current (IOUT) vs. Efficiency (η) (2) Output current (IOUT) vs. Output voltage (VOUT)
0 1000
η [%]
100
01 10 100
IOUT [mA]
50
70
80
30
10
20
40
60
90 V
IN
= 2.2 V
V
IN
= 3.6 V
V
IN
= 5.5 V
0 1000
V
OUT
[V]
2.0
1.6 1 10 100
IOUT [mA]
1.8
1.9
1.7
V
IN
= 5.5 V
V
IN
= 3.6 V
V
IN
= 2.0 V
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICATION
,
PWM CONTROL SWITCHING REGULATORS
Rev.4.0_00 S-8550/8551 Series
Seiko Instruments Inc. 21
2. 3 VOUT = 3.3 V (RFB1 = 36 kΩ, RFB2 = 8 kΩ)
(1) Output current (IOUT) vs. Efficiency (η) (2) Output current (IOUT) vs. Output voltage (VOUT)
0 1000
η [%]
100
01 10 100
IOUT [mA]
50
70
80
30
10
20
40
60
90 V
IN
= 3.7 V
V
IN
= 5.5 V
0 1000
V
OUT
[V]
3.5
3.1 1 10 100
IOUT [mA]
3.3
3.4
3.2
V
IN
= 5.5 V
V
IN
= 3.7 V
2. 4 VOUT = 4.0 V (RFB1 = 51 kΩ, RFB2 = 9 kΩ)
(1) Output current (IOUT) vs. Efficiency (η) (2) Output current (IOUT) vs. Output voltage (VOUT)
0 1000
η [%]
100
01 10 100
IOUT [mA]
50
70
80
30
10
20
40
60
90 V
IN
= 4.4 V
V
IN
= 5.5 V
0 1000
V
OUT
[V]
4.2
3.8 1 10 100
IOUT [mA]
4.0
4.1
3.9
V
IN
= 5.5 V
V
IN
= 4.4 V
3. Output current (IOUT) vs. Ripple voltage (Vr) Characteristics
3. 1 VOUT = 1.1 V (RFB1 = 36 kΩ, RFB2 = 43 kΩ)
(1) VIN = 3.6 V (2) VIN = 5.5 V
0 1000
Vr [mV]
50
01 10 100
I
OUT
[mA]
30
40
10
20
0 1000
Vr [mV]
50
01 10 100
I
OUT
[mA]
30
40
10
20
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICAT ION
,
PWM CONTROL SWITCHING REGULATORS
S-8550/8551 Series Rev.4.0_00
22 Seiko Instruments Inc.
3. 2 VOUT = 1.8 V (RFB1 = 36 kΩ, RFB2 = 18 kΩ)
(1) VIN = 3.6 V (2) VIN = 5.5 V
0 1000
V
r
[mV]
50
01 10 100
IOUT [mA]
30
40
10
20
0 1000
V
r
[mV]
50
01 10 100
IOUT [mA]
30
40
10
20
3. 3 VOUT = 3.3 V (RFB1 = 36 kΩ, RFB2 = 8 kΩ)
(1) VIN = 3.6 V (2) VIN = 5.5 V
0 1000
Vr [mV]
50
01 10 100
I
OUT
[mA]
30
40
10
20
0 1000
Vr [mV]
50
01 10 100
I
OUT
[mA]
30
40
10
20
3. 4 VOUT = 4.0 V (RFB1 = 51 kΩ, RFB2 = 9 kΩ)
(1) VIN = 5.5 V
0 1000
V
r
[mV]
50
01 10 100
IOUT [mA]
30
40
10
20
STEP-DOWN
,
BUILT-IN FET
,
SYNCHRONOUS RECTIFICATION
,
PWM CONTROL SWITCHING REGULATORS
Rev.4.0_00 S-8550/8551 Series
Seiko Instruments Inc. 23
Marking Specification
(1) SOT-23-5
(1) to (3) : Product code (Refer to Product name vs. Product code.)
(4) : Lot number
5 4
1 3
2
(1) (2) (3) (4)
SOT-23-5
To
p
vie
w
Product name vs. Product code
(a) S-8550 Series (b) S-8551 Series
Product Code Product Code
Product Name (1) (2) (3) Product Name (1) (2) (3)
S-8550AA-M5T1x R 5 A S-8551AA-M5T1x R 5 C
(2) SNT-8A
(1) Blank
(2) to (4) Product code (Refer to Product name vs. Product code)
(5), (6) Blank
(7) to (11) Lot num ber
SNT-8A
Top view
1
4
8
5
(9)
(6)
(2)
(10)
(7)
(3)
(11)
(8)
(4)
(5)
(1)
Product name vs. Product code
(a) S-8550 Series Product code
Product name （2） （3） （4）
S-8550AA-I8T1x R 5 A
Remark 1. x: G or U
2. Please select products of environment al code = U for Sn 100%, ha loge n- free pr oducts.
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
2.9±0.2
1.9±0.2
0.95±0.1
0.4±0.1
0.16 +0.1
-0.06
123
4
5
No. MP005-A-P-SD-1.2
MP005-A-P-SD-1.2
SOT235-A-PKG Dimensions
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
ø1.5 +0.1
-0 2.0±0.05
ø1.0 +0.2
-0 4.0±0.1
1.4±0.2
0.25±0.1
3.2±0.2
123
45
No. MP005-A-C-SD-2.1
MP005-A-C-SD-2.1
SOT235-A-Carrier Tape
Feed direction
4.0±0.1(10 pitches:40.0±0.2)
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
12.5max.
9.0±0.3
ø13±0.2
(60°) (60°)
QTY. 3,000
No. MP005-A-R-SD-1.1
MP005-A-R-SD-1.1
SOT235-A-Reel
Enlarged drawing in the central part
1.97±0.03
0.2±0.05
0.48±0.02
0.08
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
SNT-8A-A-PKG Dimensions
PH008-A-P-SD-2.0
No. PH008-A-P-SD-2.0
0.5
+0.05
-0.02
123 4
56
78
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
PH008-A-C-SD-1.0
SNT-8A-A-Carrier Tape
No. PH008-A-C-SD-1.0
Feed direction
4.0±0.1
2.0±0.05
4.0±0.1
ø1.5 +0.1
-0
ø0.5±0.1
2.25±0.05
0.65±0.05
0.25±0.05
2134
7865
5°
12.5max.
9.0±0.3
ø13±0.2
(60°) (60°)
Enlarged drawing in the central part
QTY.
PH008-A-R-SD-1.0
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
SNT-8A-A-Reel
No. PH008-A-R-SD-1.0
5,000
No.
TITLE
SCALE
UNIT mm
SNT-8A-A-Land Recommendation
Seiko Instruments Inc.
PH008-A-L-SD-4.0
0.3
0.2
0.52
2.01
0.52
No. PH008-A-L-SD-4.0
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1. (0.25 mm min. / 0.30 mm typ.)
2. (1.96 mm ~ 2.06 mm)
1.
2. 0.03 mm
3.
4. SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm).
1.
2.
1
2
※1. 䇋⊼ᛣ⛞Ⲭᓣⱘᆑᑺ(0.25 mm min. / 0.30 mm typ.)DŽ
※2. 䇋࣓ᇕ㺙Ё䯈ᠽሩ⛞Ⲭᓣ (1.96 mm ~ 2.06 mm)DŽ
⊼ᛣ1. 䇋࣓㛖ൟᇕ㺙ⱘϟ䴶ࠋϱ㔥ǃ⛞䫵DŽ
2. ᇕ㺙ϟǃᏗ㒓Ϟⱘ䰏⛞㝰ᑺ (Ң⛞Ⲭᓣ㸼䴶䍋) 䇋ࠊ0.03 mmҹϟDŽ
3. 㝰ⱘᓔষሎᇌᓔষԡ㕂䇋Ϣ⛞Ⲭᓣᇍ唤DŽ
4. 䆺㒚ݙᆍ䇋খ䯙 "SNTᇕ㺙ⱘᑨ⫼ᣛ"DŽ
www.sii-ic.com
• The information described herein is subject to change without notice.
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examples explain typical applications of the products, and do not guarantee the success of any specific
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failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.
