IS25LQ080 8M-BIT 3V- QUAD SERIAL FLASH MEMORY WITH MULTI-I/O SPI DATA SHEET Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 IS25LQ080 8M-BIT 3V- QUAD SERIAL FLASH MEMORY MULTI- I/O SPI FEATURES * Industry Standard Serial Interface - IS25LQ080: 8M-bit/ 1M-byte - 256-bytes per Programmable Page Standard - Standard SPI/ Dual SPI/ Quad SPI * High Performance Serial Flash (SPI) - 104 MHz SPI/ Dual SPI/ or Quad SPI - 416 MHz equivalent Quad SPI - 52MB/S Continuous Data Throughput - Supports SPI Modes 0 and 3 - More than 100,000 erase/program cycles(1) - More than 20-year data retention * Efficient Read and Program modes - Low Instruction Overhead Operations - Continuous data read with Byte Wrap around - Allows XIP operations (execute in place) - Outperforms X16 Parallel Flash * Low Power with Wide Temp. Ranges - Single 2.3V to 3.6V Voltage Supply - 10 mA Active Read Current - 5 A Standby Current - Temp Grades: -40C to +105C * Advanced Security Protection - Software and Hardware Write Protection - 256-Byte dedicated area, user-lockable, One Time Programmable Memory (OTP) * Industry Standard Pin-out & Pb-Free Packages - JB = 8-pin SOIC 208mil - JN = 8-pin SOIC 150mil - JK= 8-pin WSON 6x5 mm - JV = 8-pin VVSOP 150mil - KGD (call factory) * Flexible & Cost Efficient Memory Architecture - Uniform 4K-byte Sector Erase - Uniform 64K-byte Block Erase - Program from 1 to 256 bytes - Program/Erase Suspend and Resume GENERAL DESCRIPTION The IS25LQ080 (8M-bit) Serial Flash memory offers a storage solution with flexibility and performance in a simplified pin count package. ISSI's "Industry Standard Serial Interface" is for systems that have limited space, pins, and power. The IS25LQ080 are accessed through a 4-wire SPI Interface consisting of a Serial Data Input (Sl), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which also serve as multifunction I/O pins in Dual and Quad modes (see pin descriptions). The IS25xQ series of flash is ideal for code shadowing to RAM, execute in place (XIP) operations, and storing non-volatile data. The memory array is organized into programmable pages of 256-bytes each. The IS25LQ080 supports page program mode where 1 to 256 bytes of data can be programmed into the memory with one command. Pages can be erased in groups of 4K-byte sectors, 64K-byte blocks, and/or the entire chip. The uniform 4K-byte sectors and 64K-byte blocks allow greater flexibility for a variety of applications requiring solid data retention. The device supports the standard Serial Peripheral Interface (SPI), Dual/Quad output (SPI), and Dual/Quad I/O (SPI). Clock frequencies of up to 104MHz in SPI/Dual/Quad I/O modes allow for equivalent clock rates of up to 416MHz (104MHz x 4) allowing up to 52MB/S of throughput. These transfer rates can outperform 16-bit Parallel Flash memories allowing for efficient memory access for a XIP (execute in place) operation. The IS25LQ080 is manufactured using industry leading non-volatile memory technology. The devices are offered in industry standard lead-free packages. See Ordering Information for the density and package combinations available. 1. 100,000 Continuous Chip and Block cycling, 100,000 Continuous Sector cycling Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 IS25LQ080 Connection Diagrams CE# 1 8 Vcc CE# SO (IO1) 2 7 3 6 SCK 4 5 2 7 HOLD#(IO3) WP# (IO2) 3 GND GND 8 Vcc HOLD# (IO3) SO (IO1) WP# (IO2) 1 4 6 SCK 5 SI (IO0) SI (IO0) 8-pin WSON 6x5mm (Package: JK) 8-pin SOIC 208mil (Package: JB) 8-pin SOIC 150mil (Package: JN) 8-pin VVSOP 150mil (Package: JV) Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 3 IS25LQ080 PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION Chip Enable: The Chip Enable (CE#) pin enables and disables the devices operation. When CE# is high the device is deselected and output pins are in a high impedance state. When deselected the devices non-critical internal circuitries power down to allow minimal levels of power consumption while in a standby state. CE# INPUT When CE# is pulled low the device will be selected and brought out of standby mode. The device is considered active and instructions can be written to, data read, and written to the device. After power-up, CE# must transition from high to low before a new instruction will be accepted. Keeping CE# in a high state deselects the device and switches it into its low power state. Data will not be accepted when CE# is high. Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1): SI (IO0), SO (IO1) INPUT/OUTPUT This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI instructions use the unidirectional SI (Serial Input) pin to write instructions, addresses, or data to the device on the rising edge of the Serial Clock (SCK). Standard SPI also uses the unidirectional SO (Serial Output) to read data or status from the device on the falling edge of the serial clock (SCK). In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write instructions, addresses or data to the device on the rising edge of the Serial Clock (SCK) and read data or status from the device on the falling edge of SCK. Quad SPI instructions use the WP# and HOLD# pins as IO2 and IO3 respectively. WP# (IO2) INPUT/OUTPUT Write Protect: The WP# pin protects the Status Register from being written. When the WP# is low the status registers are write-protected and vice-versa for high. When the QE bit is set to "1", the WP# pin (Write Protect) function is not available since this pin is used for IO2. Hold: Pauses serial communication by the master device without resetting the serial sequence. When the QE bit of Status Register is set to "1", HOLD# pin is not available since it becomes IO3. HOLD# (IO3) INPUT/OUTPUT The HOLD# pin allows the device to be paused while it is selected. The HOLD# pin is active low. When HOLD# is in a low state, and CE# is low, the SO pin will be at high impedance. Device operation can resume when HOLD# pin is brought to a high state. When the QE bit of Status Register is set for Quad I/O, the HOLD# pin function is not available and becomes IO3 for Multi-I/O SPI mode. SCK INPUT Vcc POWER GND GROUND NC Unused Serial Data Clock: Synchronized Clock for input and output timing operations. Power: Device Core Power Supply Ground: Connect to ground when referenced to Vcc NC: Pins labeled "NC" stand for "No Connect" and should be left uncommitted. Table 1. Pin Descriptions Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 4 IS25LQ080 BLOCK DIAGRAM CE# SCK SI (IO0) SO (IO1) WP# (IO2) HOLD#(IO3) Figure 1. Flash Block Diagram Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 5 IS25LQ080 MEMORY CONFIGURATION Table 2 below illustrates the memory architecture of the device and its block and sector addresses. Memory Density Block No. Block Size (Kbytes) Block 0 64 Block 1 64 : Block 7 Block 8 : : Block 15 : 64 64 : : 64 8Mbit Sector No. Sector 0 Sector 1 : Sector 15 Sector 16 Sector 17 : Sector 31 : Sector 127 Sector 128 : : Sector 255 Sector Size (Kbytes) 4 4 : 4 4 4 : 4 : 4 4 : : 4 Address Range 000000h - 000FFFh 001000h - 001FFFh : 00F000h - 00FFFFh 010000h - 010FFFh 011000h - 011FFFh : 01F000h - 01FFFFh : 070000h - 07FFFFh 080000h - 08FFFFh : : 0F0000h - 0FFFFFh Table 2. Block/Sector Addresses of IS25LQ080 Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 6 IS25LQ080 REGISTERS STATUS REGISTER Refer to Tables 3 and 4 for Status Register Format and protected. Refer to Table 5 for the Block Write Status Register Bit Definitions. Protection bit settings. When a defined combination of BP3, BP2, BP1 and BP0 bits are set, the The BP3, BP2, BP1, BP0, QE, and SRWD are noncorresponding memory area is protected. Any program volatile memory cells that can be written by a Write or erase operations to that area will be inhibited. Status Register (WRSR) instruction. The default value of the BP3, BP2, BP1, BP0, QE and SRWD bits are set Note: Chip Erase (CHIP_ER) instruction can be to "0" from the factory. The Status Register can be executed only if the Block Protection Bits are not set read by the Read Status Register (RDSR). Refer to and locked Table 8 for the Instruction Set. The function of Status Register bits are described as follows: WIP bit: The Write in Progress (WIP) bit is read-only, and can be used to detect the progress or completion of a program or erase operation. When the WIP bit is "0", the device is ready for a write status register, program or erase operation. When the WIP bit is "1", the device is busy. WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal write enable latch. When the WEL is "0", the write enable latch is disabled, and all write operations, including write status register, page program, sector erase, block and chip erase operations are inhibited. When the WEL bit is "1", write operations are allowed. The WEL bit is set by a Write Enable (WREN) instruction. Each write register, program and erase instruction must be preceded by a WREN instruction. The WEL bit can be reset by a Write Disable (WRDI) instruction. It will automatically reset after the completion of a write instruction. BP3, BP2, BP1, BP0 bits: The Block Protection (BP3, BP2, BP1 and BP0) bits are used to define which memory portion of the entire memory area should be . SRWD bit: The Status Register Write Disable (SRWD) bits operate in conjunction with the Write Protection (WP#) signal to provide a Hardware Protection Mode. When the SRWD is set to "0", the Status Register is not write-protected. When the SRWD is set to "1" and the WP# is pulled low (VIL), the bits of Status Register (SRWD, BP3, BP2, BP1, BP0) become read-only, and a WRSR instruction will be ignored. If the SRWD is set to "1" and WP# is pulled high (VIH), the Status Register can be changed by a WRSR instruction. QE bit: The Quad Enable (QE) is a non-volatile bit in the status register that allows Quad operation. When the QE bit is set to "0", the pin WP# and HOLD# are enable. When the QE bit is set to "1", the pin IO2 and IO3 are enable. WARNING: The QE bit should never be set to a 1 during standard SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground. Status Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRWD QE BP3 BP2 BP1 BP0 WEL WIP Default values 0 0 0 0 0 0 0 0 * The default value of the SRWD, QE, BP3, BP2, BP1, and BP0 are set to "0" from the factory. Table 3. Status Register Format Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 7 IS25LQ080 Bit Name Bit 0 WIP Bit 1 WEL Bit 2 Bit 3 Bit 4 Bit 5 BP0 BP1 BP2 BP3 Bit 6 QE Bit 7 SRWD Definition Read/Write NonVolatile bit R No R/W No R/W Yes R/W Yes R/W Yes Write In Progress Bit: "0" indicates the device is ready "1" indicates a write cycle is in progress and the device is busy Write Enable Latch: "0" indicates the device is not write enabled (default) "1" indicates the device is write enabled Block Protection Bit: (Table 5) "0" indicates the specific blocks are not write-protected (default) "1" indicates the specific blocks are write-protected Quad Enable bit: "0" indicates the Quad output function is disabled (default) "1" indicates the Quad output function is enabled Status Register Write Disable: (See Table 3) "0" indicates the Status Register is not write-protected (default) "1" indicates the Status Register is write-protected Table 4. Status Register Bit Definition BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Status Register Bits BP2 BP1 0 0 0 0 0 1 0 1 1 0 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 Mbit- Protected Memory Area Protected Blocks Protected Portion None None 15 Upper 1/16 14 to 15 Upper 2/16 12 to 15 Upper 1/4 8 to 15 Upper 1/2 All blocks All 0 to 7 0 to 11 0 to 13 0 to 14 All blocks Lower 1/2 Lower 3/4 Lower 7/8 Lower 15/16 All Table 5. Block Write Protect Bits for IS25LQ080 Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 8 IS25LQ080 PROTECTION MODE There are two types of write-protection mechanisms: hardware and software. Both are used to prevent incorrect operation in a possibly noisy environment where data integrity cannot be guaranteed. HARDWARE WRITE-PROTECTION The devices provide two hardware write-protection features: a. When inputting a program, erase or write status register instruction, the number of clock pulses is checked to determine whether it is a multiple of eight before executing. Any incomplete instruction command sequence will be ignored. b. Write inhibit is 2.1V, all write sequence will be ignored when Vcc drops below 2.1V. c. The Write Protection (WP#) pin provides a hardware write protection method for BP3, BP2, BP1, BP0 and SRWD in the Status Register. Refer to the STATUS REGISTER description. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 SOFTWARE WRITE PROTECTION There are two types of software write protection features: a. Before the execution of any program, erase or write status register instruction, the Write Enable Latch (WEL) bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled first, the program, erase or write register instruction will be ignored. b. The Block Protection (BP3, BP2, BP1, BP0) bits can control whether the entire memory area or just a partial portion is write-protected. SRWD 0 1 0 WP# Low Low High Status Register Writable Protected Writable 1 High Writable Table 6. Hardware Write Protection on Status Register 9 IS25LQ080 SPI INSTRUCTIONS AND DEVICE OPERATION The instruction set for controlling the device is located in table 8 and can be fully controlled through the SPI bus. Instructions can be initiated with the falling edge of Chip Enable (CE#). The first byte of data clocked into the SI pin provides the instruction code. Data on the SI pin is sampled by SCKs (serial clock) rising edge with the most significant bit (MSB) read first. Instructions vary in length (bytes) and may be followed by address bytes, data bytes, and or dummy bytes (don't care). Sometimes the instruction will require a combination of commands to perform the function. Read instructions can be completed after any clocked bit. This design feature protects the device from unwanted writes. The timing for each instruction is illustrated in the following figures. Table 7 contains the Manufacturing and Device IDs. Product Identification Manufacture ID1 Manufacturer ID Manufacture ID2 Hex Code 9Dh 7Fh Device ID1 13h Device ID: Instructions are read on the rising edge of SCK. A full IS25LQ080 Device ID2 44h 8-bits must be clocked with CE# pulled high at the byte boundary before any command is accepted (expect for Table 7. Manufacture and Device Identification read). Hex Code Instruction Name Command Cycle* Operation RDID JEDEC ID READ RDMDID WREN WRDI RDSR WRSR READ FAST_READ FRDO FRDIO FRQO FRQIO MR ABh 9Fh 90h 06h 04h 05h 01h 03h 0Bh 3Bh BBh 6Bh EBh FFh Read Device ID and Release from power down JEDEC ID Read- Manufacturer and Device ID Read Manufacturer and Device ID Write Enable Write Disable Read Status Register Write Status Register Read Data Bytes from Memory at Normal Read Mode Read Data Bytes from Memory at Fast Read Mode Fast Read Dual Output Fast Read Dual I/O Fast Read Quad Output Fast Read Quad I/O Mode Reset PAGE_ PROG 02h Page Program Data Bytes Into Memory SECTOR_ER D7h/20h BLOCK_ER CHIP_ER D8h C7h/60h Quad page program Program/Erase suspend Program/Erase resume 32h 75h/B0h 7Ah/30h Maximum Frequency 4 Bytes 1 Byte 4 Bytes 1 Byte 1 Byte 1 Byte 2 Bytes 4 Bytes 5 Bytes 5 Bytes 3 Bytes 5 Bytes 2 Bytes 2 Byte 4 Bytes + 256B 104 MHz 104 MHz 104 MHz 104 MHz 104 MHz 104 MHz 104 MHz 33 MHz 104 MHz 104 MHz 104MHz 104 MHz 104MHz 104MHz Sector Erase 4 Bytes 104 MHz Block Erase Chip Erase Page Program Data Bytes Into Memory with Quad interface Interrupts the system to pause an program/erase CMD Resumes the program/erase CMD 4 Bytes 1 Byte 4 Bytes + 256B 1 Byte 1 Byte 4 Bytes + 265B 4 Bytes 104 MHz 104 MHz PSIR B1h Program One Time Programmable Area (OTP) RSIR 4Bh Read One Time Programmable Area (OTP) Table 8. Instruction Set Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 104 MHz 104 MHz 104 MHz 104 MHz 104 MHz 33 MHz *Note 1. Command Cycle includes Instruction Byte 10 IS25LQ080 HOLD OPERATION The HOLD# pin In SPI and Dual SPI mode allow an operation to be paused while it is actively selected (CE# is low). The HOLD function may be useful in cases where the SPI data and clock signals are shared with other devices. See example below, Configuring Multiple SPI Devices and Modes (0 or 3). The HOLD function is only available for SPI and Dual SPI operations. To initiate a HOLD operation, the device must be selected (CE# set low) and HOLD# pin pulled low. The HOLD operation will activate on the falling edge of the HOLD# signal if SCK is already low. If the SCK is not already low the HOLD condition will begin at the next falling edge of SCK. Inputs to SI will be ignored and SO will be in a high impedance state. The HOLD condition will terminate on the rising edge of the HOLD# signal if SCK signal is already low, if not, HOLD condition will terminate at the next SCK falling edge. The paused operation can now continue. CE# tHLCH tCHHL tHHCH SCK tCHHH tHZ tLZ SO SI HOLD# Figure 2. HOLD Timing Diagram Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 11 IS25LQ080 CONFIGURING MULTIPLE SPI DEVICES & MODE 0 AND 3 COMPATIBLE Multiple devices can be connected together on the SPI serial bus and controlled by a SPI Master controller. Figures 3 and 4 shows how a microcontroller can be connected to control multiple SPI devices. SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 is the normal state of the SCK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. The serial clock remains at "0" (SCK = 0) for Mode 0 and for Mode 3 the clock remains at "1" (SCK = 1). Refer to Figure 3 and 4. In both modes, the input data is latched on the rising edge of Serial Clock (SCK), and the output data is available from the falling edge of SCK. These devices are designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of any controller equipped with a SPI interface. For Mode 0 the CLK signal is normally low on the falling and rising edges of CE#. For Mode 3 the CLK signal is normally high on the falling and rising edges of CE#. SDO SPI Interface (0,0) or (1,1) SDI SCK SCK SO SI SCK SO SI SCK SO SI SPI Master (i.e. Microcontroller) SPI Memory Device CS3 CS2 SPI Memory Device SPI Memory Device CS1 CE# CE# WP# HOLD# CE# WP# HOLD# WP# HOLD# Note: 1. The Write Protect (WP #) and Hold (HOLD #) signals should be driven high or low as necessary. Figure 3. Conceptual Diagram using an SPI Master with Multiple SPI Flash Memory Devices Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 12 IS25LQ080 SCK Mode 0 (0,0) SCK Mode 3 (1,1) SI MSB Input mode SO MSB Figure 4. SPI Mode 0 and 3 Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 13 IS25LQ080 RDID (ABh): READ DEVICE ID AND RELEASE FROM POWER-DOWN The read device identification (RDID) instruction is for reading out an 8-bit Electronic Signature whose value is shown in Table 7 as Device ID1. The RDID instruction code is followed by three dummy bytes, for a total of four command cycles, each bit being latched-in on SI during the rising edge of SCK. Then Device ID1 is shifted out on SO with the MSB first, each bit being shifted out during the falling edge of SCK. The RDID instruction is ended when CE# goes high. Device ID1 outputs repeatedly if clock cycles continue on SCK and CE# is held low. To release the device from the RDID instruction, drive CE# high as shown in figure 5. The RDID instruction can also release the device from the power-down state. It is a multi-purpose instruction. To release the device from the power-down state, the instruction is issued by driving the CE# pin low and shifting the instruction code "ABh" and driving CE# high. The CE# pin must remain high during the tRES time duration before the device will resume normal operation and other instructions are accepted. If the Release from Power-down instruction is issued while an Erase, Program or Write cycle is in process the instruction is ignored and will not have any effects on the current cycle. The JEDEC ID read instruction is recommended for new designs. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 14 IS25LQ080 CE# 0 1 7 8 9 38 31 46 47 39 54 SCK INSTRUCTION SI SO 3 Dummy Bytes 1010 1011b HIGH IMPEDANCE Device ID1 Device ID1 Device ID1 Read Device ID TRES Release from Power-Down Figure 5. Read Device ID (Top Diagram) and Release from Power-Down (Bottom Diagram) Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 15 IS25LQ080 JEDEC ID READ (9Fh): Read Manufacture Product Identification by JEDEC ID For compatibility reasons several instructions are The command shifts out the most significant bit on the available for electronically obtaining the identity of the falling edge of SCK. device. The JEDEC ID read command was adopted to allow compatibility and identification. If CE# stays low after the last bit of Device ID2 the electronic identification is repeated continuously until This instruction is initiated by driving the CE# pin low CE# is pulled high. and shifting the instruction code "9Fh". The JEDEC ID READ instruction allows the user to read Manufacturer ID1, Device ID1, and Device ID2. Figure 6. Read Product Identification by JEDEC ID READ Sequence RDMDID (90h): READ DEVICE MANUFACTURER AND DEVICE ID OPERATION The Read Device Manufacturer and Device ID instruction is very similar to the RDID instruction. The RDMDID instruction is initiated by driving the CE# pin low and shifting the instruction code "90h" followed by three bytes. Two dummy bytes plus one address byte (A7~A0), each bit being latched-in on SI during the rising edge of SCK. The Manufacture and Device ID can be read Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 continuously, alternating from one to the others. The instruction is completed by driving CE# high. If the last bit (A7~A0) is initially set to 0, then Manufacture ID1 -> Device ID1 -> Manufacture ID2 is shifted out on SO with the MSB first. Each bit shifted out during the falling edge of SCK. If A0 = 1, then the output sequence becomes Device ID1 -> Manufacture ID1 -> Manufacture ID2. 16 IS25LQ080 CE# 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 1 A0 ... SCK 3 - BYTE ADDRESS SIO INSTRUCTION = 1001 0000b 23 22 42 43 ... 3 21 2 HIGH IMPEDANCE SO CE# 32 33 34 35 36 37 38 39 40 41 44 45 46 47 2 1 0 SCK SIO Data Out1 SO 7 6 5 4 3 Data Out2 2 1 0 7 6 5 4 3 Figure 7. Read Product Identification by RDMDID READ Sequence Figure 7. (cont.) Read Product Identification by RDMDID READ Sequence Note : 1. ADDRESS A0 = 0, will output the Manufacture ID1 -> Device ID1 -> Manufacture ID2 2. ADDRESS A0 = 1, will output the Device ID1 -> Manufacture ID1 -> Manufacture ID2 Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 17 IS25LQ080 WREN (06h): WRITE ENABLE OPERATION The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit is reset to the write protected state after power-up. The WEL bit must be write enabled before any write operation, including sector, block erase, chip erase, page program, and write status register. The WEL bit will be reset to the write-protect state automatically upon completion of a write operation. The WREN instruction is required before any above operation is executed. Figure 8. Write Enable Sequence WRDI (04h): WRITE DISABLE OPERATION The Write Disable instruction resets the Write Enable reset after power-up and upon completion of the Write Latch (WEL) bit in the Status Register to a 0. The Write Status Register, Page Program, Quad Page Program, Disable instruction is entered by driving CE# low, Sector Erase, Block Erase and Chip Erase. shifting the instruction code "04h" into the SI pin and then driving CE# high. The WEL bit is automatically Figure 9. Write Disable Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 18 IS25LQ080 RDSR (05h): READ STATUS REGISTER OPERATION The Read Status Register (RDSR) instruction provides access to the Status Register. During the execution of a program, erase or write status register operation, all other instructions will be ignored except the RDSR instruction, which can be used to check the progress or completion of an operation by reading the WIP bit of the Status Register. The instruction is entered by driving CE# low and shifting the instruction code "05h"into the SI pin on the rising edge of SCK. The status register bits are then shifted out on the SO pin at the falling edge of SCK with most significant bit (MSB) first. The Read Status Register instruction may be used at any time, even while a Program, Erase or Write Status Register cycle is in progress. This allows the WIP status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously. The instruction is completed by driving CE# high. Figure 10. Read Status Register Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 19 IS25LQ080 WRSR (01h): WRITE STATUS REGISTER OPERATION The Write Status Register (WRSR) instruction allows the Status Register to be written. A Write Enable instruction must previously have been executed for the device to accept the Write Status Register Instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving CE# low, sending the instruction code "01h", and then writing the status register data into the non-volatile BP3, BP2, BP1, BP0, QE, and SRWD bits. The user can enable or disable the block protection and status register write protection features by writing "0"s or "1"s. Figure 11. Write Status Register Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 20 IS25LQ080 READ (03h): READ DATA OPERATION The READ instruction code is transmitted via the SI line, followed by three address bytes (A23 - A0) of the first memory location to be read. A total of 24 address bits are shifted in, but only AMS (most significant address) - A0 are decoded. The remaining bits (A23 - AMS) are ignored. The first byte addressed can be at any memory location. Upon completion, any data on the Sl pin will be ignored. Refer to Table 9 for the related Address Key. The first byte data (D7 - D0) addressed is then shifted out on the SO line, MSB first. A single byte of data, or up to the whole memory array, can be read out in one READ instruction. The address is automatically incremented after each byte of data is Address AN (AMS - A0) IS25LQ080 A21 - A0 Don't Care Bits A23 - A22 shifted out. The read operation can be terminated at any time by driving CE# high (VIH). When the highest address of the devices is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read in one continuous READ instruction. If a Read Data instruction is issued while an Erase, Program, or Write cycle is in process (WIP=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of fC (see AC Electrical Characteristics). Table 9. Address Key Figure 12. Read Data Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 21 IS25LQ080 FAST_READ (0Bh): FAST READ DATA OPERATION The FAST_READ instruction code is followed by three address bytes (A23 - A0) and a dummy byte (8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of SCK. The dummy byte allows the devices internal circuits additional time for setting up the initial address. During the dummy cycle the data value on the SI pin is a "don't care". The FAST_READ instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of fCT (see AC Electrical Characteristics). Figure 13. Fast Read Data Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 22 IS25LQ080 FRDO (3Bh): FAST READ DUAL OUTPUT OPERATION The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast_Read (0Bh) instruction except that data is output on two pins. This allows data to be transferred from the device at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code. Similar to the Fast_Read instruction, FRDO instruction can operate at the highest possible frequency of fCT (see AC Electrical Characteristics). address. The input data during the dummy byte is "don't care". The first byte addressed can be at any memory location. The address is automatically incremented after each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single FRDO instruction. FRDO instruction is terminated by driving CE# high (VIH). If a FRDO This is accomplished by adding 1 dummy byte after the instruction is issued while an Erase, Program or Write 24-bit address as. The dummy cycle allow the device's cycle is in process (WIP=1) the instruction is ignored internal circuits additional time for setting up the initial and will not have any effects on the current cycle CE# 0 1 2 3 4 5 6 7 8 9 10 11 SCK 28 30 31 2 1 0 29 ... 3 - BYTE ADDRESS SI INSTRUCTION = 0011 1011b 23 22 21 ... 3 HIGH IMPEDANCE SO CE# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 6 4 2 0 6 4 2 0 6 1 7 SCK IO0 HIGH IMPEDANCE DATA OUT 1 IO1 HIGH IMPEDANCE 7 5 3 DATA OUT 2 1 7 5 3 Figure 14. Fast Read Dual-Output Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 23 IS25LQ080 FRDIO (BBh): FAST READ DUAL I/O OPERATION The FRDIO instruction is similar to the FRDO instruction, but allows the address bits to be input two bits at a time. This may allow for code to be executed directly from the SPI in some applications (XIP). The FRDIO instruction code is followed by three address bytes (A23 - A0) and a mode byte, transmitted via the IO0 and IO1 lines, with each pair of bits latched-in during the rising edge of SCK. The address MSB is input on IO1, the next bit on IO0, and continues to shift in alternating on the two pins. The mode byte contains the value Ax, where x is a "don't care" value. The MSB is output on IO1, while simultaneously the next bit is output on IO0. The first byte addressed can be at any memory location. The address is automatically incremented after each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single FRDIO instruction. FRDIO instruction is terminated by driving CE# high (VIH). The device remains in this mode until it receives a Mode Reset (FFh) command. In subsequent FRDIO execution, the command code is not input, saving The first data byte addressed is shifted out on the IO1 timing cycles. If a FRDIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) and IO0 lines, with each pair of bits shifted out at a maximum frequency fCT, during the falling edge of SCK. the instruction is ignored and will not have any effects on the current cycle CE# 0 2 1 3 4 5 6 8 7 9 10 SCK 11 18 19 20 21 ... MODE BITS 3 - BYTE ADDRESS IO0 INSTRUCTION = 1011 1011b 22 21 19 ... 2 0 6 4 23 22 20 ... 3 1 7 5 IO1 CE# 22 23 24 25 26 6 4 2 27 28 29 30 4 2 31 SCK IO0 0 6 DATA OUT 1 IO1 7 5 3 0 6 1 7 DATA OUT 2 1 7 5 3 Figure 15. Fast Read Dual I/O Sequence (with command decode cycles) Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 24 IS25LQ080 CE# 0 1 2 3 10 11 13 14 15 16 17 18 19 20 21 6 4 2 0 6 4 ... SCK 3 - BYTE ADDRESS IO0 12 22 21 19 ... 2 MODE BITS 0 6 4 DATA OUT 1 IO1 23 22 20 ... 3 1 7 5 7 5 3 DATA OUT 2 1 7 5 Figure 16. Fast Read Dual I/O Sequence (without command decode cycles) FRQO (6Bh): FAST READ QUAD OUTPUT OPERATION The FRQO instruction code is followed by three address bytes (A23 - A0) and a dummy byte (8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of SCK. The first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits shifted out at a maximum frequency fCT, during the falling edge of SCK. The first bit (MSB) is output on IO3, while simultaneously the second bit is output on IO2, and the third bit is output on IO1, etc. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 The first byte addressed can be at any memory location. The address is automatically incremented after each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single FRQO instruction. FRQO instruction is terminated by driving CE# high (VIH). If a FRQO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is ignored and will not have any effects on the current cycle. 25 IS25LQ080 CE# 0 1 2 3 4 5 6 7 8 9 10 11 28 30 31 2 1 0 47 48 29 ... SCK 3 - BYTE ADDRESS SI INSTRUCTION = 0110 1011b 23 22 21 42 43 ... 3 HIGH IMPEDANCE SO CE# 32 33 34 35 36 37 38 39 40 41 44 45 46 SCK DATA OUT 1 IO0 IO1 HIGH IMPEDANCE IO2 HIGH IMPEDANCE IO3 DATA OUT 2 ... DATA OUT n 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 Figure 17. Fast Read Quad-Output Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 26 IS25LQ080 FRQIO (EBh): FAST READ QUAD I/O OPERATION The FRQIO instruction is similar to the FRQO instruction, but allows the address bits to be input four bits at a time. This may allow for code to be executed directly from the device in some applications (XIP). The FRQIO instruction code is followed by three address bytes (A23 - A0) and a mode byte, transmitted via the IO0, IO1, IO2, and IO3 lines, with each group of four bits simultaneously latched-in during the rising edge of SCK. The mode byte contains the value Ax, where x is a "don't care" value. After four dummy clocks, the first data byte addressed is shifted out. Each group of four bits are shifted out at a maximum frequency fCT during the falling edge of SCK. Figure 18 illustrates the timing sequence. The first byte addressed can be at any memory location. The address is automatically incremented Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 after each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single FRQIO instruction. FRQIO instruction is terminated by driving CE# high. The device expects the next operation to be another FRQIO and will remain in this mode until it receives a Mode Reset (FFh) command. In subsequent FRDIO execution, the command code does not need to be entered thus reducing the overhead for fast data readout. See Figure 19. If a FRQIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is ignored and will not have any effects on the current cycle. 27 IS25LQ080 CE# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK 3 - BYTE ADDRESS IO0 INSTRUCTION = 1110 1011b 20 16 12 MODE BITS 8 4 0 4 IO1 21 17 13 9 5 1 5 IO2 22 18 14 10 6 2 6 IO3 23 19 15 11 7 3 7 CE# 16 17 18 19 20 21 22 23 24 25 26 27 SCK 4 dummy cycles DATA OUT 1 DATA OUT 2 DATA OUT 3 DATA OUT 4 IO0 4 0 4 0 4 0 4 0 4 IO1 5 1 5 1 5 1 5 1 5 IO2 6 2 6 2 6 2 6 2 6 IO3 7 3 7 3 7 3 7 3 7 Figure 18. Fast Read Quad I/O Sequence (with command decode cycles) Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 28 IS25LQ080 CE# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK 3 - BYTE ADDRESS MODE BITS 4 Dummy Clock IO0 20 16 12 8 4 0 4 IO1 21 17 13 9 5 1 5 IO2 22 18 14 10 6 2 6 IO3 23 19 15 11 7 3 7 DATA OUT 1 DATA OUT 2 Figure 19. Fast Read Quad I/O Sequence (without command decode cycles) Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 29 IS25LQ080 MR (FFh): MODE RESET OPERATION The Mode Reset command is used to conclude subsequent FRDIO and FRQIO operations. It resets the Mode bits to a value that is not Ax. It should only be executed after an FRDIO or FRQIO operation and is recommended as the first command after a system reset. Figure 20 illustrates the difference in timing sequence for a Mode Reset issued after the FRDIO or FRQIO operation. Mode Reset for Dual I/O Mode Reset for Quad I/O CE# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK SIO SI SO INSTRUCTION = 1111 1111b INSTRUCTION = 1111 1111b HIGH IMPEDANCE Figure 20. Mode Reset Command Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 30 IS25LQ080 PAGE_PROG (02h): PAGE PROGRAM OPERATION The Page Program (PAGE_PROG) instruction allows from 1 to 256 bytes of data to be programmed into the device with a single operation. Memory areas protected by the Block Protection bits (BP3, BP2, BP1, and BP0) cannot be programmed. A PAGE_PROG instruction which attempts to program into a page that is write-protected will be ignored. The Write Enable Latch (WEL) bit must be set to 1 before the execution of a PAGE_PROG instruction. Once the device is selected (CE# = low) the PAGE_PROG instruction code, three address bytes, and program data (1 to 256 bytes) are input via the Sl line. Program operation will start immediately after CE# is pulled high. If more than 256 bytes of data are sent to a page, the address counter rolls over within the same page, and any previously latched in data is overwritten. The Page Program operation does not need to start at any specific address and can be used to partially write a page. If the end of the page is reached, the address will wrap around to the beginning of the page and any previous data will be overwritten. During a program operation, all instructions will be ignored except the RDSR instruction. The progress or completion of the program operation can be determined by reading the WIP bit of the Status Register via a RDSR instruction. If the WIP bit is "1", the program operation is still in progress. If WIP bit is "0", the program operation has completed. Note: A program operation can alter "1"s into "0"s, but an erase operation is required to change "0"s back to "1"s. A byte cannot be reprogrammed without first erasing the whole sector or block. Figure 21. Page Program Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 31 IS25LQ080 Quad Page Program (32h): Quad Input Page Program Operation The Quad Page Program instruction allows from 1 to 256 bytes of data to be programmed into the device with a single operation. Memory areas protected by the Block Protection bits (BP3, BP2, BP1, and BP0) cannot be programmed. A Quad Page Program instruction which attempts to program into a page that is write-protected will be ignored. Before the execution of the Quad Page Program instruction, the QE bit in the status register must be set to "1", and the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction. . Once the device is selected (CE# = low) the Quad Page Program instruction code, three address bytes, and program data (1 to 256 bytes) via the four pins (IO0, IO1, IO2 and IO3). Program operation will start immediately after CE# is pulled high. The Quad Page Program operation does not need to start at any specific address and can be used to partially write a page. If the end of the page is reached, the address will wrap around to the beginning of the page and any previous data will be overwritten. During a program operation, all instructions will be ignored except the RDSR instruction. The progress or completion of the program operation can be determined by reading the WIP bit of the Status Register via a RDSR instruction. If the WIP bit is "1", the program operation is still in progress. If the WIP bit is "0", the program operation has completed. Note: A program operation can alter "1"s into "0"s, but an erase operation is required to change "0"s back to "1"s. A byte cannot be reprogrammed without first erasing the whole sector or block. If more than 256 bytes of data are sent to a page, the address counter rolls over within the same page, and any previously latched in data is overwritten. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 32 IS25LQ080 CE# 0 2 1 3 4 5 6 7 8 9 10 11 28 29 30 31 1 0 ... SCK 3 - BYTE ADDRESS IO0 INSTRUCTION = 0101 0010b 00110010b 23 22 21 ... 3 2 IO1 IO2 IO3 CE# 32 33 34 35 36 37 38 39 SCK DATA IN 1 IO0 DATA IN 2 ... DATA IN n 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 IO2 6 2 6 2 6 2 6 2 6 IO3 7 3 7 3 7 3 7 3 7 IO1 Figure 22. Quad Page Program Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 33 IS25LQ080 ERASE OPERATION The memory array is organized into uniform 4 Kbyte sectors or 64 Kbyte uniform blocks (a block consists of sixteen adjacent sectors). BLOCK_ER (D8h): BLOCK ERASE OPERATION The Block Erase (BLOCK_ER) instruction erases a 64 Kbyte block. Before the execution of a BLOCK_ER Before a byte can be reprogrammed, the sector or instruction the Write Enable Latch (WEL) must be set block that contains the byte must be erased (erasing via a Write Enable (WREN) instruction. The WEL is sets bits to "1"). In order to erase the devices, there are reset automatically after the completion of a block three erase instructions available: Sector Erase erase operation. (SECTOR_ER), Block Erase (BLOCK_ER) and Chip Erase (CHIP_ER). A sector erase operation allows any A BLOCK_ER instruction is entered after CE# is pulled individual sector to be erased without affecting the data low to select the device and stays low during the entire in other sectors. A block erase operation erases any instruction sequence. The BLOCK_ER instruction code individual block. A chip erase operation erases the and three address bytes are input via SI. Erase whole memory array of a device. A sector erase, block operation will start immediately after CE# is pulled erase, or chip erase operation can be executed prior to high. The internal control logic automatically handles any programming operation. the erase voltage and timing. Refer to Figure 24 for Block Erase Sequence. During an erase operation all instruction will be ignored except the Read Status Register (RDSR) instruction. The progress or completion of the erase operation can CHIP_ER COMMAND (C7h/60h): be determined by reading the WIP bit in the Status Register using a RDSR instruction. If the WIP bit is "1", the erase operation is still in progress. If the WIP bit is CHIP ERASE OPERATION The CHIP_ER instruction supports dual instructions of "0", the erase operation has been completed. C7h or 60h. Before the execution of CHIP_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is SECTOR_ER (D7h/20h): reset automatically after completion of a chip erase operation. SECTOR ERASE OPERATION The SECTOR_ER instruction supports dual The CHIP_ER instruction is entered after CE# is pulled instructions of D7h or 20h and erases a 4 Kbyte sector. low to select the device and stays low during the entire Before the execution of a SECTOR_ER instruction the instruction sequence. The CHIP_ER instruction code is Write Enable Latch (WEL) must be set via a Write input via SI. Erase operation will start immediately after Enable (WREN) instruction. The WEL bit is reset CE# is pulled high. The internal control logic automatically after the completion of an erase automatically handles the erase voltage and timing. operation. Refer to Figure 25 for Chip Erase Sequence. The SECTOR_ER instruction is entered after CE# is pulled low to select the device and stays low during the entire instruction sequence. The SECTOR_ER instruction code and three address bytes are input via SI. Erase operation will start immediately after CE# is pulled high. The internal control logic automatically handles the erase voltage and timing. Refer to Figure 23 for Sector Erase Sequence. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 34 IS25LQ080 Figure 23. Sector Erase Sequence Figure 24. Block Erase Sequence Figure 25. Chip Erase Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 35 IS25LQ080 One Time Programmable Secure Area (OTP) : 255 Bytes of OTP + 1 Control Byte PSIR (B1h): Program Security Information instruction The PSIR command is used to program the 255 Bytes (plus one additional control Byte) of secured memory area set aside for one time programmable security area. Information can be stored in the array but not altered. Passcodes, Unique IDs, Identifiers, etc. can be stored in this area to prevent counterfeiting or even unwanted access. Before instructions can be accepted a write enable (WREN) instruction must have been previously executed to set the write enable latch (WEL) bit. Once the device has been selected via the CE# pin, the instruction code is followed by three address bytes to program the secured area and up to 255 bytes of data (plus 1 control Byte) to the SI line. CE# pin must be pulled high after the eighth bits of the last data byte has been latched in, otherwise the instruction is not executed. If more than 255 bytes of data + 1 Control Byte is sent to the secured area the address counter may roll over and re-write the secured information. Warning: Do not attempt to write more than the 256 Bytes to the OTP area After CE# pin is driven high, the self-timed page program cycle (whose duration is tpotp) is initiated. While the program PSIR cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed program cycle, and it is 0 when it is completed. At some unspecified time before the cycle is complete, the write enable latch (WEL) bit is reset. CE# 0 1 2 3 4 5 6 8 7 9 10 11 28 29 30 31 2 1 0 ... SCK SI INSTRUCTION = 1011 0001b 23 22 MSB ... 21 24-bit address CE# 32 33 34 35 36 37 38 39 40 41 42 43 ... SCK MSB SI 7 6 5 4 3 2 1 0 Data Byte 1 7 6 5 Data Byte 2 ... Data Byte n Note: 1 n 256 2. The security area is from 000000h to 0000FEh. 3. The protection lock bit is in the address 0000FFh Figure 26. Program Security Information Row Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 36 IS25LQ080 Locking the Secure (OTP) Memory Bit 0 of byte 256 is used to permanently lock the OTP memory array. 1. When bit 0 of byte 256 = '1', the 255 bytes of the OTP memory array can be programmed. 2. When bit 0 of byte 256 = `0', the 255 bytes of the OTP memory array is read-only and cannot be programmed anymore. Once bit 0 of the control byte has been programmed to `0', it can no longer be set to `1'. Therefore, as soon as bit 0 of byte 256 (control byte) is set to `0', the 255 bytes of the OTP memory array permanently become read-only. Any program instruction issued while an erase, program, or write cycle is in progress is rejected without having any effect on the current instruction. OTP control byte Byte Byte Byte255 255 Byte256 256 Byte1 Byte2 X X X X X Bit 1~bit 7 do not care X X Bit 0 When bit 0 = 0 the 256 OTP bytes become read only Figure 27. Control Byte to lock security memory Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 37 IS25LQ080 RSIR (4Bh): Read Security Information Area The RSIR instruction reads the security memory. There is no rollover mechanism while reading the secured area. The read instruction must be sent with the maximum of 256 bytes to read, once the 256th byte has been read, the same (256th) byte continues being read on the SO pin revealing the locked or unlocked status of the Control Byte. CE# 0 1 2 3 4 5 6 8 7 9 10 11 28 29 30 31 2 1 0 32 33 7 6 34 35 36 37 38 39 4 3 2 1 ... SCK SI INSTRUCTION = 0100 1011b 23 22 MSB 21 ... 24-bit address SO 5 0 Data Out0 CE# 40 41 42 43 44 45 46 47 ... SCK SI MSB SO 7 6 5 4 3 2 1 0 Data outpur 1 7 6 5 Data output 2 ... Data output N Note: 1 n 256 2. The security area is from 000000h to 0000FEh. 3. The protection lock bit is in the address 0000FFh Figure 28. Read Security information instruction Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 38 IS25LQ080 Program/Erase Suspend (75h/B0h) The Program/Erase Suspend instruction (75h/B0h) allows the system to interrupt a Sector Erase, Block Erase, or Page Program operation. Erase instructions (20h, D7h, D8h, C7h, 60h) are not allowed during the Erase Suspend instruction. Erase Suspend is valid only during the Sector or Block erase operation. If Erase Suspend is issued during a chip erase operation it will be ignored. Program instructions (02h, 32h, B1h) are not allowed during Program Suspend. Program Suspend is valid only during the Page_PROG or Quad Page Program operation. A maximum time of Tws (See AC Characteristics) is required to elapse before any new read or program instructions are issued. The WEL bit in the Status Register will clear to 0 after an Erase Suspend instruction. Unexpected power off during the Erase suspend state will reset the device and release the suspend state. The data within the page, sector, or block that was being suspended may become corrupted. Figure 29. Program/Erase Suspend Instruction shown with 75h (Alternatively B0h can be used) Program/Erase Resume (7Ah/30h) The Program/Erase Resume instruction must be written to resume the Sector Erase, Block Erase, or Page Program operations after a Program/Erase suspend. Poll the WIP bit in the Status register or wait the specified time TSE and TBE. The total time before and after a suspend function will not exceed TSE or TBE when resuming a sector erase or block erase respectively. Resume instructions will be ignored if a Program/Erase Suspend operation is still active. Resume instruction is ignored if the previous Program/Erase Suspend operation was interrupted by an unexpected power off. Figure 30. Program/Erase Resume Instruction 7Ah (Alternatively 30h can be used) *Note: 1. 500ns delay needed from write command to suspend command 2. 1ms delay needed from Erase Resume to Erase Suspend Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 39 IS25LQ080 SECTOR LOCK/UNLOCK FUNCTIONS SECTOR UNLOCK OPERATION (SECUNLOCK, 26h) The Sector Unlock command allows the user to select a specific sector to allow program and erase operations. This instruction is effective when the blocks are designated as write-protected through the BP0, BP1, BP2, and BP3 bits in the Status Register. Only one sector can be enabled at any time. If many SECUNLOCK commands are input, only the last sector designated by the last SECUNLOCK command will be unlocked. The instruction code is followed by a 24-bit address specifying the target sector, but A0 through A11 are not decoded. The remaining sectors within the same block remain as read-only. Figure 8.30 Sector Unlock Sequence CE # Mode 3 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 1 0 SCK Mode 0 3-byte Address SI SO Instruction = 26h 23 22 21 ... 3 2 High Impedance Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 40 IS25LQ080 SECTOR LOCK OPERATION (SECLOCK, 24h) The Sector Lock command relocks a sector that was previously unlocked by the Sector Unlock command. The instruction code does not require an address to be specified, as only one sector can be enabled at a time. The remaining sectors within the same block remain in read-only mode. Figure 8.31 Sector Lock Sequence CE # Mode 3 0 1 2 3 4 5 6 7 SCK Mode 0 SI SO Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 Instruction = 24h High Impedance 41 IS25LQ080 ABSOLUTE MAXIMUM RATINGS Storage Temperature -55oC to +125oC Standard Package Lead-free Package Input Voltage with Respect to Ground on All Pins (2) All Output Voltage with Respect to Ground VCC (2) 240oC for 3 Seconds 260oC for 3 Seconds -0.5 V to VCC + 0.5 V -0.5 V to VCC + 0.5 V -0.5 V to +6.0 V Surface Mount Lead Soldering Temperature Table 10. Absolute Max Ratings Notes: 1. Applied conditions greater than those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. The functional operation of the device conditions that exceed those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affect device reliability. 2. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot VCC by + 2.0 V for a period of time not to exceed 20 ns. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot GND by -2.0 V for a period of time not to exceed 20 ns. DC AND AC OPERATING RANGE Part Number Operating Temperature Vcc Power Supply IS25LQ080 Extended Grade -40oC to +105oC 2.30 V - 3.60 V Table 11. Voltage and Temperature Ratings Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 42 IS25LQ080 DC CHARACTERISTICS Applicable over recommended operating range from: TAC = -40C to +105C, VCC = 2.70 V to 3.60 V (unless otherwise noted). Symbol Parameter ICC1 Vcc Active Read Current ICC2 Vcc Program/Erase Current ISB1 ISB2 Vcc Standby Current CMOS Vcc Standby Current TTL ILI ILO VIL VIH VOL VOH Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Condition VCC = 3.60V at 33 MHz, SO = Open VCC = 3.60V at 33 MHz, SO = Open VCC = 3.60V, CE# = VCC VCC = 3.60V, CE# = VIH to VCC Min VIN = 0V to VCC VIN = 0V to VCC -0.5 0.7VCC 2.30V <VCC< 3.60V IOL = 2.1 mA IOH = -100 A Typ Max Units 10 15 mA 15 30 mA 5 30 3 A mA 1 1 0.3Vcc VCC+0.3 0.45 A A V V V V VCC - 0.2 Table 12. DC Characteristics Table Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 43 IS25LQ080 AC CHARACTERISTICS Applicable over recommended operating range from TA = -40C to +105C, VCC = 2.70 V to 3.60 V CL = 1 TTL Gate and 30 pF (unless otherwise noted). Symbol fCT fC tRI tFI tCKH tCKL tCEH tCS tCH Parameter Clock Frequency for fast read mode Clock Frequency for read mode Input Rise Time Input Fall Time SCK High Time SCK Low Time CE# High Time CE# Setup Time CE# Hold Time Min 0 0 tDS tDH tHS tHD tV tOH Data In Setup Time Data in Hold Time Hold Setup Time Hold Time Output Valid Output Hold Time Normal Mode 2 2 15 15 tLZ tHZ tDIS tSE tBE tCE tPP tres tw Hold to Output Low Z Hold to Output High Z Output Disable Time Sector Erase Time (4KB) Block Erase Time (64KB) Chip Erase Time (8Mb) Page Program Time Time required after release from Power Down Write Status Register time CE# High to next Instruction after Suspend TWS Typ Max 104 33 8 8 4 4 25 10 5 8 0 120 250 3 0.5 5 200 200 100 300 1000 6 1 3 50 20 Units MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms s ms s ms s Table 13. AC Characteristics Table Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 44 IS25LQ080 AC CHARACTERISTICS (CONTINUED) Figure 31. SERIAL INPUT/OUTPUT TIMING (1) Note: 1. For SPI Mode 0 (0,0) Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 45 IS25LQ080 AC CHARACTERISTICS (CONTINUED) Figure 32. HOLD TIMING PIN CAPACITANCE (f = 1 MHz, T = 25C ) CIN COUT Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0 V VOUT = 0 V Note: These parameters are characterized but not 100% tested. Table. 14 Pin Capacitance 30pF Figure 33. Output load test and input test waveform and measurement levels Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 46 IS25LQ080 POWER-UP AND POWER-DOWN At Power-up and Power-down, the device must not be selected until Vcc reaches Vcc(min) during power-up and tVCE has elapsed or Vcc has reached Vss at Power-down. VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, Vcc is still below Vcc(min). No instructions should be sent until: - Vcc passes the VWI threshold and tPUW delay has elapsed - Vcc passed the Vcc(min) level and tVCE delay has elapsed For most applications it is recommended that a simple pull-up resistor on CE# can be used to insure safe and proper Power-up and Power-down sequences. At Power-up, the device is in the following state: - The device is in the Standby mode - The Write Enable Latch (WEL) bit is reset To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is incorporated. The logic inside the device holds reset while Vcc is less than the POR threshold value (Vwi) during power up, the device does not respond to any instruction until a time delay of tPUW has elapsed after the moment that Vcc rises above the At Power-down, when Vcc drops from the operating voltage to below the Vwi, all write operations are disabled and the device does not respond to any instructions. Vcc Vcc(max) All Write Commands are Rejected Chip Selection Not Allowed Vcc(min) Reset State V (write inhibit) tVCE Read Access Allowed Device fully accessible tPUW Time Figure 34. Power up Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 47 IS25LQ080 PROGRAM/ERASE PERFORMANCE Parameter Sector Erase Time Typ 120 Max 300 Unit ms Remarks From writing erase command to erase completion Block Erase Time Chip Erase Time Page Programming Time Byte Program 250 3 0.5 8 1000 6 1 25 ms s ms us From writing erase command to erase completion From writing erase command to erase completion From writing program command to program completion Note: These parameters are characterized and are not 100% tested. RELIABILITY CHARACTERISTICS(1) Endurance(2) Data Retention ESD - Human Body Model ESD - Machine Model Latch-Up 100,000 Cycles 20 Years 2,000 Volts 200 Volts 100 + ICC1 mA JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78 Note: (1) These parameters are characterized and are not 100% tested (2) 100,000 Continuous Chip and Block cycling, 100,000 Continuous Sector cycling Table 14. Program/Erase and Reliability data Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 48 IS25LQ080 PACKAGE TYPE INFORMATION JB: 8-Pin SOIC 208mil Broad Small Outline Integrated Circuit Package (Unit: millimeters) Note: Package dimensions are shown in mm Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 49 IS25LQ080 JN: 8-Pin 150mil Broad Small Outline Integrated Circuit (SOIC) Package (measure in millimeters) Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 50 IS25LQ080 JV: 8-Pin 150mil VVSOP Package Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 51 IS25LQ080 Continued: 8-Pin 150mil VVSOP Package Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 52 IS25LQ080 JK: 8-Pin WSON Ultra-Thin Small Outline No-Lead Package (Unit: millimeters) Note: Package dimensions are shown in mm Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 53 IS25LQ080 ORDERING INFORMATION: Density Frequency (MHz) Temperature Range -40C to +105C 8M 104 Call Factory Order Part Number *Package IS25LQ080-JBLE 8-pin SOIC 208mil IS25LQ080-JNLE 8-pin SOIC 150mil IS25LQ080-JVLE 8-pin VVSOP 150mil IS25LQ080-JKLE 8-pin WSON (6x5mm) KGD KGD (Call Factory) * Automotive grades (A* = A1, A2, A3) Call Factory for other Package options available Extended Grade = E -40oC to 105oC Integrated Silicon Solution, Inc.- www.issi.com Rev. C 05/14/2015 54