Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
05/14/2015
IS25LQ080
8M-BIT
3V- QUAD SERIAL FL ASH MEMORY W ITH
MULTI-I/O SPI
DATA SHEET
IS25LQ080
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
05/14/2015
FEATURES
• Industry Standard Serial Int erface
- IS25LQ080: 8M-bit/ 1M-byte
- 256-bytes per Programmable Page Standard
- Standard SPI/ Dual SPI/ Quad SPI
• High Performance Serial Flash (SPI)
- 104 MHz SPI/ Dual SPI/ or Q uad SPI
- 416 MHz equivalent Quad SPI
- 52MB/S Continuous Data Throughput
- Supports SPI Modes 0 and 3
- More than 100,000 erase/program cycles(1)
- More than 20-year data retention
• Efficient Read and Program modes
- Low Instruction O v erhea d O perations
- Continuous data rea d w ith Byte Wr ap aroun d
- Allows XIP operations (execute in place)
- Outperforms X16 Parallel Flash
• Flexib le & Cost Efficient Memory Architecture
- Uniform 4K-byte Sector Er a s e
- Uniform 64K-byte Blo ck Erase
- Program from 1 to 256 bytes
- Program/Erase Suspend and Resume
• Low Power with Wide Temp. Range s
- Single 2.3V to 3.6V Voltage Supply
- 10 mA Active Read Current
- 5 µA Standby Current
- Temp Grades: -40°C to +105°C
• Advanced Security Protection
- Software and Hardware Write Protection
- 256-Byte dedicated area, user-lockable, One
Time Programmable Memory (OTP)
• Industry Standard Pin-out & Pb-Free Packages
- JB = 8-pin SOIC 208mil
- JN = 8-pin SOIC 150mi l
- JK= 8-pin WSON 6x5 mm
- JV = 8-pin VVSOP 150mil
- KGD (call factory)
GENERAL DESCRIPTION
The IS25LQ080 (8M-bit) Serial Flash memory offers a storage solution with flexibility and performance in a
simplified pin count package. ISSI’s “Industry Standard Serial Interface” is for systems that have limited space,
pins, and power . The IS25LQ080 are accessed through a 4-wire SPI Interface consisting of a Serial Data Input
(Sl), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which also serve as multi-
function I/O pins in Dual and Quad modes (see pin descriptions). The IS25xQ series of flash is ideal for code
shadowing to RAM, execute in place (XIP) operations, and storing non-volatile data.
The memory array is organized into programmable pages of 256-bytes each. The IS25LQ080 supports page
program mode where 1 to 256 bytes of data can be programmed into the memory with one command. Pages
can be erased in groups of 4K-byte sectors, 64K-byte blocks, and/or the entire chip. The uniform 4K-byte
sectors and 64K-byte blocks allow greater flexibility for a variety of applications requiring solid data retention.
The device supports the standard Serial Peripheral Interface (SPI), Dual/Quad output (SPI), and Dual/Quad I/O
(SPI). Clock frequencies of up to 104MHz in SPI/ Dual/Quad I/O modes allow for equivalent clock rates of up to
416MHz (104MHz x 4) allowing up to 52MB/S of throughput. These transfer rates can outperform 16-bit Parallel
Flash memories allowing for efficient memory access for a XIP (execute in place) operation.
The IS25LQ080 is manufactured using in dus try leading non-volatile memory technology. The devices are
offered in industry standard lead-free packages. See Ordering Information for the density and package
combinat ions av ai lab le.
1. 100,000 Conti nuous Chip and Block cycli ng, 100, 000 Continuous Sect or cycling
8M-BIT
3V- QUAD SERIAL FLASH MEMORY MULTI- I/O SPI
IS25LQ080
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
05/14/2015
3
Connection Diagrams
CE#
GND
Vcc
HOLD# (IO3)
SCK
1
2
3
4
8
7
6
5
SO (IO1)
8-pin SOIC 208mil (Package: JB)
8-pin SOIC 150mil (Package: JN)
8-pin VVSOP 150mil (Package: JV)
8-pin WSON 6x5mm (Package: JK)
SI (IO0
)
CE#
SI (IO0
)
SCK
HOLD#(IO3)
Vcc
SO (IO1)
WP# (IO2)
GND
1
2
3
4
8
7
6
5
WP# (IO2)
IS25LQ080
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
05/14/2015
4
PIN DESCRIPTIONS
SYMBOL TYPE DESCRIPTION
CE# INPUT
Chip Enable: The Chip Enable (CE#) pin enables and disables the devices
operation. When CE# is high the device is deselected and output pins are in a high
impedance state. When deselected the devices non-critical internal circuitries power
down to allow minima l levels of power consumption while in a standby state.
When CE# is pulled low the device will be selected and brought out of stan dby
mode. The device is considered active and instructions can be written to, data read,
and written to the device. After power-up, CE# must transition from high to low
before a new instruction will be accepted.
Keeping CE# in a high state desel ect s the devi ce and switches it into its low power
state. Data will not be accepted when CE# is high.
SI (IO0),
SO (IO1)
INPUT/OUTPUT
Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):
This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI
instructions use the unidirectional SI (Serial Input) pin to write instructions,
addresses, or data to the device on the rising edge of the Serial Clock (SCK).
Standard SPI also uses the un idir e cti ona l SO (Serial Output) to read data or status
from the device on the falling edge of the serial clock (SCK).
In Dual and Quad SPI mode, SI and SO become bidirec tional IO pins to write
instructions, addresses or data to the device on the rising edge of the Serial Clock
(SCK) and read data or status from the device on the falling edge of SCK. Quad SPI
instructions use the WP# and HO LD # pins as IO2 and IO3 respectively.
WP# (IO2) INPUT/OUTPUT Write Protect: The WP# pin protects the Status Register from being written. When
the WP# is low the status registers are write-protected and vice-versa for high. When
the
QE bit is set to “1”, the WP# pin (Write Protect) function is not available since this
pin is used for IO2.
HOLD# (IO3) INPUT/OUTPUT
Hold: Pauses serial communication by the master device without resetting the serial
sequence. When the QE bit of Status Register is set to “1”, HOLD# pin is not
available sin ce it becomes IO3.
The HOLD# pin allows the device to be paused while it is selected. The HOLD# pin
is active low. When HOLD# is in a low state, and CE# is low, the SO pin will be at
high impedanc e.
Device operation can resume when HOLD# pin is brought to a high state. When the
QE bit of Status Register is set for Quad I/O, the HOLD# pin function is not available
and becomes IO3 for Multi-I/O SPI mode.
SCK INPUT Serial Data Clock: Synchronized Clock for input and output timing operations.
Vcc POWER Power: Device Core Power Supply
GND GROUND Ground: Connect to ground when referenced to Vcc
NC Unused NC: Pins labeled “NC” stand for “No Connect” and should be left uncommitted.
Table 1. P in Descriptions
IS25LQ080
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
05/14/2015
5
BLOCK DIAGRAM
Figure 1. Flash Block Diagram
SI (IO0)
WP# (IO2)
SO (IO1)
SCK
CE#
HOLD#(IO3)
IS25LQ080
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
05/14/2015
6
MEMORY CONFIGURATION
Table 2 below illustrates the memory architecture of the device and its block and sector addresses.
Table 2. Block/Sector Addresses of IS25LQ080
Memory Density Block No. Block Siz e
(Kbytes) Sector No.
Sector
Size
(Kbytes)
Address Range
8Mbit
Block 0 64
Sector 0
4
000000h - 000FFFh
Sector 1 4 001000h - 001FFFh
:
:
:
Sector 15 4 00F000h - 00FFFFh
Block 1 64
Sector 16
4
010000h - 010FFFh
Sector 17 4 011000h - 011FFFh
:
:
:
Sector 31
4
01F000h - 01FFFFh
:
:
:
:
:
Block 7
64
Sector 127
4
070000h – 07FFFFh
Block 8 64 Sector 128 4 080000h – 08FFFFh
:
:
:
:
:
:
:
:
:
:
Block 15
64
Sector 255
4
0F0000h – 0FFFFFh
IS25LQ080
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
05/14/2015
7
REGISTERS
STATUS REGISTER
Refer to Tables 3 and 4 for Status Register Format and
Status Register Bit Definitions.
The BP3, BP2, BP1, BP0, QE, and SRWD are non-
volatile memory cells that can be written by a Write
Status Register (WRSR) instruction. The default value
of the BP3, BP2, BP1, BP0, QE and SRWD bits are set
to “0” from the factory. The Status Register can be
read by the Read Status Register (RDSR). Refer to
Table 8 for the Instruction Set.
The function of Status Register bits are described as
follows:
WIP bit: The Write in Progress (WIP) bit is read-only,
and can be used to detect the progress or completion
of a program or erase operation. When the WIP bit is
“0”, the device is ready for a write status register,
program or erase operation. When the WIP bit is “1”,
the device is busy.
WEL bit: The Write Enab le Latch (W EL) bit in dicat es
the status of the internal write enable latch. When the
WEL is “0”, the write enable latch is disabled, and all
write operations, including write status register, page
program, sector erase, block and chip erase operations
are inhibited. When the WEL bit is “1”, write operations
are allowed. The WEL bit is set by a Write Enable
(WREN) instr ucti on. Each write register, program and
erase instruction must be preceded by a WREN
instruction. The WEL bit can be reset by a Write
Disable (WRDI) instruction. It will automatically reset
after the completion of a write instruction.
BP3, BP2, BP1, BP0 bits: The Block Protection (BP3,
BP2, BP1 and BP0) bits are used to define which
memory portion of the entire memory area should be
protected. Refer to Table 5 for the Block Write
Protection bit settings. When a defined combination of
BP3, BP2, BP1 and BP0 bits are set, the
corresponding memory area is protected. Any program
or erase operations to that area will be inhibited.
Note: Chip Erase (CHIP_ER) instruction can be
executed only if the Block Protection Bits are not set
and locked
.
SRWD bit: The Status Register Write Disable (SRWD)
bits oper ate in conjunc ti on with the Writ e Pr otec tion
(WP#) signal to provide a Hardware Protection Mode.
When the SRWD is set to “0”, the Status Register is
not write-protected. When the SRWD is set to “1” and
the WP# is pulled low (VIL), the bits of Status Register
(SRWD, BP3, BP2, BP1, BP0) become read-only, and
a WRSR instruction will be ignored. If the SRWD is set
to “1” and WP# is pulled high (VIH), the Status Register
can be changed by a WRSR instruction.
QE bit: The Quad Enable (QE) is a non-volatile bit in
the status register that allows Quad operation. When
the QE bit is set to “0”, the pin WP# and HOLD# are
enable. When the QE bit is set to “1”, the pin IO2 and
IO3 are enable.
WARNING: The QE bit should never be set to a 1
during standard SPI or Dual SPI operation if the WP#
or HOLD# pins are tied directly to the power supply or
ground.
Status Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SRWD QE BP3 BP2 BP1 BP0 WEL WIP
Default values 0 0 0 0 0 0 0 0
* The default value of the SRWD, QE, BP3, BP2, BP1, and BP0 are set to “0” from the factory.
Table 3. Status Register Format
IS25LQ080
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
05/14/2015
8
Bit Name Definition Read/Write
Non-
Volatile
bit
Bit 0 WIP
Write In Progress Bit:
"0" indicates the device is ready
"1" indicates a write cycle is in progress and the device is busy
R No
Bit 1 WEL
Write Enable Latch:
"0" indicates the device is not write enabled (default)
"1" indicates the device is write enabled
R/W No
Bit 2
BP0
Block Protection Bit: (Table 5)
"0" indicates the specific blocks are not write-protected (default)
"1" indicates the specific blocks are write-protected R/W Yes
Bit 3
BP1
Bit 4
BP2
Bit 5
BP3
Bit 6 QE
Quad Enable bit:
“0” indicates the Quad output function is disabled (default)
“1” indicates the Quad output function is enabled
R/W Yes
Bit 7 SRWD
Status Register Write Disable: (See Table 3)
"0" indicates the Status Register is not write-protected (default)
"1" indicates the Status Register is write-protected
R/W Yes
Table 4. S tatus Register Bit Definition
Table 5. Block Write Protect Bits for IS25LQ080
Status Register Bits 8 Mbit- Protected Memory Area
BP3 BP2 BP1 BP0 Protected Blocks Protected Portion
0
0
0
0
None
None
0 0 0 1 15 Upper 1/16
0 0 1 0 14 to 15 Upper 2/16
0 0 1 1 12 to 15 Upper 1/4
0 1 0 0 8 to 15 Upper 1/2
0 1 0 1
All blocks All
0 1 1 0
0 1 1 1
1 0 0 0
1
0
0
1
1
0
1
0
1
0
1
1
0 to 7
Lower 1/2
1
1
0
0
0 to 11
Lower 3/4
1
1
0
1
0 to 13
Lower 7/8
1
1
1
0
0 to 14
Lower 15/16
1
1
1
1
All blocks
All
IS25LQ080
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
05/14/2015
9
PROTECTION MODE
There are two types of write-protection
mechanisms: hardware and software. Both are
used to prevent incorrect operation in a possibly
noisy environm ent where d at a integr ity cannot be
guaranteed.
HARDWARE WRITE-PROTECTION
The devices provide two hardware write-protection
features:
a. When inputting a program, erase or write status
register instruction, the number of clock pulses is
checked to determine whether it is a multiple of
eight before exec uti ng. Any incompl ete instr uct ion
command sequence will be ignored.
b. Write inhibit is 2.1V, al l wr ite sequenc e wi ll be
ignored when Vcc drops below 2.1V.
c. The Write Protection (WP#) pin provides a
hardware write protection method for BP3, BP2,
BP1, BP0 and SRWD in the Status Register. Refer
to the STATUS REGISTER description.
SOFTWARE WRITE PROTECTION
There are two types of software write protection
features:
a. Before the execution of any program, erase or
write status register instruction, the Write Enable
Latch (WEL) bit must be enabled by executing a
Write Enable (WREN) instruction. If the WEL bit is
not enabled first, the program, erase or write
register instruction will be ignored.
b. The Block Protection (BP3, BP2, BP 1, BP0 ) bit s
can control whether the entire memory area or just
a partial portion is write-protected.
SRWD WP# Status Register
0 Low Writable
1 Low Protected
0 High Writable
1 High Writable
Table 6. Hardware Write Protection on Status
Register
IS25LQ080
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
05/14/2015
10
SPI INSTRUCTIONS AND DEVICE OPERATION
The instruction set for controlling the device is located
in table 8 and can be fully controlled through the SPI
bus. Instructions can be in i tiat ed with the fal li ng edg e
of Chip Enable (CE#). The first byte of data clocked
into the SI pin provides the instruction code. Data on
the SI pin is sampled by SC Ks (serial clock) rising
edge with the most significant bit (MSB) read first.
Instructions vary in length (bytes) and may be followed
by address bytes, data bytes, and or dummy bytes
(don’t care). Sometimes the instruction will require a
combination of commands to perform the function.
Instructions are read on the rising edge of SCK. A full
8-bits must be clocked with CE# pulled high at the byte
boundary before any command is accepted (expect for
read).
Read instructions can be completed after any clocked
bit. This design feature protects the device from
unwanted writes. The timing for each instruction is
illustrated in the following figures.
Table 7 contains the Manufacturing and Device IDs.
Table 7. Manufacture and Device Identifi cation
Instruction Name Hex
Code
Operation
Command
Cycle*
Maximum
Frequency
RDID
ABh
Read Device ID and Release from power down
4 Bytes
104 MHz
JEDEC ID READ
9Fh
JEDEC ID Read- Manufacturer and Device ID
1 Byte
104 MHz
RDMDID
90h
Read Manufacturer and Device ID
4 Bytes
104 MHz
WREN
06h
Write Enable
1 Byte
104 MHz
WRDI
04h
Write Disable
1 Byte
104 MHz
RDSR
05h
Read Status Register
1 Byte
104 MHz
WRSR
01h
Write Status Register
2 Bytes
104 MHz
READ
03h
Read Data Bytes from Memory at Normal Read Mode
4 Bytes
33 MHz
FAST_READ
0Bh
Read Data Bytes from Memory at Fast Read Mode
5 Bytes
104 MHz
FRDO
3Bh
Fast Read Dual Output
5 Bytes
104 MHz
FRDIO
BBh
Fast Read Dual I/O
3 Bytes
104MHz
FRQO
6Bh
Fast Read Quad Output
5 Bytes
104 MHz
FRQIO
EBh
Fast Read Quad I/O
2 Bytes
104MHz
MR
FFh
Mode Reset
2 Byte
104MHz
PAGE_ PR O G 02h Page Program Data Bytes Into Memory
4 Bytes
+ 256B
104 MHz
SECTOR_ER D7h/20h Sector Eras e 4 Bytes 104 MHz
BLOCK_ER
D8h
Block Erase
4 Bytes
104 MHz
CHIP_ER
C7h/60h
Chip Erase
1 Byte
104 MHz
Quad page program 32h
Page Program Data Bytes Into Memory with Quad
interface
4 Bytes
+ 256B
104 MHz
Program/Erase suspend
75h/B0h
Interrupts the system to pause an program/erase CMD
1 Byte
104 MHz
Program/Erase resume
7Ah/30h
Resumes the program/erase CMD
1 Byte
104 MHz
PSIR B1h Program One Time Programmable Area (OTP)
4 Bytes
+ 265B
104 MHz
RSIR
4Bh
Read One Time Programmable Area (OTP)
4 Bytes
33 MHz
Table 8. Instruction Set *Note 1. Command Cycle includes Instruction Byte
Product Identification Hex Code
Manufacturer ID Manufacture I D1 9Dh
Manufactur e ID2 7Fh
Device ID:
IS25LQ080 Device ID1 13h
Device ID2 44h
IS25LQ080
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Rev. C
05/14/2015
11
HOLD OPERATION
The HOLD# pin In SPI and Dual SPI mode allow an
operation to be paused while it is actively selected
(CE# is low).
The HOLD function may be useful in cases where
the SPI data and clock signals are shared with
other devices. See example below, Configuring
Multiple SPI Devices and Modes (0 or 3).
The HOLD function is only available for SPI and
Dual SPI operations. To initiate a HOLD operation,
the device must be selected (CE# set low) and
HOLD# pin pulled low. The HOLD operation will
activate on the falling edge of the HOLD# signal if
SCK is already low. If the SCK is not already low
the HOLD cond it ion wi ll begin at the next falling
edge of SCK. Inputs to SI will be ignored and SO
will be in a high impedance state. The HOLD
condition will terminate on the rising edge of the
HOLD# signal if SCK signal is already low, if not,
HOLD condition will terminate at the next SCK
falling edge. The paus e d operation can now
continue.
SI
SO
SCK
CE#
HOLD#
tCHHL
tHLCH
tCHHH
tHHCH
tHZ tLZ
Figure 2. HOLD Timing Diagram
IS25LQ080
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Rev. C
05/14/2015
12
CONFIGURING MULTIPLE SPI DEVICES & MODE 0 AND 3 COMPATIBLE
Multiple devices can be connected together on the SPI
serial bus and controlled by a SPI Master controller.
Figures 3 and 4 shows how a microcontroller can be
connected to control multiple SPI devices.
SPI bus operation Modes 0 (0,0) and 3 (1,1) are
supported. The primary difference between Mode 0 and
Mode 3 is the normal state of the SCK signal when the
SPI bus master is in standby and data is not being
transferred to the Serial Flash.
For Mode 0 the CLK signal is normally low on the falling
and rising edges of CE#. For Mode 3 the CLK signal is
normally high on the falling and rising edges of CE#.
The serial clock remains at “0” (SCK = 0) for Mode 0
and for Mode 3 the clock remains at “1” (SCK = 1).
Refer to Figure 3 and 4.
In both modes, the input data is latched on the rising
edge of Serial Clock (SCK) , and the output data is
available from the falling edge of SCK.
These devices are designed to interface directly with
the synchronous Serial Peripheral Interface (SPI) of
any controller equipped with a SPI interface.
Figure 3. Conceptual Diagram using an SPI Maste r with Multiple SPI Flash Memory Devices
SPI Master
(i.e. Microcont rol l er)
CS3 CS2 CS1
SPI Memory
Device
SP I Memory
Device
SP I Memory
Device
SPI Interface
(0,0) or (1,1)
SDO
SDI
SCK
SCK
SCK
SCK
SO
SO
SO
SI
SI
SI
CE#
CE#
CE#
WP#
WP#
WP#
HOLD#
HOLD#
HOLD#
Note: 1. The Write Protect (WP #) and Hold (HOLD #) signals should be driven high or low as necessary.
IS25LQ080
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Figure 4. SPI Mode 0 and 3
MSB
MSB
SCK
SCK
SO
SI
Input mode
Mode 0 (0,0)
Mode 3 (1,1)
IS25LQ080
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Rev. C
05/14/2015
14
RDID (ABh): READ DEVICE ID AND RELEASE FROM POWER-DOWN
The read device identification (RDID) instruction is for
reading out an 8-bit Electronic Signature whose value
is shown in Table 7 as Device ID1. The RDID
instruction code is followed by three dummy bytes, for
a total of four command cycles, each bit being
latched-in on SI durin g the ris ing edg e of SCK. Then
Device ID1 is shifted out on SO with the MSB first,
each bit being shifted out during the falling edge of
SCK. The RDID instruction is ended when CE# goes
high. Device ID1 outputs repeatedly if clock cycles
continue on SCK and CE# is held low. To release the
device from the RDID instruction, drive CE# high as
shown in figure 5.
The RDID instruction can also release the device from
the power-down state. It is a multi-purpose instr uc t ion.
To release the device from the power-down state, the
instruction is issued by driving the CE# pin low and
shifting the instruction code “ABh” and driving CE#
high. The CE# pin must remain high during the tRES
time duration before the device will resume normal
operation and other instructions are accepted.
If the Releas e from Power-down instruction is issued
while an Erase, Program or Write cycle is in process
the instructio n is ignor ed an d will not have any effec ts
on the current cycle.
The JEDEC ID read instruction is recommended for
new designs.
IS25LQ080
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Rev. C
05/14/2015
15
Read Device ID
Release from Power-Down
Figure 5. Read Device ID (Top Diagram) and Release from Power-Down (Bottom Diagram)
TRES
0 1 8 31 38 39 46 47 54
HIGH IMPEDANCE Device ID1Devi ce ID1Device ID1
SCK
CE#
SI
SO
INSTRUCTION
97
1010 1011b
3 Dummy Bytes
IS25LQ080
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Rev. C
05/14/2015
16
JEDEC ID READ (9Fh): Read Manufacture Product Identification by JEDEC ID
For compatibility reasons several instructions are
available for electronically obtaining the identity of the
device. The JEDEC ID read command was adopted to
allow compatibility and identification.
This instruction is initiated by driving the CE# pin low
and shifting the instruction code “9Fh”. The JEDEC ID
READ instruction allows the user to read Manufacturer
ID1, Device ID1, and Device ID2.
The command shifts out the most significant bit on the
falling edge of SCK.
If CE# stays low after the last bit of Device ID2 the
electronic identification is repeated continuously until
CE# is pulled high.
Figure 6. Read Product Identifica tion by JEDEC ID READ Sequence
RDMDID (90h): READ DEVICE MANUFACTURE R AND DE V ICE ID OPERATION
The Read Device Manufacturer and Device ID
instruction is very similar to the RDID instruction. The
RDMDID instruction is initiated by driving the CE# pin
low and shifting the instruction code “90h” followed by
three bytes. Two dummy bytes plus one address byte
(A7~A0), each bit be ing lat c hed-in on SI durin g the
rising edge of SCK.
The Manufacture and Device ID can be read
continuously, alternating from one to the others. The
instruction is completed by driving CE# high.
If the last bit (A7~A0) is ini t i ally set to 0, then
Manufactur e ID1 -> Device ID1 -> Manufacture ID2 is
shifted out on SO with the MSB first. Each bit shifted
out during the falling edge of SCK. If A0 = 1, then the
output sequence becomes Device ID1 -> Manufactur e
ID1 -> Manufacture ID2.
IS25LQ080
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Rev. C
05/14/2015
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0123456 7 8910 11 28 29 30 31
...
INSTRUCTION = 1001 0000b ...
23 22 21 321A0
3 - BYTE ADDRESS
CE#
SCK
SIO
SO HIGH IMPEDANCE
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
76 5 432 1 0
CE#
SCK
SIO
SO 6 5 432 17 0
Data Out1 Data Out2
Figure 7. Read Product Identification by RDMDID READ Sequence
Figure 7. (cont.) Read Product Identification by RDMDID READ Sequence
Note : 1. ADDRESS A0 = 0, will output the Manufacture ID1 -> Device ID1 -> M anufacture ID2
2. ADDRESS A0 = 1, will out p ut the Device ID1 -> Manufacture ID1 -> Manufacture ID2
IS25LQ080
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Rev. C
05/14/2015
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WREN (06 h ): WRI TE ENABLE OP ERATION
The Write Enable (WREN) instruction is used to set the
Write Enable Latch (WEL) bit. The WEL bit is reset to
the write protected state after power-up. The WEL bit
must be write enabled before any write operation,
including sector, block erase, chip erase, page
program, and write status register. The WEL bit will be
reset to the write-protect state automatically upon
completion of a write operation. The WREN instruction
is required before any above operation is executed.
Figure 8. Write Enable Se quence
WRDI (04h): WRI T E DISABLE OPERATI ON
The Write Disable instruction resets the Write Enable
Latch (WEL) bit in the Status Register to a 0. The Write
Disable instruction is entered by driving CE# low,
shifting the instruction code “04h” into the SI pin and
then driving CE# high. The WEL bit is automatically
reset after power-up and upon completion of the Write
Status Register, Page Program, Quad Page Program,
Sector Erase, Block Erase and Chip Erase.
Figure 9. Write Disable Sequence
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RDSR (05h): READ STATUS REGI STER OPERATION
The Read Status Register (RDSR) instruction provides
access to the Status Register. During the execution of
a program, erase or write status register operation, all
other instructions will be ignored except the RDSR
instruction, which can be used to check the progress or
completion of an operation by reading the WIP bit of
the Status Register.
The instruction is entered by driving CE# low and
shifting the instruction code “05h”into the SI pin on the
rising edge of SCK. The status register bits are then
shifted out on the SO pin at the falling edge of SCK
with most significant bit (MSB) first.
The Read Status Register instruction may be used at
any time, even while a Program, Erase or Write Status
Register cycle is in progress. This allows the WIP
status bit to be checked to determine when the cycle is
complete and if the device c an accept anot her
instruction. The Status Register can be read
continuously. The instruction is completed by driving
CE# high.
Figure 10. Read Status Register Sequence
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WRSR (01h): WRITE STATUS REGISTER OPERATION
The Write Status Register (WRSR) instruction allows
the Status Register to be written. A Write Enable
instruction must previously have been executed for the
device to accept the Write Status Register Instruction
(Status Register bit WEL must equal 1). Once write
enabled, the instruction is entered by driving CE# low,
sending the instruction code “01h”, and then writing the
status register data into the non-volatile BP3, BP2,
BP1, BP0, QE, and SRWD bits. The user can enable
or disable the block protection and status register write
protection features by writing “0”s or “1”s.
Figure 11. Write Status Register Sequ en ce
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READ (03h): READ DAT A OPERATION
The READ instruction code is transmitted via the SI
line, followed by three address bytes (A23 - A0) of
the first memory location to be read. A total of 24
address bits are shifted in, but only AMS (most
significant address) - A0 are decoded. The
remaining bits (A23 – AMS) are ignored. The first
byte addressed can be at any memory location.
Upon completion, any data on the Sl pin will be
ignored. Refer to Table 9 for the related Address
Key.
The first byte data (D7 - D0) addressed is then
shifted out on the SO line, MSB first. A single byte
of data, or up to the whole memory array, can be
read out in one READ instruction. The address is
automatically incremented after each byte of data is
shifted out. The read operation can be terminated at
any time by driving CE# high (VIH). When the
highest address of the devices is reached, the
address counter will roll over to the 000000h
address, allowing the entire memory to be read in
one continuous READ instruction.
If a Read Data instruction is issued while an Erase,
Program, or Wr ite cycle i s in process (WIP=1) the
instruction is ignored and will not have any effects
on the current cycle.
The Read Data instruction allows clock rates from
D.C. to a maximum of fC (see AC Electrical
Characteristics).
Address IS25LQ080
A
N (
A
MS
– A
0)
A21 - A0
Don't Care Bits A23 – A22
Table 9. Address Key
Figure 12. Read Data Sequence
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FAST_READ (0Bh): FAST READ DATA OPERATION
The FAST_READ instruction code is followed by three
address bytes (A23 - A0) and a dummy byte (8 clocks),
transmitt ed via the SI lin e, with each bit latc h ed-in
during the rising edge of SCK. The dummy byte allows
the devices internal circuits additional time for setting
up the initial address. During the dummy cycle the data
value on the SI pin is a “don’t care”.
The FAST_READ instruction is similar to the Read
Data instruction except that it can operate at the
highest possible frequency of fCT (see AC Electrical
Characteristics).
Figure 13. Fast Read Data Sequence
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FRDO (3Bh): FAS T READ DUAL OUTP UT OPERATION
The Fast Read Dual Output (3Bh) instruction is similar
to the standard Fast_Read (0Bh) instruction except
that data is output on two pins. This allows data to be
transferred from the device at twice the rate of
standard SPI devices. The Fast Read Dual Output
instruction is ideal for quickly downloading code.
Similar to the Fast_Read instruction, FRDO instruction
can operate at the highest possible frequency of fCT
(see AC Electric al Charac te r istic s ).
This is accomplished by adding 1 dummy byte after the
24-bit address as. The dummy cycle allow the device's
internal circuits additional time for setting up the initial
address. The input data during the dummy byte is
“don’t care”.
The first byte addressed can be at any memory
location. The address is automatically incremented
after each byte of data is shifted out. When the highest
address is reached, the address counter will roll over to
the 000000h address, allowing the entire memory to be
read with a single FRDO instruction. FRDO instruction
is terminated by driving CE# high (VIH). If a FRDO
instruction is issued while an Erase, Program or Write
cycle is in process (WIP=1) the instruction is ignored
and will not have any effects on the current cycle
0123456 7 8910 11 28 29 30 31
...
INSTRUCTION = 0011 1011b ...
23 22 21 3210
3 - BYTE ADDRESS
CE#
SCK
SI
SO HIGH IMPEDANCE
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
CE#
SCK
IO0
IO1 HIGH IMPEDANCE DATA OUT 1 DATA OUT 2
HIGH IMPEDANCE
Figure 14. Fast Read Dual-Output Sequence
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FRDIO (BBh): FAST READ DUAL I/O OPERATION
The FRDIO instruction is similar to the FRDO
instruction, but allows the address bits to be input two
bits at a time. This may allow for code to be executed
directly from the SPI in some applications (XIP).
The FRDIO instruction code is followed by three
address bytes (A23 – A0) and a mode byte,
transmitted via the IO0 and IO1 lines, with each pair of
bits latched-in during the rising edge of SCK. The
address MSB is input on IO1, the next bit on IO0, and
continues to shift in alternating on the two pins. The
mode byte contains the value Ax, where x is a “don’t
care” value.
The first data byte addressed is shifted out on the IO1
and IO0 lines, with each pair of bits shifted out at a
maximum frequency fCT, during the falling edge of SCK.
The MSB is output on IO1, while simultaneously the
next bit is output on IO0.
The first byte addressed can be at any memory
location. The address is automatically incremented
after each byte of data is shifted out. When the highest
address is reached, the address counter will roll over to
the 000000h address, allowing the entire memory to be
read with a single FRDIO in s t ruction. FRDIO
instruction is terminated by driving CE# high (VIH).
The device remains in this mode until it receives a
Mode Reset (FFh) command. In subsequent FRDIO
execution, the command code is not input, saving
timing cycles. If a FRDIO i n s truc tion is issued w hi le an
Erase, Program or Write cycle is in process (WIP=1)
the instructio n is ignor ed an d will not have any effec ts
on the current cycle
0123456 7 8910 11 18 19 20 21
...
INSTRUCTION = 1011 1011b ...
23 22
21 2064
3 - BYTE ADDRESS
CE#
SCK
IO0
22 23 24 25 26 27 28 29 30 31
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
CE#
SCK
IO0
IO1
DATA OUT 1 DATA OUT 2
...
22
20 317
IO1
19
5
MODE BITS
7
6
Figure 15. Fast Read Dual I/O Sequence (with command decode cycles)
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012 3 10 11 12 13 14 15 16 17 18 19 20 21
...
...
23 22
21 2064
3 - BYTE ADDRESS
CE#
SCK
IO0
5
4
3
2
1
0
7
6
5
4
DATA OUT 1 DATA OUT 2
...
22
20 317
IO1
19
5
MODE BITS
7
6
Figure 16. Fast Read Dual I/O Sequence (without command decode cycles)
FRQO (6Bh): FAST READ QUAD OUTP UT OPERATION
The FRQO instruction code is followed by three
address bytes (A23 – A0) and a dummy byte (8
clocks), transmitted via the SI line, with each bit
latched-in during the rising edge of SCK. The first data
byte addressed is shifted out on the IO3, IO2, IO1 and
IO0 lines, with each group of four bits shifted out at a
maximum frequency fCT, during the falling e dge of SCK .
The first bit (MSB) is output on IO3, while
simultaneously the second bit is output on IO2, and the
third bit is output on IO1, etc.
The first byte addressed can be at any memory
location. The address is automatically incremented
after each byte of data is shifted out. When the highest
address is reached, the address counter will roll over to
the 000000h address, allowing the entire memory to be
read with a single FRQO instruction. FRQO instruction
is terminated by driving CE# high (VIH). If a FRQO
instruction is issued while an Erase, Program or Write
cycle is in process (WIP=1) the instruction is ignored
and will not have any effects on the current cycle.
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0123456 7 8910 11 28 29 30 31
...
INSTRUCTION = 0110 1011b ...
23 22 21 3210
3 - BYTE ADDRESS
CE#
SCK
SI
SO HIGH IMPEDANCE
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
5
4
1
0
5
4
1
0
5
4
1
0
5
4
1
0
5
4
CE#
SCK
IO0
IO1 HIGH IMPEDANCE
DATA OUT 1 DATA OUT 2
7
6
3
2
7
6
3
2
7
6
3
2
7
6
3
2
7
6
HIGH IMPEDANCE
IO2
IO3
DATA OUT n. . .
Figure 17. Fast Read Quad-Output Sequence
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FRQIO (EBh): FAST READ QUAD I/ O OPERATION
The FRQIO instruction is similar to the FRQO
instruction, but allows the address bits to be input four
bits at a time. This may allow for code to be executed
directly from the device in some applications (XIP).
The FRQIO instruction code is followed by three
address bytes (A23 – A0) and a mode byte,
transmitted via the IO0, IO1, IO2, and IO3 lines , wit h
each group of four bits simultaneously latched-in
during the rising edge of SCK. The mode byte contains
the value Ax, where x is a “don’t care” value. After four
dummy clocks, the first data byte addressed is shifted
out. Each group of four bits are shifted out at a
maximum frequency fCT dur ing the fal li ng edg e of SCK.
Figure 18 illustrates the timing sequence.
The first byte addressed can be at any memory
location. The address is automatically incremented
after each byte of data is shifted out. When the highest
address is reached, the address counter will roll over to
the 000000h address, allowing the entire memory to be
read with a single FRQIO instruction. FRQIO
instruction is terminated by driving CE# high.
The device expects the next operation to be another
FRQIO and will remain in this mode until it receives a
Mode Reset (FFh) command. In subsequent FRDIO
execution, the command code does not need to be
entered thus reducing the overhead for fast data
readout. See Figure 19.
If a FRQIO instruction is issued while an Erase,
Program or Write cycle is in process (WIP=1) the
instruction is ignored and will not have any effects on
the current cycle.
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0123456 7 8910 11 12 13 14 15
INSTRUCTION = 1110 1011b
21 17
16 404
3 - BYTE ADDRESS
CE#
SCK
IO0
16 17 18 19 20 21 22 23 24 25
1
0
5
4
1
0
5
4
1
0
5
4
1
0
5
4
CE#
SCK
IO0
IO1
DATA OUT 1
20
13 515
IO1
12
MODE BITS
5
4
22 18 14 626
23 19 15 737
IO2
IO3 11
10
9
8
3
2
7
6
3
2
7
6
3
2
7
6
3
2
7
6
7
6
IO2
IO3
DATA OUT 2 DATA OUT 3 DATA OUT 44 dummy cycles
26 27
Figure 18. Fast Read Quad I/O Sequence (with command decode cycles)
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0123456 7 8910 11 12 13 14 15
21 17
16 404
3 - BYTE ADDRESS
CE#
SCK
IO0
DATA OUT 1
20
13 515
IO1
12
MODE BITS
22 18 14 626
23 19 15 737
IO2
IO3 11
10
9
8
DATA OUT 2
4 Dummy Clock
Figure 19. Fast Read Quad I/O Sequence (with o u t command decode cycles)
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MR (FFh): MODE RESET OPERATION
The Mode Reset command is used to conclude
subsequent FRDIO and FRQIO operations. It
resets the Mode bits to a value that is not Ax. It
should only be executed after an FRDIO or FRQIO
operation and is recommended as the first
command after a system reset.
Figure 20 illustr ates t he difference in timing
sequence for a Mode Reset issued after the FRDIO
or FRQIO operation.
0123456 7 8910 11 12 13 14 15
INSTRUCTION = 1111 1111b
CE#
SCK
SIO
SO HIGH IMPEDANCE
Mode Reset for
Quad I/O
Mode Reset for
Dual I/O
INSTRUCTION = 1111 1111b
Figure 20. Mode Reset Command
SI
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PAGE_PROG (02h): PAGE PROGRAM OPERATION
The Page Program (PAGE_PROG) instruction allows
from 1 to 2 56 by tes of data to be programmed into the
device with a single operation. Memory areas
protected by the Block Protection bits (BP3, BP2, BP1,
and BP0) cannot be programmed. A PAGE_PROG
instruction which attempts to program into a page that
is write-protec ted will be ign ored. Th e Write En ab le
Latch (WEL) bit must be set to 1 before the execution
of a PAGE_PROG instruction.
Once the device is selected (CE# = low) the
PAGE_PROG instruction code, three address bytes,
and program data (1 to 256 bytes) are input via the Sl
line. Program operation will start immediately after CE#
is pulled high.
If more than 256 bytes of data are sent to a page, the
address counter rolls over within the same page, and
any previously latched in data is overwritten.
The Page Program operation does not need to start at
any specific address and can be used to partially write
a page. If the end of the page is reached, the address
will wrap around to the beginning of the page and any
previous d ata wi ll be overw r itten.
During a program operation, all instructions will be
ignored except the RDSR instruction. The progress or
completion of the program operation can be
determined by reading the WIP bit of the Status
Register via a RDSR instruction. If the WIP bit is “1”,
the program operation is still in progress. If WIP bit is
“0”, the program operation has completed.
Note: A program operation can alter “1”s into “0”s, but
an erase operation is required to change “0”s back to
“1”s. A byte cannot be reprogrammed without first
erasing the who le sector or block.
Figure 21. Page Program Seq u ence
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Quad Page Program (32h): Quad Input Page Program Operation
The Quad Page Program instruction allows from 1 to
256 bytes of data to be programmed into the device
with a single operation. Memory areas protected by
the Block Protect ion bits (BP3, BP2, BP1, and BP 0)
cannot be program me d. A Quad Page Program
instruction which attempts to program into a page
that is write-protected will be ignored. Before the
execution of the Quad Page Program instruction, the
QE bit in the status register must be set to “1”, and
the Write Enable Latch (WEL) must be enabled
through a Write Enable (WREN) instruction.
.
Once the device is selected (CE# = low) the Quad
Page Program instruction code, three address bytes,
and program data (1 to 256 bytes) via the four pins
(IO0, IO1, IO2 and IO3). Program operation will start
immediately after CE# is pulled high.
If more than 256 bytes of data are sent to a page, the
address counter rolls over within the same page, and
any previously latched in data is overwritten.
The Quad Page Program operation does not need to
start at any specific address and can be used to
partially write a page. If the end of the page is
reached, the address will wrap around to the
beginning of the page and any previous data will be
overwritten.
During a program operation, all instructions will be
ignored except the RDSR instruction. The progress
or completion of the program operation can be
determined by reading the WIP bit of the Status
Register via a RDSR instruction. If the WIP bit is “1”,
the program operation is still in progres s . If the WIP
bit is “0”, the program operation has completed.
Note: A program operation can alter “1”s into “0”s,
but an erase operation is required to change “0”s
back to “1”s. A byte cannot be reprogrammed without
first erasing the whole sector or block.
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0123456 7 8910 11 28 29 30 31
...
INSTRUCTION = 0101 0010b ...
23 22 21 3210
3 - BYTE ADDRESS
CE#
SCK
IO0
IO1
32 33 34 35 36 37 38 39
5
4
1
0
5
4
1
0
5
4
1
0
5
4
1
0
5
4
CE#
SCK
IO0
IO1
DATA IN 1 DATA IN 2
7
6
3
2
7
6
3
2
7
6
3
2
7
6
3
2
7
6
IO2
IO3
DATA IN n. . .
IO2
IO3
Figure 22. Quad Page Program Sequence
00110010b
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ERASE OPERATION
The memory array is organized into uniform 4 Kbyte
sectors or 64 Kbyte uniform blocks (a block consists of
sixteen adjacent sectors).
Before a byte can be reprogrammed, the sector or
block that contains the byte must be erased (erasing
sets bits to “1”). In order to erase the devices, there are
three erase ins truc tions av ail ab le: Sector Eras e
(SECTOR_ER), Block Erase (BLOCK_ER) and Chip
Erase (CHIP_ER). A sector erase operation allows any
individual sector to be erased without affecting the data
in other sectors. A block erase operation erases any
individual block. A chip erase operation erases the
whole memory array of a device. A sector erase, block
erase, or chip erase operation can be executed prior to
any programming operation.
During an erase oper at ion all instruc t ion wi ll be ignor e d
except the Read Status Register (RDSR) instruction.
The progress or completion of the erase operation can
be determined by reading the WIP bit in the Status
Register using a RDSR instruction. If the WIP bit is “1”,
the erase operation is still in progress. If the WIP bit is
“0”, the erase operation has been completed.
SECTOR_ER (D7h/20h):
SECTOR ERASE OPERATION
The SECTO R_ ER ins truc ti on supports dual
instructions of D7h or 20h and erases a 4 Kbyte sector.
Before the execution of a SECTOR_ER instruction the
Write Enable Latch (WEL) must be set via a Write
Enable (WREN) instruction. The WEL bit is reset
automatically after the completion of an erase
operation.
The SECTO R_ ER inst ruc ti on is entere d after CE# is
pulled low to select the device and stays low during the
entire instruction sequence. The SECT O R _ER
instruction code and three address bytes are input via
SI. Erase operation will start immediately after CE# is
pulled high. The internal control logic automatically
handles the erase voltage and timing. Refe r to Figu re
23 for Sector Eras e Seq ue nce.
BLOCK_ER (D8h):
BLOCK ERASE OPERATION
The Block Erase (BLOCK_ER) instruction erases a 64
Kbyte block. Before the execution of a BLOCK_ER
instruction the Write Enable Latch (WEL) must be set
via a Write Enable (WREN) instruction. The WEL is
reset automatically after the completion of a block
erase operation.
A BLOCK_ER instruction is entered after CE# is pulled
low to select the device and stays low during the entire
instruction sequence. The BLOCK_ER instruction code
and three address bytes are input via SI. Erase
operation will start immediately after CE# is pulled
high. The internal control logic automatically handles
the erase voltage and timing. Refer to Figure 24 for
Block Erase Sequence.
CHIP_ER COMMAND (C7h/60h):
CHIP ERA SE OPERATION
The CHIP_ER instruction supports dual instructions of
C7h or 60h. Before the execution of CHIP_ER
instruction, the Write Enable Latch (WEL) must be set
via a Write Enable (WREN) instruction. The WEL is
reset automatically after completion of a chip erase
operation.
The CHIP_ER instruction is entered after CE# is pulled
low to select the device and stays low during the entire
instruction sequence. The CHIP_ER instruction code is
input via SI. Erase operation will start immediately after
CE# is pulled high. The internal control logic
automatically handles the erase voltage and timing.
Refer to Figure 25 for Chip Erase Sequence.
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Figure 23. Sector Erase Sequence
Figure 24. Blo c k Era se Se qu ence
Figure 25. Chip Erase Sequence
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One Time Programmable Secure Area (OTP) : 255 Bytes of OTP + 1 Control Byte
PSIR (B1h): Program Security Information instruction
The PSIR command is used to program the 255 Bytes (plus one additional control Byte) of secured memory
area set aside for one time programmable security area. Information can be stored in the array but not altered.
Passcodes, Unique IDs, Identifiers, etc. can be stored in this area to prevent counterfeiting or even unwanted
access. Before instructions can be accepted a write enable (WREN) instruction must have been previously
executed to set the write enable latch (WEL) bit. Once the device has been selected via the CE# pin, the
instruction code is followed by three address bytes to program the secured area and up to 255 bytes of data
(plus 1 control Byte) to the SI line. CE# pin must be pulled high after the eighth bits of the last data byte has
been latched in, otherwise the instruction is not executed. If more than 255 bytes of data + 1 Contro l Byte is sent
to the secured area the address counter may roll over and re-write the secured information.
Warning: Do not attempt to write more than the 256 Bytes to the OTP area
After CE# pin is driven high, the self -timed page program cycle (whose duration is tpotp) is initiated. While the
program PSIR cycle is in progress, the status register may be read to check the value of the write in progress
(WIP) bit. The write in progress (WIP) bit is 1 during the self-time d pro gram cy cle, and it is 0 when it is
completed. At some unspecified time before the cycle is complete, the write enable latch (WEL) bit is reset.
0123456 7
...
INSTRUCTION = 1011 0001b ...
CE#
SCK
SI
32 33 34 35 36 37 38 39
...
...
CE#
SCK
SI
8910 11 28 29 30 31
24-bit address
2223 21 2 1 0
MSB
7
MSB
6543210
Data Byte 1
76 5
Data Byte 2 Data Byte n
41 4240 43
Note: 1 ≤ n ≤ 256
2. The security area is from 000 000 h to 0000F Eh.
3. The protection lock bit is in the address 0000FFh
Figure 26. Program Security Information Row Sequence
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Locking the Secure (OTP) Memory
Bit 0 of byte 256 is used to permanently lock the OTP memory array.
1. When bit 0 of byte 256 = ’1’, the 255 bytes of the OTP memory array can be programmed.
2. When bit 0 of byte 256 = ‘0’, the 255 bytes of the OTP memory array is read-o nly and cannot be
programmed anymore.
Once bit 0 of the control byte has been programmed to ‘0’, it can no longer be set to ‘1’.
Therefore, as soon as bit 0 of byte 256 (control byte) is set to ‘0’, the 255 bytes of the OTP memory array
permanently become read-only.
Any program instruction issued while an erase, program, or write cycle is in progress is rejected without having
any effect on the current instruction.
Byte1 Byte2 Byte256Byte255
OTP control byte
Bit 0X X X X X X X
Bit 1~bit 7 do not care
When bit 0 = 0
the 256 OTP bytes
become read only
Figure 27. Control Byte to lock security memory
Byte
255 Byte
256
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RSIR (4B h ): Read Security Inform ation Area
The RSIR instruction reads the security memory. There is no rollover mechanism while reading the secured
area. The read instruction must be sent with the max i mum of 256 bytes to read, once the 256th byte has been
read, the same (256th) byte continues being read on the SO pin revealing the locked or unlocked status of the
Control Byte.
0123456 7
...
INSTRUCTION = 0100 1011b ...
CE#
SCK
SI
40 41 42 43 44 45 46 47
...
...
CE#
SCK
SO
8910 11 28 29 30 31
24-bit address
2223 21 2 1 0
MSB
7
MSB
6543210
Data outpur 1
76 5
Data output 2 Data output N
SO 70
33 34 36 37 38 3932 35
SI
6 54321
Data Out0
Note: 1 ≤ n ≤ 256
2. The security area is from 000000h to 0000FEh.
3. The protec t ion lock bit is in the address 0000FFh
Figure 28. Read Security information instruction
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Program/Erase Suspend (75h/B0h)
The Program/Erase Suspend instruction (75h/B0h) allows the sys tem to interr u pt a Sect or Erase, Block Erase,
or Page Program operation. Erase instructions (20h, D7h, D8h, C7h, 60h) are not allowed during the Erase
Suspend instruction. Erase Suspend is valid only during the Sector or Block erase operation. If Erase Suspend
is issued during a chip erase operation it will be ignored. Program instructions (02h, 32h, B1h) are not allowed
during Program Suspend. Program Suspend is valid only during the Page_PROG or Quad Pa ge Progr a m
operation. A maximum time of Tws (See AC Characteristics) is required to elapse before any new read or
program instructions are issued. The WEL bit in the Status Register will clear to 0 after an Erase Suspend
instruction.
Unexpected power off during the Erase suspend state will reset the device and release the suspend state. The
data within the page, sector, or block that was being suspended may become corrupted.
Figure 29. Program/Erase Suspend Instruction shown with 75h (Alternatively B0h can be used)
Program/Erase Resume (7Ah/30h)
The Program/Erase Resume instruction must be written to resume the Sector Erase, Block Erase, or Page
Program oper ations after a Program/Eras e suspend. Pol l the WIP bit in th e Status regis ter or wait the s pecified
time TSE and TBE. The total time before and after a suspend function will not exceed TSE or TBE when resuming
a sector erase or block erase respectively. Resume instructions will be ignored if a Program/Erase Suspend
operation is still active.
Resume instruction is ignored if the previous Program/Erase Suspend operation was interrupted by an
unexpected power off.
Figure 30. Program/Erase Resume Instruction 7Ah (Alternatively 30h can be used)
*Note:
1. 500ns delay needed from write command to suspend command
2. 1ms delay needed from Erase Resume to Erase Suspend
IS25LQ080
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SECTOR LOCK/UNLOCK FUNCTIONS
SECTOR UNLO CK OPERATION (SECUNLOCK, 26h)
The Sector Unlock comma nd allows the user to select a s pecific sector to allow program and erase operati ons.
This instruc tion is effec tive when the blocks are des ignated as writ e-protected through the BP0, BP1, BP2, and
BP3 bits i n the Status Regi ster. Only one sec tor can be e nab led at any tim e. If many SECUN LOC K comm ands
are input, only the last sector designated by the last SECUNLOCK command will be unlocked. The instruction
code is followed by a 24-bit address specifying the target sector, but A0 through A11 are not decoded. The
remaining sectors within the same block remain as read-only.
Figure 8.30 Sector Unlock Sequence
Instruction = 26h23
CE#
SCK
SI 32
SO
1 0
3-byt e Addres s
High Impedance
22 21 ...
0 1 2 3 4 5 6 78 9 10 ... 28 29 30 31
Mode 3
Mode 0
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SECTOR LOC K OP E RATI O N (SE CLOCK, 24 h)
The Sector Lock command relocks a sector that was previously unlocked by the Sector Unlock command. The
instruction code does not require an address to be specified, as only one sector can be enabled at a time. The
remaining sectors within the same block remain in read-only mode.
Figure 8.31 Sector Lock Sequence
Instruction = 24h
CE#
SCK
SI
SO High Impedance
0 1 2 3 4 5 6 7
Mode 3
Mode 0
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature -55oC to +125oC
Surface Mount Lead Soldering Temperature Standard Pac kage 240oC for 3 Secon ds
Lead-free Package 260oC for 3 Sec on ds
Input Voltage with Respect to Ground on All Pins (2) -0.5 V to VCC + 0.5 V
All Output Voltage with Respect to Ground -0.5 V to VCC + 0.5 V
VCC (2) -0.5 V to +6.0 V
Table 10. Absolute Max Ratings
Notes:
1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only. The functional operation of the device conditions that exceed those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
condition for extended periods may affect device reliability.
2. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may
overshoot VCC by + 2.0 V for a period of time not to exceed 20 ns. Minimum DC voltage on input or I/O pins is
-0.5 V. During voltage transitions, input or I/O pins may undershoot GND by -2.0 V for a period of time not to
exceed 20 ns.
DC AND AC OPERATING RANGE
Part Number IS25LQ080
Operating Temperature Extended Grade -40oC to +105oC
Vcc Power Supply 2.30 V – 3.6 0 V
Table 11. Voltage and Temperature Ratings
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DC CHARACTERISTICS
Applicable over recommended operating range from:
TAC = -40°C to +105°C , VCC = 2.70 V to 3.60 V (unless otherwise noted).
Symbol Parameter Condition Min Typ Max Units
ICC1 Vcc Active Read Current
V
CC
= 3.60V at 33 MHz, SO =
Open
10 15 mA
ICC2 Vcc Program/Erase Current
V
CC
= 3.60V at 33 MHz, SO =
Open
15 30 mA
I
SB1
Vcc Standby Current CMOS V
CC
= 3.60V, CE# = V
CC
5 30 µA
I
SB2
Vcc Standby Current TTL V
CC
= 3.60V, CE# = V
IH
to V
CC
3 mA
I
LI
Input Leakage Current V
IN
= 0V to V
CC
1 µA
I
LO
Output Leakage Current V
IN
= 0V to V
CC
1 µA
V
IL
Input Low Voltage -0.5 0.3Vcc V
VIH Input High Volt ag e 0.7VCC VCC+0.3 V
V
OL
Output Low Vo lta ge 2.30V <VCC< 3.60V I
OL
= 2.1 mA 0.45 V
V
OH
Output High Voltage I
OH
= -100 µA V
CC
– 0.2 V
Table 12. DC Characteristics Table
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AC CHARACTERISTICS
Applicable over recommended operating range from TA = -40°C to +105°C, VCC = 2.70 V to 3.60 V
CL = 1 TTL Gate and 30 pF (unless otherwise noted).
Symbol Parameter Min Typ Max Units
f
CT
Clock Frequency for fast read mode
0
104
MHz
fC Clock Frequency for read mode 0 33 MHz
tRI Input Rise Time 8 ns
t
FI
Input Fall Time
8
ns
tCKH SCK High Time 4 ns
tCKL SCK Low Time 4 ns
tCEH CE# High Time 25 ns
tCS CE# Setup Time 10 ns
tCH CE# Hold Time 5 ns
tDS Data In Setup Time 2 ns
tDH Data in Hold Time 2 ns
tHS Hold Setup Time 15 ns
tHD Hold Time 15 ns
tV Output Valid 8 ns
tOH Output Hold Time Normal Mode 0 ns
tLZ Hold to Output Low Z 200 ns
tHZ Hold to Output High Z 200 ns
tDIS Output Disable Time 100 ns
tSE
Sector Erase Time (4KB)
120
300
ms
tBE Block Erase Time (64KB) 250 1000 ms
t
CE
Chip Erase Time (8Mb)
3
6
s
tPP Page Program Time 0.5 1 ms
t
res
Time required after release from Power Down 3 µs
tw Write Status Register time 5 50 ms
TWS CE# High to next Instruction after Suspend 20 µs
Table 13. AC Characteristics Table
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AC CHARACTERISTICS (CONTINUED)
Figure 31. SERIAL INPUT/OUTPUT TIMING (1)
Note: 1. For SPI Mode 0 (0,0)
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AC CHARACTERISTICS (CONTINUED)
Figure 32. HOLD TIMING
PIN CAPACITANCE (f = 1 MHz, T = 25°C )
Typ Max Units Conditions
CIN 4 6 pF VIN = 0 V
COUT 8 12 pF VOUT = 0 V
Note: These parameters are characterized but not 100% tested.
Table. 14 Pin Capacitance
Figure 33. Outpu t load test and input test waveform and m easurement levels
30pF
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POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must not
be selected until Vcc reaches Vcc(min) during
power-up and tVCE has elapsed or Vcc has
reached Vss at Power-down.
For most applications it is recommended that a
simple pull-up resistor on CE# can be used to
insure safe and pro per Pow er -up and Power-down
sequences.
To avoid data corruption and inadvertent write
operations during power up, a Power On Reset
(POR) circuit is incorporated. The logic inside the
device holds reset while Vcc is less than the POR
threshold value (Vwi) during power up, the device
does not respond to
any instruction until a time delay of tPUW has
elapsed after the moment that Vcc rises above the
VWI threshold. However, the correct operation of
the device is not guaranteed if, by this time , Vcc is
still below Vcc (min). N o instructions should be sent
until:
- Vcc passes the VWI threshold and tPUW delay
has elapsed
- Vcc passed the Vcc(min) level and tVCE delay
has elapsed
At Power-up, the device is in the following state:
- The device is in the Standby mode
- The Write Enable Latch (WEL) bit is reset
At Power-d own, w he n Vcc dr ops from the operating
voltage to below the Vwi, all write operations are
disabled and the device does not respond to any
instructions.
Figure 34. Power up Sequence
Chip Selection Not Allowed
All Write Commands are Rejected
tVCE Read Access Allowed Devi ce fully accessible
tPUW
Vcc
Vcc(max)
Vcc(min)
Reset State
V (write inhibit)
Time
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PROGRAM/E RASE PERFORMANCE
Parameter Typ
Max Unit
Remarks
Sector Erase Time 120 300 ms From writing erase command to erase completion
Block Erase Time 250 1000 ms From writing erase command to erase completion
Chip Erase Time 3 6 s From writing erase command to erase completion
Page Programming Time
0.5 1 ms From writing program command to program completion
Byte Program 8 25 us
Note: These parameters are characteriz ed and are not 100% tested.
RELIABILITY CHARACTERI STICS(1)
Endurance(2) 100,000 Cyc les JEDEC Standard A117
Data Retention 20 Years JEDEC Standard A103
ESD – Human Body Model 2,000 Volts JEDEC Standard A114
ESD – Mac hi ne Mod el 200 Vo lts JEDEC Standard A115
Latch-Up 100 + ICC1 mA JEDEC Standard 78
Note:
(1) These parameters are characterized and are not 100% tested
(2) 100,000 Continuous Chip and Block cycling, 100,000 Continuous Sector cycli ng
Table 14. Program/Erase and Reliability data
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PACKAGE TYPE INFORMATION
JB:
8-Pin SOIC 208mil Broad Small Outline Integrated Circuit Package (Unit: millimeters)
Note: Package dimensions are shown in mm
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JN:
8-Pin 150mil Broad Small Outline Integrated Circuit (SOIC) Package
(measure in millimeters)
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JV:
8-Pin 150mil VVSOP Package
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Rev. C
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Continued: 8-Pin 150mil VVSOP Package
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JK:
8-Pin WSON Ult ra-Thin Small Outlin e No-Lead Package (Unit: millimeters)
Note: Package dimensions are shown in mm
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ORDERING I NFORMATION:
* Automotive grades (A* = A1, A2, A3)
Call Factory for other Package options available
Density
Frequency
(MHz)
Temperature Range Order Part Number *Package
8M 104
-40°C to +105°C
IS25LQ080-JBLE 8-pin SOIC 208mil
IS25LQ080-JNLE 8-pin SOIC 150mil
IS25LQ080-JVLE 8-pin VVSOP 150mil
IS25LQ080-JKLE 8-pin WSON (6x5mm)
Call Factory KGD KGD (Call Factory)
Extended Grade = E -40oC to 105oC
