HEF40174B Hex D-type flip-flop Rev. 6 -- 14 September 2011 Product data sheet 1. General description The HEF40174B is a hex edge-triggered D-type flip-flop with six data inputs (D0 to D5), a clock input (CP), an overriding asynchronous master reset input (MR), and six buffered outputs (Q0 to Q5). Information on D0 to D5 is transferred to Q0 to Q5 on the LOW-to-HIGH transition of CP if MR is HIGH. When LOW, MR resets all flip-flops (Q0 to Q5 = LOW) independent of CP and D0 to D5. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the full industrial (40 C to +85 C) temperature range. 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the full industrial temperature range 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Applications Industrial Shift registers Buffer/storage register Pattern generator 4. Ordering information Table 1. Ordering information All types operate from 40 C to +85 C. Type number Package Name Description Version HEF40174BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF40174BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF40174B NXP Semiconductors Hex D-type flip-flop 5. Functional diagram 3 4 D0 D 9 1 6 D1 Q 11 D2 Q D 13 D3 Q D 14 D4 Q D D5 Q D Q D FF1 FF2 FF3 FF4 FF5 FF6 CP CD CP CD CP CD CP CD CP CD CP CD CP MR Q0 Q1 2 Q2 5 Q3 7 Q4 10 Q5 12 15 001aae565 Fig 1. Functional diagram D0 D1 D D2 D D3 D D4 D D5 D D FF1 FF2 FF3 FF4 FF5 FF6 CP Q CP Q CP Q CP Q CP Q CP Q CD CD CD CD CD CD CP MR Q0 Q1 Q2 Q3 Q4 Q5 001aae567 Fig 2. Logic diagram HEF40174B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 14 September 2011 (c) NXP B.V. 2011. All rights reserved. 2 of 14 HEF40174B NXP Semiconductors Hex D-type flip-flop 6. Pinning information 6.1 Pinning HEF40174B MR 1 16 VDD Q0 2 15 Q5 D0 3 14 D5 D1 4 13 D4 Q1 5 12 Q4 D2 6 11 D3 Q2 7 10 Q3 VSS 8 9 CP 001aae566 Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description MR 1 master reset input (active LOW) Q0, Q1, Q2, Q3, Q4, Q5 2, 5, 7, 10, 12, 15 buffered output D0, D1, D2, D3, D4, D5 3, 4, 6, 11, 13, 14 data input VSS 8 ground supply voltage CP 9 clock input (LOW-to-HIGH; edge-triggered) VDD 16 supply voltage 7. Functional description Table 3. Function table[1] Input Output CP D MR Q H H H L H L X H no change X X L L [1] H = HIGH voltage level; L = LOW voltage level; X = don't care; = positive-going transition; = negative-going transition. HEF40174B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 14 September 2011 (c) NXP B.V. 2011. All rights reserved. 3 of 14 HEF40174B NXP Semiconductors Hex D-type flip-flop 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage Conditions VI < 0.5 V or VI > VDD + 0.5 V Min Max Unit 0.5 +18 V - 10 mA 0.5 VDD + 0.5 V - 10 mA - 10 mA IIK input clamping current VI input voltage IOK output clamping current II/O input/output current IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature VO < 0.5 V or VO > VDD + 0.5 V total power dissipation Ptot P power dissipation 40 +85 C DIP16 package [1] - 750 mW SO16 package [2] - 500 mW - 100 mW per output [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min VDD supply voltage 3 VI input voltage 0 Tamb ambient temperature in free air 40 t/V input transition rise and fall rate VDD = 5 V Typ Max Unit - 15 V - VDD V - +85 C - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL HIGH-level input voltage LOW-level input voltage HEF40174B Product data sheet Conditions IO < 1 A IO < 1 A VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Min Max Min Max Min Max Unit 5V 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V All information provided in this document is subject to legal disclaimers. Rev. 6 -- 14 September 2011 (c) NXP B.V. 2011. All rights reserved. 4 of 14 HEF40174B NXP Semiconductors Hex D-type flip-flop Table 6. Static characteristics ...continued VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VOH VOL IOH IOL LOW-level output voltage Tamb = 40 C VDD Tamb = 25 C Tamb = 85 C Unit Min Max Min Max Min Max 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V HIGH-level output voltage IO < 1 A 5V IO < 1 A 15 V - 0.05 - 0.05 - 0.05 V HIGH-level output current VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 mA VO = 4.6 V 5V - 0.52 - 0.44 - 0.36 mA VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 LOW-level output current II input leakage current IDD supply current CI Conditions mA VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA 15 V - 0.3 - 0.3 - 1.0 A 5V - 20 - 20 - 150 A 10 V - 40 - 40 - 300 A 15 V - 80 - 80 - 600 A - - - 7.5 - - pF IO = 0 A input capacitance - 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 C; or test circuit see Figure 5; unless otherwise specified. Symbol Parameter Conditions tPHL HIGH to LOW propagation delay CP to Qn; see Figure 4 MR to Qn; see Figure 4 tPLH tt tsu LOW to HIGH propagation delay transition time set-up time HEF40174B Product data sheet CP to Qn; see Figure 4 see Figure 4 Dn to CP; see Figure 4 VDD Extrapolation formula Min Typ Max Unit 5V 48 ns + (0.55 ns/pF)CL - 75 155 ns 10 V 19 ns + (0.23 ns/pF)CL - 30 65 ns 15 V 12 ns + (0.16 ns/pF)CL - 20 45 ns 5V 58 ns + (0.55 ns/pF)CL - 85 175 ns 10 V 24 ns + (0.23 ns/pF)CL - 35 70 ns 15 V 17 ns + (0.16 ns/pF)CL - 25 50 ns 5V 48 ns + (0.55 ns/pF)CL - 75 155 ns 10 V 19 ns + (0.23 ns/pF)CL - 30 65 ns 15 V 12 ns + (0.16 ns/pF)CL - 20 45 ns 5V 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns 5V 20 10 - ns 10 V 10 5 - ns 15 V 10 5 - ns All information provided in this document is subject to legal disclaimers. Rev. 6 -- 14 September 2011 (c) NXP B.V. 2011. All rights reserved. 5 of 14 HEF40174B NXP Semiconductors Hex D-type flip-flop Table 7. Dynamic characteristics ...continued VSS = 0 V; Tamb = 25 C; or test circuit see Figure 5; unless otherwise specified. Symbol Parameter Conditions th hold time Dn to CP; see Figure 4 pulse width tW recovery time trec [1] CP input LOW; minimum width; see Figure 4 MR input LOW; minimum width; see Figure 4 MR input; see Figure 4 maximum frequency see Figure 4 fmax VDD Extrapolation formula Min Typ Max Unit 5V 10 0 - ns 10 V 5 0 - ns 15 V 5 0 - ns 5V 70 35 - ns 10 V 30 15 - ns 15 V 20 10 - ns 5V 70 35 - ns 10 V 35 15 - ns 15 V 25 10 - ns 5V 45 25 - ns 10 V 20 10 - ns 15 V 15 5 - ns 5V 5 11 - MHz 10 V 15 30 - MHz 15 V 20 45 - MHz tt is the same as tTHL and tTLH. Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol PD Parameter dynamic power dissipation VDD 5V Typical formula for PD (W) where: PD = 3500 fi + (fo CL) VDD 2 10 V PD = 16000 fi + (fo CL) VDD2 15 V PD = 42000 fi + (fo CL) VDD2 fi = input frequency in MHz, fo = output frequency in MHz, CL = output load capacitance in pF, VDD = supply voltage in V, (fo CL) = sum of the outputs. HEF40174B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 14 September 2011 (c) NXP B.V. 2011. All rights reserved. 6 of 14 HEF40174B NXP Semiconductors Hex D-type flip-flop 12. Waveforms VI MR input 0V VI CP input VM 0V VI Dn input 0V tPLH VOH Qn output VOL VM 10 % tPHL tPHL 90 % tTLH tTHL 001aak039 a. CP and MR to Qn Propagation delays and Qn transition times 1/fmax VI VM CP input 0V tsu th tW VI VM Dn input 0V trec VI VM MR input 0V tW 001aae568 b. CP and MR minimum pulse widths, MR to CP recovery time, and Dn to CP set-up and hold times VOH and VOL are typical output voltage levels that occur with the output load. Set-up and hold times are shown as positive values but may be specified as negative values. The shaded area are where input changes result in predicable output performance. Measurement points are given in Table 9. Fig 4. Waveforms showing switching times HEF40174B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 14 September 2011 (c) NXP B.V. 2011. All rights reserved. 7 of 14 HEF40174B NXP Semiconductors Hex D-type flip-flop tW VI 90 % 90 % negative pulse VM VM 10 % 0V 10 % tf tr tr tf VI 90 % positive pulse 90 % VM VM 10 % 0V 10 % tW 001aaj781 a. Input waveforms VDD VI VO G DUT RT CL 001aag182 b. Test circuit Test data is given in Table 9. Definitions for test circuit: DUT = Device Under Test CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 5. Test circuit for measuring switching times Table 9. Measurement points and test data Supply voltage 5 V to 15 V HEF40174B Product data sheet Input Load VI VM tr, tf CL VDD 0.5VI 20 ns 50 pF All information provided in this document is subject to legal disclaimers. Rev. 6 -- 14 September 2011 (c) NXP B.V. 2011. All rights reserved. 8 of 14 HEF40174B NXP Semiconductors Hex D-type flip-flop 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 6. EUROPEAN PROJECTION Package outline SOT38-4 (DIP16) HEF40174B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 14 September 2011 (c) NXP B.V. 2011. All rights reserved. 9 of 14 HEF40174B NXP Semiconductors Hex D-type flip-flop SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 7. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) HEF40174B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 14 September 2011 (c) NXP B.V. 2011. All rights reserved. 10 of 14 HEF40174B NXP Semiconductors Hex D-type flip-flop 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF40174B v.6 20110914 Product data sheet - HEF40174B v.5 Modifications: * Table 6: IOH minimum values changed to maximum HEF40174B v.5 20100106 Product data sheet - HEF40174B v.4 HEF40174B v.4 20090813 Product data sheet - HEF40174B_CNV v.3 HEF40174B_CNV v.3 19950101 Product specification - HEF40174B_CNV v.2 HEF40174B_CNV v.2 19950101 Product specification - - HEF40174B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 14 September 2011 (c) NXP B.V. 2011. All rights reserved. 11 of 14 HEF40174B NXP Semiconductors Hex D-type flip-flop 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, HEF40174B Product data sheet authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 6 -- 14 September 2011 (c) NXP B.V. 2011. All rights reserved. 12 of 14 HEF40174B NXP Semiconductors Hex D-type flip-flop Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF40174B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 14 September 2011 (c) NXP B.V. 2011. All rights reserved. 13 of 14 HEF40174B NXP Semiconductors Hex D-type flip-flop 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 September 2011 Document identifier: HEF40174B