1. General description
The HEF40174B is a hex e dge-trig ge red D-type flip-flop with six data input s (D0 to D5), a
clock input (CP), an overriding asynchronous master reset input (MR), and six buffered
outputs (Q0 to Q5). Information on D0 to D5 is transferred to Q0 to Q5 on the
LOW-to-HIGH transition of CP if MR is HIGH. When LOW, MR resets all flip-flops (Q0 to
Q5 = LOW) independent of CP and D0 to D5.
It operates over a recommended VDD power supply r ange of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is
also suitable for use over the full industrial (40 C to +85 C) temperature range.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the full industrial temperature range 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
Industrial
Shift registers
Buffer/storage register
Pattern generator
4. Ordering information
HEF40174B
Hex D-type flip-flop
Rev. 6 — 14 September 2011 Product data sheet
Table 1. Ordering information
All types operate from
40
C to +85
C.
Type number Package
Name Description Version
HEF40174BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF40174BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
HEF40174B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 14 September 2011 2 of 14
NXP Semiconductors HEF40174B
Hex D-type flip-flop
5. Functional diagram
Fig 1. Functional di agram
001aae565
D0 D1 D2 D4 D5D3
Q0 Q1 Q2 Q3 Q4 Q5
151210752
3 4 6 11 13 14
CP
MR
9
1
FF1
D
CP
CD
Q
FF2
D
CP
CD
Q
FF3
D
CP
CD
Q
FF4
D
CP
CD
Q
FF5
D
CP
CD
Q
FF6
D
CP
CD
Q
Fig 2. Logic diag ram
001aae567
D0 D1 D2 D4 D5D3
Q0 Q1 Q2 Q3 Q4 Q5
CP
FF1
D
CP
CDQ
FF2
D
CP
CDQ
FF3
D
CP
CDQ
FF4
D
CP
CDQ
FF5
D
CP
CDQ
FF6
D
CP
CDQ
MR
HEF40174B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 14 September 2011 3 of 14
NXP Semiconductors HEF40174B
Hex D-type flip-flop
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; = positive-going transition; = negative-going transition.
Fig 3. Pin configuratio n
HEF40174B
MR VDD
Q0 Q5
D0 D5
D1 D4
Q1 Q4
D2 D3
Q2 Q3
VSS CP
001aae566
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
MR 1 master reset input (active LOW)
Q0, Q1, Q2, Q3, Q4, Q5 2, 5, 7, 10, 12, 15 buffered output
D0, D1, D2, D3, D4, D5 3, 4, 6, 11, 13, 14 data input
VSS 8 ground supply voltage
CP 9 clock input (LOW-to-HIGH; edge-triggered)
VDD 16 supply voltage
Table 3. Function table[1]
Input Output
CP DMR Q
HHH
LHL
X H no change
XXLL
HEF40174B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 14 September 2011 4 of 14
NXP Semiconductors HEF40174B
Hex D-type flip-flop
8. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
9. Recommended operating conditions
10. Static characteristics
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +18 V
IIK input clamping current V I<0.5 V or VI>V
DD + 0.5 V - 10 mA
VIinput voltage 0.5 VDD + 0.5 V
IOK output clamping curre nt VO<0.5 V or VO>V
DD + 0.5 V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature 40 +85 C
Ptot total power dissipation DIP16 package [1] - 750 mW
SO16 package [2] - 500 mW
P power dissipation per output - 100 mW
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage 3 - 15 V
VIinput voltage 0 - VDD V
Tamb ambient temperature in free air 40 - +85 C
t/V input transition rise and fall rate VDD = 5 V --3.75s/V
VDD = 10 V --0.5s/V
VDD = 15 V --0.08s/V
Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 CUnit
Min Max Min Max Min Max
VIH HIGH-level input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - V
VIL LOW-level input voltage IO < 1 A 5 V -1.5-1.5-1.5V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V
HEF40174B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 14 September 2011 5 of 14
NXP Semiconductors HEF40174B
Hex D-type flip-flop
11. Dynamic characteristics
VOH HIGH-level output voltage IO < 1 A 5 V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
VOL LOW-level output voltage IO < 1 A 5 V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
IOH HIGH-level output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA
VO = 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA
VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA
VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA
IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA
VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA
IIinput leakage current 15 V - 0.3 - 0.3 - 1.0 A
IDD supply current IO = 0 A 5 V - 20 - 20 - 150 A
10 V - 40 - 40 - 300 A
15 V - 80 - 80 - 600 A
CIinput capacitance - - - - 7.5 - - pF
Table 6. Static characteristics …continued
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 CUnit
Min Max Min Max Min Max
Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25
C; or test circuit see Figure 5; unless otherwise specified.
Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit
tPHL HIGH to LOW
propagation delay CP to Qn;
see Figure 4 5 V 48 ns + (0.55 ns/pF)CL- 75 155 ns
10 V 19 ns + (0.23 ns/pF)CL-3065ns
15 V 12 ns + (0.16 ns/pF)CL-2045ns
MR to Qn;
see Figure 4 5 V 58 ns + (0.55 ns/pF)CL- 85 175 ns
10 V 24 ns + (0.23 ns/pF)CL-3570ns
15 V 17 ns + (0.16 ns/pF)CL-2550ns
tPLH LOW to HIGH
propagation delay CP to Qn;
see Figure 4 5 V 48 ns + (0.55 ns/pF)CL- 75 155 ns
10 V 19 ns + (0.23 ns/pF)CL-3065ns
15 V 12 ns + (0.16 ns/pF)CL-2045ns
tttransition time see Figure 4 5 V 10 ns + (1.00 ns/pF)CL- 60 120 ns
10 V 9 ns + (0.42 ns/pF)CL-3060ns
15 V 6 ns + (0.28 ns/pF)CL-2040ns
tsu set-up time Dn to CP;
see Figure 4 5 V 20 10 - ns
10 V 10 5 - ns
15 V 10 5 - ns
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Product data sheet Rev. 6 — 14 September 2011 6 of 14
NXP Semiconductors HEF40174B
Hex D-type flip-flop
[1] tt is the same as tTHL and tTLH.
thhold time Dn to CP;
see Figure 4 5 V 10 0 - ns
10 V 5 0 - ns
15 V 5 0 - ns
tWpulse width CP input LOW;
minimum width;
see Figure 4
5 V 70 35 - ns
10 V 30 15 - ns
15 V 20 10 - ns
MR input LOW;
minimum width;
see Figure 4
5 V 70 35 - ns
10 V 35 15 - ns
15 V 25 10 - ns
trec recovery time MR input;
see Figure 4 5 V 45 25 - ns
10 V 20 10 - ns
15 V 15 5 - ns
fmax maximum frequency see Figure 4 5 V 5 11 - MHz
10 V 15 30 - MHz
15 V 20 45 - MHz
Table 7. Dynamic characteristics …continued
VSS = 0 V; Tamb = 25
C; or test circuit see Figure 5; unless otherwise specified.
Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf
20 ns; Tamb = 25
C.
Symbol Parameter VDD Typical formula for PD (W) where:
PDdynamic power
dissipation 5 V PD = 3500 fi + (fo CL) VDD2fi = input frequency in MHz,
fo = output frequency in MHz,
CL = output load capacitance in pF,
VDD = supply voltage in V,
(fo CL) = sum of the outputs.
10 V PD = 16000 fi + (fo CL) VDD2
15 V PD = 42000 fi + (fo CL) VDD2
HEF40174B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 14 September 2011 7 of 14
NXP Semiconductors HEF40174B
Hex D-type flip-flop
12. Waveforms
a. CP and MR to Qn Propagation delays and Qn transition times
b. CP and MR mini mum pulse widths, MR to CP recovery time, and Dn to CP set-up and hold times
VOH and VOL are typical output voltage levels that occur with the output load.
Set-up and hold times are shown as positive values but may be specified as negative values.
The shaded area are where input changes result in predicable output performance.
Measurement points are given in Table 9.
Fig 4. Waveforms showing switching times
001aak039
Qn output VM
10 %
90 %
tTLH
tPLH tPHL tPHL
tTHL
VOH
VOL
CP input VM
VI
0 V
Dn input
VI
0 V
MR input
VI
0 V
001aae568
CP input
Dn input
MR input
tW
th
tsu
VM
VM
VI
0 V
VI
0 V
VI
0 V
1/fmax
trec
tW
VM
HEF40174B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 14 September 2011 8 of 14
NXP Semiconductors HEF40174B
Hex D-type flip-flop
a. Inpu t waveforms
b. Test circuit
Test data is given in Table 9.
Definitions for test circuit:
DUT = Device Under Test
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 5. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
90 %
10 %
t
f
t
r
t
r
t
f
001aaj781
VDD
VIVO
001aag182
DUT
CL
RT
G
Table 9. Measurement points and test data
Supply voltage Input Load
VIVMtr, tfCL
5Vto15V V
DD 0.5VI 20 ns 50 pF
HEF40174B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 14 September 2011 9 of 14
NXP Semiconductors HEF40174B
Hex D-type flip-flop
13. Package outline
Fig 6. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT38-4 95-01-14
03-02-13
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
b2
e
D
A2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT A
max. 12 b1(1) (1) (1)
b2cD E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min. A
max. bmax.
w
ME
e1
1.73
1.30 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 0.764.2 0.51 3.2
inches 0.068
0.051 0.021
0.015 0.014
0.009
1.25
0.85
0.049
0.033 0.77
0.73 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.030.17 0.02 0.13
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF40174B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 14 September 2011 10 of 14
NXP Semiconductors HEF40174B
Hex D-type flip-flop
Fig 7. Package outline SOT109-1 (SO16)
HEF40174B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 14 September 2011 11 of 14
NXP Semiconductors HEF40174B
Hex D-type flip-flop
14. Revision history
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF40174B v.6 20110914 Product data sheet - HEF40174B v.5
Modifications: Table 6: IOH minimum val ues changed to maximum
HEF40174B v.5 20100106 Product data sheet - HEF40174B v.4
HEF40174B v.4 20090813 Product data sheet - HEF40174B_CNV v.3
HEF40174B_CNV v.3 19950101 Product specification - HEF40174B_CNV v.2
HEF40174B_CNV v.2 19950101 Product specification - -
HEF40174B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 14 September 2011 12 of 14
NXP Semiconductors HEF40174B
Hex D-type flip-flop
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information se e the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ionThe information and data provided in a Product
data sheet shall define the specification of the product as agreed be tween
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggreg ate and cumulative li ability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-crit ical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer's own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings onl y and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
HEF40174B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 14 September 2011 13 of 14
NXP Semiconductors HEF40174B
Hex D-type flip-flop
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization fro m national authorities.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors HEF40174B
Hex D-type flip-flop
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 September 2011
Document identifier : HEF40174B
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16 Contact information. . . . . . . . . . . . . . . . . . . . . 13
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14