© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS031-1 (v1.7) October 2, 2001 www.xilinx.com Module 1 of 4
Advance Product Specification 1-800-255-7778 1
Summary of Virtex®-II Features
• Industry First Platform FPGA Solution
• IP-Immersion™ Architecture
- Densities from 40K to 8M system gates
- 420 MHz internal clock speed (Advance Data)
- 840+ Mb/s I/O (Advance Data)
• SelectRAM™ Memory Hierarchy
- 3 Mb of True Dual -Port ™ RAM in 18-Kbi t block
SelectRAM resources
- Up to 1.5 Mb of distr ibuted Sele ctRAM r esources
- Hig h-pe rfor ma nce i nte rfac es to e xte rna l me mor y
·DDR-SDRAM interface
·FCRAM inter face
·QDR™-SR AM interface
·Sigma RAM interface
•Arit hmetic Functi ons
- Dedicat ed 18-bit x 18-bit mult iplier blocks
- Fast look-a head c arry lo gic ch ains
•Flexible Logic Resources
- Up to 93,184 internal registers / latches with Clock
Enable
- Up to 93,184 look-u p tabl es (LU Ts) or c ascada ble
16-bit shift registers
- Wid e multi plexer s and wi de-inpu t func tion su pport
- Horizontal cascade chain and Sum-of-Products
support
- Int ernal 3 -stat e bussi ng
•High- Perform ance C lock Ma nagem ent Circ uitr y
- Up to 12 DCM (Digital Clock Manager) modules
·Precise clock de -skew
·Flexible freque ncy synthesis
·High-resolut ion ph ase sh ifting
- 16 global clo ck multiplexer buffers
•Active Interconnect™ Techn ology
- Fou rth ge nerati on seg mented routin g stru cture
- Pred ictab le, fas t routi ng delay, i ndepe ndent of
fanout
•Sele c tI/ O -U l tr a™ Tec hn olo gy
- Up to 1 ,10 8 u ser I/ Os
- 19 s ingle -ended standa rds and six di fferen tial
stan dards
- Programmable sink current (2mA to 24mA) per I/O
- Digital ly Controlled Imped ance (DCI) I/O: on-c hip
termination resistors for single-ended I/O standards
- PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz
compliance, and CardBus compliant
- Differentia l Signaling
·840 Mb/s Low-Volta ge Dif ferential Signaling I/O
(LVDS) with current mode drivers
·Bus LVDS I/O
·Lightning Dat a Transport (LDT) I/O with cu rrent
driver buffers
·Low-Voltage Pos itive E mitter-Co upled Logic
(LVPECL) I/O
·Built-in DDR In put and Output regis ters
- Prop riet ary hi gh-per forma nce Sele ctLin k™
Technol ogy
·High-bandwidth data path
·Double Data Rat e (DDR) link
·Web-based HDL generation meth odology
•Supporte d by Xilinx Foundation ™ and Alliance™
Seri es Devel opmen t System s
- Integrated VHDL and Verilog design flows
- Compilation of 10M system gates designs
- Int ernet Team Des ign (ITD ) tool
•SRAM -Based I n-Syst em Co nfigura tion
-Fast SelectMAP™ configuration
- Triple Data Encryption Standard (DES) security
option (Bitstream Encryption)
- IEEE1532 support
- Partial reconfiguration
- Unlimi ted re-programmabilit y
- Readbac k capab ility
•0.15 µ m 8-Laye r Metal proce ss with 0.12 µm
high -spee d transis tors
•1.5 V (V CCINT
) core po wer su pply, dedi cated 3. 3 V
VCCAUX auxil iary an d VCCO I/O power supplies
•IEEE 1149.1 compati ble bo undar y-scan logic s uppor t
•Flip-Ch ip and Wire-Bo nd Ball Gr id Array (BGA)
packages in three standard fine pitches (0.80mm,
1.00m m, a nd 1.2 7mm )
•100% f actory teste d
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Virtex-II 1.5V
Field-Programmable Gate Arrays
DS03 1-1 (v1 .7) Oct ober 2, 2001 00Advance Product Specifica tion
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Virtex-II 1.5V Field-Programma ble Gate Arrays R
Module 1 of 4 www.xilinx.com DS031-1 (v1.7) October 2, 2001
2 1-800-255-7778 Advance Product Specification
General Description
The Vir tex-II fa mily is a pla tform FPG A develope d for high
performance from low-density to high-density designs that
are ba sed on IP cores an d custo mized mo dule s. The fam ily
delivers comple te solutions for tele communication , wire-
less, netwo rki ng, vi deo, a nd DS P appl icati ons, inclu ding
PCI, LVDS, and DDR inter faces.
The leading-edge 0.15µm / 0.12µm CMOS 8-layer metal
proce ss and t he Vir tex-II archit ecture are opti mize d for high
speed with lo w power consump tion. Combin ing a wi de vari-
ety of flexible features and a large range of densities up to
10 milli on system gates, the Virtex-II family enhances p ro-
gramm able lo gic de sign cap abili ties an d is a po werful a lter-
native to mask-programmed gates arrays. As shown in
Tab le 1, the Virtex-II family comprises 12 members, ranging
from 40K to 10M system gates.
Packaging
Offerings include ball grid array (BGA) packages with
0.80mm, 1.00mm, and 1.27mm pitches. In addition to tradi-
tional wire-bond interconnects, flip-chip interconnect is used
in some of the BGA offerings. The use of flip-chip intercon-
nect offers more I/Os th an is possible in wire-bon d versions
of the similar packages. Flip-Chip construction offers the
combination of high pin count with high thermal capacity.
Tab le 2 sh ows the m axim um numbe r of use r I/Os availabl e.
The Vir tex-II dev ice/p ackage com bination table (Tab l e 6 at
the end of this section) details the maximum number of I/Os
for each device and package using wire-bond or flip-chip
tech nolo gy.
Table 1: Vi rte x-II Field-Programmable Gate Array Family Members
Device
Syst em
Gates
CLB
(1 CLB = 4 slices = Max 128 bits)
Multiplier
Blocks
SelectRAM Blocks
DCMs
Max I/O
Pads (1)
Array
Row x Col. Slices
Maximum
Distributed
RAM Kbit s
18-Kbi t
Blocks
Max RAM
(Kbits)
XC2V 40 40K 8 x 8 256 8 4 4 72 4 88
XC2V80 80K 16 x 8 512 16 8 8 144 4 120
XC2V 250 250K 24 x 16 1, 536 48 24 24 432 8 200
XC2V 500 500K 32 x 24 3, 072 96 32 32 576 8 264
XC2V 1000 1M 40 x 32 5,12 0 160 40 40 7 20 8 4 32
XC2V 1500 1.5M 48 x 40 7,680 240 48 48 864 8 5 28
XC2V 2000 2M 56 x 48 10,75 2 33 6 56 56 1,008 8 6 24
XC2V 3000 3M 64 x 56 14,33 6 44 8 96 96 1,728 12 720
XC2V 4000 4M 80 x 72 23,04 0 72 0 120 120 2 ,160 12 912
XC2V 6000 6M 96 x 88 33,79 2 1,056 144 1 44 2,592 12 1,104
XC2V 8000 8 M 1 12 x 10 4 46, 592 1,45 6 168 168 3,024 12 1,1 08
Notes:
1. See details in Ta bl e 2, “Ma ximum Number of User I/O P ads”.
Table 2: Maximum Number of User I/O Pads
Device W ire-Bond Flip-Chip
XC2V 40 88
XC2V 80 120
XC2V 250 20 0
XC2V 500 26 4
XC2V1000 328 432
XC2V1500 392 528
XC2V2000 456 624
XC2V3000 516 720
XC2V 4000 9 12
XC2V 6000 1, 104
XC2V 8000 1, 108
Virtex-II 1.5V Field-Programmable Gate Arrays
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DS031-1 (v1.7) October 2, 2001 www.xilinx.com Module 1 of 4
Advance Product Specification 1-800-255-7778 3
Architecture
Virt ex-II Arra y Ov ervie w
Virt ex-I I device s are u ser-pro gramm able g ate ar rays wi th var ious conf igur able el ement s. The Virt ex-II arch itect ure i s
opti mized fo r high -dens ity and high -perf ormanc e log ic des igns. As shown i n Figure 1, t he program mable dev ice is
comprised of input/output blocks (IOBs) and internal configurable logic blocks (CLBs).
Programmable I/O blocks provide the interface between
pack age pins a nd the inter nal conf igur able logi c. Mos t
popul ar and leadin g-edg e I/O st andard s are sup port ed by
the programmable IOBs.
The internal configurable logic includes four major elements
orga nized in a regula r array.
•Configurable Logic Blocks (CLBs) provide functional
eleme nts for c ombina tori al and s ynchro nous logic,
incl uding b asic st orage e lemen ts. BUFT s (3-st ate
buffers) associated with each CLB element drive
dedi cated s egment able ho rizont al rout ing re source s.
•Block Select RAM memory modules p rovide large
18-K bit sto rage el ement s of True Du al-Por t RAM.
•Mult iplier blocks a re 18-bi t x 18-b it de dicate d
multiplier s.
•DCM (Digital Clock Manager) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock multiplication
and division, coarse and fine-grained clock phase
shifting.
A new gen eratio n of progra mmab le routin g resour ces call ed
Activ e Interc onnect Technolo gy interc onnects all of t hese
eleme nts. T he ge neral routin g matr ix ( GRM) i s an ar ray of
routi ng switch es. Each p rogramma ble elem ent is tie d to a
switch ma trix, allowing multiple c onnections to the genera l
routing ma trix. T he overall program mable int erconnect ion is
hiera rchic al and d esigne d to sup port hi gh-sp eed des igns.
All programmable elements, including the routing
resou rces, a re cont roll ed by valu es stor ed in st atic memory
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.
Virt ex-II Fea tures
This sec tio n br ie fly d es crib es V ir tex- II f eat ures.
Input/Output Blocks (IO Bs)
IOBs ar e prog ramma ble and can be cat egoriz ed as fol lows:
•Input block with an optional single-data-rate or
double-da ta-rate (DD R) registe r
•Outpu t block w ith an option al sing le-da ta-rat e or DD R
regis ter, and an opti onal 3 -state buffer, to be dr iven
direc tly or t hrough a singl e or DD R regist er
•Bi-d irecti onal bl ock (any combi nation of inpu t and
outpu t c onfi gu ratio ns)
These registers are either edge-triggered D-type flip-flops
or level-s ensitive la tches.
IOBs support the following single-ended I/O standards:
•LVTTL, LVCMOS (3.3 V, 2.5 V, 1.8 V, and 1.5 V)
•PCI-X at 133 MHz, PCI (3.3 V at 33 MHz and 66 MHz)
•GTL and GTLP
•HSTL (Class I, II, III, and IV)
Figure 1: Virt ex- II Arch itec tur e O verv iew
Global Clock Mux
DCM DCM IOB
CLB
Programmable I/Os
Block SelectRAM Multiplier
Configurable Logic
DS031_28_100900
Virtex-II 1.5V Field-Programma ble Gate Arrays R
Module 1 of 4 www.xilinx.com DS031-1 (v1.7) October 2, 2001
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•SSTL (3.3 V and 2.5 V, Class I and II)
•AGP- 2X
The di gitally controll ed imped ance (D CI) I/O fea ture aut o-
matically provides on-chip termination for each I/O element.
The IOB elements also support the following differential sig-
nalin g I/O st andar ds:
•LVD S
•BLVDS ( Bus LVD S)
•ULVDS
•LDT
•LVPECL
Two adja cent pad s are used fo r each dif ferent ial pai r. Two or
four IOB blocks connect to one switch matrix to access the
routi ng res ources .
Configurable Logic Blocks (CLBs)
CLB re sources inclu de four sli ces and t wo 3-state bu ffers.
Each slice is equivalent and contains:
•Two function generators (F & G)
•Two stor age elem ents
•Arithmetic lo gic gates
•Large multip lexers
•Wide fu nctio n c apa bil ity
•Fast carry look-ahead chain
•Horizontal cascade chain (OR gate)
The function generators F & G are configurable as 4-input
look- up tabl es (LU Ts), as 16- bit sh ift re giste rs, or as 16- bit
distributed SelectRAM memory.
In addi tion, th e two stora ge elemen ts are eit her edge- trig-
gered D-type flip-flops or level-se nsitive latches.
Each CLB has internal fast interconnect and connects to a
switch matrix to access general routing resources.
Block SelectRAM Memory
The block SelectRAM memory resources are 18K b of True
Dual- Port R AM, pro grammab le fro m 16K x 1 bi t to 512 x 36
bits, in various depth and width configurations. Each port is
total ly syn chron ous an d inde pende nt, of ferin g three
"read-during-write" modes. Block SelectRAM me mory is
cascadable to implement large embedded storage blocks.
Suppo rte d memor y config urat ions fo r dual- por t and sin-
gle-port modes are shown in Table 3.
A multiplier block is associated with each SelectRAM mem-
ory bl ock. Th e mult ipli er bloc k is a d edicat ed 18 x 18-bit
mult ipli er a nd is op timi zed for o pera ti ons b as ed o n the blo ck
Sele ctRAM c onten t on on e port . The 1 8 x 18 mu ltipli er can
be us ed indepe ndently of the block Sel ectRAM r esourc e.
Read /multipl y/accumu late oper ations a nd DSP fi lter struc -
tures are extremely efficient.
Both the SelectRAM memory and the multiplier resource
are connected to four switch matrices to access the general
routi ng res ources .
Global Clocking
The DC M and g loba l clock multi plexer buffers pr ovide a
complete solution for designing high-speed clocking
schemes.
Up to 12 DCM blocks are available. To generate de-skewed
internal or external clocks, each DCM can be used to elimi-
nate clock distribution delay. The DCM also provides 90-,
180-, and 270-degree phase-shifted versions of its output
clocks. Fine-grained phase shifting offers high-resolution
phase adju stmen ts in inc rem ents of 1 /256 of the clo ck
peri od. Very fl exible freq uency synth esis pr ovide s a c lock
output frequency equal to any M/D ratio of the input clock
frequ ency, w here M and D a re tw o inte gers. For the exact
timing parameters, see Virtex™-II Electrical Characteris-
tics.
Virtex-II devices have 16 global clock MUX buffers, with up
to eight clock nets per quadrant. Each global clock MUX
buffer can select one of the two clock inputs and switch
glitch-free from one clock to the other. Each DCM block is
able t o drive up to four of the 1 6 global clock MUX buf fers.
Routing Resources
The IOB, CLB, block Select RAM, multiplier, and DCM ele-
ments all use the sa me inter conne ct sche me and th e same
access to the global routing matrix. Timing models are
share d, gr eatly improvi ng the pre dicta bilit y of t he perf or-
mance of high -spee d desig ns.
There are a total of 16 global clock lines, with eight available
per qu adrant . In add itio n, 24 ve rtica l and h orizon tal lo ng
lines per row or column as well as massive secondary and
local routin g reso urces pr ovide fast int erco nnect . Virt ex-II
buffer ed in terco nnect s are relat ively unaffe cted by net
fanout and the inte rconne ct layout is de signed to mi nimize
crosstalk.
Horizontal and vertical routing resources for each row or
column include:
•24 lon g lines
•120 hex lines
•40 doub le line s
•16 direct connect lines (total in all four directions)
Table 3: Dual- Port And Single-Port C onfigurations
16K x 1 bit 2K x 9 bits
8K x 2 bits 1K x 18 bits
4K x 4 bits 512 x 36 bits
Virtex-II 1.5V Field-Programmable Gate Arrays
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DS031-1 (v1.7) October 2, 2001 www.xilinx.com Module 1 of 4
Advance Product Specification 1-800-255-7778 5
Boundary Scan
Boundary scan instructions and associated data registers
support a standard methodology for accessing and config-
urin g Virtex -II devic es that compli es with IEEE stan dards
1149.1 - 1993 and 1532. A system mod e and a test mode
are implemented. In system mode, a Virtex-II device per-
form s its in tende d missio n even w hile exec utin g non-test
boundary-scan instructions. In test mode, boundary-scan
test instruc tions co ntrol th e I/O pi ns for tes ting pu rposes.
The Virtex-II Test Access Port (TAP) supports BYPASS,
PRELOAD, SAMPLE, IDCODE, and USERCODE non-test
instructions. The EXTEST, INTEST, and HIGHZ test instruc-
tion s are al so supp orted .
Configuration
Virt ex-II de vices a re conf igured by loadin g data i nto in terna l
configurat ion memory, using the followin g five modes:
•Slave- ser ial mod e
•Master- serial mode
•Slave SelectMAP mode
•Master SelectMAP mode
•Boundary-Scan mode (IEEE 1532)
A Data Encryption Standard (DES) decryp tor is available
on-chip to secure the bitstreams. One or two triple-DES key
sets c an be u sed to opti onall y encr ypt the con figu ration
informatio n.
Readback and Integrated L ogic Analyzer
Conf igurat ion dat a stor ed in Virtex -II co nfigur atio n memor y
can be read back for verification. Along with the configura-
tion data, the contents of all flip-flops/latches, distributed
SelectRAM, and block SelectRAM memory resources can
be rea d back. This capa bility is us eful for rea l-time de bug-
ging .
The I ntegra ted Logi c Anal yzer (I LA) c ore and softwar e pro-
vides a complete solution for accessing and verifying
Virtex-II devices.
Virtex-II Device/Package Combinations
and Maximum I/O
Wire-bond and flip-chip packages are available. Tabl e 4 and
Tab le 5 sh ow the ma ximum po ssib le numbe r of use r I/Os in
wire-bond and flip-chip packages, respectively. Tab le 6
shows the numb er of avai lable us er I/O s for all device/ pack-
age co mbina tions.
•CS denote s wire-bond chip-scal e ball grid array (BGA)
(0.8 0 mm p itch ).
•FG denote s wire-bond f ine-pitch BGA (1.00 mm pitch ).
•FF denotes flip-chip fine-pitch BGA (1.00mm pitch).
•BG denotes standard BGA (1.27m m pitch).
•BF denotes flip-chip BGA (1.27mm pitch).
The number of I/Os per package include all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
PWRDWN_B, TCK, TDI , TDO, TMS, HSWAP_EN, DXN,
DXP, AND RSVD) and VBATT.
Table 4: Wi re-Bo nd Packag es Inf ormati on
Package CS144 FG256 FG456 FG676 BG575 BG728
Pitch (mm) 0.80 1.00 1.00 1.00 1.27 1.27
Size (mm) 12 x 12 17 x 17 23 x 23 27 x 27 31 x 31 35 x 35
I/Os 92 172 324 484 408 516
Table 5: Flip-Chip Packages Information
Package FF896 FF1152 FF1517 BF957
Pitch (mm) 1.00 1.00 1.00 1.27
Size (mm) 31 x 31 35 x 35 40 x 40 40 x 40
I/Os 624 824 1, 108 684
Virtex-II 1.5V Field-Programma ble Gate Arrays R
Module 1 of 4 www.xilinx.com DS031-1 (v1.7) October 2, 2001
6 1-800-255-7778 Advance Product Specification
Virtex-II Ordering Information
Virtex-II ordering information is shown in Figure2
Table 6: Vi rtex -II Devic e/Pack age Com bina tions and Maxi mum Num ber of Availabl e I/Os (A dvan ce Inform ation )
Packa ge
Available I/Os
XC2V
40
XC2V
80
XC2V
250
XC2V
500
XC2V
1000
XC2V
1500
XC2V
2000
XC2V
3000
XC2V
4000
XC2V
6000
XC2V
8000
CS144 88 92 9 2
FG256 88 120 172 172 172
FG4 56 200 26 4 324
FG6 76 392 45 6 4 84
FF896 432 528 624
FF11 52 720 824 824 824
FF15 17 912 1,104 1,108
BG575 328 392 408
BG72 8 456 516
BF95 7 624 6 84 68 4 684 684
Notes:
1. All devices in a particular package are pin-out (footprint) compatible. In addition, the FG456 and FG676 packages are compatible, as
are the FF896 and FF1152 packages.
Figure 2: Virt ex- II Ordering Informat ion
Example: XC2V1000-5FG456C
Device Type Temperature Range
C = Commercial (Tj = 0˚C to +85˚C)
I = Industrial (Tj = -40˚C to +100˚C)
Number of Pins
Package Type
Speed Grade
(-4, -5, -6)
DS031_35_033001
Virtex-II 1.5V Field-Programmable Gate Arrays
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DS031-1 (v1.7) October 2, 2001 www.xilinx.com Module 1 of 4
Advance Product Specification 1-800-255-7778 7
Revision History
This section records the change history for this module of the data sheet.
Virtex-II Data Sheet
The Vi rtex- II Dat a Sheet c ontai ns the fo llowing modu les:
•DS03 1-1, Vi rtex- II 1.5V FPGAs: I ntrod uctio n and
Order ing In format ion (M odule 1 )
•DS03 1-2, Vi rtex- II 1.5V FPGAs: Functional Description
(Module 2)
•DS03 1-3, Vi rtex- II 1.5V FPGAs: D C and Switching
Characteristics (Module 3)
•DS03 1-4, Vi rtex- II 1.5V FPGAs: P inout Tab les
(Module4)
Date Version Revision
11/0 7/00 1.0 E arly ac cess dra ft.
12/0 6/00 1.1 I nitial releas e.
01/1 5/01 1.2 A dded val ues to t he tabl es in th e Virtex -II Pe rform ance Cha racte ristic s and Virtex-II
Switching Characteristics sections.
01/2 5/01 1.3 Th e data s heet was divi ded int o four mo dules (per the curren t style stan dard).
04/02/01 1.5 Skipped v1.4 to sync up modules. Reverted to traditional double-column format.
07/30/01 1.6 Made minor changes to items listed under Summ ary of Vi rtex ®-II Features.
10/0 2/01 1.7 Mi nor ed its.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS031-2 (v1.9) November 29, 2001 www.xilinx.com Module 2 of 4
Advance Product Specification 1-800-255-7778 1
Detailed Description
Input/Output Blocks (IOBs)
Virtex-II I/O blocks (IOBs) are provided in groups of two or
four on the perimeter of each device. Each IOB can be used
as input and/or output for single-ended I/Os. Two IOBs can
be used as a differential pair. A differential pair is always
connected to the same switch matrix, as shown in Figure 1.
IOB blocks are designed for high performances I/Os, sup-
porting 19 single-ended standards, as well as differential
signaling with LVDS, LDT, Bus LVDS, and LVPECL.
Supported I/O Standards
Virtex-II IOB blocks feature SelectI/O inputs and outputs
that support a wide variety of I/O signaling standards. In
addition to the internal supply voltage (VCCINT = 1.5V), out-
put driver supply voltage (VCCO) is dependent on the I/O
standard (see Ta ble 1 ). An auxiliary supply voltage
(VCCAUX = 3.3 V) is required, regardless of the I/O stan-
dard used. For exact supply voltage absolute maximum rat-
ings, see DC Input and Output Levels.
0
Virtex-II 1.5V
Field-Programmable Gate Arrays
DS031-2 (v1.9) November 29, 2001 00Advance Product Specification
R
Figure 1: Virtex-II Input/Output Tile
IOB
PAD4
IOB
PAD3
Differential Pair
IOB
PAD2
IOB
PAD1
Differential Pair
Switch
Matrix
DS031_30_101600
Table 1: Supported Single-Ended I/O Standards
I/O
Standard
Output
VCCO
Input
VCCO
Input
VREF
Board
Termination
Voltage (VTT)
LVTTL 3.3 3.3 N/A N/A
LVCMOS33 3.3 3.3 N/A N/A
LVCMOS25 2.5 2.5 N/A N/A
LVCMOS18 1.8 1.8 N/A N/A
LVCMOS15 1.5 1.5 N/A N/A
PCI33_3 3.3 3.3 N/A N/A
PCI66_3 3.3 3.3 N/A N/A
PCI-X 3.3 3.3 N/A N/A
GTL Note 1 Note 1 0.8 1.2
GTLP Note 1 Note 1 1.0 1.5
HSTL_I 1.5 N/A 0.75 0.75
HSTL_II 1.5 N/A 0.75 0.75
HSTL_III 1.5 N/A 0.9 1.5
HSTL_IV 1.5 N/A 0.9 1.5
SSTL2_I 2.5 N/A 1.25 1.25
SSTL2_II 2.5 N/A 1.25 1.25
SSTL3_I 3.3 N/A 1.5 1.5
SSTL3_II 3.3 N/A 1.5 1.5
AGP-2X/AGP 3.3 N/A 1.32 N/A
Notes:
1. VCCO of GTL or GTLP should not be lower than the
termination voltage or the voltage seen at the I/O pad.
Virtex-II 1.5V Field-Programmable Gate Arrays R
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All of the user IOBs have fixed-clamp diodes to VCCO and to
ground. The IOBs are not compatible or compliant with 5 V
I/O standards (not 5 V tolerant).
Table 3 lists supported I/O standards with Digitally Con-
trolled Impedance. See Digitally Controlled Impedance
(DCI), page 9.
Logic Resources
IOB blocks include six storage elements, as shown in
Figure 2.
Each storage element can be configured either as an
edge-triggered D-type flip-flop or as a level-sensitive latch.
On the input, output, and 3-state path, one or two DDR reg-
isters can be used.
Double data rate is directly accomplished by the two regis-
ters on each path, clocked by the rising edges (or falling
edges) from two different clock nets. The two clock signals
are generated by the DCM and must be 180 degrees out of
phase, as shown in Figure 3. There are two input, output,
and 3-state data signals, each being alternately clocked out.
Table 2: Supported Differential Signal I/O Standards
I/O
Standard
Output
VCCO
Input
VCCO
Input
VREF
Output
VOD
LVPECL_33 3.3 N/A N/A 490 mV
to 1.22 V
LDT_25 2.5 N/A N/A 0.430 - 0.670
LVDS_33 3.3 N/A N/A 0.250 - 0.400
LVDS_25 2.5 N/A N/A 0.250 - 0.400
LVDSEXT_33 3.3 N/A N/A 0.330 - 0.700
LVDSEXT_25 2.5 N/A N/A 0.330 - 0.700
BLVDS_25 2.5 N/A N/A 0.250 - 0.450
ULVDS_25 2.5 N/A N/A 0.430 - 0.670
Table 3: Supported DCI I/O Standards
I/O
Standard
Output
VCCO
Input
VCCO
Input
VREF
Termination
Type
LVDCI_33(1) 3.3 3.3 N/A Series
LVDCI_DV2_33(1) 3.3 3.3 N/A Series
LVDCI_25(1) 2.5 2.5 N/A Series
LVDCI_DV2_25(1) 2.5 2.5 N/A Series
LVDCI_18(1) 1.8 1.8 N/A Series
LVDCI_DV2_18(1) 1.8 1.8 N/A Series
LVDCI_15(1) 1.5 1.5 N/A Series
LVDCI_DV2_15(1) 1.5 1.5 N/A Series
GTL_DCI 1.2 1.2 0.8 Single
GTLP_DCI 1.5 1.5 1.0 Single
HSTL_I_DCI 1.5 1.5 0.75 Split
HSTL_II_DCI 1.5 1.5 0.75 Split
HSTL_III_DCI 1.5 1.5 0.9 Single
HSTL_IV_DCI 1.5 1.5 0.9 Single
SSTL2_I_DCI(2) 2.5 2.5 1.25 Split
SSTL2_II_DCI(2) 2.5 2.5 1.25 Split
SSTL3_I_DCI(2) 3.3 3.3 1.5 Split
SSTL3_II_DCI(2) 3.3 3.3 1.5 Split
Notes:
1. LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled
impedance buffers, matching the reference resistors or half
of the reference resistors.
2. These are SSTL compatible.
Figure 2: Virtex-II IOB Block
Reg
OCK1
Reg
OCK2
Reg
ICK1
Reg
ICK2
DDR mux Input
PAD
3-State
Reg
OCK1
Reg
OCK2
DDR mux
Output
IOB
DS031_29_100900
Virtex-II 1.5V Field-Programmable Gate Arrays
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DS031-2 (v1.9) November 29, 2001 www.xilinx.com Module 2 of 4
Advance Product Specification 1-800-255-7778 3
This DDR mechanism can be used to mirror a copy of the
clock on the output. This is useful for propagating a clock
along the data that has an identical delay. It is also useful for
multiple clock generation, where there is a unique clock
driver for every clock load. Virtex-II devices can produce
many copies of a clock with very little skew.
Each group of two registers has a clock enable signal (ICE
for the input registers, OCE for the output registers, and
TCE for the 3-state registers). The clock enable signals are
active High by default. If left unconnected, the clock enable
for that storage element defaults to the active state.
Each IOB block has common synchronous or asynchronous
set and reset (SR and REV signals).
SR forces the storage element into the state specified by the
SRHIGH or SRLOW attribute. SRHIGH forces a logic “1”.
SRLOW forces a logic “0”. When SR is used, a second input
(REV) forces the storage element into the opposite state. The
reset condition predominates over the set condition. The ini-
tial state after configuration or global initialization state is
defined by a separate INIT0 and INIT1 attribute. By default,
the SRLOW attribute forces INIT0, and the SRHIGH attribute
forces INIT1.
For each storage element, the SRHIGH, SRLOW, INIT0,
and INIT1 attributes are independent. Synchronous or
asynchronous set / reset is consistent in an IOB block.
All the control signals have independent polarity. Any
inverter placed on a control input is automatically absorbed.
Each register or latch (independent of all other registers or
latches) (see Figure 4) can be configured as follows:
• No set or reset
• Synchronous set
• Synchronous reset
• Synchronous set and reset
• Asynchronous set (preset)
• Asynchronous reset (clear)
• Asynchronous set and reset (preset and clear)
The synchronous reset overrides a set, and an asynchro-
nous clear overrides a preset.
Figure 3: Double Data Rate Registers
D1
CLK1
DDR MUX
Q1
FDDR
D2
CLK2
(50/50 duty cycle clock)
CLOCK
QQ
Q2
D1
CLK1
DDR MUX
DCM
Q1
FDDR
D2
CLK2
Q2
180°0°
DS031_26_100900
Virtex-II 1.5V Field-Programmable Gate Arrays R
Module 2 of 4 www.xilinx.com DS031-2 (v1.9) November 29, 2001
4 1-800-255-7778 Advance Product Specification
Input/Output Individual Options
Each device pad has optional pull-up, pull-down, and
weak-keeper in LVTTL and LVCMOS SelectI/O configura-
tions, as illustrated in Figure 5. Values of the optional
pull-up and pull-down resistors are in the range 10 - 60 K
W
,
which is the specification for VCCO when operating at 3.3 V
(from 3.0 to 3.6 V only). The clamp diode is always present,
even when power is not.
The optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low. If the pin is con-
nected to a multiple-source signal, the weak-keeper holds
the signal in its last state if all drivers are disabled. Maintain-
Figure 4: Register / Latch Configuration in an IOB Block
FF
LATCH
SR REV
D1 Q1
CE
CK1
FF
LATCH
SR REV
D2
FF1
FF2
DDR MUX
Q2
CE
CK2
REV
SR
(O/T) CLK1
(OQ or TQ)
(O/T) CE
(O/T) 1
(O/T) CLK2
(O/T) 2
Attribute INIT1
INIT0
SRHIGH
SRLOW
Attribute INIT1
INIT0
SRHIGH
SRLOW Reset Type
SYNC
ASYNC
DS031_25_110300
Shared
by all
registers
Figure 5: LVTTL, LVCMOS or PCI SelectI/O Standards
VCCO
VCCO
VCCO
Weak
Keeper
Program
Delay
OBUF
IBUF
Program Current
Clamp
Diode
10-60KΩ
10-60KΩ
PAD
VCCAUX = 3.3V
DS031_23_011601
VCCINT = 1.5V
Virtex-II 1.5V Field-Programmable Gate Arrays
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DS031-2 (v1.9) November 29, 2001 www.xilinx.com Module 2 of 4
Advance Product Specification 1-800-255-7778 5
ing a valid logic level in this way eliminates bus chatter;
pull-up or pull-down override the weak-keeper circuit.
LVTTL sinks and sources current up to 24 mA. The current
is programmable for LVTTL and LVCMOS SelectI/O stan-
dards (see Table 4). Drive-strength and slew-rate controls
for each output driver, minimize bus transients. For LVDCI
and LVDCI_DV2 standards, drive strength and slew-rate
controls are not available.
Figure 6 shows the SSTL2, SSTL3, and HSTL configura-
tions. HSTL can sink current up to 48 mA. (HSTL IV)
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. Virtex-II
uses two memory cells to control the configuration of an I/O
as an input. This is to reduce the probability of an I/O con-
figured as an input from flipping to an output when sub-
jected to a single event upset (SEU) in space applications.
Prior to configuration, all outputs not involved in configura-
tion are forced into their high-impedance state. The
pull-down resistors and the weak-keeper circuits are inac-
tive. The dedicated pin HSWAP_EN controls the pull-up
resistors prior to configuration. By default, HSWAP_EN is
set high, which disables the pull-up resistors on user I/O
pins. When HSWAP_EN is set low, the pull-up resistors are
activated on user I/O pins.
All Virtex-II IOBs support IEEE 1149.1 compatible boundary
scan testing.
Input Path
The Virtex-II IOB input path routes input signals directly to
internal logic and / or through an optional input flip-flop or
latch, or through the DDR input registers. An optional delay
element at the D-input of the storage element eliminates
pad-to-pad hold time. The delay is matched to the internal
clock-distribution delay of the Virtex-II device, and when
used, assures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signaling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, VREF
. The need to supply VREF imposes
constraints on which standards can be used in the same
bank. See I/O banking description.
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output and / or the
3-state signal can be routed to the buffer directly from the
internal logic or through an output / 3-state flip-flop or latch,
or through the DDR output / 3-state registers.
Each output driver can be individually programmed for a
wide range of low-voltage signaling standards. In most sig-
naling standards, the output High voltage depends on an
externally supplied VCCO voltage. The need to supply VCCO
imposes constraints on which standards can be used in the
same bank. See I/O banking description.
I/O Banking
Some of the I/O standards described above require VCCO
and VREF voltages. These voltages are externally supplied
and connected to device pins that serve groups of IOB
blocks, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
Eight I/O banks result from dividing each edge of the FPGA
into two banks, as shown in Figure 7 and Figure 8. Each
bank has multiple VCCO pins, all of which must be con-
Table 4: LVTTL and LVCMOS Programmable Currents (Sink and Source)
SelectI/O Programmable Current (Worst-Case Guaranteed Minimum)
LVTTL 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA
LVCMOS33 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA
LVCMOS25 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA
LVCMOS18 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA n/a
LVCMOS15 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA n/a
Figure 6: SSTL or HSTL SelectI/O Standards
VCCO
OBUF
VREF
Clamp
Diode
PAD
VCCAUX = 3.3V
VCCINT = 1.5V
DS031_24_100900
Virtex-II 1.5V Field-Programmable Gate Arrays R
Module 2 of 4 www.xilinx.com DS031-2 (v1.9) November 29, 2001
6 1-800-255-7778 Advance Product Specification
nected to the same voltage. This voltage is determined by
the output standards in use.
Within a bank, output standards can be mixed only if they
use the same VCCO. Tabl e 5 lists compatible output stan-
dards. GTL and GTLP appear under all voltages because
their open-drain outputs do not depend on VCCO.
Some input standards require a user-supplied threshold
voltage, VREF
. In this case, certain user-I/O pins are auto-
matically configured as inputs for the VREF voltage. Approx-
imately one in six of the I/O pins in the bank assume this
role. Table 6 lists compatible input standards.
VREF pins within a bank are interconnected internally, and
consequently only one VREF voltage can be used within
each bank. However, for correct operation, all VREF pins in
the bank must be connected to the external reference volt-
age source.
The VCCO and the VREF pins for each bank appear in the
device pinout tables. Within a given package, the number of
VREF and VCCO pins can vary depending on the size of
device. In larger devices, more I/O pins convert to VREF
pins. Since these are always a superset of the VREF pins
used for smaller devices, it is possible to design a PCB that
permits migration to a larger device if necessary.
All VREF pins for the largest device anticipated must be con-
nected to the VREF voltage and not used for I/O. In smaller
devices, some VCCO pins used in larger devices do not con-
nect within the package. These unconnected pins can be
left unconnected externally, or, if necessary, they can be
connected to the VCCO voltage to permit migration to a
larger device.
Figure 7: Virtex-II I/O Banks: Top View for Wire-Bond
Packages (CS, FG, & BG)
Figure 8: Virtex-II I/O Banks: Top View for Flip-Chip
Packages (FF & BF)
ug002_c2_014_112900
Bank 0 Bank 1
Bank 5 Bank 4
Bank 7
Bank 6
Bank 2
Bank 3
ds031_66_112900
Bank 1 Bank 0
Bank 4 Bank 5
Bank 2
Bank 3
Bank 7
Bank 6
Table 5: Compatible Output Standards
VCCO Compatible Standards
3.3 V PCI, LVTTL, SSTL3 (I & II), AGP-2X, LVDS_33,
LVDSEXT_33, LVCMOS33, LVDCI_33,
LVDCI_DV2_33, SSTL3_DCI (I & II), LVPECL,
GTL, GTLP
2.5 V SSTL2 (I & II), LVCMOS25, GTL, GTLP,
LVDS_25, LVDSEXT_25, LVDCI_25,
LVDCI_DV2_25, SSTL2_DCI (I & II), LDT,
ULVDS, BLVDS
1.8 V LVCMOS18, GTL, GTLP, LVDCI_18,
LVDCI_DV2_18
1.5 V HSTL (I, II, III, & IV), LVCMOS15, GTL, GTLP,
LVDCI_15, LVDCI_DV2_15, GTLP_DCI,
HSTL_DCI (I,II, III & IV)
1.2V GTL_DCI
Virtex-II 1.5V Field-Programmable Gate Arrays
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Advance Product Specification 1-800-255-7778 7
Table 6: Compatible Input Standards
VCCO
VREF
3.3V 2.5V 1.8V 1.5V 1.2V
No VREF LVTTL, LVDCI_33,
LVDCI_DV2_33,
LVCMOS33,
PCI33_3, PCI66_3,
PCI-X, LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS,
ULVDS_252
LVCMOS25,
LVDCI_25,
LVDCI_DV2_25,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMO S18,
LVDCI_18,
LVDCI_DV2_18,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMO S15,
LVDCI_15,
LVDCI_DV2_15,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
1.5V LVTTL, LVDCI_33,
LVDCI_DV2_33,
LVCMOS33,
PCI33_3, PCI66_3,
PCI-X, LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25,
SSTL3_I_DCI,
SSTL3_II_DCI
LVCMOS25,
LVDCI_25,
LVDCI_DV2_25,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMO S18,
LVDCI_18,
LVDCI_DV2_18,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMO S15,
LVDCI_15,
LVDCI_DV2_15,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
SSTL3_I, SSTL3_II SSTL3_I, SSTL3_II SSTL3_I, SSTL3_II SSTL3_I, SSTL3_II SSTL3_I, SSTL3_II
1.32V LVTTL, LVDCI_33,
LVDCI_DV2_33,
LVCMOS33,
PCI33_3, PCI66_3,
PCI-X, LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMOS25,
LVDCI_25,
LVDCI_DV2_25,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMO S18,
LVDCI_18,
LVDCI_DV2_18,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMO S15,
LVDCI_15,
LVDCI_DV2_15,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
AGP-2X/AGP AGP-2X/AGP AGP-2X/AGP AGP-2X/AGP AGP-2X/AGP
1.25V LVTTL, LVDCI_33,
LVDCI_DV2_33,
LVCMOS33,
PCI33_3, PCI66_3,
PCI-X, LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMOS25,
LVDCI_25,
LVDCI_DV2_25,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25,
SSTL2_I_DCI,
SSTL2_II_DCI
LVCMO S18,
LVDCI_18,
LVDCI_DV2_18,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMO S15,
LVDCI_15,
LVDCI_DV2_15,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
SSTL2_I, SSTL2_II SSTL2_I, SSTL2_II SSTL2_I, SSTL2_II SSTL2_I, SSTL2_II SSTL2_I, SSTL2_II
Virtex-II 1.5V Field-Programmable Gate Arrays R
Module 2 of 4 www.xilinx.com DS031-2 (v1.9) November 29, 2001
8 1-800-255-7778 Advance Product Specification
1.0V LVTTL, LVDCI_33,
LVDCI_DV2_33,
LVCMOS33,
PCI33_3, PCI66_3,
PCI-X, LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMOS25,
LVDCI_25,
LVDCI_DV2_25,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMO S18,
LVDCI_18,
LVDCI_DV2_18,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMO S15,
LVDCI_15,
LVDCI_DV2_15,
GTLP_DCI,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
GTLP GTLP GTLP GTLP GTLP
0.9V LVTTL, LVDCI_33,
LVDCI_DV2_33,
LVCMOS33,
PCI33_3, PCI66_3,
PCI-X, LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMOS25,
LVDCI_25,
LVDCI_DV2_25,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMO S18,
LVDCI_18,
LVDCI_DV2_18,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMO S15,
LVDCI_15,
LVDCI_DV2_15,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25,
HSTL_III_DCI,
HSTL_IV_DCI
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
HSTL_III, HSTL_IV HSTL_III, HSTL_IV HSTL_III, HSTL_IV HSTL_III, HSTL_IV HSTL_III, HSTL_IV
0.8V LVTTL, LVDCI_33,
LVDCI_DV2_33,
LVCMOS33,
PCI33_3, PCI66_3,
PCI-X, LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMOS25,
LVDCI_25,
LVDCI_DV2_25,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMO S18,
LVDCI_18,
LVDCI_DV2_18,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMO S15,
LVDCI_15,
LVDCI_DV2_15,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
GTL_DCI,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
GTLGTLGTLGTLGTL
0.75V LVTTL, LVDCI_33,
LVDCI_DV2_33,
LVCMOS33,
PCI33_3, PCI66_3,
PCI-X, LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMOS25,
LVDCI_25,
LVDCI_DV2_25,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMO S18,
LVDCI_18,
LVDCI_DV2_18,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
LVCMO S15,
LVDCI_15,
LVDCI_DV2_15,
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25,
HSTL_I_DCI,
HSTL_II_DCI
LVDS_33,
LVDSEXT_33,
LVPECL_33,
LVDS_25,
LVDSEXT_25, LDT,
BLVDS, ULVDS_25
HSTL_I, HSTL_II HSTL_I, HSTL_II HSTL_I, HSTL_II HSTL_I, HSTL_II HSTL_I, HSTL_II
Notes:
1. Inputs that are VREF controlled are completely independent of those that are VCCO controlled. Therefore, VREF controlled inputs can
also be placed in banks with inputs and outputs of different voltages that are VCCO controlled.
2. All non-DCI differential inputs are VCCAUX controlled. This makes them (Inputs Only) very flexible in terms of banking rules.
Table 6: Compatible Input Standards
VCCO
VREF
3.3V 2.5V 1.8V 1.5V 1.2V
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Advance Product Specification 1-800-255-7778 9
Digitally Controlled Impedance (DCI)
Today’s chip output signals with fast edge rates require ter-
mination to prevent reflections and maintain signal integrity.
High pin count packages (especially ball grid arrays) can
not accommodate external termination resistors.
Virtex-II DCI provides controlled impedance drivers and
on-chip termination for single-ended I/Os. This eliminates
the need for external resistors, and improves signal integrity.
The DCI feature can be used on any IOB by selecting one of
the DCI I/O standards.
When applied to inputs, DCI provides input parallel termina-
tion. When applied to outputs, DCI provides controlled
impedance drivers (series termination) or output parallel
termination.
DCI operates independently on each I/O bank. When a DCI
I/O standard is used in a particular I/O bank, external refer-
ence resistors must be connected to two dual-function pins
on the bank. These resistors, voltage reference of N transis-
tor (VRN) and the voltage reference of P transistor (VRP)
are shown in Figure 9.
When used with a terminated I/O standard, the value of
resistors are specified by the standard (typically 50
W
).
When used with a controlled impedance driver, the resistors
set the output impedance of the driver within the specified
range (25
W
to 100
W)
. For all series and parallel termina-
tions listed in Table 7 and Table 8, the reference resistors
must have the same value for any given bank. One percent
resistors are recommended.
The DCI system adjusts the I/O impedance to match the two
external reference resistors, or half of the reference resis-
tors, and compensates for impedance changes due to volt-
age and/or temperature fluctuations. The adjustment is
done by turning parallel transistors in the IOB on or off.
Controlled Impedance Drivers (Series
Termination)
DCI can be used to provide a buffer with a controlled output
impedance. It is desirable for this output impedance to
match the transmission line impedance (Z). Virtex-II input
buffers also support LVDCI and LVDCI_DV2 I/O standards.
Controlled Impedance Drivers (Parallel
Termination)
DCI also provides on-chip termination for SSTL3, SSTL2,
HSTL (Class I, II, III, or IV), and GTL/GTLP receivers or
transmitters on bidirectional lines.
Table 8 lists the on-chip parallel terminations available in Vir-
tex-II devices. VCCO must be set according to Table 3. Note
that there is a VCCO requirement for GTL_DCI and
GTLP_DCI, due to the on-chip termination resistor.
Figure 9: DCI in a Virtex-II Bank
DS031_50_101200
VCCO
GND
DCI
DCI
DCI
DCI
VRN
VRP
1 Bank
RREF (1%)
RREF (1%)
Figure 10: Internal Series Termination
Table 7: SelectI/O Controlled Impedance Buffers
VCCO DCI DCI Half Impedance
3.3 V LVDCI_33 LVDCI_DV2_33
2.5 V LVDCI_25 LVDCI_DV2_25
1.8 V LVDCI_18 LVDCI_DV2_18
1.5 V LVDCI_15 LVDCI_DV2_15
Table 8: SelectI/O Buffers With On-Chip Parallel
Termination
I/O Standard
External
Termination
On-Chip
Termination
SSTL3 Class I SSTL3_I SSTL3_I_DCI(1)
SSTL3 Class II SSTL3_II SSTL3_II_DCI(1)
SSTL2 Class I SSTL2_I SSTL2_I_DCI(1)
SSTL2 Class II SSTL2_II SSTL2_II_DCI(1)
HSTL Class I HSTL_I HSTL_I_DCI
HSTL Class II HSTL_II HSTL_II_DCI
HSTL Class III HSTL_III HSTL_III_DCI
HSTL Class IV HSTL_IV HSTL_IV_DCI
GTL GTL GTL_DCI
GTLP GTLP GTLP_DCI
Notes:
1. SSTL Compatible
Z
IOB
Z
Virtex-II DCI
DS031_51_110600
VCCO = 3.3 V, 2.5 V, 1.8 V or 1.5 V
Virtex-II 1.5V Field-Programmable Gate Arrays R
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10 1-800-255-7778 Advance Product Specification
Figure 11 provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, and HSTL_IV_DCI I/O
standards. For a complete list, see the Virtex-II User Guide.
Figure 11: HSTL DCI Usage Examples
Virtex-II DCI
RR
VCCO VCCO
RR
VCCO VCCO
R
VCCO
R
VCCO
Virtex-II DCI
Virtex-II DCI
R
VCCO
R
VCCO
Virtex-II DCI
RR
VCCO/2 VCCO/2
2R
Virtex-II DCI
2R
R
VCCO VCCO/2
Virtex-II DCI
2R
R
VCCO/2
2R
VCCO
2R
Virtex-II DCI
2R
VCCO
Virtex-II DCI
2R
2R
VCCO
DS031_65a_100201
Conventional
DCI Transmit
Conventional
Receive
Conventional
Transmit
DCI Receive
DCI Transmit
DCI Receive
Bidirectional
Reference
Resistor
Recommended
Z0
VRN = VRP = R = Z0
50 Ω
VRN = VRP = R = Z0
50 Ω
VRN = VRP = R = Z0
50 Ω
VRN = VRP = R = Z0
50 Ω
HSTL_I HSTL_II HSTL_III HSTL_IV
N/A N/A
Virtex-II DCI
R
VCCO
R
VCCO
R
VCCO
Virtex-II DCI
R
VCCO
Virtex-II DCI
Z0
R
VCCO/2
Virtex-II DCI
R
VCCO/2
Virtex-II DCI
2R
2R
VCCO
Virtex-II DCI Virtex-II DCI
2R
2R
VCCO
Z0
Z0
Z0
Z0
Z0
Z0Z0
Z0
Z0
Z0
Z0Z0
Z0
Z0
Z0
Virtex-II DCI
Virtex-II DCI
Z0
Virtex-II DCI
2R
2R
VCCO
2R
2R
VCCO
Virtex-II DCI
Z0
Virtex-II DCI
R
VCCO
R
VCCO
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Advance Product Specification 1-800-255-7778 11
Figure 12 provides examples illustrating the use of the SSTL2_I_DCI, SSTL2_II_DCI, SSTL3_I_DCI, and SSTL3_II_DCI I/O
standards. For a complete list, see the Virtex-II User Guide.
Figure 12: SSTL DCI Usage Examples
DS031_65b_100201
Conventional
DCI Transmit
Conventional
Receive
Conventional
Transmit
DCI Receive
DCI Transmit
DCI Receive
Bidirectional
Reference
Resistor
Recommended
Z0
VRN = VRP = R = Z0
50 Ω
VRN = VRP = R = Z0
50 Ω
VRN = VRP = R = Z0
50 Ω
VRN = VRP = R = Z0
50 Ω
SSTL2_I SSTL2_II SSTL3_I SSTL3_II
N/A N/A
Virtex-II DCI
Z0
R
VCCO/2
Z0
R/2
RR
VCCO/2 VCCO/2
Z0
R/2
RR
VCCO/2 VCCO/2
Z0
R/2
R
VCCO/2
Z0
R/2
R
VCCO/2
Z0
R/2
Virtex-II DCI
2R
2R
VCCO
R
VCCO/2
Z0
R/2
Virtex-II DCI
2R
2R
VCCO
Z0
R/2
Virtex-II DCI
2R
2R
VCCO
Z0
R/2
Virtex-II DCI
2R
2R
VCCO
Virtex-II DCI
R
VCCO VCCO/2
2R
Virtex-II DCI
R
VCCO VCCO/2
2R
Virtex-II DCI
R
VCCO/2
Z0Z0Z0
Virtex-II DCI
R
VCCO/2
Z02R
2R
2R
Virtex-II DCI
2R
VCCO
Virtex-II DCI
2R
2R
VCCO
Z0
Virtex-II DCI
Virtex-II DCI
2R
2R
VCCO
Z0
2R
Virtex-II DCI
2R
VCCO
Virtex-II DCI
2R
2R
VCCO
Z0
Virtex-II DCI
2R
2R
VCCO
Virtex-II DCI
Z0
Virtex-II DCI
2R
2R
VCCO
2R
2R
VCCO
Virtex-II DCI
Z0
Virtex-II DCI
2R
2R
VCCO
2R
2R
VCCO
25Ω
25Ω
25Ω
25Ω
25Ω
25Ω
25Ω
25Ω
25Ω
25Ω
25Ω
25Ω
Virtex-II 1.5V Field-Programmable Gate Arrays R
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12 1-800-255-7778 Advance Product Specification
Configurable Logic Blocks (CLBs)
The Virtex-II configurable logic blocks (CLB) are organized
in an array and are used to build combinatorial and synchro-
nous logic designs. Each CLB element is tied to a switch
matrix to access the general routing matrix, as shown in
Figure 13. A CLB element comprises 4 similar slices, with
fast local feedback within the CLB. The four slices are split
in two columns of two slices with two independent carry
logic chains and one common shift chain.
Slice Description
Each slice includes two 4-input function generators, carry
logic, arithmetic logic gates, wide function multiplexers and
two storage elements. As shown in Figure 14, each 4-input
function generator is programmable as a 4-input LUT, 16
bits of distributed SelectRAM memory, or a 16-bit vari-
able-tap shift register element.
The output from the function generator in each slice drives
both the slice output and the D input of the storage element.
Figure 15 shows a more detailed view of a single slice.
Configurations
Look-Up Table
Virtex-II function generators are implemented as 4-input
look-up tables (LUTs). Four independent inputs are pro-
vided to each of the two function generators in a slice (F and
G). These function generators are each capable of imple-
menting any arbitrarily defined boolean function of four
inputs. The propagation delay is therefore independent of
the function implemented. Signals from the function gener-
ators can exit the slice (X or Y output), can input the XOR
dedicated gate (see arithmetic logic), or input the carry-logic
multiplexer (see fast look-ahead carry logic), or feed the D
input of the storage element, or go to the MUXF5 (not
shown in Figure 15).
In addition to the basic LUTs, the Virtex-II slice contains
logic (MUXF5 and MUXFX multiplexers) that combines
function generators to provide any function of five, six,
seven, or eight inputs. The MUXFX are either MUXF6,
MUXF7 or MUXF8 according to the slice considered in the
CLB. Selected functions up to nine inputs (MUXF5 multi-
plexer) can be implemented in one slice. The MUXFX can
also be a MUXF6, MUXF7, or MUXF8 multiplexers to map
any functions of six, seven, or eight inputs and selected
wide logic functions.
Register/Latch
The storage elements in a Virtex-II slice can be configured
either as edge-triggered D-type flip-flops or as level-sensi-
tive latches. The D input can be directly driven by the X or Y
output via the DX or DY input, or by the slice inputs bypass-
ing the function generators via the BX or BY input. The clock
enable signal (CE) is active High by default. If left uncon-
nected, the clock enable for that storage element defaults to
the active state.
In addition to clock (CK) and clock enable (CE) signals,
each slice has set and reset signals (SR and BY slice
inputs). SR forces the storage element into the state speci-
fied by the attribute SRHIGH or SRLOW. SRHIGH forces a
logic “1” when SR is asserted. SRLOW forces a logic “0”.
When SR is used, a second input (BY) forces the storage
element into the opposite state. The reset condition is pre-
dominant over the set condition. (See Figure 16.)
The initial state after configuration or global initial state is
defined by a separate INIT0 and INIT1 attribute. By default,
setting the SRLOW attribute sets INIT0, and setting the
SRHIGH attribute sets INIT1.
For each slice, set and reset can be set to be synchronous
or asynchronous. Virtex-II devices also have the ability to
set INIT0 and INIT1 independent of SRHIGH and SRLOW.
The control signals clock (CLK), clock enable (CE) and
set/reset (SR) are common to both storage elements in one
slice. All of the control signals have independent polarity. Any
inverter placed on a control input is automatically absorbed.
Figure 13: Virtex-II CLB Element
Figure 14: Virtex-II Slice Configuration
Slice
X1Y1
Slice
X1Y0
Slice
X0Y1
Slice
X0Y0
Fast
Connects
to neighbors
Switch
Matrix
DS031_32_101600
SHIFT CIN
COUT
TBUF X0Y1 COUT
CIN
TBUF X0Y0
Register
MUXF5
MUXFx
CY
SRL16
RAM16
LUT
G
Register
Arithmetic Logic
CY
LUT
F
DS031_31_100900
SRL16
RAM16
ORCY
Virtex-II 1.5V Field-Programmable Gate Arrays
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Advance Product Specification 1-800-255-7778 13
Figure 15: Virtex-II Slice (Top Half)
G4
SOPIN
A4
G3 A3
G2 A2
G1 A1
WG4 WG4
WG3 WG3
WG2 WG2
WG1
BY
WG1
Dual-Port
LUT
FF
LATCH
RAM
ROM
Shift-Reg
D
0
MC15
WS
SR
SR
REV
DI
G
Y
G2
G1
BY
1
0
PROD
DQ
CECE CKCLK
MUXCY YB
DIG
DY
Y
01
MUXCY
01
1
SOPOUT
DYMUX
GYMUX
YBMUX
ORCY
WSG
WE[2:0] SHIFTOUT
CYOG
XORG
WE
CLK
WSF
ALTDIG
CE
SR
CLK
SLICEWE[2:0]
MULTAND
Shared between
x & y Registers
SHIFTIN COUT
CIN DS031_01_080601
Q
Virtex-II 1.5V Field-Programmable Gate Arrays R
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14 1-800-255-7778 Advance Product Specification
The set and reset functionality of a register or a latch can be
configured as follows:
•No set or reset
•Synchronous set
•Synchronous reset
•Synchronous set and reset
•Asynchronous set (preset)
•Asynchronous reset (clear)
•Asynchronous set and reset (preset and clear)
The synchronous reset has precedence over a set, and an
asynchronous clear has precedence over a preset.
Distributed SelectRAM Memory
Each function generator (LUT) can implement a 16 x 1-bit
synchronous RAM resource called a distributed SelectRAM
element. The SelectRAM elements are configurable within
a CLB to implement the following:
•Single-Port 16 x 8 bit RAM
•Single-Port 32 x 4 bit RAM
•Single-Port 64 x 2 bit RAM
•Single-Port 128 x 1 bit RAM
•Dual-Port 16 x 4 bit RAM
•Dual-Port 32 x 2 bit RAM
•Dual-Port 64 x 1 bit RAM
Distributed SelectRAM memory modules are synchronous
(write) resources. The combinatorial read access time is
extremely fast, while the synchronous write simplifies
high-speed designs. A synchronous read can be imple-
mented with a storage element in the same slice. The dis-
tributed SelectRAM memory and the storage element share
the same clock input. A Write Enable (WE) input is active
High, and is driven by the SR input.
Table 9 shows the number of LUTs (2 per slice) occupied by
each distributed SelectRAM configuration.
For single-port configurations, distributed SelectRAM mem-
ory has one address port for synchronous writes and asyn-
chronous reads.
For dual-port configurations, distributed SelectRAM mem-
ory has one port for synchronous writes and asynchronous
reads and another port for asynchronous reads. The func-
tion generator (LUT) has separated read address inputs
(A1, A2, A3, A4) and write address inputs (WG1/WF1,
WG2/WF2, WG3/WF3, WG4/WF4).
In single-port mode, read and write addresses share the
same address bus. In dual-port mode, one function genera-
tor (R/W port) is connected with shared read and write
addresses. The second function generator has the A inputs
(read) connected to the second read-only port address and
the W inputs (write) shared with the first read/write port
address.
Figure 16: Register / Latch Configuration in a Slice
FF
FFY
LATCH
SR REV
DQ
CE
CK
YQ
FF
FFX
LATCH
SR REV
DQ
CE
CK
XQ
CE
DX
DY
BY
CLK
BX
SR
Attribute
INIT1
INIT0
SRHIGH
SRLOW
Attribute
INIT1
INIT0
SRHIGH
SRLOW
Reset Type
SYNC
ASYNC
DS031_22_110600
Table 9: Distributed SelectRAM Configurations
RAM Number of LUTs
16 x 1S 1
16 x 1D 2
32 x 1S 2
32 x 1D 4
64 x 1S 4
64 x 1D 8
128 x 1S 8
Notes:
1. S = single-port configuration; D = dual-port configuration
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Advance Product Specification 1-800-255-7778 15
Figure 17, Figure 18, and Figure 19 illustrate various exam-
ple configurations.
Similar to the RAM configuration, each function generator
(LUT) can implement a 16 x 1-bit ROM. Five configurations
are available: ROM16x1, ROM32x1, ROM64x1,
ROM128x1, and ROM256x1. The ROM elements are cas-
cadable to implement wider or/and deeper ROM. ROM con-
tents are loaded at configuration. Table 10 shows the
number of LUTs occupied by each configuration.
Figure 17: Distributed SelectRAM (RAM16x1S)
Figure 18: Single-Port Distributed SelectRAM
(RAM32x1S)
A[3:0]
D
D
DIWS
WSG
WE
WCLK
RAM 16x1S
DQ
RAM
WE
CK
A[4:1]
WG[4:1]
Output
Registered
Output
(optional)
(SR)
4
4
(BY)
DS031_02_100900
A[3:0]
D
WSG
F5MUX
WE
WCLK
RAM 32x1S
DQ
WE
WE0
CK
WSF
D
DIWS
RAM
G[4:1]
A[4]
WG[4:1]
D
DIWS
RAM
F[4:1]
WF[4:1]
Output
Registered
Output
(optional)
(SR)
4
(BY)
(BX)
4
DS031_03_110100
Figure 19: Dual-Port Distributed SelectRAM
(RAM16x1D)
Table 10: ROM Configuration
ROM Number of LUTs
16 x 1 1
32 x 1 2
64 x 1 4
128 x 1 8 (1 CLB)
256 x 1 16 (2 CLBs)
A[3:0]
D
WSG
WE
WCLK
RAM 16x1D
WE
CK
D
DIWS
RAM
G[4:1]
WG[4:1]
dual_port
RAM
dual_port
4
(BY)
DPRA[3:0]
SPO
A[3:0]
WSG
WE
CK
D
DIWS
G[4:1]
WG[4:1]
DPO
4
4
DS031_04_110100
(SR)
Virtex-II 1.5V Field-Programmable Gate Arrays R
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16 1-800-255-7778 Advance Product Specification
Shift Registers
Each function generator can also be configured as a 16-bit
shift register. The write operation is synchronous with a
clock input (CLK) and an optional clock enable, as shown in
Figure 20. A dynamic read access is performed through the
4-bit address bus, A[3:0]. The configurable 16-bit shift regis-
ter cannot be set or reset. The read is asynchronous, how-
ever the storage element or flip-flop is available to
implement a synchronous read. The storage element
should always be used with a constant address. For exam-
ple, when building an 8-bit shift register and configuring the
addresses to point to the 7th bit, the 8th bit can be the
flip-flop. The overall system performance is improved by
using the superior clock-to-out of the flip-flops.
An additional dedicated connection between shift registers
allows connecting the last bit of one shift register to the first
bit of the next, without using the ordinary LUT output. (See
Figure 21.) Longer shift registers can be built with dynamic
access to any bit in the chain. The shift register chaining
and the MUXF5, MUXF6, and MUXF7 multiplexers allow up
to a 128-bit shift register with addressable access to be
implemented in one CLB.
Figure 20: Shift Register Configurations
A[3:0]
SHIFTIN
SHIFTOUT
D(BY)
D
MC15
DI
WSG
CE (SR)
CLK
SRLC16
DQ
SHIFT-REG
WE
CK
A[4:1] Output
Registered
Output
(optional)
4
DS031_05_110600
WS
Figure 21: Cascadable Shift Register
SRLC16
MC15
MC15
D
SRLC16
DI
SHIFTIN
CASCADABLE OUT
SLICE S0
SLICE S1
SLICE S2
SLICE S3
1 Shift Chain
in CLB
CLB
DS031_06_110200
FF
FF
D
SRLC16
MC15
MC15
D
SRLC16
DI
SHIFTIN
SHIFTOUT
FF
FF
D
SRLC16
MC15
MC15
D
SRLC16
DI
DI
SHIFTIN
IN
SHIFTOUT
FF
FF
D
SRLC16
MC15
MC15
D
SRLC16
DI
SHIFTOUT
FF
FF
D
DI
DI
DI
OUT
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Advance Product Specification 1-800-255-7778 17
Multiplexers
Virtex-II function generators and associated multiplexers
can implement the following:
•4:1 multiplexer in one slice
•8:1 multiplexer in two slices
•16:1 multiplexer in one CLB element (4 slices)
•32:1 multiplexer in two CLB elements (8 slices)
Each Virtex-II slice has one MUXF5 multiplexer and one
MUXFX multiplexer. The MUXFX multiplexer implements
the MUXF6, MUXF7, or MUXF8, as shown in Figure 22.
Each CLB element has two MUXF6 multiplexers, one
MUXF7 multiplexer and one MUXF8 multiplexer. Examples
of multiplexers are shown in the Virtex-II User Guide. Any
LUT can implement a 2:1 multiplexer.
Fast Lookahead Carry Logic
Dedicated carry logic provides fast arithmetic addition and
subtraction. The Virtex-II CLB has two separate carry
chains, as shown in the Figure 23.
The height of the carry chains is two bits per slice. The carry
chain in the Virtex-II device is running upward. The dedi-
cated carry path and carry multiplexer (MUXCY) can also
be used to cascade function generators for implementing
wide logic functions.
Arithmetic Logic
The arithmetic logic includes an XOR gate that allows a
2-bit full adder to be implemented within a slice. In addition,
a dedicated AND (MULT_AND) gate (shown in Figure 15)
improves the efficiency of multiplier implementation.
Figure 22: MUXF5 and MUXFX multiplexers
Slice S1
Slice S0
Slice S3
Slice S2
CLB
DS031_08_100201
F5
F6
F5
F7
F5
F6
F5
F8
MUXF8 combines
the two MUXF7 outputs
(Two CLBs)
MUXF6 combines the two MUXF5
outputs from slices S2 and S3
MUXF7 combines the two MUXF6
outputs from slices S0 and S2
MUXF6 combines the two MUXF5
outputs from slices S0 and S1
G
F
G
F
G
F
G
F
Virtex-II 1.5V Field-Programmable Gate Arrays R
Module 2 of 4 www.xilinx.com DS031-2 (v1.9) November 29, 2001
18 1-800-255-7778 Advance Product Specification
Figure 23: Fast Carry Logic Path
FF
LUT
OI MUXCY
FF
LUT
OI MUXCY
FF
LUT
OI MUXCY
FF
LUT
OI MUXCY
CIN
CIN CIN
COUT
FF
LUT
OI MUXCY
FF
LUT
OI MUXCY
FF
LUT
OI MUXCY
FF
LUT
OI MUXCY
CIN
COUT
COUT
to CIN of S2 of the next CLB
COUT
to S0 of the next CLB
(First Carry Chain)
(Second Carry Chain)
SLICE S1
SLICE S0
SLICE S3
SLICE S2
CLB
DS031_07_110200
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Advance Product Specification 1-800-255-7778 19
Sum of Products
Each Virtex-II slice has a dedicated OR gate named ORCY,
ORing together outputs from the slices carryout and the ORCY
from an adjacent slice. The ORCY gate with the dedicated
Sum of Products (SOP) chain are designed for implementing
large, flexible SOP chains. One input of each ORCY is con-
nected through the fast SOP chain to the output of the previous
ORCY in the same slice row. The second input is connected to
the output of the top MUXCY in the same slice, as shown in
Figure 24.
LUTs and MUXCYs can implement large AND gates or
other combinatorial logic functions. Figure 25 illustrates
LUT and MUXCY resources configured as a 16-input AND
gate.
Figure 24: Horizontal Cascade Chain
MUXCY
4
MUXCY
4
Slice 1
ds031_64_110300
ORCY
LUT
LUT
MUXCY
4
MUXCY
4
Slice 0
VCC
LUT
LUT
MUXCY
4
MUXCY
4
Slice 3
ORCY
LUT
LUT
MUXCY
4
MUXCY
4
Slice 2
VCC
LUT
LUT
SOP
CLB
MUXCY
4
MUXCY
4
Slice 1
ORCY
LUT
LUT
MUXCY
4
MUXCY
4
Slice 0
VCC
LUT
LUT
MUXCY
4
MUXCY
4
Slice 3
ORCY
LUT
LUT
MUXCY
4
MUXCY
4
Slice 2
VCC
LUT
LUT
CLB
Figure 25: Wide-Input AND Gate (16 Inputs)
MUXCY
AND
4
16
MUXCY
4
“0”
01
01
“0”
01
“0”
MUXCY
4
Slice
OUT
OUT
Slice
LUT
DS031_41_110600
LUT
LUT
VCC
MUXCY
4
01
LUT
Virtex-II 1.5V Field-Programmable Gate Arrays R
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3-State Buffers
Introduction
Each Virtex-II CLB contains two 3-state drivers (TBUFs)
that can drive on-chip busses. Each 3-state buffer has its
own 3-state control pin and its own input pin.
Each of the four slices have access to the two 3-state buff-
ers through the switch matrix, as shown in Figure 26.
TBUFs in neighboring CLBs can access slice outputs by
direct connects. The outputs of the 3-state buffers drive hor-
izontal routing resources used to implement 3-state busses.
The 3-state buffer logic is implemented using AND-OR logic
rather than 3-state drivers, so that timing is more predict-
able and less load dependant especially with larger devices.
Locations / Organization
Four horizontal routing resources per CLB are provided for
on-chip 3-state busses. Each 3-state buffer has access
alternately to two horizontal lines, which can be partitioned
as shown in Figure 27. The switch matrices corresponding
to SelectRAM memory and multiplier or I/O blocks are
skipped.
Number of 3-State Buffers
Table 11 shows the number of 3-state buffers available in
each Virtex-II device. The number of 3-state buffers is twice
the number of CLB elements.
Figure 26: Virtex-II 3-State Buffers
Slice
S3
Slice
S2
Slice
S1
Slice
S0
Switch
Matrix
DS031_37_060700
TBUF
TBUF
Table 11: Virtex-II 3-State Buffers
Device
3-State Buffers
per Row
Total Number
of 3-State Buffers
XC2V40 16 128
XC2V80 16 256
XC2V250 32 768
XC2V500 48 1,536
XC2V1000 64 2,560
XC2V1500 80 3,840
XC2V2000 96 5,376
XC2V3000 112 7,168
XC2V4000 144 11,520
XC2V6000 176 16,896
XC2V8000 208 23,296
Figure 27: 3-State Buffer Connection to Horizontal Lines
Switch
matrix
CLB-II
Switch
matrix
CLB-II
DS031_09_032700
Programmable
connection
3 - state lines
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Advance Product Specification 1-800-255-7778 21
CLB/Slice Configurations
Table 12 summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can be
implemented in one of the configurations listed. Table 13 shows the available resources in all CLBs.
18-Kbit Block SelectRAM Resources
Introduction
Virtex-II devices incorporate large amounts of 18-Kbit block
SelectRAM. These complement the distributed SelectRAM
resources that provide shallow RAM structures imple-
mented in CLBs. Each Virtex-II block SelectRAM is an
18-Kbit true dual-port RAM with two independently clocked
and independently controlled synchronous ports that
access a common storage area. Both ports are functionally
identical. CLK, EN, WE, and SSR polarities are defined
through configuration.
Each port has the following types of inputs: Clock and Clock
Enable, Write Enable, Set/Reset, and Address, as well as
separate Data/parity data inputs (for write) and Data/parity
data outputs (for read).
Operation is synchronous; the block SelectRAM behaves
like a register. Control, address and data inputs must (and
need only) be valid during the set-up time window prior to a
rising (or falling, a configuration option) clock edge. Data
outputs change as a result of the same clock edge.
Configuration
The Virtex-II block SelectRAM supports various configura-
tions, including single- and dual-port RAM and various
data/address aspect ratios. Supported memory configura-
tions for single- and dual-port modes are shown in Ta ble 14.
Table 12: Logic Resources in One CLB
Slices LUTs Flip-Flops MULT_ANDs
Arithmetic &
Carry-Chains
SOP
Chains
Distributed
SelectRAM
Shift
Registers TBUF
4 8 8 8 2 2 128 bits 128 bits 2
Table 13: Virtex-II Logic Resources Available in All CLBs
Device
CLB Array:
Row x
Column
Number
of
Slices
Number
of
LUTs
Max Distributed
SelectRAM or Shift
Register (bits)
Number
of
Flip-Flops
Number
of
Carry-Chains(1)
Number
of SOP
Chains(1)
XC2V40 8 x 8 256 516 8,192 516 16 16
XC2V80 16 x 8 512 1,024 16,384 1,024 16 32
XC2V250 24 x 16 1,536 3,072 49,152 3,072 32 48
XC2V500 32 x 24 3,072 6,144 98,304 6,144 48 64
XC2V1000 40 x 32 5,120 10,240 163,840 10,240 64 80
XC2V1500 48 x 40 7,680 15,360 245,760 15,360 80 96
XC2V2000 56 x 48 10,752 21,504 344,064 21,504 96 112
XC2V3000 64 x 56 14,336 28,672 458,752 28,672 112 128
XC2V4000 80 x 72 23,040 46,080 737,280 46,080 144 160
XC2V6000 96 x 88 33,792 67,584 1,081,344 67,584 176 192
XC2V8000 112 x 104 46,592 93,184 1,490,944 93,184 208 224
Notes:
1. The carry-chains and SOP chains can be split or cascaded.
Table 14: Dual- and Single-Port Configurations
16K x 1 bit 2K x 9 bits
8K x 2 bits 1K x 18 bits
4K x 4 bits 512 x 36 bits
Virtex-II 1.5V Field-Programmable Gate Arrays R
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Single-Port Configuration
As a single-port RAM, the block SelectRAM has access to
the 18-Kbit memory locations in any of the 2K x 9-bit,
1K x 18-bit, or 512 x 36-bit configurations and to 16-Kbit
memory locations in any of the 16K x 1-bit, 8K x 2-bit, or
4K x 4-bit configurations. The advantage of the 9-bit, 18-bit
and 36-bit widths is the ability to store a parity bit for each
eight bits. Parity bits must be generated or checked exter-
nally in user logic. In such cases, the width is viewed as 8 +
1, 16 + 2, or 32 + 4. These extra parity bits are stored and
behave exactly as the other bits, including the timing param-
eters. Video applications can use the 9-bit ratio of Virtex-II
block SelectRAM memory to advantage.
Each block SelectRAM cell is a fully synchronous memory
as illustrated in Figure 28. Input data bus and output data
bus widths are identical.
Dual-Port Configuration
As a dual-port RAM, each port of block SelectRAM has
access to a common 18-Kbit memory resource. These are
fully synchronous ports with independent control signals for
each port. The data widths of the two ports can be config-
ured independently, providing built-in bus-width conversion.
Table 15 illustrates the different configurations available on
ports A & B.
If both ports are configured in either 2K x 9-bit, 1K x 18-bit,
or 512 x 36-bit configurations, the 18-Kbit block is accessi-
ble from port A or B. If both ports are configured in either
16K x 1-bit, 8K x 2-bit. or 4K x 4-bit configurations, the
16 K-bit block is accessible from Port A or Port B. All other
configurations result in one port having access to an 18-Kbit
memory block and the other port having access to a 16 K-bit
subset of the memory block equal to 16 Kbits.
Figure 28: 18-Kbit Block SelectRAM Memory in
Single-Port Mode
DOP
DIP
ADDR
WE
EN
SSR
CLK
18-Kbit Block SelectRAM
DS031_10_102000
DI
DO
Table 15: Dual-Port Mode Configurations
Port A 16K x 1 16K x 1 16K x 1 16K x 1 16K x 1 16K x 1
Port B 16K x 1 8K x 2 4K x 4 2K x 9 1K x 18 512 x 36
Port A 8K x 2 8K x 2 8K x 2 8K x 2 8K x 2
Port B 8K x 2 4K x 4 2K x 9 1K x 18 512 x 36
Port A 4K x 4 4K x 4 4K x 4 4K x 4
Port B 4K x 4 2K x 9 1K x 18 512 x 36
Port A 2K x 9 2K x 9 2K x 9
Port B 2K x 9 1K x 18 512 x 36
Port A 1K x 18 1K x 18
Port B 1K x 18 512 x 36
Port A 512 x 36
Port B 512 x 36
Virtex-II 1.5V Field-Programmable Gate Arrays
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Advance Product Specification 1-800-255-7778 23
Each block SelectRAM cell is a fully synchronous memory,
as illustrated in Figure 29. The two ports have independent
inputs and outputs and are independently clocked.
Port Aspect Ratios
Table 16 shows the depth and the width aspect ratios for the
18-Kbit block SelectRAM. Virtex-II block SelectRAM also
includes dedicated routing resources to provide an efficient
interface with CLBs, block SelectRAM, and multipliers.
Read/Write Operations
The Virtex-II block SelectRAM read operation is fully syn-
chronous. An address is presented, and the read operation
is enabled by control signals WEA and WEB in addition to
ENA or ENB. Then, depending on clock polarity, a rising or
falling clock edge causes the stored data to be loaded into
output registers.
The write operation is also fully synchronous. Data and
address are presented, and the write operation is enabled
by control signals WEA or WEB in addition to ENA or ENB.
Then, again depending on the clock input mode, a rising or
falling clock edge causes the data to be loaded into the
memory cell addressed.
A write operation performs a simultaneous read operation.
Three different options are available, selected by configura-
tion:
1. “WRITE_FIRST”
The “WRITE_FIRST” option is a transparent mode. The
same clock edge that writes the data input (DI) into the
memory also transfers DI into the output registers DO
as shown in Figure 30.
Figure 29: 18-Kbit Block SelectRAM in Dual-Port Mode
DOPA
DOPB
DIPA
ADDRA
WEA
ENA
SSRA
CLKA
DIPB
ADDRB
WEB
ENB
SSRB
CLKB
18-Kbit Block SelectRAM
DS031_11_102000
DOB
DOA
DIA
DIB
Table 16: 18-Kbit Block SelectRAM Port Aspect Ratio
Width Depth Address Bus Data Bus Parity Bus
1 16,384 ADDR[13:0] DATA[0] N/A
2 8,192 ADDR[12:0] DATA[1:0] N/A
4 4,096 ADDR[11:0] DATA[3:0] N/A
9 2,048 ADDR[10:0] DATA[7:0] Parity[0]
18 1,024 ADDR[9:0] DATA[15:0] Parity[1:0]
36 512 ADDR[8:0] DATA[31:0] Parity[3:0]
Figure 30: WRITE_FIRST Mode
CLK
WE
Data_in
Data_in
New
aa
Address
Internal
Memory DO Data_out = Data_in
Data_out
DI
DS031_14_102000
New
RAM Contents New
Old
Virtex-II 1.5V Field-Programmable Gate Arrays R
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2. “READ_FIRST”
The “READ_FIRST” option is a read-before-write mode.
The same clock edge that writes data input (DI) into the memory also transfers the prior content of the memory cell
addressed into the data output registers DO, as shown in Figure 31.
3. “NO_CHANGE”
The “NO_CHANGE” option maintains the content of the output registers, regardless of the write operation. The clock edge
during the write mode has no effect on the content of the data output register DO. When the port is configured as
“NO_CHANGE”, only a read operation loads a new value in the output register DO, as shown in Figure 32.
Figure 31: READ_FIRST Mode
CLK
WE
Data_in
Data_in
New
aa
Old
Address
Internal
Memory DO Prior stored data
Data_out
DI
DS031_13_102000
RAM Contents New
Old
Figure 32: NO_CHANGE Mode
CLK
WE
Data_in
Data_in
New
aa
Last Read Cycle Content (no change)
Address
Internal
Memory DO No change during write
Data_out
DI
DS031_12_102000
RAM Contents New
Old
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Advance Product Specification 1-800-255-7778 25
Control Pins and Attributes
Virtex-II SelectRAM memory has two independent ports
with the control signals described in Ta ble 17. All control
inputs including the clock have an optional inversion.
Initial memory content is determined by the INIT_xx
attributes. Separate attributes determine the output register
value after device configuration (INIT) and SSR is asserted
(SRVAL). Both attributes (INIT_B and SRVAL) are available
for each port when a block SelectRAM resource is config-
ured as dual-port RAM.
Locations
Virtex-II SelectRAM memory blocks are located in either
four or six columns. The number of blocks per column
depends of the device array size and is equivalent to the
number of CLBs in a column divided by four. Column loca-
tions are shown in Table 18.
Table 17: Control Functions
Control Signal Function
CLK Read and Write Clock
EN Enable affects Read, Write, Set, Reset
WE Write Enable
SSR Set DO register to SRVAL (attribute)
Table 18: SelectRAM Memory Floor Plan
Device Columns
SelectRAM Blocks
Per Column Total
XC2V40 2 2 4
XC2V80 2 4 8
XC2V250 4 6 24
XC2V500 4 8 32
XC2V1000 4 10 40
XC2V1500 4 12 48
XC2V2000 4 14 56
XC2V3000 6 16 96
XC2V4000 6 20 120
XC2V6000 6 24 144
XC2V8000 6 28 168
Figure 33: Block SelectRAM (2-column, 4-column, and 6-column)
2 CLB columns
2 CLB columns
2 CLB columns
n CLB columns
2 CLB columns
n CLB columns
2 CLB columns
2 CLB columns
2 CLB columns
n CLB columns
n CLB columns
n CLB columns
2 CLB columns
n CLB columns
SelectRAM Blocks
SelectRAM Blocks
ds031_38_101000
2 CLB column
2 CLB columns
SelectRAM Blocks
2 CLB column
2 CLB columns
Virtex-II 1.5V Field-Programmable Gate Arrays R
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26 1-800-255-7778 Advance Product Specification
Total Amount of SelectRAM Memory
Table 19 shows the amount of block SelectRAM memory
available for each Virtex-II device. The 18-Kbit SelectRAM
blocks are cascadable to implement deeper or wider single- or
dual-port memory resources.
18-Bit x 18-Bit Multipliers
Introduction
A Virtex-II multiplier block is an 18-bit by 18-bit 2’s comple-
ment signed multiplier. Virtex-II devices incorporate many
embedded multiplier blocks. These multipliers can be asso-
ciated with an 18-Kbit block SelectRAM resource or can be
used independently. They are optimized for high-speed
operations and have a lower power consumption compared
to an 18-bit x 18-bit multiplier in slices.
Each SelectRAM memory and multiplier block is tied to four
switch matrices, as shown in Figure 34.
Association With Block SelectRAM Memory
The interconnect is designed to allow SelectRAM memory
and multiplier blocks to be used at the same time, but some
interconnect is shared between the SelectRAM and the
multiplier. Thus, SelectRAM memory can be used only up to
18 bits wide when the multiplier is used, because the multi-
plier shares inputs with the upper data bits of the
SelectRAM memory.
This sharing of the interconnect is optimized for an
18-bit-wide block SelectRAM resource feeding the multi-
plier. The use of SelectRAM memory and the multiplier with
an accumulator in LUTs allows for implementation of a digi-
tal signal processor (DSP) multiplier-accumulator (MAC)
function, which is commonly used in finite and infinite
impulse response (FIR and IIR) digital filters.
Configuration
The multiplier block is an 18-bit by 18-bit signed multiplier
(2's complement). Both A and B are 18-bit-wide inputs, and
the output is 36 bits. Figure 35 shows a multiplier block.
Table 19: Virtex-II SelectRAM Memory Available
Device
Total SelectRAM Memory
Blocks in Kbits in Bits
XC2V40 4 72 73,728
XC2V80 8 144 147,456
XC2V250 24 432 442,368
XC2V500 32 576 589,824
XC2V1000 40 720 737,280
XC2V1500 48 864 884,736
XC2V2000 56 1,008 1,032,192
XC2V3000 96 1,728 1,769,472
XC2V4000 120 2,160 2,211,840
XC2V6000 144 2,592 2,654,208
XC2V8000 168 3,024 3,096,576
Figure 34: SelectRAM and Multiplier Blocks
Figure 35: Multiplier Block
Switch
Matrix
Switch
Matrix
18-Kbit block
SelectRAM
18 x 18 Multiplier
Switch
Matrix
Switch
Matrix
DS031_33_101000
MULT 18 x 18
A[17:0]
P[35:0]
B[17:0]
Multiplier Block
DS031_40_100400
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Advance Product Specification 1-800-255-7778 27
Locations / Organization
Multiplier organization is identical to the 18-Kbit SelectRAM
organization, because each multiplier is associated with an
18-Kbit block SelectRAM resource.
In addition to the built-in multiplier blocks, the CLB elements
have dedicated logic to implement efficient multipliers in
logic. (Refer to Configurable Logic Blocks (CLBs)).
Table 20: Multiplier Floor Plan
Device Columns
Multipliers
Per Column Total
XC2V40 2 2 4
XC2V80 2 4 8
XC2V250 4 6 24
XC2V500 4 8 32
XC2V1000 4 10 40
XC2V1500 4 12 48
XC2V2000 4 14 56
XC2V3000 6 16 96
XC2V4000 6 20 120
XC2V6000 6 24 144
XC2V8000 6 28 168
Figure 36: Multipliers (2-column, 4-column, and 6-column)
DS031_39_101000
2 CLB columns
2 CLB columns
2 CLB columns
n CLB columns
2 CLB columns
n CLB columns
2 CLB columns
2 CLB columns
2 CLB columns
n CLB columns
n CLB columns
n CLB columns
2 CLB columns
n CLB columns
Multiplier Blocks
Multiplier Blocks
2 CLB column
2 CLB columns
Multiplier Blocks
2 CLB column
2 CLB columns
Virtex-II 1.5V Field-Programmable Gate Arrays R
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Global Clock Multiplexer Buffers
Virtex-II devices have 16 clock input pins that can also be
used as regular user I/Os. Eight clock pads are on the top
edge of the device, in the middle of the array, and eight are
on the bottom edge, as illustrated in Figure 37.
The global clock multiplexer buffer represents the input to
dedicated low-skew clock tree distribution in Virtex-II
devices. Like the clock pads, eight global clock multiplexer
buffers are on the top edge of the device and eight are on
the bottom edge.
Each global clock buffer can either be driven by the clock
pad to distribute a clock directly to the device, or driven by
the Digital Clock Manager (DCM), discussed in Digital
Clock Manager (DCM), page 30. Each global clock buffer
can also be driven by local interconnects. The DCM has
clock output(s) that can be connected to global clock buffer
inputs, as shown in Figure 38.
Global clock buffers are used to distribute the clock to some
or all synchronous logic elements (such as registers in
CLBs and IOBs, and SelectRAM blocks.
Eight global clocks can be used in each quadrant of the
Virtex-II device. Designers should consider the clock distri-
bution detail of the device prior to pin-locking and floorplan-
ning (see the Virtex-II User Guide).
Figure 39 shows clock distribution in Virtex-II devices.
Figure 37: Virtex-II Clock Pads
8 clock pads
8 clock pads
Virtex-II
Device
DS031_42_101000
Figure 38: Virtex-II Clock Distribution Configurations
Clock
Pad
Clock
Buffer
I
0
Clock Distribution
Clock
Pad
Clock
Buffer
I
0
Clock Distribution
CLKIN
CLKOUT
DCM
DS031_43_101000
Figure 39: Virtex-II Clock Distribution
8
8
8
8
NW
NW NE
SW SE
NE
SW SE
DS031_45_120200
8 BUFGMUX
8 BUFGMUX
8 max
8 BUFGMUX
8 BUFGMUX
16 Clocks
16 Clocks
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In each quadrant, up to eight clocks are organized in clock
rows. A clock row supports up to 16 CLB rows (eight up and
eight down). For the largest devices a new clock row is
added, as necessary.
To reduce power consumption, any unused clock branches
remain static.
Global clocks are driven by dedicated clock buffers (BUFG),
which can also be used to gate the clock (BUFGCE) or to mul-
tiplex between two independent clock inputs (BUFGMUX).
The most common configuration option of this element is as
a buffer. A BUFG function in this (global buffer) mode, is
shown in Figure 40.
The Virtex-II global clock buffer BUFG can also be config-
ured as a clock enable/disable circuit (Figure 41), as well as
a two-input clock multiplexer (Figure 42). A functional
description of these two options is provided below. Each of
them can be used in either of two modes, selected by con-
figuration: rising clock edge or falling clock edge.
This section describes the rising clock edge option. For the
opposite option, falling clock edge, just change all "rising"
references to "falling" and all "High" references to "Low",
except for the description of the CE or S levels. The rising
clock edge option uses the BUFGCE and BUFGMUX prim-
itives. The falling clock edge option uses the BUFGCE_1
and BUFGMUX_1 primitives.
BUFGCE
If the CE input is active (High) prior to the incoming rising
clock edge, this Low-to-High-to-Low clock pulse passes
through the clock buffer. Any level change of CE during the
incoming clock High time has no effect.
If the CE input is inactive (Low) prior to the incoming rising
clock edge, the following clock pulse does not pass through
the clock buffer, and the output stays Low. Any level change
of CE during the incoming clock High time has no effect. CE
must not change during a short setup window just prior to
the rising clock edge on the BUFGCE input I. Violating this
setup time requirement can result in an undefined runt
pulse output.
BUFGMUX
BUFGMUX can switch between two unrelated, even asyn-
chronous clocks. Basically, a Low on S selects the CLK0
input, a High on S selects the S1 input. Switching from one
clock to the other is done in such a way that the output High
and Low time is never shorter than the shortest High or Low
time of either input clock. As long as the presently selected
clock is High, any level change of S has no effect .
If the presently selected clock is Low while S changes, or if
it goes Low after S has changed, the output is kept Low until
the other ("to-be-selected") clock has made a transition
from High to Low. At that instant, the new clock starts driv-
ing the output.
The two clock inputs can be asynchronous with regard to
each other, and the S input can change at any time, except
for a short setup time prior to the rising edge of the presently
selected clock; that is, prior to the rising edge of the
BUFGMUX output O. Violating this setup time requirement
can result in an undefined runt pulse output.
All Virtex-II devices have 16 global clock multiplexer buffers.
Figure 43 shows a switchover from CLK0 to CLK1.
•The current clock is CLK0.
•S is activated High.
•If CLK0 is currently High, the multiplexer waits for CLK0
to go Low.
•Once CLK0 is Low, the multiplexer output stays Low
until CLK1 transitions High to Low.
•When CLK1 transitions from High to Low, the output
switches to CLK1.
•No glitches or short pulses can appear on the output.
Figure 40: Virtex-II BUFG Function
Figure 41: Virtex-II BUFGCE Function
O
I
BUFG
DS031_61_101200
O
I
CE
BUFGCE
DS031_62_101200
Figure 42: Virtex-II BUFGMUX Function
Figure 43: Clock Multiplexer Waveform Diagram
O
I0
I1
S
BUFGMUX
DS031_63_112900
S
CLK0
CLK1
OUT
Wait for Low
Switch
DS031_46_112900
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Digital Clock Manager (DCM)
The Virtex-II DCM offers a wide range of powerful clock
management features.
•Clock De-skew: The DCM generates new system
clocks (either internally or externally to the FPGA),
which are phase-aligned to the input clock, thus
eliminating clock distribution delays.
•Frequency Synthesis: The DCM generates a wide
range of output clock frequencies, performing very
flexible clock multiplication and division.
•Phase Shifting: The DCM provides both coarse phase
shifting and fine-grained phase shifting with dynamic
phase shift control.
The DCM utilizes fully digital delay lines allowing robust
high-precision control of clock phase and frequency. It also
utilizes fully digital feedback systems, operating dynamically
to compensate for temperature and voltage variations dur-
ing operation.
Up to four of the nine DCM clock outputs can drive inputs to
global clock buffers or global clock multiplexer buffers simul-
taneously (see Figure 44). All DCM clock outputs can simul-
taneously drive general routing resources, including routes
to output buffers.
The DCM can be configured to delay the completion of the
Virtex-II configuration process until after the DCM has
achieved lock. This guarantees that the chip does not begin
operating until after the system clocks generated by the
DCM have stabilized.
The DCM has the following general control signals:
•RST input pin: resets the entire DCM
•LOCKED output pin: asserted High when all enabled
DCM circuits have locked.
•STATUS output pins (active High): shown in Table 21.
Clock De-Skew
The DCM de-skews the output clocks relative to the input
clock by automatically adjusting a digital delay line. Addi-
tional delay is introduced so that clock edges arrive at inter-
nal registers and block RAMs simultaneously with the clock
edges arriving at the input clock pad. Alternatively, external
clocks, which are also de-skewed relative to the input clock,
can be generated for board-level routing. All DCM output
clocks are phase-aligned to CLK0 and, therefore, are also
phase-aligned to the input clock.
To achieve clock de-skew, the CLKFB input must be con-
nected, and its source must be either CLK0 or CLK2X. Note
that CLKFB must always be connected, unless only the
CLKFX or CLKFX180 outputs are used and de-skew is not
required.
Frequency Synthesis
The DCM provides flexible methods for generating new
clock frequencies. Each method has a different operating
frequency range and different AC characteristics. The
CLK2X and CLK2X180 outputs double the clock frequency.
The CLKDV output creates divided output clocks with divi-
sion options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5,
8, 9, 10, 11, 12, 13, 14, 15, and 16.
The CLKFX and CLKFX180 outputs can be used to pro-
duce clocks at the following frequency:
FREQCLKFX = (M/D) * FREQCLKIN
where M and D are two integers. Specifications for M and D
are provided under DCM Timing Parameters. By default,
M=4 and D=1, which results in a clock output frequency four
times faster than the clock input frequency (CLKIN).
CLK2X180 is phase shifted 180 degrees relative to CLK2X.
CLKFX180 is phase shifted 180 degrees relative to CLKFX.
All frequency synthesis outputs automatically have 50/50
duty cycles (with the exception of the CLKDV output when
performing a non-integer divide in high-frequency mode).
Note that CLK2X and CLK2X180 are not available in
high-frequency mode.
Figure 44: Digital Clock Manager
CLKIN
CLKFB CLK180
CLK270
CLK0
CLK90
CLK2X
CLK2X180
CLKDV
DCM
DS031_67_112900
CLKFX
CLKFX180
LOCKED
STATUS[7:0]
PSDONE
RST
DSSEN
PSINCDEC
PSEN
PSCLK
clock signal
control signal
Table 21: DCM Status Pins
Status Pin Function
0 Phase Shift Overflow
1 CLKIN Stopped
2 CLKFX Stopped
3N/A
4N/A
5N/A
6N/A
7N/A
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Phase Shifting
The DCM provides additional control over clock skew
through either coarse or fine-grained phase shifting. The
CLK0, CLK90, CLK180, and CLK270 outputs are each
phase shifted by ¼ of the input clock period relative to each
other, providing coarse phase control. Note that CLK90 and
CLK270 are not available in high-frequency mode.
Fine-phase adjustment affects all nine DCM output clocks.
When activated, the phase shift between the rising edges of
CLKIN and CLKFB is a specified fraction of the input clock
period.
In variable mode, the PHASE_SHIFT value can also be
dynamically incremented or decremented as determined by
PSINCDEC synchronously to PSCLK, when the PSEN
input is active. Figure 45 illustrates the effects of fine-phase
shifting. For more information on DCM features, see the
Virtex-II User Guide.
Table 22 lists fine-phase shifting control pins, when used in
variable mode.
Two separate components of the phase shift range must be
understood:
•PHASE_SHIFT attribute range
•FINE_SHIFT_RANGE DCM timing parameter range
The PHASE_SHIFT attribute is the numerator in the following
equation:
Phase Shift (ns) = (PHASE_SHIFT/256) * PERIODCLKIN
The full range of this attribute is always -255 to +255, but its
practical range varies with CLKIN frequency, as constrained
by the FINE_SHIFT_RANGE component, which represents
the total delay achievable by the phase shift delay line. Total
delay is a function of the number of delay taps used in the
circuit. Across process, voltage, and temperature, this abso-
lute range is guaranteed to be as specified under DCM Tim-
ing Parameters.
Absolute range (fixed mode) = ± FINE_SHIFT_RANGE
Absolute range (variable mode) = ± FINE_SHIFT_RANGE/2
The reason for the difference between fixed and variable
modes is as follows. For variable mode to allow symmetric,
dynamic sweeps from -255/256 to +255/256, the DCM sets
the "zero phase skew" point as the middle of the delay line,
thus dividing the total delay line range in half. In fixed mode,
since the PHASE_SHIFT value never changes after configu-
ration, the entire delay line is available for insertion into
either the CLKIN or CLKFB path (to create either positive or
negative skew).
Taking both of these components into consideration, the fol-
lowing are some usage examples:
•If PERIODCLKIN = 2 * FINE_SHIFT_RANGE, then
PHASE_SHIFT in fixed mode is limited to ± 128, and in
variable mode it is limited to ± 64.
•If PERIODCLKIN = FINE_SHIFT_RANGE, then
PHASE_SHIFT in fixed mode is limited to ± 255, and in
variable mode it is limited to ± 128.
•If PERIODCLKIN
£
0.5 * FINE_SHIFT_RANGE, then
PHASE_SHIFT is limited to ± 255 in either mode.
Table 22: Fine-Phase Shifting Control Pins
Control Pin Direction Function
PSINCDEC in Increment or decrement
PSEN in Enable ± phase shift
PSCLK in Clock for phase shift
PSDONE out Active when completed
Figure 45: Fine-Phase Shifting Effects
CLKOUT_PHASE_SHIFT
= FIXED
CLKOUT_PHASE_SHIFT
= VARIABLE
CLKOUT_PHASE_SHIFT
= NONE
CLKIN
CLKIN
CLKIN
CLKFB
(PS/256) x PERIODCLKIN
(PS negative)
(PS/256) x PERIODCLKIN
(PS positive)
(PS/256) x PERIODCLKIN
(PS negative)
(PS/256) x PERIODCLKIN
(PS positive) DS031_48_101201
CLKFB
CLKFB
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Operating Modes
The frequency ranges of DCM input and output clocks
depend on the operating mode specified, either
low-frequency mode or high-frequency mode, according to
Table 23. (For actual values, see Virtex-II Switching Char-
acteristics). The CLK2X, CLK2X180, CLK90, and CLK270
outputs are not available in high-frequency mode.
High or low-frequency mode is selected by an attribute.
Locations/Organization
Virtex-II DCMs are placed on the top and bottom of each
block RAM and multiplier column. The number of DCMs
depends on the device size, as shown in Table 24.
Table 23: DCM Frequency Ranges
Output Clock
Low-Frequency Mode High-Frequency Mode
CLKIN Input CLK Output CLKIN Input CLK Output
CLK0, CLK180 CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_1X_HF
CLK90, CLK270 CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF NA NA
CLK2X, CLK2X180 CLKIN_FREQ_DLL_LF CLKOUT_FREQ_2X_LF NA NA
CLKDV CLKIN_FREQ_DLL_LF CLKOUT_FREQ_DV_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_DV_HF
CLKFX, CLKFX180 CLKIN_FREQ_FX_LF CLKOUT_FREQ_FX_LF CLKIN_FREQ_FX_HF CLKOUT_FREQ_FX_HF
Table 24: DCM Organization
Device Columns DCMs
XC2V40 2 4
XC2V80 2 4
XC2V250 4 8
XC2V500 4 8
XC2V1000 4 8
XC2V1500 4 8
XC2V2000 4 8
XC2V3000 6 12
XC2V4000 6 12
XC2V6000 6 12
XC2V8000 6 12
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Active Interconnect Technology
Local and global Virtex-II routing resources are optimized for speed and timing predictability, as well as to facilitate IP cores
implementation. Virtex-II Active Interconnect Technology is a fully buffered programmable routing matrix. All routing
resources are segmented to offer the advantages of a hierarchical solution. Virtex-II logic features like CLBs, IOBs, block
RAM, multipliers, and DCMs are all connected to an identical switch matrix for access to global routing resources, as shown
in Figure 46.
Each Virtex-II device can be represented as an array of switch matrixes with logic blocks attached, as illustrated in
Figure 47.
Figure 46: Active Interconnect Technology
Figure 47: Routing Resources
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
CLB
18Kb
BRAM
MULT
18 x 18
Switch
Matrix
IOB
Switch
Matrix
DCM
DS031_55_101000
Switch
Matrix IOB Switch
Matrix IOB Switch
Matrix IOB Switch
Matrix DCM Switch
Matrix
Switch
Matrix IOB Switch
Matrix CLB Switch
Matrix CLB Switch
Matrix
Switch
Matrix
Switch
Matrix IOB Switch
Matrix CLB Switch
Matrix CLB Switch
Matrix
Switch
Matrix
Switch
Matrix IOB Switch
Matrix CLB Switch
Matrix CLB Switch
Matrix
Switch
Matrix
Switch
Matrix IOB Switch
Matrix CLB Switch
Matrix CLB Switch
Matrix
Switch
Matrix
SelectRAM
Multiplier
DS031_34_110300
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Place-and-route software takes advantage of this regular
array to deliver optimum system performance and fast com-
pile times. The segmented routing resources are essential
to guarantee IP cores portability and to efficiently handle an
incremental design flow that is based on modular imple-
mentations. Total design time is reduced due to fewer and
shorter design iterations.
Hierarchical Routing Resources
Most Virtex-II signals are routed using the global routing
resources, which are located in horizontal and vertical rout-
ing channels between each switch matrix.
As shown in Figure 48, Virtex-II has fully buffered program-
mable interconnections, with a number of resources
counted between any two adjacent switch matrix rows or
columns. Fanout has minimal impact on the performance of
each net.
•The long lines are bidirectional wires that distribute
signals across the device. Vertical and horizontal long
lines span the full height and width of the device.
•The hex lines route signals to every third or sixth block
away in all four directions. Organized in a staggered
pattern, hex lines can only be driven from one end.
Hex-line signals can be accessed either at the endpoints
or at the midpoint (three blocks from the source).
•The double lines route signals to every first or second
block away in all four directions. Organized in a
staggered pattern, double lines can be driven only at
their endpoints. Double-line signals can be accessed
either at the endpoints or at the midpoint (one block
from the source).
•The direct connect lines route signals to neighboring
blocks: vertically, horizontally, and diagonally.
•The fast connect lines are the internal CLB local
interconnections from LUT outputs to LUT inputs.
Dedicated Routing
In addition to the global and local routing resources, dedi-
cated signals are available.
•There are eight global clock nets per quadrant (see
Global Clock Multiplexer Buffers).
•Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses
within a row. (See 3-State Buffers.)
•Two dedicated carry-chain resources per slice column
(two per CLB column) propagate carry-chain MUXCY
output signals vertically to the adjacent slice. (See
CLB/Slice Configurations.)
Figure 48: Hierarchical Routing Resources
24 Horizontal Long Lines
24 Vertical Long Lines
120 Horizontal Hex Lines
120 Vertical Hex Lines
40 Horizontal Double Lines
40 Vertical Double Lines
16 Direct Connections
(total in all four directions)
8 Fast Connects
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•One dedicated SOP chain per slice row (two per CLB
row) propagate ORCY output logic signals horizontally
to the adjacent slice. (See Sum of Products.)
•One dedicated shift-chain per CLB connects the output
of LUTs in shift-register mode to the input of the next
LUT in shift-register mode (vertically) inside the CLB.
(See Shift Registers, page 16.)
Creating a Design
Creating Virtex-II designs is easy with Xilinx Integrated Syn-
thesis Environment (ISE) development systems, which sup-
port advanced design capabilities, including ProActive
Timing Closure, integrated logic analysis, and the fastest
place and route runtimes in the industry. ISE solutions
enable designers to get the performance they need, quickly
and easily.
As a result of the ongoing cooperative development efforts
between Xilinx and EDA Alliance partners, designers can
take advantage of the benefits provided by EDA technolo-
gies in the programmable logic design process. Xilinx devel-
opment systems are available in a number of easy to use
configurations, collectively known as the ISE Series.
ISE Alliance
The ISE Alliance solution is designed to plug and play within
an existing design environment. Built using industry standard
data formats and netlists, these stable, flexible products
enable Alliance EDA partners to deliver their best design
automation capabilities to Xilinx customers, along with the
time to market benefits of ProActive Timing Closure.
ISE Foundation
The ISE Foundation solution delivers the benefits of true
HDL-based design in a seamlessly integrated design envi-
ronment. An intuitive project navigator, as well as powerful
HDL design and two HDL synthesis tools, ensure that
high-quality results are achieved quickly and easily. The ISE
Foundation product includes:
•State Diagram entry using Xilinx StateCAD
•Automatic HDL Testbench generation using Xilinx
HDLBencher
•HDL Simulation using ModelSim XE
Design Flow
Virtex-II design flow proceeds as follows:
•Design Entry
•Synthesis
•Implementation
•Verification
Most programmable logic designers iterate through these
steps several times in the process of completing a design.
Design Entry
All Xilinx ISE development systems support the mainstream
EDA design entry capabilities, ranging from schematic
design to advanced HDL design methodologies. Given the
high densities of the Virtex-II family, designs are created
most efficiently using HDLs. To further improve their time to
market, many Xilinx customers employ incremental, modu-
lar, and Intellectual Property (IP) design techniques. When
properly used, these techniques further accelerate the logic
design process.
To enable designers to leverage existing investments in
EDA tools, and to ensure high performance design flows,
Xilinx jointly develops tools with leading EDA vendors,
including:
•Aldec®
•Cadence®
•Exemplar®
•Mentor Graphics®
•Model Technology®
•Synopsys®
•Synplicity®
Complete information on Alliance Series partners and their
associated design flows is available at www.xilinx.com on
the Xilinx Alliance Series web page.
The ISE Foundation product offers schematic entry and
HDL design capabilities as part of an integrated design
solution - enabling one-stop shopping. These capabilities
are powerful, easy to use, and they support the full portfolio
of Xilinx programmable logic devices. HDL design capabil-
ities include a color-coded HDL editor with integrated lan-
guage templates, state diagram entry, and Core generation
capabilities.
Synthesis
The ISE Alliance product is engineered to support
advanced design flows with the industry's best synthesis
tools. Advanced design methodologies include:
•Physical Synthesis
•Incremental synthesis
•RTL floorplanning
•Direct physical mapping
The ISE Foundation product seamlessly integrates synthesis
capabilities purchased directly from Exemplar, Synopsys, and
Synplicity. In addition, it includes the capabilities of Xilinx
Synthesis Technology.
A benefit of having two seamlessly integrated synthesis
engines within an ISE design flow is the ability to apply alter-
native sets of optimization techniques on designs, helping to
ensure that designers can meet even the toughest timing
requirements.
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Design Implementation
The ISE Series development systems include Xilinx tim-
ing-driven implementation tools, frequently called “place
and route” or “fitting” software. This robust suite of tools
enables the creation of an intuitive, flexible, tightly inte-
grated design flow that efficiently bridges “logical” and
“physical” design domains. This simplifies the task of defin-
ing a design, including its behavior, timing requirements,
and optional layout (or floorplanning), as well as simplifying
the task of analyzing reports generated during the imple-
mentation process.
The Virtex-II implementation process is comprised of Syn-
thesis, translation, mapping, place and route, and configu-
ration file generation. While the tools can be run individually,
many designers choose to run the entire implementation
process with the click of a button. To assist those who prefer
to script their design flows, Xilinx provides Xflow, an auto-
mated single command line process.
Design Verification
In addition to conventional design verification using static
timing analysis or simulation techniques, Xilinx offers pow-
erful in-circuit debugging techniques using ChipScope ILA
(Integrated Logic Analysis). The reconfigurable nature of
Xilinx FPGAs means that designs can be verified in real
time without the need for extensive sets of software simula-
tion vectors.
For simulation, the system extracts post-layout timing infor-
mation from the design database, and back-annotates this
information into the netlist for use by the simulator. The back
annotation features a variety of patented Xilinx techniques,
resulting in the industry’s most powerful simulation flows.
Alternatively, timing-critical portions of a design can be ver-
ified using the Xilinx static timing analyzer or a third party
static timing analysis tool like Synopsys Prime Time™, by
exporting timing data in the STAMP data format.
For in-circuit debugging, ChipScope ILA enables designers
to analyze the real-time behavior of a device while operating
at full system speeds. Logic analysis commands and cap-
tured data are transferred between the ChipScope software
and ILA cores within the Virtex-II FPGA, using industry
standard JTAG protocols. These JTAG transactions are
driven over an optional download cable (MultiLINX or
JTAG), connecting the Virtex device in the target system to
a PC or workstation.
ChipScope ILA was designed to look and feel like a logic
analyzer, making it easy to begin debugging a design imme-
diately. Modifications to the desired logic analysis can be
downloaded directly into the system in a matter of minutes.
Other Unique Features of Virtex-II Design Flow
Xilinx design flows feature a number of unique capabilities.
Among these are efficient incremental HDL design flows; a
robust capability that is enabled by Xilinx exclusive hierar-
chical floorplanning capabilities. Another powerful design
capability only available in the Xilinx design flow is “Modular
Design”, part of the Xilinx suite of team design tools, which
enables autonomous design, implementation, and verifica-
tion of design modules.
Incremental Synthesis
Xilinx unique hierarchical floorplanning capabilities enable
designers to create a programmable logic design by isolating
design changes within one hierarchical “logic block”, and
perform synthesis, verification and implementation pro-
cesses on that specific logic block. By preserving the logic in
unchanged portions of a design, Xilinx incremental design
makes the high-density design process more efficient.
Xilinx hierarchical floorplanning capabilities can be speci-
fied using the high-level floorplanner or a preferred RTL
floorplanner (see the Xilinx web site for a list of supported
EDA partners). When used in conjunction with one of the
EDA partners’ floorplanners, higher performance results
can be achieved, as many synthesis tools use this more
predictable detailed physical implementation information to
establish more aggressive and accurate timing estimates
when performing their logic optimizations.
Modular Design
Xilinx innovative modular design capabilities take the incre-
mental design process one step further by enabling the
designer to delegate responsibility for completing the
design, synthesis, verification, and implementation of a hier-
archical “logic block” to an arbitrary number of designers -
assigning a specific region within the target FPGA for exclu-
sive use by each of the team members.
This team design capability enables an autonomous
approach to design modules, changing the hand-off point to
the lead designer or integrator from “my module works in
simulation” to “my module works in the FPGA”. This unique
design methodology also leverages the Xilinx hierarchical
floorplanning capabilities and enables the Xilinx (or EDA
partner) floorplanner to manage the efficient implementa-
tion of very high-density FPGAs.
Configuration
Virtex-II devices are configured by loading application spe-
cific configuration data into the internal configuration mem-
ory. Configuration is carried out using a subset of the device
pins, some of which are dedicated, while others can be
re-used as general purpose inputs and outputs once config-
uration is complete.
Depending on the system design, several configuration
modes are supported, selectable via mode pins. The mode
pins M2, M1 and M0 are dedicated pins. An additional pin,
HSWAP_EN is used in conjunction with the mode pins to
select whether user I/O pins have pull-ups during configura-
tion. By default, HSWAP_EN is tied High (internal pull-up)
which shuts off the pull-ups on the user I/O pins during con-
figuration. When HSWAP_EN is tied Low, user I/Os have
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pull-ups during configuration. Other dedicated pins are
CCLK (the configuration clock pin), DONE, PROG_B, and
the boundary-scan pins: TDI, TDO, TMS, and TCK.
Depending on the configuration mode chosen, CCLK can
be an output generated by the FPGA, or an input accepting
an externally generated clock. The configuration pins and
boundary scan pins are independent of the VCCO. The aux-
iliary power supply (VCCAUX) of 3.3 V is used for these pins.
All configuration pins are LVTTL 12 mA. (See Virtex-II DC
Characteristics.)
A persist option is available which can be used to force the
configuration pins to retain their configuration function even
after device configuration is complete. If the persist option is
not selected then the configuration pins with the exception
of CCLK, PROG_B, and DONE can be used as user I/O in
normal operation. The persist option does not apply to the
boundary-scan related pins. The persist feature is valuable
in applications which employ partial reconfiguration or
reconfiguration on the fly.
Configuration Modes
Virtex-II supports the following five configuration modes:
•Slave-serial mode
•Master-serial mode
•Slave SelectMAP mode
•Master SelectMAP mode
•Boundary-Scan mode (IEEE 1532/IEEE 1149)
A detailed description of configuration modes is provided in
the Virtex-II User Guide.
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other serial source
of configuration data. The CCLK pin on the FPGA is an
input in this mode. The serial bitstream must be setup at the
DIN input pin a short time before each rising edge of the
externally generated CCLK.
Multiple FPGAs can be daisy-chained for configuration from
a single source. After a particular FPGA has been config-
ured, the data for the next device is routed internally to the
DOUT pin. The data on the DOUT pin changes on the rising
edge of CCLK.
Slave-serial mode is selected by applying <111> to the
mode pins (M2, M1, M0). A weak pull-up on the mode pins
makes slave serial the default mode if the pins are left
unconnected.
Master-Serial Mode
In master-serial mode, the CCLK pin is an output pin. It is
the Virtex-II FPGA device that drives the configuration clock
on the CCLK pin to a Xilinx Serial PROM which in turn feeds
bit-serial data to the DIN input. The FPGA accepts this data
on each rising CCLK edge. After the FPGA has been
loaded, the data for the next device in a daisy-chain is pre-
sented on the DOUT pin after the rising CCLK edge.
The interface is identical to slave serial except that an inter-
nal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK which always starts at a slow default frequency. Con-
figuration bits then switch CCLK to a higher frequency for
the remainder of the configuration.
Slave SelectMAP Mode
The SelectMAP mode is the fastest configuration option.
Byte-wide data is written into the Virtex-II FPGA device with
a BUSY flag controlling the flow of data. An external data
source provides a byte stream, CCLK, an active Low Chip
Select (CS_B) signal and a Write signal (RDWR_B). If
BUSY is asserted (High) by the FPGA, the data must be
held until BUSY goes Low. Data can also be read using the
SelectMAP mode. If RDWR_B is asserted, configuration
data is read out of the FPGA as part of a readback opera-
tion.
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained to permit high-speed 8-bit readback using the per-
sist option.
Multiple Virtex-II FPGAs can be configured using the
SelectMAP mode, and be made to start-up simultaneously.
To configure multiple devices in this way, wire the individual
CCLK, Data, RDWR_B, and BUSY pins of all the devices in
parallel. The individual devices are loaded separately by
deasserting the CS_B pin of each device in turn and writing
the appropriate data.
Master SelectMAP Mode
This mode is a master version of the SelectMAP mode. The
device is configured byte-wide on a CCLK supplied by the
Virtex-II FPGA device. Timing is similar to the Slave Serial-
MAP mode except that CCLK is supplied by the Virtex-II
FPGA.
Boundary-Scan (JTAG, IEEE 1532) Mode
In boundary-scan mode, dedicated pins are used for config-
uring the Virtex-II device. The configuration is done entirely
through the IEEE 1149.1 Test Access Port (TAP). Virtex-II
device configuration using Boundary scan is compliant with
IEEE 1149.1-1993 standard and the new IEEE 1532 stan-
dard for In-System Configurable (ISC) devices. The IEEE
1532 standard is backward compliant with the IEEE
1149.1-1993 TAP and state machine. The IEEE Standard
1532 for In-System Configurable (ISC) devices is intended
to be programmed, reprogrammed, or tested on the board
via a physical and logical protocol.
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes.
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Table 26 lists the total number of bits required to configure
each device.
Configuration Sequence
The configuration of Virtex-II devices is a three-phase pro-
cess. First, the configuration memory is cleared. Next, con-
figuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.
Configuration is automatically initiated on power-up unless
it is delayed by the user. The INIT_B pin can be held Low
using an open-drain driver. An open-drain is required since
INIT_B is a bidirectional open-drain pin that is held Low by a
Virtex-II FPGA device while the configuration memory is
being cleared. Extending the time that the pin is Low causes
the configuration sequencer to wait. Thus, configuration is
delayed by preventing entry into the phase where data is
loaded.
The configuration process can also be initiated by asserting
the PROG_B pin. The end of the memory-clearing phase is
signaled by the INIT_B pin going High, and the completion
of the entire process is signaled by the DONE pin going
High. The Global Set/Reset (GSR) signal is pulsed after the
last frame of configuration data is written but before the
start-up sequence. The GSR signal resets all flip-flops on
the device.
The default start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary. One CCLK cycle later, the Global Write Enable (GWE)
signal is released. This permits the internal storage ele-
ments to begin changing state in response to the logic and
the user clock.
The relative timing of these events can be changed via con-
figuration options in software. In addition, the GTS and
GWE events can be made dependent on the DONE pins of
multiple devices all going High, forcing the devices to start
synchronously. The sequence can also be paused at any
stage, until lock has been achieved on any or all DCMs, as
well as the DCI.
Readback
In this mode, configuration data from the Virtex-II FPGA
device can be read back. Readback is supported only in the
SelectMAP (master and slave) and Boundary Scan mode.
Along with the configuration data, it is possible to read back
the contents of all registers, distributed SelectRAM, and
block RAM resources. This capability is used for real-time
debugging. For more detailed configuration information, see
the Virtex-II User Guide.
Table 25: Virtex-II Configuration Mode Pin Settings
Configuration Mode(1) M2 M1 M0 CCLK Direction Data Width Serial DOUT(2)
Master Serial 0 0 0 Out 1 Yes
Slave Serial 1 1 1 In 1 Yes
Master SelectMAP 0 1 1 Out 8 No
Slave SelectMAP 1 1 0 In 8 No
Boundary Scan 1 0 1 N/A 1 No
Notes:
1. The HSWAP_EN pin controls the pullups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin
controls whether or not the pullups are used.
2. Daisy chaining is possible only in modes where Serial DOUT is used. For example, in SelectMAP modes, the first device does NOT
support daisy chaining of downstream devices.
Table 26: Virtex-II Bitstream Lengths
Device # of Configuration Bits
XC2V40 360,096
XC2V80 635,296
XC2V250 1,697,184
XC2V500 2,761,888
XC2V1000 4,082,592
XC2V1500 5,659,296
XC2V2000 7,492,000
XC2V3000 10,494,368
XC2V4000 15,659,936
XC2V6000 21,849,504
XC2V8000 29,063,072
Virtex-II 1.5V Field-Programmable Gate Arrays
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Advance Product Specification 1-800-255-7778 39
Bitstream Encryption
Virtex-II devices have an on-chip decryptor using one or two
sets of three keys for triple-key Data Encryption Standard
(DES) operation. Xilinx software tools offer an optional
encryption of the configuration data (bitstream) with a tri-
ple-key DES determined by the designer.
The keys are stored in the FPGA by JTAG instruction and
retained by a battery connected to the VBATT pin, when the
device is not powered. Virtex-II devices can be configured
with the corresponding encrypted bitstream, using any of
the configuration modes described previously.
A detailed description of how to use bitstream encryption is
provided in the Virtex-II User Guide. Your local FAE can also
provide specific information on this feature.
Partial Reconfiguration
Partial reconfiguration of Virtex-II devices can be accom-
plished in either Slave SelectMAP mode or Boundary-Scan
mode. Instead of resetting the chip and doing a full configu-
ration, new data is loaded into a specified area of the chip,
while the rest of the chip remains in operation. Data is
loaded on a column basis, with the smallest load unit being
a configuration “frame” of the bitstream (device size depen-
dent).
Partial reconfiguration is useful for applications that require
different designs to be loaded into the same area of a chip,
or that require the ability to change portions of a design
without having to reset or reconfigure the entire chip.
Revision History
This section records the change history for this module of the data sheet.
Virtex-II Data Sheet
The Virtex-II Data Sheet contains the following modules:
•DS031-1, Virtex-II 1.5V FPGAs: Introduction and
Ordering Information (Module 1)
•DS031-2, Virtex-II 1.5V FPGAs: Functional Description
(Module 2)
•DS031-3, Virtex-II 1.5V FPGAs: DC and Switching
Characteristics (Module 3)
•DS031-4, Virtex-II 1.5V FPGAs: Pinout Tables
(Module 4)
Date Version Revision
11/07/00 1.0 Early access draft.
12/06/00 1.1 Initial release.
01/15/01 1.2 Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II
Switching Characteristics sections.
01/25/01 1.3 The data sheet was divided into four modules (per the current style standard). A note was
added to Table 1 .
04/02/01 1.5 •Under Input/Output Individual Options, the range of values for optional pull-up and
pull-down resistors was changed to 10 - 60 K
W
from 50 - 100 K
W.
•Skipped v1.4 to sync up modules. Reverted to traditional double-column format.
07/30/01 1.6 •Added Table 6
.
•Changed definition of multiply and divide integer ranges under Digital Clock Manager
(DCM).
•Made numerous minor edits throughout this module.
10/02/01 1.7 •Updated descriptions under Digitally Controlled Impedance (DCI), Global Clock
Multiplexer Buffers, Digital Clock Manager (DCM), and Creating a Design.
10/12/01 1.8 •Made clarifying edits under Digital Clock Manager (DCM).
11/29/01 1.9 •Changed bitstream lengths for each device in Table 26.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS031-3 (v2.0) November 28, 2001 www.xilinx.com Module 3 of 4
Advance Product Specification 1-800-255-7778 1
Virtex™-II Electrical Characteristics
Virtex-II devices are provided in –4, –5 , and –6 speed
grades, with –6 having the highest performance.
Virtex-II DC and AC characteristics are specified for both
commercial and industrial grades. Except the operating tem-
perature range or unless otherwise noted, all the DC and AC
electrical parameters are the same for a particular speed
grade (that is, the timing characteristics of a –4 speed grade
industrial device are the same as for a –4 speed grade com-
mercial device). However, only selected speed grades
and/or devices might be available in the industrial range.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The parame-
ters included are common to popular designs and typical
applications. Contact Xilinx for design considerations
requiring more detailed information.
All specifications are subject to change without notice.
Virtex-II DC Characteristics
0
Virtex-II 1.5V
Field-Programmable Gate Arrays
DS031-3 (v2.0) November 28, 2001 00Advance Product Specification
R
Table 1: Absolute Maximum Ratings
Symbol Description Units
VCCINT Internal Supply voltage relative to GND –0.5 to 1.65 V
VCCAUX Auxiliary supply voltage relative to GND –0.5 to 4.0 V
VCCO Output drivers supply voltage relative to GND –0.5 to 4.0 V
VBATT Key memory battery backup supply –0.5 to 4.0 V
VREF Input Reference Voltage –0.5 to 4.0 V
VIN Input voltage relative to GND (user and dedicated I/Os) –0.5 to 4.0 V
VTS Voltage applied to 3-state output (user and dedicated I/Os) –0.5 to 4.0 V
TSTG Storage temperature (ambient) –65 to +150
°
C
TSOL Maximum soldering temp. +220
°
C
TJOperating junction temperature +125
°
C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Table 2: Recommended Operating Conditions
Symbol Description Min Max Units
VCCINT
Internal Supply voltage relative to GND, TJ=0
°
C to +85
°
C Commercial 1.425 1.575 V
Internal Supply voltage relative to GND, TJ= – 40
°
C to +100
°
C Industrial 1.425 1.575 V
VCCAUX
Auxiliary supply voltage relative to GND, TJ=0
°
C to +85
°
CCommercial3.03.6V
Auxiliary supply voltage relative to GND, TJ= – 40
°
C to +100
°
C Industrial 3.0 3.6 V
VCCO
Supply voltage relative to GND, TJ=0
°
C to +85
°
CCommercial1.23.6V
Supply voltage relative to GND, TJ= – 40
°
C to +100
°
C Industrial 1.2 3.6 V
VBATT
Battery voltage relative to GND, TJ=0
°
C to +85
°
CCommercial1.03.6V
Battery voltage relative to GND, TJ= – 40
°
C to +100
°
C Industrial 1.0 3.6 V
Notes:
1. If VCCAUX and VCCO are both at 3.3 V, they must use a common supply voltage.
2. If battery is not used, do not connect VBATT.
3. For LVDS operation, VCCAUX min is 3.13 V and max is 3.47 V.
Virtex-II 1.5V Field-Programmable Gate Arrays R
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Table 3: DC Characteristics Over Recommended Operating Conditions
Symbol Description Device Min Max Units
VDRINT Data Retention VCCINT Voltage All 1.2 V
VDRI Data Retention VCCAUX Voltage All 2.5 V
IREF VREF current per bank All –10 +10
m
A
ILInput leakage current All –10 +10
m
A
CIN Input capacitance All 10 pF
IRPU Pad pull-up (when selected) @ VIN = 0 V, VCCO = 3.3 V (sample tested) All Note 1 250
m
A
IRPD Pad pull-down (when selected) @ VIN = 3.6 V (sample tested) All Note 1 250
m
A
IBATT Battery supply current All 100 nA
Notes:
1. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.
Table 4: Quiescent Supply Current
Symbol Description Device Min Typical Max Units
ICCINTQ
Quiescent VCCINT supply current XC2v40
XC2v80
XC2v250
XC2v500
XC2v1000
XC2v1500
XC2v2000
XC2v3000
XC2v4000
XC2v6000
XC2v8000
75
75
75
100
100
150
200
200
250
250
TBD
TBD
TBD
TBD
TBD
250
TBD
TBD
TBD
TBD
1000
TBD
mA
ICCOQ
Quiescent VCCO supply current(1,2) XC2v40
XC2v80
XC2v250
XC2v500
XC2v1000
XC2v1500
XC2v2000
XC2v3000
XC2v4000
XC2v6000
XC2v8000
1
1
1
1
1
2
2
2
2
2
TBD
TBD
TBD
TBD
TBD
2
TBD
TBD
TBD
TBD
4
TBD
mA
ICCAUXQ
Quiescent VCCAUX supply current(1,2) XC2v40
XC2v80
XC2v250
XC2v500
XC2v1000
XC2v1500
XC2v2000
XC2v3000
XC2v4000
XC2v6000
XC2v8000
10
10
10
10
10
20
20
20
25
25
TBD
TBD
TBD
TBD
TBD
25
TBD
TBD
TBD
TBD
100
TBD
mA
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating.
2. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the Power Estimator or
XPOWER™.
3. Data are retained even if VCCO drops to 0 V.
4. Values specified for quiescent supply current parameters are Commercial Grade only.
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Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current
during power-on to insure proper device operation. The
actual current consumed depends on the power-on ramp
rate of the power supply.
The VCCINT
, VCCAUX, and VCCO power supplies shall ramp
on no faster than 1 ms and no slower than 50 ms. Ramp on
is defined as: 0 VDC to minimum supply voltages.
VCCAUX and VCCO for bank 4 must be connected together
(3.3 VDC) to meet the following specification.
Table 5 shows the minimum current required by Virtex-II
devices for proper power on and configuration.
Power supplies can be turned on in any sequence, as long
as VCCAUX and VCCO are connected together for bank 4.
If any VCCO bank powers up before VCCAUX, then each bank
draws up to 600 mA, worst case, until the VCCAUX powers
on(1). This does not harm the device. If the current is limited
to the minimum value above, or larger, the device powers on
properly after all three supplies have passed through their
power on reset threshold voltages.
Once initialized and configured, use the power calculator to
estimate current drain on these supplies.
Notes:
1. The 600 mA is transient current (peak); it eventually
dissipates even if VCCAUX does not power up.
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages.
Values for IOL and IOH are guaranteed over the recom-
mended operating conditions at the VOL and VOH test
points. Only selected standards are tested. These are cho-
sen to ensure that all standards meet their specifications.
The selected standards are tested at minimum VCCO with
the respective VOL and VOH voltage levels shown. Other
standards are sample tested.
Table 5: Power On Current for Virtex-II Devices
Device (mA)
2v40 2v80 2v250 2v500 2v1000 2v1500 2v2000 2v3000 2v4000 2v6000 2v8000
ICCINTMIN 250 250 250 250 500 500 500 500 750 1000 TBD
ICCAUXMIN 100 100 100 100 100 100 100 100 100 100 TBD
ICCOMIN 50 50 50 50 50 100 100 100 100 100 TBD
Notes:
1. Values specified for power on current parameters are Commercial Grade only.
Table 6: DC Input and Output Levels
Input/Output
Standard
VIL VIH VOL VOH IOL IOH
V, min V, max V, min V, max V, Max V, Min mA mA
LVTTL(1) –0.5 0.8 2.0 VCCO + 0.5 0.4 2.4 24 –24
LVCMOS33 –0.5 0.8 2.0 VCCO + 0.5 0.4 VCCO –0.4 24 – 24
LVCMOS25 –0.5 0.7 1.7 VCCO + 0.5 0.4 VCCO –0.4 24 –24
LVCMOS18 –0.5 20% VCCO 70% VCCO VCCO + 0.5 0.4 VCCO –0.45 16 –16
LVCMOS15 –0.5 20% VCCO 70% VCCO VCCO + 0.5 0.4 VCCO –0.45 16 –16
PCI33_3 –0.5 30% VCCO 50% VCCO VCCO + 0.5 10% VCCO 90% VCCO Note 2 Note 2
PCI66_3 –0.5 30% VCCO 50% VCCO VCCO + 0.5 10% VCCO 90% VCCO Note 2 Note 2
PCI– X – 0.5 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2
GTLP –0.5 VREF –0.1 VREF + 0.1 VCCO + 0.5 0.6 n/a 36 n/a
GTL –0.5 VREF –0.05 VREF + 0.05 VCCO + 0.5 0.4 n/a 40 n/a
HSTL I –0.5 VREF –0.1 VREF + 0.1 VCCO + 0.5 0.4 VCCO –0.4 8 – 8
HSTL II –0.5 VREF –0.1 VREF + 0.1 VCCO + 0.5 0.4 VCCO –0.4 16 –16
Virtex-II 1.5V Field-Programmable Gate Arrays R
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LDT Differential Signal DC Specifications (LDT_25)
LVDS DC Specifications (LVDS_33 & LVDS_25)
HSTL III –0.5 VREF –0.1 VREF + 0.1 VCCO + 0.5 0.4 VCCO –0.4 24 – 8
HSTL IV –0.5 VREF –0.1 VREF + 0.1 VCCO + 0.5 0.4 VCCO –0.4 48 – 8
SSTL3 I –0.5 VREF –0.2 VREF + 0.2 VCCO + 0.5 VREF –0.6 VREF + 0.6 8 – 8
SSTL3 II –0.5 VREF –0.2 VREF + 0.2 VCCO + 0.5 VREF –0.8 VREF + 0.8 16 –16
SSTL2 I –0.5 VREF –0.2 VREF + 0.2 VCCO + 0.5 VREF –0.65 VREF + 0.65 7.6 –7.6
SSTL2 II –0.5 VREF –0.2 VREF + 0.2 VCCO + 0.5 VREF –0.80 VREF + 0.80 15.2 –15.2
AGP –0.5 VREF –0.2 VREF + 0.2 VCCO + 0.5 10% VCCO 90% VCCO Note 2 Note 2
Notes:
1. VOL and VOH for lower drive currents are sample tested. The DONE pin is always LVTTL 12 mA.
2. Tested according to the relevant specifications.
Table 6: DC Input and Output Levels (Continued)
Input/Output
Standard
VIL VIH VOL VOH IOL IOH
V, min V, max V, min V, max V, Max V, Min mA mA
Table 7: LDT DC Specifications
DC Parameter Symbol Conditions Min Typ Max Units
Differential Output Voltage VOD RT = 100 ohm across Q and Q signals 500 600 700 mV
Change in VOD Magnitude
D
VOD –15 15 mV
Output Common Mode Voltage VOCM RT = 100 ohm across Q and Q signals 560 600 640 mV
Change in VOS Magnitude
D
VOCM –15 15 mV
Input Differential Voltage VID 200 600 1000 mV
Change in VID Magnitude
D
VID –15 15 mV
Input Common Mode Voltage VICM 500 600 700 mV
Change in VICM Magnitude
D
VICM –15 15 mV
Table 8: LVDS DC Specifications
DC Parameter Symbol Conditions Min Typ Max Units
Supply Voltage VCCO 3.3 or 2.5 V
Output High Voltage for Q and Q VOH RT = 100
W
across Q and Q signals 1.475 V
Output Low Voltage for Q and Q VOL RT = 100
W
across Q and Q signals 0.925 V
Differential Output Voltage (Q – Q),
Q = High (Q –Q), Q = High VODIFF RT = 100
W
across Q and Q signals 250 350 400 mV
Output Common-Mode Voltage VOCM RT = 100
W
across Q and Q signals 1.125 1.2 1.275 V
Differential Input Voltage (Q – Q),
Q = High (Q – Q), Q = High VIDIFF Common-mode input voltage = 1.25 V 100 350 N/A mV
Input Common-Mode Voltage VICM Differential input voltage =
±
350 mV 0.2 1.25 2.2 V
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Extended LVDS DC Specifications (LVDSEXT_33 & LVDSEXT_25)
LVPECL DC Specifications
These values are valid when driving a 100
W
differential
load only, i.e., a 100
W
resistor between the two receiver
pins. The VOH levels are 200 mV below standard LVPECL
levels and are compatible with devices tolerant of lower
common-mode ranges. Table 10 summarizes the DC output
specifications of LVPECL.
Table 9: Extended LVDS DC Specifications
DC Parameter Symbol Conditions Min Typ Max Units
Supply Voltage VCCO 3.3 or 2.5 V
Output High Voltage for Q and Q VOH RT = 100
W
across Q and Q signals 1.70 V
Output Low Voltage for Q and Q VOL RT = 100
W
across Q and Q signals 0.705 V
Differential Output Voltage (Q – Q),
Q = High (Q –Q), Q = High VODIFF RT = 100
W
across Q and Q signals 440 820 mV
Output Common-Mode Voltage VOCM RT = 100
W
across Q and Q signals 1.125 1.200 1.275 V
Differential Input Voltage (Q – Q),
Q = High (Q –Q), Q = High VIDIFF Common-mode input voltage = 1.25 V 100 350 N/A mV
Input Common-Mode Voltage VICM Differential input voltage =
±
350 mV 0.2 1.25 2.2 V
Table 10: LVPECL DC Specifications
DC Parameter Min Max Min Max Min Max Units
VCCO 3.0 3.3 3.6 V
VOH 1.8 2.11 1.92 2.28 2.13 2.41 V
VOL 0.96 1.27 1.06 1.43 1.30 1.57 V
VIH 1.49 2.72 1.49 2.72 1.49 2.72 V
VIL 0.86 2.125 0.86 2.125 0.86 2.125 V
Differential Input Voltage 0.3 –0.3 –0.3 –V
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Virtex-II Performance Characteristics
This section provides the performance characteristics of
some common functions and designs implemented in
Virtex-II devices. The numbers reported here are worst-case
values; they have all been fully characterized. Note that
these values are subject to the same guidelines as Virtex-II
Switching Characteristics, page 8 (speed files).
Table 11 provides pin-to-pin values (in nanoseconds)
including IOB delays; that is, delay through the device from
input pin to output pin. In the case of multiple inputs and out-
puts, the worst delay is reported.
Table 12 shows internal (register-to-register) performance. Values are reported in MHz.
Table 11: Pin-to-Pin Performance
Description Pin-to-Pin (w/ I/O delays) Device Used & Speed Grade
Basic Functions
16-bit Address Decoder 6.3 XC2V1000 – 5
32-bit Address Decoder 7.7 XC2V1000 – 5
64-bit Address Decoder 9.3 XC2V1000 – 5
4:1 MUX 5.7 XC2V1000 – 5
8:1 MUX 6.5 XC2V1000 – 5
16:1 MUX 6.7 XC2V1000 – 5
32:1 MUX 8.7 XC2V1000 – 5
Combinatorial (pad to LUT to pad) 5.0 XC2V1000 – 5
Memory
Block RAM
Pad to setup 1.6
Clock to Pad 9.5
Distributed RAM
Pad to setup 2.7 XC2V1000 – 5
Clock to Pad 5.1 (no clk skew) XC2V1000 – 5
Table 12: Register-to-Register Performance
Description Register-to-Register Performance Device Used & Speed Grade
Basic Functions
16-bit Address Decoder 398 XC2V1000 – 5
32-bit Address Decoder 291 XC2V1000 – 5
64-bit Address Decoder 275 XC2V1000 – 5
4:1 MUX 563 XC2V1000 – 5
8:1 MUX 454 XC2V1000 – 5
16:1 MUX 414 XC2V1000 – 5
32:1 MUX 323 XC2V1000 – 5
Register to LUT to Register 613 XC2V1000 – 5
8-bit Adder 292 XC2V1000 – 5
16-bit Adder 239 XC2V1000 – 5
64-bit Adder 114 XC2V1000 – 5
64-bit Counter 114 XC2V1000 – 5
64-bit Accumulator 110 XC2V1000 – 5
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Multiplier 18x18 (with Block RAM inputs) 88 XC2V1000 – 5
Multiplier 18x18 (with Register inputs) 105 XC2V1000 – 5
Memory
Block RAM
Single-Port 4096 x 4 bits 265
Single-Port 2048 x 9 bits N/A
Single-Port 1024 x 18 bits N/A
Single-Port 512 x 36 bits N/A
Dual-Port A:4096 x 4 bits & B:1024 x 18 bits N/A
Dual-Port A:1024 x 18 bits & B:1024 x 18 bits N/A
Dual-Port A:2048 x 9 bits & B: 512 x 36 bits N/A
Distributed RAM
Single-Port 32 x 8-bit 385 XC2V1000 – 5
Single-Port 64 x 8-bit 335 XC2V1000 – 5
Single-Port 128 x 8-bit 266 XC2V1000 – 5
Dual-Port 16 x 8 400 XC2V1000 – 5
Dual-Port 32 x 8 300 XC2V1000 – 5
Dual-Port 64 x 8 294 XC2V1000 – 5
Shift Registers
128-bit SRL N/A
256-bit SRL N/A
FIFOs (Async. in Block RAM)
1024 x 18-bit N/A
1024 x 18-bit N/A
FIFOs (Sync. in SRL)
128 x 8-bit N/A
128 x 16-bit N/A
CAMs in Block RAM
32 x 9-bit N/A
64 x 9-bit N/A
128 x 9-bit N/A
256 x 9-bit N/A
CAMs in SRL
32 x 16-bit N/A
64 x 32-bit N/A
128 x 40-bit N/A
256 x 48-bit N/A
1024 x 16-bit N/A
1024 x 72-bit N/A
Table 12: Register-to-Register Performance (Continued)
Description Register-to-Register Performance Device Used & Speed Grade
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Virtex-II Switching Characteristics
Switching characteristics are specified on a
per-speed-grade basis and can be designated as Advance,
Preliminary, or Production. Note that Virtex-II Performance
Characteristics, page 6 are subject to these guidelines, as
well. Each designation is defined as follows:
Advance: These speed files are based on simulations only
and are typically available soon after device design specifi-
cations are frozen. Although speed grades with this desig-
nation are considered relatively stable and conservative,
some under-reporting might still occur.
Preliminary: These speed files are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
Production: These speed files are released once enough
production silicon of a particular device family member has
been characterized to provide full correlation between
speed files and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.
Since individual family members are produced at different
times, the migration from one category to another depends
completely on the status of the fabrication process for each
device. Table 13 correlates the current status of each Vir-
tex-II device with a corresponding speed file designation.
All specifications are always representative of worst-case
supply voltage and junction temperature conditions.
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the Xilinx static timing analyzer
and back-annotate to the simulation net list. Unless other-
wise noted, values apply to all Virtex-II devices.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for
LVTTL levels. For other standards, adjust the delays with
the values shown in IOB Input Switching Characteristics
Standard Adjustments, page 10.
Table 13: Virtex-II Device Speed Grade Designations
Device
Speed Grade Designations
Advance Preliminary Production
XC2V40 –6, –5, – 4
XC2V80 –6, –5, – 4
XC2V250 –6, –5, – 4
XC2V500 –6, –5, – 4
XC2V1000 – 6 – 5, – 4
XC2V1500 –6, –5, – 4
XC2V2000 –6, –5, – 4
XC2V3000 –6, –5, – 4
XC2V4000 –6, –5, – 4
XC2V6000 –6, –5, – 4
XC2V8000 –5, – 4
Table 14: IOB Input Switching Characteristics
Speed Grade
UnitsDescription Symbol Device – 6 – 5 – 4
Propagation Delays
Pad to I output, no delay TIOPI All 0.69 0.76 0.88 ns, max
Pad to I output, with delay TIOPID 2v40 3.15 3.46 3.98 ns, max
2v80 3.15 3.46 3.98 ns, max
2v250 3.15 3.46 3.98 ns, max
2v500 3.15 3.46 3.98 ns, max
2v1000 3.15 3.46 3.98 ns, max
2v1500 3.15 3.46 3.98 ns, max
2v2000 3.15 3.46 3.98 ns, max
2v3000 3.24 3.56 4.10 ns, max
2v4000 3.24 3.56 4.10 ns, max
2v6000 3.51 3.86 4.44 ns, max
2v8000 TBD TBD TBD ns, max
Virtex-II 1.5V Field-Programmable Gate Arrays
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Propagation Delays
Pad to output IQ via transparent
latch, no delay TIOPLI All 0.99 1.08 1.24 ns, max
Pad to output IQ via transparent
latch, with delay
TIOPLID 2v40 3.44 3.78 4.35 ns, max
2v80 3.44 3.78 4.35 ns, max
2v250 3.44 3.78 4.35 ns, max
2v500 3.44 3.78 4.35 ns, max
2v1000 3.44 3.78 4.35 ns, max
2v1500 3.44 3.78 4.35 ns, max
2v2000 3.44 3.78 4.35 ns, max
2v3000 3.53 3.88 4.46 ns, max
2v4000 3.53 3.88 4.46 ns, max
2v6000 3.80 4.18 4.81 ns, max
2v8000 TBD TBD TBD ns, max
Clock CLK to output IQ TIOCKIQ All 0.63 0.69 0.80 ns, max
Setup and Hold Times With Respect to Clock at IOB Input
Register
Pad, no delay TIOPICK/TIOICKP All 0.88/–0.36 0.96/–0.39 1.11/–0.45 ns, min
Pad, with delay TIOPICKD/TIOICKPD 2v40 3.33/–2.07 3.66/–2.28 4.21/–2.63 ns, min
2v80 3.33/–2.07 3.66/–2.28 4.21/–2.63 ns, min
2v250 3.33/–2.07 3.66/–2.28 4.21/–2.63 ns, min
2v500 3.33/–2.07 3.66/–2.28 4.21/–2.63 ns, min
2v1000 3.33/–2.07 3.66/–2.28 4.21/–2.63 ns, min
2v1500 3.33/–2.07 3.66/–2.28 4.21/–2.63 ns, min
2v2000 3.33/–2.07 3.66/–2.28 4.21/–2.63 ns, min
2v3000 3.42/–2.14 3.76/–2.35 4.33/–2.71 ns, min
2v4000 3.42/–2.14 3.76/–2.35 4.33/–2.71 ns, min
2v6000 3.69/–2.33 4.06/–2.56 4.67/–2.95 ns, min
2v8000 TBD TBD TBD ns, min
ICE input TIOICECK/TIOCKICE All 0.19/ 0.03 0.21/ 0.04 0.24/ 0.04 ns, min
SR input (IFF, synchronous) TIOSRCKI All 0.27 0.30 0.34 ns, min
Set/Reset Delays
SR input to IQ (asynchronous) TIOSRIQ All 1.11 1.22 1.40 ns, max
GSR to output IQ TGSRQ All 7.27 7.99 9.19 ns, max
Notes:
1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 18.
Table 14: IOB Input Switching Characteristics (Continued)
Speed Grade
UnitsDescription Symbol Device – 6 – 5 – 4
Virtex-II 1.5V Field-Programmable Gate Arrays R
Module 3 of 4 www.xilinx.com DS031-3 (v2.0) November 28, 2001
10 1-800-255-7778 Advance Product Specification
IOB Input Switching Characteristics Standard Adjustments
Table 15: IOB Input Switching Characteristics Standard Adjustments
Speed Grade
Description Symbol Standard –6–5–4Units
Data Input Delay Adjustments
Standard-specific data input delay
adjustments
TILVTTL LVTTL 0.00 0.00 0.00 ns
TILVCMOS33 LVCMOS33 0.00 0.00 0.00 ns
TILVCMOS25 LVCMOS25 0.10 0.11 0.12 ns
TILVCMOS18 LVCMOS18 0.39 0.43 0.49 ns
TILVCMOS15 LVCMOS15 0.91 1.00 1.15 ns
TILVDS_25 LVDS_25 0.55 0.60 0.69 ns
TILVDS_33 LVDS_33 0.55 0.60 0.69 ns
TILVPECL_33 LVPECL 0.55 0.60 0.69 ns
TIPCI33_3 PCI, 33 MHz, 3.3 V 0.00 0.00 0.00 ns
TIPCI66_3 PCI, 66 MHz, 3.3 V 0.00 0.00 0.00 ns
TIPCIX PCI–X, 133 MHz, 3.3 V 0.00 0.00 0.00 ns
TIGTL GTL 0.38 0.42 0.48 ns
TIGTLP GTLP 0.38 0.42 0.48 ns
TIHSTL_I HSTL I 0.38 0.42 0.48 ns
TIHSTL_II HSTL II 0.38 0.42 0.48 ns
TIHSTL_III HSTL III 0.38 0.42 0.48 ns
TIHSTL_IV HSTL IV 0.38 0.42 0.48 ns
TIHSTL_I_18 HSTL I_18 0.38 0.42 0.48 ns
TIHSTL_II_18 HSTL II_18 0.38 0.42 0.48 ns
TIHSTL_III_18 HSTL III_18 0.38 0.42 0.48 ns
TIHSTL_IV_18 HSTL IV_18 0.38 0.42 0.48 ns
TISSTL2_I SSTL2 I 0.38 0.42 0.48 ns
TISSTL2_II SSTL2 II 0.38 0.42 0.48 ns
TISSTL3_I SSTL3 I 0.32 0.35 0.40 ns
TISSTL3_II SSTL3 II 0.32 0.35 0.40 ns
TIAGP AGP 0.32 0.35 0.40 ns
TILVDCI_33 LVDCI_33 0.00 0.00 0.00 ns
TILVDCI_25 LVDCI_25 0.10 0.11 0.12 ns
TILVDCI_18 LVDCI_18 0.39 0.43 0.49 ns
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TILVDCI_15 LVDCI_15 0.91 1.00 1.14 ns
TILVDCI_DV2_33 LVDCI_DV2_33 0.00 0.00 0.00 ns
TILVDCI_DV2_25 LVDCI_DV2_25 0.10 0.11 0.12 ns
TILVDCI_DV2_18 LVDCI_DV2_18 0.39 0.43 0.49 ns
TILVDCI_DV2_15 LVDCI_DV2_15 0.91 1.00 1.14 ns
TIGTL_DCI GTL_DCI 0.38 0.42 0.48 ns
TIGTLP_DCI GTLP_DCI 0.38 0.42 0.48 ns
TIHSTL_I_DCI HSTL_I_DCI 0.38 0.42 0.48 ns
TIHSTL_II_DCI HSTL_II_DCI 0.38 0.42 0.48 ns
TIHSTL_III_DCI HSTL_III_DCI 0.38 0.42 0.48 ns
TIHSTL_IV_DCI HSTL_IV_DCI 0.38 0.42 0.48 ns
TIHSTL_I_DCI_18 HSTL_I_DCI_18 0.38 0.42 0.48 ns
TIHSTL_II_DCI_18 HSTL_II_DCI_18 0.38 0.42 0.48 ns
TIHSTL_III_DCI_18 HSTL_III_DCI_18 0.38 0.42 0.48 ns
TIHSTL_IV_DCI_18 HSTL_IV_DCI_18 0.38 0.42 0.48 ns
TISSTL2_I_DCI SSTL2_I_DCI 0.38 0.42 0.48 ns
TISSTL2_II_DCI SSTL2_II_DCI 0.38 0.42 0.48 ns
TISSTL3_I_DCI SSTL3_I_DCI 0.32 0.35 0.40 ns
TISSTL3_II_DCI SSTL3_II_DCI 0.32 0.35 0.40 ns
TILDT_25 LDT_25 0.45 0.49 0.56 ns
TIULVDS_25 ULVDS_25 0.45 0.49 0.56 ns
Notes:
1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 18.
Table 15: IOB Input Switching Characteristics Standard Adjustments (Continued)
Speed Grade
Description Symbol Standard –6–5–4Units
Virtex-II 1.5V Field-Programmable Gate Arrays R
Module 3 of 4 www.xilinx.com DS031-3 (v2.0) November 28, 2001
12 1-800-255-7778 Advance Product Specification
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 13.
Table 16: IOB Output Switching Characteristics
Speed Grade
Description Symbol –6–5–4Units
Propagation Delays
O input to Pad TIOOP 2.39 2.63 3.03 ns, max
O input to Pad via transparent latch TIOOLP 2.69 2.95 3.40 ns, max
3-State Delays
T input to Pad high-impedance(1) TIOTHZ 0.51 0.56 0.64 ns, max
T input to valid data on Pad TIOTON 2.34 2.57 2.96 ns, max
T input to Pad high-impedance via transparent
latch(1) TIOTLPHZ 0.80 0.88 1.01 ns, max
T input to valid data on Pad via transparent latch TIOTLPON 2.63 2.89 3.33 ns, max
GTS to Pad high impedance(1) TGTS 6.56 7.22 8.30 ns, max
Sequential Delays
Clock CLK to Pad TIOCKP 2.72 2.99 3.44 ns, max
Clock CLK to Pad high-impedance
(synchronous)(1) TIOCKHZ 0.95 1.04 1.20 ns, max
Clock CLK to valid data on Pad (synchronous) TIOCKON 2.78 3.06 3.51 ns, max
Setup and Hold Times Before/After Clock CLK
O input TIOOCK/TIOCKO 0.31/–0.08 0.34/–0.09 0.39/–0.11 ns, min
OCE input TIOOCECK/TIOCKOCE 0.19/–0.06 0.21/–0.07 0.24/–0.08 ns, min
SR input (OFF) TIOSRCKO/TIOCKOSR 0.27/–0.05 0.30/–0.06 0.34/–0.07 ns, min
3–State Setup Times, T input TIOTCK/TIOCKT 0.28/–0.06 0.31/–0.07 0.35/–0.08 ns, min
3–State Setup Times, TCE input TIOTCECK/TIOCKTCE 0.19/–0.06 0.21/–0.07 0.24/–0.08 ns, min
3–State Setup Times, SR input (TFF) TIOSRCKT/TIOCKTSR 0.27/–0.05 0.30/–0.06 0.34/–0.07 ns, min
Set/Reset Delays
SR input to Pad (asynchronous) TIOSRP 3.37 3.71 4.26 ns, max
SR input to Pad high-impedance
(asynchronous)(1) TIOSRHZ 1.52 1.67 1.92 ns, max
SR input to valid data on Pad (asynchronous) TIOSRON 3.35 3.68 4.23 ns, max
GSR to Pad TIOGSRQ 5.44 5.98 6.88 ns, max
Notes:
1. The 3-state turn-off delays should not be adjusted.
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Advance Product Specification 1-800-255-7778 13
IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.
Table 17: IOB Output Switching Characteristics Standard Adjustments
Speed Grade
Description Symbol Standard –6 –5 –4Units
Output Delay Adjustments
Standard-specific adjustments for output
delays terminating at pads (based on
standard capacitive load, Csl)
TOLVTTL_S2 LVTTL, Slow, 2 mA 8.53 9.38 10.79 ns
TOLVTTL_S4 4 mA 5.15 5.67 6.52 ns
TOLVTTL_S6 6 mA 3.75 4.12 4.74 ns
TOLVTTL_S8 8 mA 2.57 2.83 3.25 ns
TOLVTTL_S12 12 mA 2.00 2.19 2.52 ns
TOLVTTL_S16 16 mA 1.17 1.28 1.48 ns
TOLVTTL_S24 24 mA 0.85 0.94 1.08 ns
TOLVTTL_F2 LVTTL, Fast, 2 mA 5.37 5.90 6.79 ns
TOLVTTL_F4 4 mA 2.19 2.41 2.77 ns
TOLVTTL_F6 6 mA 0.94 1.03 1.18 ns
TOLVTTL_F8 8 mA 0.06 0.07 0.08 ns
TOLVTTL_F12 12 mA 0.00 0.00 0.00 ns
TOLVTTL_F16 16 mA –0.30 –0.33 –0.38 ns
TOLVTTL_F24 24 mA –0.44 –0.48 –0.55 ns
TOLVDS_25 LVDS –1.02 –1.12 –1.29 ns
TOLVDS_33 LVDS –1.07 –1.18 –1.36 ns
TOLVDSEXT_25 LVDS –0.94 –1.03 –1.19 ns
TOLVDSEXT_33 LVDS –0.95 –1.05 –1.21 ns
TOLDT_25 LDT –1.01 –1.11 –1.28 ns
TOBLVDS_25 BLVDS 0.63 0.69 0.79 ns
TOULVDS_25 ULVDS –1.01 –1.11 –1.28 ns
TOLVPECL_33 LVPECL 0.74 0.81 0.93 ns
TOPCI33_3 PCI, 33 MHz, 3.3 V 1.06 1.17 1.34 ns
TOPCI66_3 PCI, 66 MHz, 3.3 V –0.14 –0.15 –0.18 ns
TOPCIX PCI–X, 133 MHz, 3.3 V –0.14 –0.16 –0.18 ns
TOGTL GTL 1.13 1.24 1.43 ns
TOGTLP GTLP 0.43 0.47 0.54 ns
TOHSTL_I HSTL I 0.19 0.21 0.24 ns
TOHSTL_II HSTL II 0.01 0.01 0.01 ns
TOHSTL_III HSTL III –0.17 –0.18 –0.21 ns
TOHSTL_IV HSTL IV –0.22 –0.24 –0.28 ns
TOHSTL_I_18 HSTL I_18 0.22 0.25 0.28 ns
TOHSTL_II_18 HSTL II_18 0.13 0.14 0.16 ns
TOHSTL_III_18 HSTL III_18 0.11 0.12 0.14 ns
TOHSTL_IV_18 HSTL IV_18 0.15 0.17 0.19 ns
Virtex-II 1.5V Field-Programmable Gate Arrays R
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14 1-800-255-7778 Advance Product Specification
TOSSTL2_I SSTL2 I 0.20 0.22 0.25 ns
TOSSTL2_II SSTL2 II –0.36 –0.39 –0.45 ns
TOSSTL3_I SSTL3 I 0.29 0.32 0.36 ns
TOSSTL3_II SSTL3 II –0.14 –0.16 –0.18 ns
TOAGP AGP –0.44 –0.48 –0.56 ns
TOLVCMOS33_S2 LVCMOS33, Slow, 2 mA 7.03 7.74 8.90 ns
TOLVCMOS33_S4 4 mA 3.83 4.22 4.85 ns
TOLVCMOS33_S6 6 mA 2.73 3.00 3.45 ns
TOLVCMOS33_S8 8 mA 1.97 2.17 2.50 ns
TOLVCMOS33_S12 12 mA 1.46 1.60 1.84 ns
TOLVCMOS33_S16 16 mA 0.87 0.96 1.10 ns
TOLVCMOS33_S24 24 mA 0.82 0.91 1.04 ns
TOLVCMOS33_F2 LVCMOS33, Fast, 2 mA 5.46 6.01 6.91 ns
TOLVCMOS33_F4 4 mA 2.12 2.33 2.68 ns
TOLVCMOS33_F6 6 mA 0.62 0.68 0.79 ns
TOLVCMOS33_F8 8 mA –0.08 –0.09 –0.11 ns
TOLVCMOS33_F12 12 mA –0.22 –0.24 –0.28 ns
TOLVCMOS33_F16 16 mA –0.42 –0.46 –0.53 ns
TOLVCMOS33_F24 24 mA –0.51 –0.56 –0.65 ns
TOLVCMOS25_S2 LVCMOS25, Slow, 2 mA 8.34 9.17 10.55 ns
TOLVCMOS25_S4 4 mA 4.69 5.16 5.93 ns
TOLVCMOS25_S6 6 mA 4.14 4.56 5.24 ns
TOLVCMOS25_S8 8 mA 3.61 3.97 4.57 ns
TOLVCMOS25_S12 12 mA 2.51 2.76 3.18 ns
TOLVCMOS25_S16 16 mA 1.98 2.18 2.51 ns
TOLVCMOS25_S24 24 mA 1.62 1.78 2.05 ns
TOLVCMOS25_F2 LVCMOS25, Fast, 2 mA 3.90 4.29 4.94 ns
TOLVCMOS25_F4 4 mA 0.92 1.01 1.17 ns
TOLVCMOS25_F6 6 mA 0.41 0.45 0.51 ns
TOLVCMOS25_F8 8 mA 0.23 0.25 0.29 ns
TOLVCMOS25_F12 12 mA –0.13 –0.14 –0.17 ns
TOLVCMOS25_F16 16 mA –0.22 –0.24 –0.28 ns
TOLVCMOS25_F24 24 mA –0.38 –0.42 –0.48 ns
TOLVCMOS18_S2 LVCMOS18, Slow, 2 mA 15.71 17.28 19.87 ns
TOLVCMOS18_S4 4 mA 10.38 11.42 13.13 ns
TOLVCMOS18_S6 6 mA 7.46 8.21 9.44 ns
TOLVCMOS18_S8 8 mA 6.92 7.61 8.75 ns
TOLVCMOS18_S12 12 mA 5.31 5.84 6.71 ns
TOLVCMOS18_S16 16 mA 5.05 5.56 6.39 ns
TOLVCMOS18_F2 LVCMOS18, Fast, 2 mA 4.64 5.10 5.87 ns
Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued)
Speed Grade
Description Symbol Standard –6 –5 –4Units
Virtex-II 1.5V Field-Programmable Gate Arrays
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TOLVCMOS18_F4 4 mA 1.48 1.63 1.87 ns
TOLVCMOS18_F6 6 mA 0.66 0.73 0.83 ns
TOLVCMOS18_F8 8 mA 0.59 0.65 0.75 ns
TOLVCMOS18_F12 12 mA 0.12 0.14 0.16 ns
TOLVCMOS18_F16 16 mA 0.13 0.14 0.16 ns
TOLVCMOS15_S2 LVCMOS15, Slow, 2 mA 19.67 21.63 24.88 ns
TOLVCMOS15_S4 4 mA 13.13 14.44 16.61 ns
TOLVCMOS15_S6 6 mA 12.55 13.80 15.87 ns
TOLVCMOS15_S8 8 mA 9.54 10.49 12.06 ns
TOLVCMOS15_S12 12 mA 9.46 10.41 11.97 ns
TOLVCMOS15_S16 16 mA 8.56 9.41 10.83 ns
TOLVCMOS15_F2 LVCMOS15, Fast, 2 mA 4.32 4.75 5.46 ns
TOLVCMOS15_F4 4 mA 1.59 1.75 2.02 ns
TOLVCMOS15_F6 6 mA 1.21 1.33 1.53 ns
TOLVCMOS15_F8 8 mA 0.79 0.87 1.00 ns
TOLVCMOS15_F12 12 mA 0.63 0.69 0.79 ns
TOLVCMOS15_F16 16 mA 0.59 0.65 0.75 ns
TOLVDCI_33 LVDCI_33 0.66 0.73 0.83 ns
TOLVDCI_25 LVDCI_25 0.57 0.62 0.71 ns
TOLVDCI_18 LVDCI_18 1.40 1.54 1.77 ns
TOLVDCI_15 LVDCI_15 2.96 3.26 3.75 ns
TOLVDCI_DV2_33 LVDCI_DV2_33 0.15 0.17 0.19 ns
TOLVDCI_DV2_25 LVDCI_DV2_25 0.31 0.34 0.39 ns
TOLVDCI_DV2_18 LVDCI_DV2_18 1.07 1.18 1.35 ns
TOLVDCI_DV2_15 LVDCI_DV2_15 2.05 2.25 2.59 ns
TOGTL_DCI GTL_DCI 2.82 3.10 3.56 ns
TOGTLP_DCI GTLP_DCI 2.03 2.23 2.56 ns
TOHSTL_I_DCI HSTL_I_DCI 0.50 0.55 0.63 ns
TOHSTL_II_DCI HSTL_II_DCI 0.39 0.43 0.50 ns
TOHSTL_III_DCI HSTL_III_DCI 0.15 0.17 0.19 ns
TOHSTL_IV_DCI HSTL_IV_DCI –0.01 –0.01 –0.02 ns
TOHSTL_I_DCI_18 HSTL_I_DCI_18 0.21 0.23 0.26 ns
TOHSTL_II_DCI_18 HSTL_II_DCI_18 0.94 1.03 1.19 ns
TOHSTL_III_DCI_18 HSTL_III_DCI_18 0.18 0.20 0.23 ns
TOHSTL_IV_DCI_18 HSTL_IV_DCI_18 – 0.14 –0.16 –0.18 ns
TOSSTL2_I_DCI SSTL2_I_DCI 0.25 0.28 0.32 ns
TOSSTL2_II_DCI SSTL2_II_DCI 0.05 0.06 0.07 ns
TOSSTL3_I_DCI SSTL3_I_DCI 0.30 0.33 0.38 ns
TOSSTL3_II_DCI SSTL3_II_DCI 0.16 0.18 0.20 ns
Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued)
Speed Grade
Description Symbol Standard –6 –5 –4Units
Virtex-II 1.5V Field-Programmable Gate Arrays R
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16 1-800-255-7778 Advance Product Specification
Table 18: Delay Measurement Methodology
Standard VL(1) VH(1) Meas. Point VREF (Typ)(2)
LVTTL 0 3 1.4 –
LVCMOS33 0 3.3 1.65 –
LVCMOS25 0 2.5 1.25 –
LVCMOS18 0 1.8 0.9 –
LVCMOS15 0 1.5 0.75 –
PCI33_3 Per PCI Specification –
PCI66_3 Per PCI Specification –
PCIX33_3 Per PCI–X Specification –
GTL VREF –0.2 VREF +0.2 V
REF 0.80
GTLP VREF –0.2 VREF +0.2 V
REF 1.0
HSTL Class I VREF –0.5 VREF +0.5 V
REF 0.75
HSTL Class II VREF –0.5 VREF +0.5 V
REF 0.75
HSTL Class III VREF –0.5 VREF +0.5 V
REF 0.90
HSTL Class IV VREF –0.5 VREF +0.5 V
REF 0.90
SSTL3 I & II VREF –1.0 VREF +1.0 V
REF 1.5
SSTL2 I & II VREF –0.75 VREF +0.75 V
REF 1.25
AGP VREF –(0.2xVCCO)V
REF +(0.2xV
CCO)V
REF Per AGP Spec
LVDS_25 1.2 –0.125 1.2 +0.125 1.2
LVDS_33 1.2 –0.125 1.2 +0.125 1.2
LVDSEXT_25 1.2 –0.125 1.2 +0.125 1.2
LVDSEXT_33 1.2 –0.125 1.2 +0.125 1.2
ULVDS_25 0.6 –0.125 0.6 +0.125 0.6
LDT_25 0.6 –0.125 0.6 +0.125 0.6
LVPECL 1.6 –0.3 1.6 + 0.3 1.6
Notes:
1. Input waveform switches between VLand VH.
2. Measurements are made at VREF (Typ), Maximum, and Minimum. Worst-case values are reported.
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Advance Product Specification 1-800-255-7778 17
Table 19: Standard Capacitive Loads
Standard Csl (pF)
LVTTL Fast Slew Rate, 2mA drive 35
LVTTL Fast Slew Rate, 4mA drive 35
LVTTL Fast Slew Rate, 6mA drive 35
LVTTL Fast Slew Rate, 8mA drive 35
LVTTL Fast Slew Rate, 12mA drive 35
LVTTL Fast Slew Rate, 16mA drive 35
LVTTL Fast Slew Rate, 24mA drive 35
LVTTL Slow Slew Rate, 2mA drive 35
LVTTL Slow Slew Rate, 4mA drive 35
LVTTL Slow Slew Rate, 6mA drive 35
LVTTL Slow Slew Rate, 8mA drive 35
LVTTL Slow Slew Rate, 12mA drive 35
LVTTL Slow Slew Rate, 16mA drive 35
LVTTL Slow Slew Rate, 24mA drive 35
LVCMOS33 35
LVCMOS25 35
LVCMOS18 35
LVCMOS15 35
PCI 33MHZ 3.3 V 10
PCI 66 MHz 3.3 V 10
PCI–X 133 MHz 3.3 V 10
GTL 0
GTLP 0
HSTL Class I 20
HSTL Class II 20
HSTL Class III 20
HSTL Class IV 20
SSTL2 Class I 30
SSTL2 Class II 30
SSTL3 Class I 30
SSTL3 Class II 30
AGP 10
Notes:
1. I/O parameter measurements are made with the capacitance values shown above.
2. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it.
3. Use of IBIS models results in a more accurate prediction of the propagation delay:
a. Model the output in an IBIS simulation into the standard capacitive load.
b. Record the relative time to the VOH or VOL transition of interest.
c. Remove the capacitance, and model the actual PCB traces (transmission lines) and actual loads from the appropriate IBIS
models for driven devices.
d. Record the results from the new simulation.
e. Compare with the capacitance simulation. The increase or decrease in delay from the capacitive load delay simulation should
be added or subtracted from the value above to predict the actual delay.
Virtex-II 1.5V Field-Programmable Gate Arrays R
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Clock Distribution Switching Characteristics
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used (see Figure 15). The values listed below are
worst-case. Precise values are provided by the timing analyzer.
Table 20: Clock Distribution Switching Characteristics
Description Symbol
Speed Grade
Units
–6 –5 –4
Global Clock Buffer I input to O output TGIO 0.17 0.19 0.21 ns, max
Table 21: CLB Switching Characteristics
Description Symbol
Speed Grade
Units
–6 –5 –4
Combinatorial Delays
4-input function: F/G inputs to X/Y outputs TILO 0.35 0.39 0.44 ns, max
5-input function: F/G inputs to F5 output TIF5 0.57 0.63 0.72 ns, max
5-input function: F/G inputs to X output TIF5X 0.76 0.83 0.95 ns, max
FXINA or FXINB inputs to Y output via MUXFX TIFXY 0.36 0.39 0.45 ns, max
FXINA input to FX output via MUXFX TINAFX 0.26 0.28 0.32 ns, max
FXINB input to FX output via MUXFX TINBFX 0.26 0.28 0.32 ns, max
SOPIN input to SOPOUT output via ORCY TSOPSOP 0.35 0.38 0.44 ns, max
Incremental delay routing through transparent latch
to XQ/YQ outputs TIFNCTL 0.41 0.45 0.51 ns, max
Sequential Delays
FF Clock CLK to XQ/YQ outputs TCKO 0.45 0.50 0.57 ns, max
Latch Clock CLK to XQ/YQ outputs TCKLO 0.54 0.59 0.68 ns, max
Setup and Hold Times Before/After Clock CLK
BX/BY inputs TDICK/TCKDI 0.30/–0.07 0.33/–0.08 0.37/–0.09 ns, min
DY inputs TDYCK/TCKDY 0.30/–0.07 0.33/–0.08 0.37/–0.09 ns, min
DX inputs TDXCK/TCKDX 0.30/–0.07 0.33/–0.08 0.37/–0.09 ns, min
CE input TCECK/TCKCE 0.19/–0.06 0.21/–0.07 0.24/–0.08 ns, min
SR/BY inputs (synchronous) TRCK/TCKR 0.21/–0.02 0.23/–0.03 0.26/–0.03 ns, min
Clock CLK
Minimum Pulse Width, High TCH 0.61 0.67 0.77 ns, min
Minimum Pulse Width, Low TCL 0.61 0.67 0.77 ns, min
Set/Reset
Minimum Pulse Width, SR/BY inputs TRPW 0.61 0.67 0.77 ns, min
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous) TRQ 1.06 1.17 1.34 ns, max
Toggle Frequency (MHz) (for export control) FTOG 826.45 751.31 653.59 MHz
Virtex-II 1.5V Field-Programmable Gate Arrays
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Advance Product Specification 1-800-255-7778 19
CLB Distributed RAM Switching Characteristics
CLB Shift Register Switching Characteristics
Table 22: CLB Distributed RAM Switching Characteristics
Description Symbol
Speed Grade
Units
–6 –5 –4
Sequential Delays
Clock CLK to X/Y outputs (WE active) in 16 x 1 mode TSHCKO16 1.63 1.79 2.05 ns, max
Clock CLK to X/Y outputs (WE active) in 32 x 1 mode TSHCKO32 1.97 2.17 2.49 ns, max
Clock CLK to F5 output TSHCKOF5 1.77 1.94 2.23 ns, max
Setup and Hold Times Before/After Clock CLK
BX/BY data inputs (DIN) TDS/TDH 0.53/–0.09 0.58/–0.10 0.67/–0.11 ns, min
F/G address inputs TAS/TAH 0.40/ 0.00 0.44/ 0.00 0.50/ 0.00 ns, min
CE input (WE) TWES/TWEH 0.42/–0.01 0.46/–0.01 0.53/–0.01 ns, min
Clock CLK
Minimum Pulse Width, High TWPH 0.57 0.63 0.72 ns, min
Minimum Pulse Width, Low TWPL 0.57 0.63 0.72 ns, min
Minimum clock period to meet address write cycle time TWC 1.14 1.25 1.44 ns, min
Table 23: CLB Shift Register Switching Characteristics
Description Symbol
Speed Grade
Units
–6 –5 –4
Sequential Delays
Clock CLK to X/Y outputs TREG 2.31 2.54 2.92 ns, max
Clock CLK to X/Y outputs TREG32 2.65 2.92 3.35 ns, max
Clock CLK to XB output via MC15 LUT output TREGXB 2.23 2.46 2.82 ns, max
Clock CLK to YB output via MC15 LUT output TREGYB 2.18 2.40 2.75 ns, max
Clock CLK to Shiftout TCKSH 1.92 2.11 2.43 ns, max
Clock CLK to F5 output TREGF5 2.45 2.69 3.09 ns, max
Setup and Hold Times Before/After Clock CLK
BX/BY data inputs (DIN) TSRLDS/TSRLDH 0.53/–0.07 0.58/–0.08 0.67/–0.09 ns, min
CE input (WS) TWSS/TWSH 0.19/–0.06 0.21/–0.07 0.24/–0.08 ns, min
Clock CLK
Minimum Pulse Width, High TSRPH 0.57 0.63 0.72 ns, min
Minimum Pulse Width, Low TSRPL 0.57 0.63 0.72 ns, min
Virtex-II 1.5V Field-Programmable Gate Arrays R
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Multiplier Switching Characteristics
Table 24: Multiplier Switching Characteristics
Description Symbol
Speed Grade
Units
–6 –5 –4
Propagation Delay to Output Pin
Input to Pin35 TMULT_P35 6.49 8.50 10.36 ns, max
Input to Pin34 TMULT_P34 6.36 8.33 10.14 ns, max
Input to Pin33 TMULT_P33 6.23 8.16 9.92 ns, max
Input to Pin32 TMULT_P32 6.10 7.99 9.70 ns, max
Input to Pin31 TMULT_P31 5.97 7.82 9.48 ns, max
Input to Pin30 TMULT_P30 5.84 7.65 9.26 ns, max
Input to Pin29 TMULT_P29 5.71 7.48 9.04 ns, max
Input to Pin28 TMULT_P28 5.58 7.31 8.82 ns, max
Input to Pin27 TMULT_P27 5.45 7.14 8.60 ns, max
Input to Pin26 TMULT_P26 5.32 6.97 8.38 ns, max
Input to Pin25 TMULT_P25 5.19 6.80 8.16 ns, max
Input to Pin24 TMULT_P24 5.06 6.63 7.94 ns, max
Input to Pin23 TMULT_P23 4.93 6.46 7.72 ns, max
Input to Pin22 TMULT_P22 4.80 6.29 7.50 ns, max
Input to Pin21 TMULT_P21 4.67 6.12 7.28 ns, max
Input to Pin20 TMULT_P20 4.54 5.95 7.06 ns, max
Input to Pin19 TMULT_P19 4.41 5.78 6.84 ns, max
Input to Pin18 TMULT_P18 4.28 5.61 6.62 ns, max
Input to Pin17 TMULT_P17 4.15 5.44 6.40 ns, max
Input to Pin16 TMULT_P16 4.02 5.27 6.18 ns, max
Input to Pin15 TMULT_P15 3.89 5.10 5.96 ns, max
Input to Pin14 TMULT_P14 3.76 4.93 5.74 ns, max
Input to Pin13 TMULT_P13 3.63 4.76 5.52 ns, max
Input to Pin12 TMULT_P12 3.50 4.59 5.30 ns, max
Input to Pin11 TMULT_P11 3.37 4.42 5.08 ns, max
Input to Pin10 TMULT_P10 3.24 4.25 4.86 ns, max
Input to Pin9 TMULT_P9 3.11 4.08 4.64 ns, max
Input to Pin8 TMULT_P8 2.98 3.91 4.42 ns, max
Input to Pin7 TMULT_P7 2.85 3.74 4.20 ns, max
Input to Pin6 TMULT_P6 2.72 3.57 3.98 ns, max
Input to Pin5 TMULT_P5 2.59 3.40 3.76 ns, max
Input to Pin4 TMULT_P4 2.46 3.23 3.54 ns, max
Input to Pin3 TMULT_P3 2.33 3.06 3.32 ns, max
Input to Pin2 TMULT_P2 2.20 2.89 3.10 ns, max
Input to Pin1 TMULT_P1 2.07 2.72 2.88 ns, max
Input to Pin0 TMULT_P0 1.94 2.55 2.66 ns, max
Virtex-II 1.5V Field-Programmable Gate Arrays
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Advance Product Specification 1-800-255-7778 21
Table 25: Pipelined Multiplier Switching Characteristics
Description Symbol
Speed Grade
Units–6 –5 –4
Setup and Hold Times Before/After Clock
Data Inputs TMULIDCK/TMULCKID 3.00/0.000 3.45/0.000 3.89/0.000 ns, max
Clock Enable TMULIDCK_CE/TMULCKID_CE 0.72/0.000 0.80/0.000 0.86/0.000 ns, max
Reset TMULIDCK_RST/TMULCKID_RST 0.72/0.000 0.80/0.000 0.86/0.000 ns, max
Clock to Output Pin
Clock to Pin35 TMULTCK_P35 4.11 6.91 8.11 ns, max
Clock to Pin34 TMULTCK_P34 3.98 6.75 7.92 ns, max
Clock to Pin33 TMULTCK_P33 3.86 6.59 7.74 ns, max
Clock to Pin32 TMULTCK_P32 3.73 6.43 7.55 ns, max
Clock to Pin31 TMULTCK_P31 3.60 6.27 7.37 ns, max
Clock to Pin30 TMULTCK_P30 3.47 6.11 7.18 ns, max
Clock to Pin29 TMULTCK_P29 3.34 5.95 6.99 ns, max
Clock to Pin28 TMULTCK_P28 3.22 5.79 6.81 ns, max
Clock to Pin27 TMULTCK_P27 3.09 5.63 6.62 ns, max
Clock to Pin26 TMULTCK_P26 2.96 5.47 6.44 ns, max
Clock to Pin25 TMULTCK_P25 2.83 5.31 6.25 ns, max
Clock to Pin24 TMULTCK_P24 2.70 5.15 6.06 ns, max
Clock to Pin23 TMULTCK_P23 2.58 4.99 5.88 ns, max
Clock to Pin22 TMULTCK_P22 2.45 4.83 5.69 ns, max
Clock to Pin21 TMULTCK_P21 2.32 4.67 5.51 ns, max
Clock to Pin20 TMULTCK_P20 2.19 4.51 5.32 ns, max
Clock to Pin19 TMULTCK_P19 2.06 4.35 5.13 ns, max
Clock to Pin18 TMULTCK_P18 1.94 4.19 4.95 ns, max
Clock to Pin17 TMULTCK_P17 1.81 4.03 4.76 ns, max
Clock to Pin16 TMULTCK_P16 1.68 3.87 4.58 ns, max
Clock to Pin15 TMULTCK_P15 1.68 3.71 4.39 ns, max
Clock to Pin14 TMULTCK_P14 1.68 3.55 4.20 ns, max
Clock to Pin13 TMULTCK_P13 1.68 3.39 4.02 ns, max
Clock to Pin12 TMULTCK_P12 1.68 3.23 3.83 ns, max
Clock to Pin11 TMULTCK_P11 1.68 3.07 3.65 ns, max
Clock to Pin10 TMULTCK_P10 1.68 2.91 3.46 ns, max
Clock to Pin9 TMULTCK_P9 1.68 2.75 3.27 ns, max
Clock to Pin8 TMULTCK_P8 1.68 2.59 3.09 ns, max
Clock to Pin7 TMULTCK_P7 1.68 2.43 2.90 ns, max
Clock to Pin6 TMULTCK_P6 1.68 2.27 2.72 ns, max
Clock to Pin5 TMULTCK_P5 1.68 2.11 2.53 ns, max
Clock to Pin4 TMULTCK_P4 1.68 1.95 2.34 ns, max
Clock to Pin3 TMULTCK_P3 1.68 1.79 2.16 ns, max
Clock to Pin2 TMULTCK_P2 1.68 1.63 1.97 ns, max
Clock to Pin1 TMULTCK_P1 1.68 1.47 1.79 ns, max
Clock to Pin0 TMULTCK_P0 1.68 1.31 1.60 ns, max
Virtex-II 1.5V Field-Programmable Gate Arrays R
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22 1-800-255-7778 Advance Product Specification
Block SelectRAM Switching Characteristics
TBUF Switching Characteristics
JTAG Test Access Port Switching Characteristics
Table 26: Block SelectRAM Switching Characteristics
Description Symbol
Speed Grade
Units
–6 –5 –4
Sequential Delays
Clock CLK to DOUT output TBCKO 2.10 2.31 2.65 ns, max
Setup and Hold Times Before Clock CLK
ADDR inputs TBACK/TBCKA 0.29/ 0.00 0.32/ 0.00 0.36/ 0.00 ns, min
DIN inputs TBDCK/TBCKD 0.29/ 0.00 0.32/ 0.00 0.36/ 0.00 ns, min
EN input TBECK/TBCKE 0.95/–0.46 1.04/–0.50 1.20/–0.58 ns, min
RST input TBRCK/TBCKR 1.31/–0.71 1.44/–0.78 1.65/–0.90 ns, min
WEN input TBWCK/TBCKW 0.57/–0.19 0.63/–0.21 0.72/–0.25 ns, min
Clock CLK
Minimum Pulse Width, High TBPWH 1.17 1.29 1.48 ns, min
Minimum Pulse Width, Low TBPWL 1.17 1.29 1.48 ns, min
Table 27: TBUF Switching Characteristics
Description Symbol
Speed Grade
Units
–6 –5 –4
Combinatorial Delays
IN input to OUT output TIO 0.23 0.25 0.29 ns, max
TRI input to OUT output high-impedance TOFF 0.44 0.48 0.55 ns, max
TRI input to valid data on OUT output TON 0.44 0.48 0.55 ns, max
Table 28: JTAG Test Access Port Switching Characteristics
Description Symbol Units
TMS and TDI Setup times before TCK TTAP TK 5.5 ns, min
TMS and TDI Hold times after TCK TTCKTAP 0.0 ns, min
Output delay from clock TCK to output TDO TTCKTDO 10.0 ns, max
Maximum TCK clock frequency FTCK 33 MHz, max
Virtex-II 1.5V Field-Programmable Gate Arrays
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Advance Product Specification 1-800-255-7778 23
Virtex-II Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, With DCM
Table 29: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, With DCM
Description Symbol Device
Speed Grade
Units
–6 –5 –4
LVTTL Global Clock Input to Output Delay
using Output Flip-flop, 12 mA, Fast Slew
Rate, with DCM.
For data output with different standards,
adjust the delays with the values shown in
IOB Output Switching Characteristics
Standard Adjustments, page 13.
Global Clock and OFF with DCM TICKOFDCM 2v40 2.19 2.40 2.76 ns
2v80 2.19 2.40 2.76 ns
2v250 2.19 2.40 2.76 ns
2v500 2.19 2.40 2.76 ns
2v1000 2.19 2.40 2.76 ns
2v1500 2.19 2.40 2.76 ns
2v2000 2.19 2.40 2.76 ns
2v3000 2.28 2.50 2.88 ns
2v4000 2.28 2.50 2.88 ns
2v6000 2.73 3.00 3.45 ns
2v8000 TBD TBD TBD ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
Table 1 8.
3. DCM output jitter is already included in the timing calculation.
Virtex-II 1.5V Field-Programmable Gate Arrays R
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Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM
Table 30: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM
Description Symbol Device
Speed Grade
Units
–6 –5 –4
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, without
DCM.
For data output with different standards, adjust
the delays with the values shown in IOB Output
Switching Characteristics Standard
Adjustments, page 13.
Global Clock and OFF without DCM TICKOF 2v40 4.28 4.70 4.98 ns
2v80 4.28 4.70 4.98 ns
2v250 4.50 5.00 5.75 ns
2v500 4.50 5.00 5.75 ns
2v1000 5.10 5.40 5.90 ns
2v1500 5.10 5.40 5.90 ns
2v2000 5.20 5.55 6.10 ns
2v3000 5.20 5.70 6.55 ns
2v4000 5.50 6.00 6.90 ns
2v6000 5.73 6.30 7.22 ns
2v8000 TBD TBD TBD ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
Table 1 8.
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Advance Product Specification 1-800-255-7778 25
Virtex-II Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Setup and Hold for LVTTL Standard, With DCM
Table 31: Global Clock Setup and Hold for LVTTL Standard, With DCM
Description Symbol Device
Speed Grade
Units
–6 –5 –4
Input Setup and Hold Time
Relative to Global Clock Input
Signal for LVTTL Standard.
For data input with different
standards, adjust the setup time
delay by the values shown in IOB
Input Switching
Characteristics Standard
Adjustments, page 10.
No Delay
Global Clock and IFF with DCM
TPSDCM/TPHDCM 2v40 1.60/–0.90 1.60/–0.90 1.84/–0.76 ns
2v80 1.60/–0.90 1.60/–0.90 1.84/–0.76 ns
2v250 1.60/–0.90 1.60/–0.90 1.84/–0.76 ns
2v500 1.60/–0.90 1.60/–0.90 1.84/–0.76 ns
2v1000 1.60/–0.90 1.60/–0.90 1.84/–0.76 ns
2v1500 1.60/–0.90 1.60/–0.90 1.84/–0.76 ns
2v2000 1.70/–0.90 1.70/–0.90 1.96/–0.76 ns
2v3000 1.70/–0.90 1.70/–0.90 1.96/–0.76 ns
2v4000 1.70/–0.90 1.70/–0.90 1.96/–0.76 ns
2v6000 1.70/–0.90 1.70/–0.90 1.96/–0.76 ns
2v8000 TBD TBD TBD ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. DCM output jitter is already included in the timing calculation.
Virtex-II 1.5V Field-Programmable Gate Arrays R
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Global Clock Setup and Hold for LVTTL Standard, Without DCM
,
Table 32: Global Clock Setup and Hold for LVTTL Standard, Without DCM
Description Symbol Device
Speed Grade
Units
–6 –5 –4
Input Setup and Hold Time
Relative to Global Clock Input
Signal for LVTTL Standard.
For data input with different
standards, adjust the setup time
delay by the values shown in IOB
Input Switching Characteristics
Standard Adjustments,
page 10.
Full Delay
Global Clock and IFF without
DCM
TPSFD/TPHFD 2v40 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns
2v80 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns
2v250 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns
2v500 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns
2v1000 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns
2v1500 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns
2v2000 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns
2v3000 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns
2v4000 1.92/ 0.00 1.92/ 0.00 2.21/ 0.00 ns
2v6000 1.92/ 0.46 1.92/ 0.50 2.21/ 0.50 ns
2v8000 TBD TBD TBD ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
Virtex-II 1.5V Field-Programmable Gate Arrays
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Advance Product Specification 1-800-255-7778 27
DCM Timing Parameters
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605; all devices are
100% functionally tested. Because of the difficulty in directly
measuring many internal timing parameters, those parame-
ters are derived from benchmark timing patterns. The fol-
lowing guidelines reflect worst-case values across the
recommended operating conditions. All output jitter and
phase specifications are determined through statistical
measurement at the package pins.
Operating Frequency Ranges
e
Table 33: Operating Frequency Ranges
Description Symbol Constraints
Speed Grade
Units
– 6 – 5 – 4
Output Clocks (Low Frequency Mode)
CLK0, CLK90, CLK180, CLK270 CLKOUT_FREQ_1X_LF_Min 24.00 24.00 24.00 MHz
CLKOUT_FREQ_1X_LF_Max 230.00 210.00 180.00 MHz
CLK2X, CLK2X180 CLKOUT_FREQ_2X_LF_Min 48.00 48.00 48.00 MHz
CLKOUT_FREQ_2X_LF_Max 450.00 420.00 360.00 MHz
CLKDV CLKOUT_FREQ_DV_LF_Min 1.50 1.50 1.50 MHz
CLKOUT_FREQ_DV_LF_Max 150.00 140.00 120.00 MHz
CLKFX, CLKFX180 CLKOUT_FREQ_FX_LF_Min 24.00 24.00 24.00 MHz
CLKOUT_FREQ_FX_LF_Max 260.00 240.00 210.00 MHz
Input Clocks (Low Frequency Mode)
CLKIN (using DLL outputs1) CLKIN_FREQ_DLL_LF_Min 24.00 24.00 24.00 MHz
CLKIN_FREQ_DLL_LF_Max 230.00 210.00 180.00 MHz
CLKIN (using CLKFX outputs) CLKIN_FREQ_FX_LF_Min 1.00 1.00 1.00 MHz
CLKIN_FREQ_FX_LF_Max 260.00 240.00 210.00 MHz
PSCLK PSCLK_FREQ_LF_Min 0.01 0.01 0.01 MHz
PSCLK_FREQ_LF_Max 450.00 420.00 360.00 MHz
Output Clocks (High Frequency Mode)
CLK0, CLK180 CLKOUT_FREQ_1X_HF_Min 48.00 48.00 48.00 MHz
CLKOUT_FREQ_1X_HF_Max 450.00 420.00 360.00 MHz
CLKDV CLKOUT_FREQ_DV_HF_Min 3.00 3.00 3.00 MHz
CLKOUT_FREQ_DV_HF_Max 300.00 280.00 240.00 MHz
CLKFX, CLKFX180 CLKOUT_FREQ_FX_HF_Min 210.00 210.00 210.00 MHz
CLKOUT_FREQ_FX_HF_Max 350.00 320.00 270.00 MHz
Input Clocks (High Frequency Mode)
CLKIN (using DLL outputs1) CLKIN_FREQ_DLL_HF_Min 48.00 48.00 48.00 MHz
CLKIN_FREQ_DLL_HF_Max 450.00 420.00 360.00 MHz
CLKIN (using CLKFX outputs) CLKIN_FRQ_FX_HF_Min 50.00 50.00 50.00 MHz
CLKIN_FRQ_FX_HF_Max 350.00 320.00 270.00 MHz
PSCLK PSCLK_FREQ_HF_Min 0.01 0.01 0.01 MHz
PSCLK_FREQ_HF_Max 450.00 420.00 360.00 MHz
Notes:
1. “”DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
Virtex-II 1.5V Field-Programmable Gate Arrays R
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Input Clock Tolerances
Table 34: Input Clock Tolerances
Description Symbol
Constraints
FCLKIN
Speed Grade
Units
– 6 – 5 – 4
Min Max Min Max Min Max
Input Clock Low/high Pulse Width
PSCLK PSCLK_PULSE < 1MHz 25.00 25.00 25.00 ns
CLKIN(2) CLKIN_PULSE 1 – 10 MHz 25.00 25.00 25.00 ns
10 – 25 MHz 10.00 10.00 10.00 ns
25 – 50 MHz5.005.005.00 ns
50 – 100 MHz 3.00 3.00 3.00 ns
100 – 150 MHz 2.40 2.40 2.40 ns
150 – 200 MHz 2.00 2.00 2.00 ns
200 – 250 MHz 1.80 1.80 1.80 ns
250 – 300 MHz 1.50 1.50 1.50 ns
300 – 350 MHz 1.30 1.30 1.30 ns
350 – 400 MHz 1.15 1.15 1.15 ns
> 400 MHz 1.05 1.05 1.05 ns
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
CLKIN (using DLL outputs1) CLKIN_CYC_JITT_DLL_LF ±300 ±300 ±300 ps
CLKIN (using CLKFX outputs) CLKIN_CYC_JITT_FX_LF ±300 ±300 ±300 ps
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
CLKIN (using DLL outputs1) CLKIN_CYC_JITT_DLL_HF ±150 ±150 ±150 ps
CLKIN (using CLKFX outputs) CLKIN_CYC_JITT_FX_HF ±150 ±150 ±150 ps
Input Clock Period Jitter (Low Frequency Mode)
CLKIN (using DLL outputs1) CLKIN_PER_JITT_DLL_LF ±1 ±1 ±1 ns
CLKIN (using CLKFX outputs) CLKIN_PER_JITT_FX_LF ±1 ±1 ±1 ns
Input Clock Period Jitter (High Frequency Mode)
CLKIN (using DLL outputs1) CLKIN_PER_JITT_DLL_HF ±1 ±1 ±1 ns
CLKIN (using CLKFX outputs) CLKIN_PER_JITT_FX_HF ±1 ±1 ±1 ns
Feedback Clock Path Delay Variation
CLKFB off-chip feedback CLKFB_DELAY_VAR_EXT ±1 ±1 ±1 ns
Notes:
1. “”DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. Specification also applies to PSCLK.
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Output Clock Jitter
Output Clock Phase Alignment
Table 35: Output Clock Jitter
Description Symbol Constraints
Speed Grade
Units
– 6 – 5 – 4
Clock Synthesis Period Jitter
CLK0 CLKOUT_PER_JITT_0 ±100 ±100 ±100 ps
CLK90 CLKOUT_PER_JITT_90 ±150 ±150 ±150 ps
CLK180 CLKOUT_PER_JITT_180 ±150 ±150 ±150 ps
CLK270 CLKOUT_PER_JITT_270 ±150 ±150 ±150 ps
CLK2X, CLK2X180 CLKOUT_PER_JITT_2X ±200 ±200 ±200 ps
CLKDV (integer division) CLKOUT_PER_JITT_DV1 ±150 ±150 ±150 ps
CLKDV (non-integer division) CLKOUT_PER_JITT_DV2 ±300 ±300 ±300 ps
CLKFX, CLKFX180 CLKOUT_PER_JITT_FX Note 1 Note 1 Note 1 ps
Notes:
1. Values for this parameter are available on www.xilinx.com.
Table 36: Output Clock Phase Alignment
Description Symbol Constraints
Speed Grade
Units
– 6 – 5 – 4
Phase Offset Between CLKIN and CLKFB
CLKIN/CLKFB CLKIN_CLKFB_PHASE ±50 ±50 ±50 ps
Phase Offset Between Any DCM Outputs
All CLK* outputs CLKOUT_PHASE ±140 ±140 ±140 ps
Duty Cycle Precision
DLL outputs(1) CLKOUT_DUTY_CYCLE_DLL ±150 ±150 ±150 ps
CLKFX outputs CLKOUT_DUTY_CYCLE_FX ±100 ±100 ±100 ps
Notes:
1. “”DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. Specification also applies to PSCLK.
Virtex-II 1.5V Field-Programmable Gate Arrays R
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30 1-800-255-7778 Advance Product Specification
Miscellaneous Timing Parameters
Frequency Synthesis
Parameter Cross Reference
Table 37: Miscellaneous Timing Parameters
Description Symbol
Constraints
FCLKIN Speed Grade Units
– 6 – 5 – 4
Time Required to Achieve LOCK
Using DLL outputs(1) LOCK_DLL
LOCK_DLL_60 > 60MHz 20.0 20.0 20.0
m
s
LOCK_DLL_50_60 50 - 60 MHz 25.0 25.0 25.0
m
s
LOCK_DLL_40_50 40 - 50 MHz 50.0 50.0 50.0
m
s
LOCK_DLL_30_40 30 - 40 MHz 90.0 90.0 90.0
m
s
LOCK_DLL_24_30 24 - 30 MHz 120.0 120.0 120.0
m
s
Using CLKFX outputs LOCK_FX_MIN 10.0 10.0 10.0 ms
LOCK_FX_MAX 10.0 10.0 10.0 ms
Additional lock time with
fine-phase shifting LOCK_DLL_FINE_SHIFT 50.0 50.0 50.0
m
s
Fine-Phase Shifting
Absolute shifting range FINE_SHIFT_RANGE 10.0 10.0 10.0 ns
Delay Lines
Tap delay resolution DCM_TAP_MIN 30.0 30.0 30.0 ps
DCM_TAP_MAX 60.0 60.0 60.0 ps
Notes:
1. “”DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. Specification also applies to PSCLK.
Table 38: Frequency Synthesis
Attribute Min Max
CLKFX_MULTIPLY 2 32
CLKFX_DIVIDE 1 32
Table 39: Parameter Cross Reference
Libraries Guide Data Sheet
DLL_CLKOUT_{MIN|MAX}_LF CLKOUT_FREQ_{1X|2X|DV}_LF
DFS_CLKOUT_{MIN|MAX}_LF CLKOUT_FREQ_FX_LF
DLL_CLKIN_{MIN|MAX}_LF CLKIN_FREQ_DLL_LF
DFS_CLKIN_{MIN|MAX}_LF CLKIN_FREQ_FX_LF
DLL_CLKOUT_{MIN|MAX}_HF CLKOUT_FREQ_{1X|DV}_HF
DFS_CLKOUT_{MIN|MAX}_HF CLKOUT_FREQ_FX_HF
DLL_CLKIN_{MIN|MAX}_HF CLKIN_FREQ_DLL_HF
DFS_CLKIN_{MIN|MAX}_HF CLKIN_FREQ_FX_HF
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Revision History
This section records the change history for this module of the data sheet.
Virtex-II Data Sheet
The Virtex-II Data Sheet contains the following modules:
•DS031-1, Virtex-II 1.5V FPGAs: Introduction and
Ordering Information (Module 1)
•DS031-2, Virtex-II 1.5V FPGAs: Functional Description
(Module 2)
•DS031-3, Virtex-II 1.5V FPGAs: DC and Switching
Characteristics (Module 3)
•DS031-4, Virtex-II 1.5V FPGAs: Pinout Tables
(Module 4)
Date Version Revision
11/07/00 1.0 Early access draft.
12/06/00 1.1 Initial release.
01/15/01 1.2 Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II
Switching Characteristics sections.
01/25/01 1.3 •The data sheet was divided into four modules (per the current style standard).
•Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables.
•Table 18, “Delay Measurement Methodology,” on page 16
04/23/01 1.5 •Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables.
•Added TREG32 symbol to Table 23.
•Skipped v1.4 to sync with other modules. Reverted to traditional double-column format.
07/30/01 1.6 •Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables.
•Added values to the Virtex-II Pin-to-Pin Output Parameter Guidelines and Virtex-II
Pin-to-Pin Input Parameter Guidelines tables.
•Added Frequency Synthesis table.
10/02/01 1.7 •Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables.
•Updated the speed grade designations used in data sheets, and added Table 13, which
shows the current speed grade designation for each device.
10/05/01 1.8 •Corrected the speed grade designation for the XC2V1000 device in Table 13.
10/12/01 1.9 •Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables.
11/28/01 2.0 •Updated values in Table 3, Tabl e 4, Table 5, Virtex-II Performance Characteristics,
and Virtex-II Switching Characteristics tables.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 1
This document provides Virtex®-II Device/Package Combinations and Maximum I/Os Available and Virtex-II Pin
Definitions, followed by pinout tables for the following packages:
•CS144 Chip-Scale BGA Package
•FG256 Fine-Pitch BGA Package
•FG456 Fine-Pitch BGA Package
•FG676 Fine-Pitch BGA Package
•BG575 Standard BGA Package
•BG728 Standard BGA Package
•FF896 Flip-Chip Fine-Pitch BGA Package
•FF1152 Flip-Chip Fine-Pitch BGA Package
•FF1517 Flip-Chip Fine-Pitch BGA Package
•BF957 Flip-Chip BGA Package
Virtex®-II Device/Package
Combinations and Maximum I/Os
Available
Wire-bond and flip-chip packages are available. Table 1 and
Table 2 show the maximum number of user I/Os possible in
wire-bond and flip-chip packages, respectively.
Table 3 shows the number of user I/Os available for all
device/package combinations.
• CS denotes wire-bond chip-scale ball grid array (BGA)
(0.80 mm pitch).
• FG denotes wire-bond fine-pitch BGA (1.00 mm pitch).
• FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).
• BG denotes standard BGA (1.27 mm pitch).
• BF denotes flip-chip BGA (1.27 mm pitch).
The number of I/Os per package include all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
DXP, AND RSVD).
0Virtex-II 1.5V
Field-Programmable Gate Arrays
Pinout Information
DS031-4 (v1.6) November 7, 2001 00Advance Product Specification
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Table 1: Wire-Bond Packages Information
Package CS144 FG256 FG456 FG676 BG575 BG728
Pitch (mm) 0.80 1.00 1.00 1.00 1.27 1.27
Size (mm) 12 x 12 17 x 17 23 x 23 27 x 27 31 x 31 35 x 35
I/Os 92 172 324 484 408 516
Table 2: Flip-Chip Packages Information
Package FF896 FF1152 FF1517 BF957
Pitch (mm) 1.00 1.00 1.00 1.27
Size (mm) 31 x 31 35 x 35 40 x 40 40 x 40
I/Os 624 824 1,108 684
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Virtex-II Pin Definitions
This section describes the pinouts for Virtex-II devices in the
following packages:
•CS144: wire-bond chip-scale ball grid array (BGA) of
0.80 mm pitch
•FG256, FG456, and FG676: wire-bond fine-pitch BGA
of 1.00 mm pitch
•FF896, FF1152, FF1517: flip-chip fine-pitch BGA of
1.00 mm pitch
•BG575 and BG728: wire-bond BGA of 1.27 mm pitch
•BF957: flip-chip BGA of 1.27 mm pitch
All of the devices supported in a particular package are
pinout compatible and are listed in the same table (one
table per package). In addition, the FG456 and FG676
packages are compatible, as are the FF896 and FF1152
packages. Pins that are not available for the smallest
devices are listed in right-hand columns.
Each device is split into eight I/O banks to allow for flexibility
in the choice of I/O standards (see the Virtex-II Data Sheet).
Global pins, including JTAG, configuration, and
power/ground pins, are listed at the end of each table.
Table 4 provides definitions for all pin types.
The FG256 pinouts (Table 6) is included as an example. All
Virtex-II pinout tables are available on the distribution
CD-ROM, or on the web (at http://www.xilinx.com).
Table 3: Virtex-II Device/Package Combinations and Maximum Number of Available I/Os
Package
Available I/Os
XC2V
40
XC2V
80
XC2V
250
XC2V
500
XC2V
1000
XC2V
1500
XC2V
2000
XC2V
3000
XC2V
4000
XC2V
6000
XC2V
8000
CS144 88 92 92
FG256 88 120 172 172 172
FG456 200 264 324
FG676 392 456 484
FF896 432 528 624
FF1152 720 824 824 824
FF1517 912 1,104 1,108
BG575 328 392 408
BG728 456 516
BF957 624 684 684 684 684
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Pin Definitions
Table 4 provides a description of each pin type listed in Virtex-II pinout tables.
Table 4: Virtex-II Pin Definitions
Pin Name Direction Description
User I/O Pins
IO_LXXY_# Input/Output All user I/O pins are capable of differential signalling and can implement LVDS, ULVDS,
BLVDS, or LDT pairs. Each user I/O is labeled “IO_LXXY_#”, where:
IO indicates a user I/O pin.
LXXY indicates a differential pair, with XX a unique pair in the bank and Y = P/N for
the positive and negative sides of the differential pair.
# indicates the bank number (0 through 7)
Dual-Function Pins
IO_LXXY_#/ZZZ The dual-function pins are labelled “IO_LXXY_#/ZZZ”, where ZZZ can be one of the
following pins:
Per Bank - VRP, VRN, or VREF
Globally - GCLKX(S/P), BUSY/DOUT, INIT_B, DIN/D0 – D7, RDWR_B, or CS_B
With /ZZZ:
DIN / D0, D1, D2,
D3, D4, D5, D6,
D7
Input/Output In SelectMAP mode, D0 through D7 are configuration data pins. These pins become
user I/Os after configuration, unless the SelectMAP port is retained.
In bit-serial modes, DIN (D0) is the single-data input. This pin becomes a user I/O after
configuration.
CS_B Input In SelectMAP mode, this is the active-low Chip Select signal. The pin becomes a user
I/O after configuration, unless the SelectMAP port is retained.
RDWR_B Input In SelectMAP mode, this is the active-low Write Enable signal. The pin becomes a user
I/O after configuration, unless the SelectMAP port is retained.
BUSY/DOUT Output In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. The
pin becomes a user I/O after configuration, unless the SelectMAP port is retained.
In bit-serial modes, DOUT provides preamble and configuration data to downstream
devices in a daisy-chain. The pin becomes a user I/O after configuration.
INIT_B Bidirectional
(open-drain)
When Low, this pin indicates that the configuration memory is being cleared. When held
Low, the start of configuration is delayed. During configuration, a Low on this output
indicates that a configuration data error has occurred. The pin becomes a user I/O after
configuration.
GCLKx (S/P) Input These are clock input pins that connect to Global Clock Buffers. These pins become
regular user I/Os when not needed for clocks.
VRP Input This pin is for the DCI voltage reference resistor of P transistor (per bank).
VRN Input This pin is for the DCI voltage reference resistor of N transistor (per bank).
ALT_VRP Input This is the alternative pin for the DCI voltage reference resistor of P transistor.
ALT_VRN Input This is the alternative pin for the DCI voltage reference resistor of N transistor.
VREF Input These are input threshold voltage pins. They become user I/Os when an external
threshold voltage is not needed (per bank).
Dedicated Pins(1)
CCLK Input/Output Configuration clock. Output in Master mode or Input in Slave mode.
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PROG_B Input Active Low asynchronous reset to configuration logic. This pin has a permanent weak
pull-up resistor.
DONE Input/Output DONE is a bidirectional signal with an optional internal pull-up resistor. As an output,
this pin indicates completion of the configuration process. As an input, a Low level on
DONE can be configured to delay the start-up sequence.
M2, M1, M0 Input Configuration mode selection.
HSWAP_EN Input Enable I/O pullups during configuration.
TCK Input Boundary Scan Clock.
TDI Input Boundary Scan Data Input.
TDO Output Boundary Scan Data Output.
TMS Input Boundary Scan Mode Select.
PWRDWN_B Input Power down pin.
Other Pins
DXN, DXP N/A Temperature-sensing diode pins (Anode: DXP, Cathode: DXN).
VBATT Input Decryptor key memory backup supply. (Do not connect if battery is not used.)
RSVD N/A Reserved pin - do not connect.
VCCO Input Power-supply pins for the output drivers (per bank).
VCCAUX Input Power-supply pins for auxiliary circuits.
VCCINT Input Power-supply pins for the internal core logic.
GND Input Ground.
Notes:
1. All dedicated pins (JTAG and configuration) are powered by VCCAUX (independent of the bank VCCO voltage).
Table 4: Virtex-II Pin Definitions (Continued)
Pin Name Direction Description
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
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CS144 Chip-Scale BGA Package
As shown in Table 5, XC2V40, XC2V80, and XC2V250 Virtex-II devices are available in the CS144 package. Pins in the
XC2V40, XC2V80, and XC2V250 devices are the same except for pin differences in the XC2V40 device, shown in the No
Connect column. Following this table are the CS144 Chip-Scale BGA Package Specifications (0.80mm pitch).
Table 5: CS144 — XC2V40, XC2V80, and XC2V250
Bank Pin Description Pin Number No Connect in the XC2V40
0 IO_L01N_0 B3
0 IO_L01P_0 A3
0 IO_L02N_0 C4
0 IO_L02P_0 B4
0 IO_L03N_0/VRP_0 A4
0 IO_L03P_0/VRN_0 D5
0 IO_L94N_0/VREF_0 A5
0 IO_L94P_0 D6
0 IO_L95N_0/GCLK7P C6
0 IO_L95P_0/GCLK6S B6
0 IO_L96N_0/GCLK5P A6
0 IO_L96P_0/GCLK4S D7
1 IO_L96N_1/GCLK3P A7
1 IO_L96P_1/GCLK2S B7
1 IO_L95N_1/GCLK1P A8
1 IO_L95P_1/GCLK0S B8
1 IO_L94N_1 C8
1 IO_L94P_1/VREF_1 D8
1 IO_L03N_1/VRP_1 C9
1 IO_L03P_1/VRN_1 D9
1 IO_L02N_1 A10
1 IO_L02P_1 B10
1 IO_L01N_1 C10
1 IO_L01P_1 D10
2 IO_L01N_2 C13
2 IO_L01P_2 D11
2 IO_L02N_2/VRP_2 D12
2 IO_L02P_2/VRN_2 D13
2 IO_L03N_2 E10
2 IO_L03P_2/VREF_2 E11
2 IO_L93N_2 E13 NC
2 IO_L93P_2/VREF_2 F11 NC
2 IO_L94N_2 F12
2 IO_L94P_2 G10
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2 IO_L96N_2 G11
2 IO_L96P_2 G13
3 IO_L96N_3 G12
3 IO_L96P_3 H12
3 IO_L94N_3 H11
3 IO_L94P_3 J13
3 IO_L03N_3/VREF_3 J10
3 IO_L03P_3 K13
3 IO_L02N_3/VRP_3 K12
3 IO_L02P_3/VRN_3 K11
3 IO_L01N_3 K10
3 IO_L01P_3 L13
4 IO_L01N_4/DOUT M11
4 IO_L01P_4/INIT_B N11
4 IO_L02N_4/D0 L10
4 IO_L02P_4/D1 M10
4 IO_L03N_4/D2/ALT_VRP_4 N10
4 IO_L03P_4/D3/ALT_VRN_4 K9
4 IO_L94N_4/VREF_4 N9
4 IO_L94P_4 K8
4 IO_L95N_4/GCLK3S L8
4 IO_L95P_4/GCLK2P M8
4 IO_L96N_4/GCLK1S N8
4 IO_L96P_4/GCLK0P K7
5 IO_L96N_5/GCLK7S N7
5 IO_L96P_5/GCLK6P M7
5 IO_L95N_5/GCLK5S N6
5 IO_L95P_5/GCLK4P M6
5 IO_L94N_5 L6
5 IO_L94P_5/VREF_5 K6
5 IO_L03N_5/D4/ALT_VRP_5 L5
5 IO_L03P_5/D5/ALT_VRN_5 K5
5 IO_L02N_5/D6 N4
5 IO_L02P_5/D7 M4
5 IO_L01N_5/RDWR_B L4
5 IO_L01P_5/CS_B K4
Table 5: CS144 — XC2V40, XC2V80, and XC2V250
Bank Pin Description Pin Number No Connect in the XC2V40
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6 IO_L01P_6 L3
6 IO_L01N_6 L2
6 IO_L02P_6/VRN_6 L1
6 IO_L02N_6/VRP_6 K3
6 IO_L03P_6 K2
6 IO_L03N_6/VREF_6 K1
6 IO_L94P_6 J2
6 IO_L94N_6 H4
6 IO_L96P_6 H3
6 IO_L96N_6 H1
7 IO_L96P_7 G4
7 IO_L96N_7 G3
7 IO_L94P_7 G1
7 IO_L94N_7 F1
7 IO_L93P_7/VREF_7 F2 NC
7 IO_L93N_7 F4 NC
7 IO_L03P_7/VREF_7 E2
7 IO_L03N_7 E3
7 IO_L02P_7/VRN_7 E4
7 IO_L02N_7/VRP_7 D1
7 IO_L01P_7 D2
7 IO_L01N_7 D3
0 VCCO_0 B5
0 VCCO_0 C3
1 VCCO_1 A11
1 VCCO_1 A9
2 VCCO_2 F10
2 VCCO_2 C12
3 VCCO_3 L12
3 VCCO_3 J12
4 VCCO_4 M9
4 VCCO_4 L11
5 VCCO_5 N3
5 VCCO_5 N5
6 VCCO_6 J3
6 VCCO_6 M1
7 VCCO_7 D4
7 VCCO_7 F3
Table 5: CS144 — XC2V40, XC2V80, and XC2V250
Bank Pin Description Pin Number No Connect in the XC2V40
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8 1-800-255-7778 Advance Product Specification
NA CCLK M13
NA PROG_B B1
NA DONE N12
NA M0 N2
NA M1 M2
NA M2 M3
NA TCK B12
NA TDI C1
NA TDO C11
NA TMS A13
NA PWRDWN_B M12
NA HSWAP_EN A1
NA RSVD A2
NA RSVD B2
NA VBATT A12
NA RSVD B11
NA VCCAUX C2
NA VCCAUX N1
NA VCCAUX N13
NA VCCAUX B13
NA VCCINT H2
NA VCCINT L7
NA VCCINT H13
NA VCCINT C7
NA GND E1
NA GND G2
NA GND J1
NA GND J4
NA GND M5
NA GND L9
NA GND J11
NA GND H10
NA GND F13
NA GND E12
NA GND B9
NA GND C5
Table 5: CS144 — XC2V40, XC2V80, and XC2V250
Bank Pin Description Pin Number No Connect in the XC2V40
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FG256 Fine-Pitch BGA Package
As shown in Tabl e 6 , XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Virtex-II devices are available in the FG256
fine-pitch BGA package. The pins in the XC2V250, XC2V500, and XC2V1000 devices are same. The No Connect columns
show pin differences for the XC2V40 and XC2V80 devices. Following this table are the FG256 Fine-Pitch BGA Package
Specifications (1.00mm pitch).
Table 6: FG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V40 No Connect in XC2V80
0 IO_L01N_0 C4
0 IO_L01P_0 B4
0 IO_L02N_0 D5
0 IO_L02P_0 C5
0 IO_L03N_0/VRP_0 B5
0 IO_L03P_0/VRN_0 A5
0 IO_L04N_0/VREF_0 D6 NC NC
0 IO_L04P_0 C6 NC NC
0 IO_L05N_0 B6 NC NC
0 IO_L05P_0 A6 NC NC
0 IO_L92N_0 E6 NC NC
0 IO_L92P_0 E7 NC NC
0 IO_L93N_0 D7 NC NC
0 IO_L93P_0 C7 NC NC
0 IO_L94N_0/VREF_0 B7
0 IO_L94P_0 A7
0 IO_L95N_0/GCLK7P D8
0 IO_L95P_0/GCLK6S C8
0 IO_L96N_0/GCLK5P B8
0 IO_L96P_0/GCLK4S A8
1 IO_L96N_1/GCLK3P A9
1 IO_L96P_1/GCLK2S B9
1 IO_L95N_1/GCLK1P C9
1 IO_L95P_1/GCLK0S D9
1 IO_L94N_1 A10
1 IO_L94P_1/VREF_1 B10
1 IO_L93N_1 C10 NC NC
1 IO_L93P_1 D10 NC NC
1 IO_L92N_1 E10 NC NC
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1 IO_L92P_1 E11 NC NC
1 IO_L05N_1 A11 NC NC
1 IO_L05P_1 B11 NC NC
1 IO_L04N_1 C11 NC NC
1 IO_L04P_1/VREF_1 D11 NC NC
1 IO_L03N_1/VRP_1 A12
1 IO_L03P_1/VRN_1 B12
1 IO_L02N_1 C12
1 IO_L02P_1 D12
1 IO_L01N_1 B13
1 IO_L01P_1 C13
2 IO_L01N_2 C16
2 IO_L01P_2 D16
2 IO_L02N_2/VRP_2 D14
2 IO_L02P_2/VRN_2 D15
2 IO_L03N_2 E13
2 IO_L03P_2/VREF_2 E14
2 IO_L04N_2 E15 NC
2 IO_L04P_2 E16 NC
2 IO_L06N_2 F13 NC
2 IO_L06P_2 F14 NC
2 IO_L43N_2 F15 NC NC
2 IO_L43P_2 F16 NC NC
2 IO_L45N_2 F12 NC NC
2 IO_L45P_2/VREF_2 G12 NC NC
2 IO_L91N_2 G13 NC
2 IO_L91P_2 G14 NC
2 IO_L93N_2 G15 NC
2 IO_L93P_2/VREF_2 G16 NC
2 IO_L94N_2 H13
2 IO_L94P_2 H14
2 IO_L96N_2 H15
2 IO_L96P_2 H16
Table 6: FG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V40 No Connect in XC2V80
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
12 1-800-255-7778 Advance Product Specification
3 IO_L96N_3 J16
3 IO_L96P_3 J15
3 IO_L94N_3 J14
3 IO_L94P_3 J13
3 IO_L93N_3/VREF_3 K16 NC
3 IO_L93P_3 K15 NC
3 IO_L91N_3 K14 NC
3 IO_L91P_3 K13 NC
3 IO_L45N_3/VREF_3 K12 NC NC
3 IO_L45P_3 L12 NC NC
3 IO_L43N_3 L16 NC NC
3 IO_L43P_3 L15 NC NC
3 IO_L06N_3 L14 NC
3 IO_L06P_3 L13 NC
3 IO_L04N_3 M16 NC
3 IO_L04P_3 M15 NC
3 IO_L03N_3/VREF_3 M14
3 IO_L03P_3 M13
3 IO_L02N_3/VRP_3 N15
3 IO_L02P_3/VRN_3 N14
3 IO_L01N_3 N16
3 IO_L01P_3 P16
4 IO_L01N_4/DOUT T14
4 IO_L01P_4/INIT_B T13
4 IO_L02N_4/D0 P13
4 IO_L02P_4/D1 R13
4 IO_L03N_4/D2/ALT_VRP_4 N12
4 IO_L03P_4/D3/ALT_VRN_4 P12
4 IO_L04N_4/VREF_4 R12 NC NC
4 IO_L04P_4 T12 NC NC
4 IO_L05N_4/VRP_4 N11 NC NC
4 IO_L05P_4/VRN_4 P11 NC NC
Table 6: FG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V40 No Connect in XC2V80
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 13
4 IO_L91N_4/VREF_4 R11 NC NC
4 IO_L91P_4 T11 NC NC
4 IO_L92N_4 M11 NC NC
4 IO_L92P_4 M10 NC NC
4 IO_L93N_4 N10 NC NC
4 IO_L93P_4 P10 NC NC
4 IO_L94N_4/VREF_4 R10
4 IO_L94P_4 T10
4 IO_L95N_4/GCLK3S N9
4 IO_L95P_4/GCLK2P P9
4 IO_L96N_4/GCLK1S R9
4 IO_L96P_4/GCLK0P T9
5 IO_L96N_5/GCLK7S T8
5 IO_L96P_5/GCLK6P R8
5 IO_L95N_5/GCLK5S P8
5 IO_L95P_5/GCLK4P N8
5 IO_L94N_5 T7
5 IO_L94P_5/VREF_5 R7
5 IO_L93N_5 P7 NC NC
5 IO_L93P_5 N7 NC NC
5 IO_L92N_5 M7 NC NC
5 IO_L92P_5 M6 NC NC
5 IO_L91N_5 T6 NC NC
5 IO_L91P_5/VREF_5 R6 NC NC
5 IO_L05N_5/VRP_5 P6 NC NC
5 IO_L05P_5/VRN_5 N6 NC NC
5 IO_L04N_5 T5 NC NC
5 IO_L04P_5/VREF_5 R5 NC NC
5 IO_L03N_5/D4/ALT_VRP_5 P5
5 IO_L03P_5/D5/ALT_VRN_5 N5
5 IO_L02N_5/D6 R4
5 IO_L02P_5/D7 P4
5 IO_L01N_5/RDWR_B T4
Table 6: FG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V40 No Connect in XC2V80
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
14 1-800-255-7778 Advance Product Specification
5 IO_L01P_5/CS_B T3
6 IO_L01P_6 P1
6 IO_L01N_6 N1
6 IO_L02P_6/VRN_6 N3
6 IO_L02N_6/VRP_6 N2
6 IO_L03P_6 M4
6 IO_L03N_6/VREF_6 M3
6 IO_L04P_6 M2 NC
6 IO_L04N_6 M1 NC
6 IO_L06P_6 L4 NC
6 IO_L06N_6 L3 NC
6 IO_L43P_6 L2 NC NC
6 IO_L43N_6 L1 NC NC
6 IO_L45P_6 L5 NC NC
6 IO_L45N_6/VREF_6 K5 NC NC
6 IO_L91P_6 K4 NC
6 IO_L91N_6 K3 NC
6 IO_L93P_6 K2 NC
6 IO_L93N_6/VREF_6 K1 NC
6 IO_L94P_6 J4
6 IO_L94N_6 J3
6 IO_L96P_6 J2
6 IO_L96N_6 J1
7 IO_L96P_7 H1
7 IO_L96N_7 H2
7 IO_L94P_7 H3
7 IO_L94N_7 H4
7 IO_L93P_7/VREF_7 G1 NC
7 IO_L93N_7 G2 NC
7 IO_L91P_7 G3 NC
7 IO_L91N_7 G4 NC
7 IO_L45P_7/VREF_7 G5 NC NC
Table 6: FG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V40 No Connect in XC2V80
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 15
7 IO_L45N_7 F5 NC NC
7 IO_L43P_7 F1 NC NC
7 IO_L43N_7 F2 NC NC
7 IO_L06P_7 F3 NC
7 IO_L06N_7 F4 NC
7 IO_L04P_7 E1 NC
7 IO_L04N_7 E2 NC
7 IO_L03P_7/VREF_7 E3
7 IO_L03N_7 E4
7 IO_L02P_7/VRN_7 D2
7 IO_L02N_7/VRP_7 D3
7 IO_L01P_7 D1
7 IO_L01N_7 C1
0 VCCO_0 F8
0 VCCO_0 F7
0 VCCO_0 E8
1 VCCO_1 F10
1 VCCO_1 F9
1 VCCO_1 E9
2 VCCO_2 H12
2 VCCO_2 H11
2 VCCO_2 G11
3 VCCO_3 K11
3 VCCO_3 J12
3 VCCO_3 J11
4 VCCO_4 M9
4 VCCO_4 L10
4 VCCO_4 L9
5 VCCO_5 M8
5 VCCO_5 L8
5 VCCO_5 L7
6 VCCO_6 K6
6 VCCO_6 J6
Table 6: FG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V40 No Connect in XC2V80
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
16 1-800-255-7778 Advance Product Specification
6 VCCO_6 J5
7 VCCO_7 H6
7 VCCO_7 H5
7 VCCO_7 G6
NA CCLK P15
NA PROG_B A2
NA DONE R14
NA M0 T2
NA M1 P2
NA M2 R3
NA HSWAP_EN B3
NA TCK A15
NA TDI C2
NA TDO C15
NA TMS B14
NA PWRDWN_B T15
NA RSVD A4
NA RSVD A3
NA VBATT A14
NA RSVD A13
NA VCCAUX R16
NA VCCAUX R1
NA VCCAUX B16
NA VCCAUX B1
NA VCCINT N13
NA VCCINT N4
NA VCCINT M12
NA VCCINT M5
NA VCCINT E12
NA VCCINT E5
NA VCCINT D13
NA VCCINT D4
Table 6: FG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V40 No Connect in XC2V80
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 17
NA GND T16
NA GND T1
NA GND R15
NA GND R2
NA GND P14
NA GND P3
NA GND L11
NA GND L6
NA GND K10
NA GND K9
NA GND K8
NA GND K7
NA GND J10
NA GND J9
NA GND J8
NA GND J7
NA GND H10
NA GND H9
NA GND H8
NA GND H7
NA GND G10
NA GND G9
NA GND G8
NA GND G7
NA GND F11
NA GND F6
NA GND C14
NA GND C3
NA GND B15
NA GND B2
NA GND A16
NA GND A1
Table 6: FG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V40 No Connect in XC2V80
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 19
FG456 Fine-Pitch BGA Package
As shown in Table 7, XC2V250, XC2V500, and XC2V1000 Virtex-II devices are available in the FG456 fine-pitch BGA
package. Pins in the XC2V250, XC2V500, and XC2V1000 devices are the same, except for the pin differences in the
XC2V250 and XC2V500 devices shown in the No Connect columns. Following this table are the FG456 Fine-Pitch BGA
Package Specifications (1.00mm pitch).
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500
0 IO_L01N_0 B4
0 IO_L01P_0 A4
0 IO_L02N_0 C4
0 IO_L02P_0 C5
0 IO_L03N_0/VRP_0 B5
0 IO_L03P_0/VRN_0 A5
0 IO_L04N_0/VREF_0 D6
0 IO_L04P_0 C6
0 IO_L05N_0 B6
0 IO_L05P_0 A6
0 IO_L06N_0 E7
0 IO_L06P_0 E8
0 IO_L21N_0 D7 NC NC
0 IO_L21P_0/VREF_0 C7 NC NC
0 IO_L22N_0 B7 NC NC
0 IO_L22P_0 A7 NC NC
0 IO_L24N_0 D8 NC NC
0 IO_L24P_0 C8 NC NC
0 IO_L49N_0 B8 NC
0 IO_L49P_0 A8 NC
0 IO_L51N_0 E9 NC
0 IO_L51P_0/VREF_0 F9 NC
0 IO_L52N_0 D9 NC
0 IO_L52P_0 C9 NC
0 IO_L54N_0 B9 NC
0 IO_L54P_0 A9 NC
0 IO_L91N_0/VREF_0 E10
0 IO_L91P_0 F10
0 IO_L92N_0 D10
0 IO_L92P_0 C10
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
20 1-800-255-7778 Advance Product Specification
0 IO_L93N_0 B10
0 IO_L93P_0 A10
0 IO_L94N_0/VREF_0 E11
0 IO_L94P_0 F11
0 IO_L95N_0/GCLK7P D11
0 IO_L95P_0/GCLK6S C11
0 IO_L96N_0/GCLK5P B11
0 IO_L96P_0/GCLK4S A11
1 IO_L96N_1/GCLK3P F12
1 IO_L96P_1/GCLK2S F13
1 IO_L95N_1/GCLK1P E12
1 IO_L95P_1/GCLK0S D12
1 IO_L94N_1 C12
1 IO_L94P_1/VREF_1 B12
1 IO_L93N_1 A13
1 IO_L93P_1 B13
1 IO_L92N_1 C13
1 IO_L92P_1 D13
1 IO_L91N_1 E13
1 IO_L91P_1/VREF_1 E14
1 IO_L54N_1 A14 NC
1 IO_L54P_1 B14 NC
1 IO_L52N_1 C14 NC
1 IO_L52P_1 D14 NC
1 IO_L51N_1/VREF_1 A15 NC
1 IO_L51P_1 B15 NC
1 IO_L49N_1 C15 NC
1 IO_L49P_1 D15 NC
1 IO_L24N_1 F14 NC NC
1 IO_L24P_1 E15 NC NC
1 IO_L22N_1 A16 NC NC
1 IO_L22P_1 B16 NC NC
1 IO_L21N_1/VREF_1 C16 NC NC
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 21
1 IO_L21P_1 D16 NC NC
1 IO_L06N_1 E16
1 IO_L06P_1 E17
1 IO_L05N_1 A17
1 IO_L05P_1 B17
1 IO_L04N_1 C17
1 IO_L04P_1/VREF_1 D17
1 IO_L03N_1/VRP_1 A18
1 IO_L03P_1/VRN_1 B18
1 IO_L02N_1 C18
1 IO_L02P_1 D18
1 IO_L01N_1 A19
1 IO_L01P_1 B19
2 IO_L01N_2 C21
2 IO_L01P_2 C22
2 IO_L02N_2/VRP_2 E18
2 IO_L02P_2/VRN_2 F18
2 IO_L03N_2 D21
2 IO_L03P_2/VREF_2 D22
2 IO_L04N_2 E19
2 IO_L04P_2 E20
2 IO_L06N_2 E21
2 IO_L06P_2 E22
2 IO_L19N_2 F19 NC NC
2 IO_L19P_2 F20 NC NC
2 IO_L21N_2 F21 NC NC
2 IO_L21P_2/VREF_2 F22 NC NC
2 IO_L22N_2 G18 NC NC
2 IO_L22P_2 H18 NC NC
2 IO_L24N_2 G19 NC NC
2 IO_L24P_2 G20 NC NC
2 IO_L43N_2 G21
2 IO_L43P_2 G22
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
22 1-800-255-7778 Advance Product Specification
2 IO_L45N_2 H19
2 IO_L45P_2/VREF_2 H20
2 IO_L46N_2 H21
2 IO_L46P_2 H22
2 IO_L48N_2 J17
2 IO_L48P_2 J18
2 IO_L49N_2 J19 NC
2 IO_L49P_2 J20 NC
2 IO_L51N_2 J21 NC
2 IO_L51P_2/VREF_2 J22 NC
2 IO_L52N_2 K17 NC
2 IO_L52P_2 K18 NC
2 IO_L54N_2 K19 NC
2 IO_L54P_2 K20 NC
2 IO_L91N_2 K21
2 IO_L91P_2 K22
2 IO_L93N_2 L17
2 IO_L93P_2/VREF_2 L18
2 IO_L94N_2 L19
2 IO_L94P_2 L20
2 IO_L96N_2 L21
2 IO_L96P_2 L22
3 IO_L96N_3 M21
3 IO_L96P_3 M20
3 IO_L94N_3 M19
3 IO_L94P_3 M18
3 IO_L93N_3/VREF_3 M17
3 IO_L93P_3 N17
3 IO_L91N_3 N22
3 IO_L91P_3 N21
3 IO_L54N_3 N20 NC
3 IO_L54P_3 N19 NC
3 IO_L52N_3 N18 NC
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 23
3 IO_L52P_3 P18 NC
3 IO_L51N_3/VREF_3 P22 NC
3 IO_L51P_3 P21 NC
3 IO_L49N_3 P20 NC
3 IO_L49P_3 P19 NC
3 IO_L48N_3 R22
3 IO_L48P_3 R21
3 IO_L46N_3 R20
3 IO_L46P_3 R19
3 IO_L45N_3/VREF_3 R18
3 IO_L45P_3 P17
3 IO_L43N_3 T22
3 IO_L43P_3 T21
3 IO_L24N_3 T20 NC NC
3 IO_L24P_3 T19 NC NC
3 IO_L22N_3 U22 NC NC
3 IO_L22P_3 U21 NC NC
3 IO_L21N_3/VREF_3 U20 NC NC
3 IO_L21P_3 U19 NC NC
3 IO_L19N_3 T18 NC NC
3 IO_L19P_3 U18 NC NC
3 IO_L06N_3 V22
3 IO_L06P_3 V21
3 IO_L04N_3 V20
3 IO_L04P_3 V19
3 IO_L03N_3/VREF_3 W22
3 IO_L03P_3 W21
3 IO_L02N_3/VRP_3 Y22
3 IO_L02P_3/VRN_3 Y21
3 IO_L01N_3 W20
3 IO_L01P_3 AA20
4 IO_L01N_4/DOUT AB19
4 IO_L01P_4/INIT_B AA19
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
24 1-800-255-7778 Advance Product Specification
4 IO_L02N_4/D0 V18
4 IO_L02P_4/D1 V17
4 IO_L03N_4/D2/ALT_VRP_4 W18
4 IO_L03P_4/D3/ALT_VRN_4 Y18
4 IO_L04N_4/VREF_4 AA18
4 IO_L04P_4 AB18
4 IO_L05N_4/VRP_4 W17
4 IO_L05P_4/VRN_4 Y17
4 IO_L06N_4 AA17
4 IO_L06P_4 AB17
4 IO_L19N_4 V16 NC NC
4 IO_L19P_4 V15 NC NC
4 IO_L21N_4 W16 NC NC
4 IO_L21P_4/VREF_4 Y16 NC NC
4 IO_L22N_4 AA16 NC NC
4 IO_L22P_4 AB16 NC NC
4 IO_L24N_4 W15 NC NC
4 IO_L24P_4 Y15 NC NC
4 IO_L49N_4 AA15 NC
4 IO_L49P_4 AB15 NC
4 IO_L51N_4 U14 NC
4 IO_L51P_4/VREF_4 V14 NC
4 IO_L52N_4 W14 NC
4 IO_L52P_4 Y14 NC
4 IO_L54N_4 AA14 NC
4 IO_L54P_4 AB14 NC
4 IO_L91N_4/VREF_4 U13
4 IO_L91P_4 V13
4 IO_L92N_4 W13
4 IO_L92P_4 Y13
4 IO_L93N_4 AA13
4 IO_L93P_4 AB13
4 IO_L94N_4/VREF_4 U12
4 IO_L94P_4 V12
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 25
4 IO_L95N_4/GCLK3S W12
4 IO_L95P_4/GCLK2P Y12
4 IO_L96N_4/GCLK1S AA12
4 IO_L96P_4/GCLK0P AB12
5 IO_L96N_5/GCLK7S AA11
5 IO_L96P_5/GCLK6P Y11
5 IO_L95N_5/GCLK5S W11
5 IO_L95P_5/GCLK4P V11
5 IO_L94N_5 U11
5 IO_L94P_5/VREF_5 U10
5 IO_L93N_5 AB10
5 IO_L93P_5 AA10
5 IO_L92N_5 Y10
5 IO_L92P_5 W10
5 IO_L91N_5 V10
5 IO_L91P_5/VREF_5 V9
5 IO_L54N_5 AB9 NC
5 IO_L54P_5 AA9 NC
5 IO_L52N_5 Y9 NC
5 IO_L52P_5 W9 NC
5 IO_L51N_5/VREF_5 AB8 NC
5 IO_L51P_5 AA8 NC
5 IO_L49N_5 Y8 NC
5 IO_L49P_5 W8 NC
5 IO_L24N_5 U9 NC NC
5 IO_L24P_5 V8 NC NC
5 IO_L22N_5 AB7 NC NC
5 IO_L22P_5 AA7 NC NC
5 IO_L21N_5/VREF_5 Y7 NC NC
5 IO_L21P_5 W7 NC NC
5 IO_L19N_5 AB6 NC NC
5 IO_L19P_5 AA6 NC NC
5 IO_L06N_5 Y6
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
26 1-800-255-7778 Advance Product Specification
5 IO_L06P_5 W6
5 IO_L05N_5/VRP_5 V7
5 IO_L05P_5/VRN_5 V6
5 IO_L04N_5 AB5
5 IO_L04P_5/VREF_5 AA5
5 IO_L03N_5/D4/ALT_VRP_5 Y5
5 IO_L03P_5/D5/ALT_VRN_5 W5
5 IO_L02N_5/D6 AB4
5 IO_L02P_5/D7 AA4
5 IO_L01N_5/RDWR_B Y4
5 IO_L01P_5/CS_B AA3
6 IO_L01P_6 V5
6 IO_L01N_6 U5
6 IO_L02P_6/VRN_6 Y2
6 IO_L02N_6/VRP_6 Y1
6 IO_L03P_6 V4
6 IO_L03N_6/VREF_6 V3
6 IO_L04P_6 W2
6 IO_L04N_6 W1
6 IO_L06P_6 U4
6 IO_L06N_6 U3
6 IO_L19P_6 V2 NC NC
6 IO_L19N_6 V1 NC NC
6 IO_L21P_6 U2 NC NC
6 IO_L21N_6/VREF_6 U1 NC NC
6 IO_L22P_6 T5 NC NC
6 IO_L22N_6 R5 NC NC
6 IO_L24P_6 T4 NC NC
6 IO_L24N_6 T3 NC NC
6 IO_L43P_6 T2
6 IO_L43N_6 T1
6 IO_L45P_6 R4
6 IO_L45N_6/VREF_6 R3
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 27
6 IO_L46P_6 R2
6 IO_L46N_6 R1
6 IO_L48P_6 P6
6 IO_L48N_6 P5
6 IO_L49P_6 P4 NC
6 IO_L49N_6 P3 NC
6 IO_L51P_6 P2 NC
6 IO_L51N_6/VREF_6 P1 NC
6 IO_L52P_6 N6 NC
6 IO_L52N_6 N5 NC
6 IO_L54P_6 N4 NC
6 IO_L54N_6 N3 NC
6 IO_L91P_6 N2
6 IO_L91N_6 N1
6 IO_L93P_6 M6
6 IO_L93N_6/VREF_6 M5
6 IO_L94P_6 M4
6 IO_L94N_6 M3
6 IO_L96P_6 M2
6 IO_L96N_6 M1
7 IO_L96P_7 L2
7 IO_L96N_7 L3
7 IO_L94P_7 L4
7 IO_L94N_7 L5
7 IO_L93P_7/VREF_7 K1
7 IO_L93N_7 K2
7 IO_L91P_7 K3
7 IO_L91N_7 K4
7 IO_L54P_7 L6 NC
7 IO_L54N_7 K6 NC
7 IO_L52P_7 K5 NC
7 IO_L52N_7 J5 NC
7 IO_L51P_7/VREF_7 J1 NC
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
28 1-800-255-7778 Advance Product Specification
7 IO_L51N_7 J2 NC
7 IO_L49P_7 J3 NC
7 IO_L49N_7 J4 NC
7 IO_L48P_7 H1
7 IO_L48N_7 H2
7 IO_L46P_7 H3
7 IO_L46N_7 H4
7 IO_L45P_7/VREF_7 J6
7 IO_L45N_7 H5
7 IO_L43P_7 G1
7 IO_L43N_7 G2
7 IO_L24P_7 G3 NC NC
7 IO_L24N_7 G4 NC NC
7 IO_L22P_7 F1 NC NC
7 IO_L22N_7 F2 NC NC
7 IO_L21P_7/VREF_7 F3 NC NC
7 IO_L21N_7 F4 NC NC
7 IO_L19P_7 G5 NC NC
7 IO_L19N_7 F5 NC NC
7 IO_L06P_7 E1
7 IO_L06N_7 E2
7 IO_L04P_7 E3
7 IO_L04N_7 E4
7 IO_L03P_7/VREF_7 D1
7 IO_L03N_7 D2
7 IO_L02P_7/VRN_7 C1
7 IO_L02N_7/VRP_7 C2
7 IO_L01P_7 E5
7 IO_L01N_7 E6
0 VCCO_0 G11
0 VCCO_0 G10
0 VCCO_0 G9
0 VCCO_0 F8
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 29
0 VCCO_0 F7
1 VCCO_1 G14
1 VCCO_1 G13
1 VCCO_1 G12
1 VCCO_1 F16
1 VCCO_1 F15
2 VCCO_2 L16
2 VCCO_2 K16
2 VCCO_2 J16
2 VCCO_2 H17
2 VCCO_2 G17
3 VCCO_3 T17
3 VCCO_3 R17
3 VCCO_3 P16
3 VCCO_3 N16
3 VCCO_3 M16
4 VCCO_4 U16
4 VCCO_4 U15
4 VCCO_4 T14
4 VCCO_4 T13
4 VCCO_4 T12
5 VCCO_5 U8
5 VCCO_5 U7
5 VCCO_5 T11
5 VCCO_5 T10
5 VCCO_5 T9
6 VCCO_6 T6
6 VCCO_6 R6
6 VCCO_6 P7
6 VCCO_6 N7
6 VCCO_6 M7
7 VCCO_7 L7
7 VCCO_7 K7
7 VCCO_7 J7
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
30 1-800-255-7778 Advance Product Specification
7 VCCO_7 H6
7 VCCO_7 G6
NA CCLK Y19
NA PROG_B A2
NA DONE AB20
NA M0 AB2
NA M1 W3
NA M2 AB3
NA HSWAP_EN B3
NA TCK C19
NA TDI D3
NA TDO D20
NA TMS B20
NA PWRDWN_B AB21
NA DXN D5
NA DXP A3
NA VBATT A21
NA RSVD A20
NA VCCAUX AB11
NA VCCAUX AA22
NA VCCAUX AA1
NA VCCAUX M22
NA VCCAUX L1
NA VCCAUX B22
NA VCCAUX B1
NA VCCAUX A12
NA VCCINT U17
NA VCCINT U6
NA VCCINT T16
NA VCCINT T15
NA VCCINT T8
NA VCCINT T7
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 31
NA VCCINT R16
NA VCCINT R7
NA VCCINT H16
NA VCCINT H7
NA VCCINT G16
NA VCCINT G15
NA VCCINT G8
NA VCCINT G7
NA VCCINT F17
NA VCCINT F6
NA GND AB22
NA GND AB1
NA GND AA21
NA GND AA2
NA GND Y20
NA GND Y3
NA GND W19
NA GND W4
NA GND P14
NA GND P13
NA GND P12
NA GND P11
NA GND P10
NA GND P9
NA GND N14
NA GND N13
NA GND N12
NA GND N11
NA GND N10
NA GND N9
NA GND M14
NA GND M13
NA GND M12
NA GND M11
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
32 1-800-255-7778 Advance Product Specification
NA GND M10
NA GND M9
NA GND L14
NA GND L13
NA GND L12
NA GND L11
NA GND L10
NA GND L9
NA GND K14
NA GND K13
NA GND K12
NA GND K11
NA GND K10
NA GND K9
NA GND J14
NA GND J13
NA GND J12
NA GND J11
NA GND J10
NA GND J9
NA GND D19
NA GND D4
NA GND C20
NA GND C3
NA GND B21
NA GND B2
NA GND A22
NA GND A1
Table 7: FG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank Pin Description Pin Number No Connect in XC2V250 No Connect in XC2V500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
34 1-800-255-7778 Advance Product Specification
FG676 Fine-Pitch BGA Package
As shown in Table 8, XC2V1500, XC2V2000, and XC2V3000 Virtex-II devices are available in the FG676 fine-pitch BGA
package. Pins in the XC2V1500, XC2V2000, and XC2V3000 devices are the same, except for the pin differences in the
XC2V1500 and XC2V2000 devices shown in the No Connect columns. Following this table are the FG676 Fine-Pitch BGA
Package Specifications (1.00mm pitch).
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
0 IO_L01N_0 D6
0 IO_L01P_0 C6
0 IO_L02N_0 B1
0 IO_L02P_0 A2
0 IO_L03N_0/VRP_0 D7
0 IO_L03P_0/VRN_0 C7
0 IO_L04N_0/VREF_0 B3
0 IO_L04P_0 A3
0 IO_L05N_0 G6
0 IO_L05P_0 G7
0 IO_L06N_0 E6
0 IO_L06P_0 E7
0 IO_L19N_0 B4
0 IO_L19P_0 A4
0 IO_L21N_0 B5
0 IO_L21P_0/VREF_0 A5
0 IO_L22N_0 B6
0 IO_L22P_0 A6
0 IO_L24N_0 A7
0 IO_L24P_0 A8
0 IO_L25N_0 E8 NC NC
0 IO_L25P_0 D8 NC NC
0 IO_L27N_0 G8 NC NC
0 IO_L27P_0/VREF_0 F8 NC NC
0 IO_L49N_0 C8
0 IO_L49P_0 B8
0 IO_L51N_0 D9
0 IO_L51P_0/VREF_0 E9
0 IO_L52N_0 F9
0 IO_L52P_0 G9
0 IO_L54N_0 B9
0 IO_L54P_0 A9
0 IO_L67N_0 C9
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 35
0 IO_L67P_0 C10
0 IO_L69N_0 F10
0 IO_L69P_0/VREF_0 G10
0 IO_L70N_0 E10
0 IO_L70P_0 D10
0 IO_L72N_0 A10
0 IO_L72P_0 A11
0 IO_L73N_0 F11 NC
0 IO_L73P_0 E11 NC
0 IO_L75N_0 G11 NC
0 IO_L75P_0/VREF_0 H11 NC
0 IO_L76N_0 D11 NC
0 IO_L76P_0 C11 NC
0 IO_L78N_0 B11 NC
0 IO_L78P_0 B12 NC
0 IO_L91N_0/VREF_0 G12
0 IO_L91P_0 H12
0 IO_L92N_0 F12
0 IO_L92P_0 E12
0 IO_L93N_0 D12
0 IO_L93P_0 C12
0 IO_L94N_0/VREF_0 G13
0 IO_L94P_0 H13
0 IO_L95N_0/GCLK7P F13
0 IO_L95P_0/GCLK6S E13
0 IO_L96N_0/GCLK5P D13
0 IO_L96P_0/GCLK4S C13
1 IO_L96N_1/GCLK3P H14
1 IO_L96P_1/GCLK2S H15
1 IO_L95N_1/GCLK1P G14
1 IO_L95P_1/GCLK0S F14
1 IO_L94N_1 E14
1 IO_L94P_1/VREF_1 D14
1 IO_L93N_1 A12
1 IO_L93P_1 A13
1 IO_L92N_1 A14
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
36 1-800-255-7778 Advance Product Specification
1 IO_L92P_1 A15
1 IO_L91N_1 B15
1 IO_L91P_1/VREF_1 C15
1 IO_L78N_1 D15 NC
1 IO_L78P_1 E15 NC
1 IO_L76N_1 F15 NC
1 IO_L76P_1 G15 NC
1 IO_L75N_1/VREF_1 G16 NC
1 IO_L75P_1 F16 NC
1 IO_L73N_1 A16 NC
1 IO_L73P_1 A17 NC
1 IO_L72N_1 B16
1 IO_L72P_1 C16
1 IO_L70N_1 D16
1 IO_L70P_1 E16
1 IO_L69N_1/VREF_1 C17
1 IO_L69P_1 D17
1 IO_L67N_1 H16
1 IO_L67P_1 G17
1 IO_L54N_1 E17
1 IO_L54P_1 F17
1 IO_L52N_1 A18
1 IO_L52P_1 A19
1 IO_L51N_1/VREF_1 E18
1 IO_L51P_1 D18
1 IO_L49N_1 B18
1 IO_L49P_1 C18
1 IO_L27N_1/VREF_1 F19 NC NC
1 IO_L27P_1 F18 NC NC
1 IO_L25N_1 G18 NC NC
1 IO_L25P_1 G19 NC NC
1 IO_L24N_1 B19
1 IO_L24P_1 C19
1 IO_L22N_1 D19
1 IO_L22P_1 E19
1 IO_L21N_1/VREF_1 A20
1 IO_L21P_1 A21
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 37
1 IO_L19N_1 E20
1 IO_L19P_1 F20
1 IO_L06N_1 B21
1 IO_L06P_1 B22
1 IO_L05N_1 A22
1 IO_L05P_1 A23
1 IO_L04N_1 C21
1 IO_L04P_1/VREF_1 D21
1 IO_L03N_1/VRP_1 C20
1 IO_L03P_1/VRN_1 D20
1 IO_L02N_1 A24
1 IO_L02P_1 A25
1 IO_L01N_1 B23
1 IO_L01P_1 B24
2 IO_L01N_2 B26
2 IO_L01P_2 C26
2 IO_L02N_2/VRP_2 G20
2 IO_L02P_2/VRN_2 H20
2 IO_L03N_2 C25
2 IO_L03P_2/VREF_2 D25
2 IO_L04N_2 E23
2 IO_L04P_2 E24
2 IO_L06N_2 G21
2 IO_L06P_2 G22
2 IO_L19N_2 D26
2 IO_L19P_2 E26
2 IO_L21N_2 F23
2 IO_L21P_2/VREF_2 F24
2 IO_L22N_2 E25
2 IO_L22P_2 F25
2 IO_L24N_2 H22
2 IO_L24P_2 H21
2 IO_L25N_2 G23 NC NC
2 IO_L25P_2 G24 NC NC
2 IO_L43N_2 F26
2 IO_L43P_2 G26
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
38 1-800-255-7778 Advance Product Specification
2 IO_L45N_2 H23
2 IO_L45P_2/VREF_2 H24
2 IO_L46N_2 J21
2 IO_L46P_2 J20
2 IO_L48N_2 H25
2 IO_L48P_2 H26
2 IO_L49N_2 J22
2 IO_L49P_2 J23
2 IO_L51N_2 K21
2 IO_L51P_2/VREF_2 K22
2 IO_L52N_2 K20
2 IO_L52P_2 L20
2 IO_L54N_2 J24
2 IO_L54P_2 J25
2 IO_L67N_2 K23
2 IO_L67P_2 K24
2 IO_L69N_2 J26
2 IO_L69P_2/VREF_2 K26
2 IO_L70N_2 L22
2 IO_L70P_2 L21
2 IO_L72N_2 L25
2 IO_L72P_2 L26
2 IO_L73N_2 L19 NC
2 IO_L73P_2 M19 NC
2 IO_L75N_2 L23 NC
2 IO_L75P_2/VREF_2 L24 NC
2 IO_L76N_2 M22 NC
2 IO_L76P_2 M21 NC
2 IO_L78N_2 M23 NC
2 IO_L78P_2 M24 NC
2 IO_L91N_2 M25
2 IO_L91P_2 M26
2 IO_L93N_2 M20
2 IO_L93P_2/VREF_2 N20
2 IO_L94N_2 N22
2 IO_L94P_2 N21
2 IO_L96N_2 N24
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 39
2 IO_L96P_2 N23
3 IO_L96N_3 N26
3 IO_L96P_3 P26
3 IO_L94N_3 P23
3 IO_L94P_3 P22
3 IO_L93N_3/VREF_3 P19
3 IO_L93P_3 N19
3 IO_L91N_3 P21
3 IO_L91P_3 P20
3 IO_L78N_3 R26 NC
3 IO_L78P_3 R25 NC
3 IO_L76N_3 R20 NC
3 IO_L76P_3 R19 NC
3 IO_L75N_3/VREF_3 R24 NC
3 IO_L75P_3 R23 NC
3 IO_L73N_3 R22 NC
3 IO_L73P_3 R21 NC
3 IO_L72N_3 T26
3 IO_L72P_3 T25
3 IO_L70N_3 T20
3 IO_L70P_3 T19
3 IO_L69N_3/VREF_3 T24
3 IO_L69P_3 T23
3 IO_L67N_3 T22
3 IO_L67P_3 T21
3 IO_L54N_3 U26
3 IO_L54P_3 V26
3 IO_L52N_3 U24
3 IO_L52P_3 U23
3 IO_L51N_3/VREF_3 U22
3 IO_L51P_3 U21
3 IO_L49N_3 V25
3 IO_L49P_3 V24
3 IO_L48N_3 V23
3 IO_L48P_3 V22
3 IO_L46N_3 W26
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
40 1-800-255-7778 Advance Product Specification
3 IO_L46P_3 Y26
3 IO_L45N_3/VREF_3 U20
3 IO_L45P_3 V20
3 IO_L43N_3 W25
3 IO_L43P_3 W24
3 IO_L25N_3 V21 NC NC
3 IO_L25P_3 W21 NC NC
3 IO_L24N_3 AA26
3 IO_L24P_3 AA25
3 IO_L22N_3 Y24
3 IO_L22P_3 Y23
3 IO_L21N_3/VREF_3 W22
3 IO_L21P_3 W23
3 IO_L19N_3 AB26
3 IO_L19P_3 AB25
3 IO_L06N_3 AC26
3 IO_L06P_3 AC25
3 IO_L04N_3 AD26
3 IO_L04P_3 AD25
3 IO_L03N_3/VREF_3 AA24
3 IO_L03P_3 AA23
3 IO_L02N_3/VRP_3 AB24
3 IO_L02P_3/VRN_3 AB23
3 IO_L01N_3 Y22
3 IO_L01P_3 AA22
4 IO_L01N_4/DOUT AD21
4 IO_L01P_4/INIT_B AC21
4 IO_L02N_4/D0 Y20
4 IO_L02P_4/D1 Y19
4 IO_L03N_4/D2/ALT_VRP_4 AA20
4 IO_L03P_4/D3/ALT_VRN_4 AB20
4 IO_L04N_4/VREF_4 AC22
4 IO_L04P_4 AE21
4 IO_L05N_4/VRP_4 AE26
4 IO_L05P_4/VRN_4 AF25
4 IO_L06N_4 W20
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 41
4 IO_L06P_4 Y21
4 IO_L19N_4 AE24
4 IO_L19P_4 AF24
4 IO_L21N_4 AE23
4 IO_L21P_4/VREF_4 AF23
4 IO_L22N_4 AE22
4 IO_L22P_4 AF22
4 IO_L24N_4 AF21
4 IO_L24P_4 AF20
4 IO_L25N_4 AA19 NC NC
4 IO_L25P_4 AB19 NC NC
4 IO_L27N_4 AD20 NC NC
4 IO_L27P_4/VREF_4 AC20 NC NC
4 IO_L28N_4 AC19 NC NC
4 IO_L28P_4 AD19 NC NC
4 IO_L49N_4 AE19
4 IO_L49P_4 AF19
4 IO_L51N_4 AA18
4 IO_L51P_4/VREF_4 AB18
4 IO_L52N_4 Y18
4 IO_L52P_4 Y17
4 IO_L54N_4 AC18
4 IO_L54P_4 AD18
4 IO_L67N_4 AE18
4 IO_L67P_4 AF18
4 IO_L69N_4 AA17
4 IO_L69P_4/VREF_4 AB17
4 IO_L70N_4 AC17
4 IO_L70P_4 AD17
4 IO_L72N_4 AF17
4 IO_L72P_4 AF16
4 IO_L73N_4 AB16 NC
4 IO_L73P_4 AC16 NC
4 IO_L75N_4 AA16 NC
4 IO_L75P_4/VREF_4 Y16 NC
4 IO_L76N_4 AD16 NC
4 IO_L76P_4 AE16 NC
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
42 1-800-255-7778 Advance Product Specification
4 IO_L78N_4 Y15 NC
4 IO_L78P_4 AA15 NC
4 IO_L91N_4/VREF_4 W15
4 IO_L91P_4 W16
4 IO_L92N_4 AB15
4 IO_L92P_4 AC15
4 IO_L93N_4 AD15
4 IO_L93P_4 AE15
4 IO_L94N_4/VREF_4 W14
4 IO_L94P_4 Y14
4 IO_L95N_4/GCLK3S AA14
4 IO_L95P_4/GCLK2P AB14
4 IO_L96N_4/GCLK1S AC14
4 IO_L96P_4/GCLK0P AD14
5 IO_L96N_5/GCLK7S AC13
5 IO_L96P_5/GCLK6P AB13
5 IO_L95N_5/GCLK5S AA13
5 IO_L95P_5/GCLK4P Y13
5 IO_L94N_5 W13
5 IO_L94P_5/VREF_5 W12
5 IO_L93N_5 AF15
5 IO_L93P_5 AF14
5 IO_L92N_5 AF13
5 IO_L92P_5 AF12
5 IO_L91N_5 AE12
5 IO_L91P_5/VREF_5 AD12
5 IO_L78N_5 AC12 NC
5 IO_L78P_5 AB12 NC
5 IO_L76N_5 AA12 NC
5 IO_L76P_5 Y12 NC
5 IO_L75N_5/VREF_5 AF11 NC
5 IO_L75P_5 AF10 NC
5 IO_L73N_5 AE11 NC
5 IO_L73P_5 AD11 NC
5 IO_L72N_5 AC11
5 IO_L72P_5 AB11
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 43
5 IO_L70N_5 W11
5 IO_L70P_5 Y10
5 IO_L69N_5/VREF_5 Y11
5 IO_L69P_5 AA11
5 IO_L67N_5 AF9
5 IO_L67P_5 AF8
5 IO_L54N_5 AE9
5 IO_L54P_5 AD9
5 IO_L52N_5 AB10
5 IO_L52P_5 AA10
5 IO_L51N_5/VREF_5 AD10
5 IO_L51P_5 AC10
5 IO_L49N_5 AE8
5 IO_L49P_5 AF7
5 IO_L28N_5 AD8 NC NC
5 IO_L28P_5 AC8 NC NC
5 IO_L27N_5/VREF_5 AB9 NC NC
5 IO_L27P_5 AC9 NC NC
5 IO_L25N_5 AA9 NC NC
5 IO_L25P_5 Y9 NC NC
5 IO_L24N_5 AF6
5 IO_L24P_5 AE6
5 IO_L22N_5 AB8
5 IO_L22P_5 AA8
5 IO_L21N_5/VREF_5 AC7
5 IO_L21P_5 AD7
5 IO_L19N_5 AF5
5 IO_L19P_5 AE5
5 IO_L06N_5 AF4
5 IO_L06P_5 AE4
5 IO_L05N_5/VRP_5 AF3
5 IO_L05P_5/VRN_5 AE3
5 IO_L04N_5 Y8
5 IO_L04P_5/VREF_5 Y7
5 IO_L03N_5/D4/ALT_VRP_5 AB7
5 IO_L03P_5/D5/ALT_VRN_5 AA7
5 IO_L02N_5/D6 AD6
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
44 1-800-255-7778 Advance Product Specification
5 IO_L02P_5/D7 AC6
5 IO_L01N_5/RDWR_B AB6
5 IO_L01P_5/CS_B AC5
6 IO_L01P_6 AF2
6 IO_L01N_6 AE1
6 IO_L02P_6/VRN_6 AB4
6 IO_L02N_6/VRP_6 AB3
6 IO_L03P_6 AD2
6 IO_L03N_6/VREF_6 AD1
6 IO_L04P_6 AC2
6 IO_L04N_6 AC1
6 IO_L06P_6 AB2
6 IO_L06N_6 AB1
6 IO_L19P_6 AA4
6 IO_L19N_6 AA3
6 IO_L21P_6 Y6
6 IO_L21N_6/VREF_6 Y5
6 IO_L22P_6 W6
6 IO_L22N_6 W7
6 IO_L24P_6 AA2
6 IO_L24N_6 AA1
6 IO_L25P_6 Y4 NC NC
6 IO_L25N_6 Y3 NC NC
6 IO_L43P_6 W5
6 IO_L43N_6 W4
6 IO_L45P_6 W2
6 IO_L45N_6/VREF_6 W3
6 IO_L46P_6 Y1
6 IO_L46N_6 W1
6 IO_L48P_6 V6
6 IO_L48N_6 V7
6 IO_L49P_6 V5
6 IO_L49N_6 V4
6 IO_L51P_6 V3
6 IO_L51N_6/VREF_6 V2
6 IO_L52P_6 V1
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 45
6 IO_L52N_6 U1
6 IO_L54P_6 U7
6 IO_L54N_6 T7
6 IO_L67P_6 U4
6 IO_L67N_6 U3
6 IO_L69P_6 U6
6 IO_L69N_6/VREF_6 U5
6 IO_L70P_6 T5
6 IO_L70N_6 T6
6 IO_L72P_6 T8
6 IO_L72N_6 R8
6 IO_L73P_6 T2 NC
6 IO_L73N_6 T1 NC
6 IO_L75P_6 T4 NC
6 IO_L75N_6/VREF_6 T3 NC
6 IO_L76P_6 R6 NC
6 IO_L76N_6 R5 NC
6 IO_L78P_6 R4 NC
6 IO_L78N_6 R3 NC
6 IO_L91P_6 R2
6 IO_L91N_6 R1
6 IO_L93P_6 R7
6 IO_L93N_6/VREF_6 P7
6 IO_L94P_6 P6
6 IO_L94N_6 P5
6 IO_L96P_6 P4
6 IO_L96N_6 P3
7 IO_L96P_7 P1
7 IO_L96N_7 N1
7 IO_L94P_7 N4
7 IO_L94N_7 N5
7 IO_L93P_7/VREF_7 N6
7 IO_L93N_7 N7
7 IO_L91P_7 P8
7 IO_L91N_7 N8
7 IO_L78P_7 M1 NC
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
46 1-800-255-7778 Advance Product Specification
7 IO_L78N_7 M2 NC
7 IO_L76P_7 M5 NC
7 IO_L76N_7 M6 NC
7 IO_L75P_7/VREF_7 M3 NC
7 IO_L75N_7 M4 NC
7 IO_L73P_7 M7 NC
7 IO_L73N_7 M8 NC
7 IO_L72P_7 L1
7 IO_L72N_7 L2
7 IO_L70P_7 L5
7 IO_L70N_7 L6
7 IO_L69P_7/VREF_7 L3
7 IO_L69N_7 L4
7 IO_L67P_7 K1
7 IO_L67N_7 J1
7 IO_L54P_7 K3
7 IO_L54N_7 K4
7 IO_L52P_7 K5
7 IO_L52N_7 K6
7 IO_L51P_7/VREF_7 L8
7 IO_L51N_7 L7
7 IO_L49P_7 J2
7 IO_L49N_7 H1
7 IO_L48P_7 J3
7 IO_L48N_7 J4
7 IO_L46P_7 J5
7 IO_L46N_7 J6
7 IO_L45P_7/VREF_7 H5
7 IO_L45N_7 H4
7 IO_L43P_7 K7
7 IO_L43N_7 J7
7 IO_L25P_7 H2 NC NC
7 IO_L25N_7 H3 NC NC
7 IO_L24P_7 G1
7 IO_L24N_7 F1
7 IO_L22P_7 G3
7 IO_L22N_7 G4
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 47
7 IO_L21P_7/VREF_7 F3
7 IO_L21N_7 F2
7 IO_L19P_7 H6
7 IO_L19N_7 H7
7 IO_L06P_7 E1
7 IO_L06N_7 E2
7 IO_L04P_7 D1
7 IO_L04N_7 D2
7 IO_L03P_7/VREF_7 C1
7 IO_L03N_7 C2
7 IO_L02P_7/VRN_7 E3
7 IO_L02N_7/VRP_7 E4
7 IO_L01P_7 G5
7 IO_L01N_7 F4
0 VCCO_0 J13
0 VCCO_0 J12
0 VCCO_0 J11
0 VCCO_0 H10
0 VCCO_0 H9
0 VCCO_0 B10
0 VCCO_0 B7
1 VCCO_1 B17
1 VCCO_1 J16
1 VCCO_1 J15
1 VCCO_1 J14
1 VCCO_1 H18
1 VCCO_1 H17
1 VCCO_1 B20
2 VCCO_2 N18
2 VCCO_2 M18
2 VCCO_2 L18
2 VCCO_2 K25
2 VCCO_2 K19
2 VCCO_2 J19
2 VCCO_2 G25
3 VCCO_3 Y25
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
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48 1-800-255-7778 Advance Product Specification
3 VCCO_3 V19
3 VCCO_3 U25
3 VCCO_3 U19
3 VCCO_3 T18
3 VCCO_3 R18
3 VCCO_3 P18
4 VCCO_4 AE20
4 VCCO_4 AE17
4 VCCO_4 W18
4 VCCO_4 W17
4 VCCO_4 V16
4 VCCO_4 V15
4 VCCO_4 V14
5 VCCO_5 AE10
5 VCCO_5 AE7
5 VCCO_5 W10
5 VCCO_5 W9
5 VCCO_5 V13
5 VCCO_5 V12
5 VCCO_5 V11
6 VCCO_6 Y2
6 VCCO_6 V8
6 VCCO_6 U8
6 VCCO_6 U2
6 VCCO_6 T9
6 VCCO_6 R9
6 VCCO_6 P9
7 VCCO_7 N9
7 VCCO_7 M9
7 VCCO_7 L9
7 VCCO_7 K8
7 VCCO_7 K2
7 VCCO_7 J8
7 VCCO_7 G2
NA CCLK AB21
NA PROG_B C4
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 49
NA DONE AD22
NA M0 AD4
NA M1 AA5
NA M2 AD5
NA HSWAP_EN D5
NA TCK E21
NA TDI F5
NA TDO F22
NA TMS D22
NA PWRDWN_B AD23
NA DXN F7
NA DXP C5
NA VBATT C23
NA RSVD C22
NA VCCAUX AD13
NA VCCAUX AC24
NA VCCAUX AC3
NA VCCAUX P24
NA VCCAUX N3
NA VCCAUX D24
NA VCCAUX D3
NA VCCAUX C14
NA VCCINT W19
NA VCCINT W8
NA VCCINT V18
NA VCCINT V17
NA VCCINT V10
NA VCCINT V9
NA VCCINT U18
NA VCCINT U9
NA VCCINT K18
NA VCCINT K9
NA VCCINT J18
NA VCCINT J17
NA VCCINT J10
NA VCCINT J9
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
50 1-800-255-7778 Advance Product Specification
NA VCCINT H19
NA VCCINT H8
NA GND AF26
NA GND AF1
NA GND AE25
NA GND AE14
NA GND AE13
NA GND AE2
NA GND AD24
NA GND AD3
NA GND AC23
NA GND AC4
NA GND AB22
NA GND AB5
NA GND AA21
NA GND AA6
NA GND U17
NA GND U16
NA GND U15
NA GND U14
NA GND U13
NA GND U12
NA GND U11
NA GND U10
NA GND T17
NA GND T16
NA GND T15
NA GND T14
NA GND T13
NA GND T12
NA GND T11
NA GND T10
NA GND R17
NA GND R16
NA GND R15
NA GND R14
NA GND R13
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 51
NA GND R12
NA GND R11
NA GND R10
NA GND P25
NA GND P17
NA GND P16
NA GND P15
NA GND P14
NA GND P13
NA GND P12
NA GND P11
NA GND P10
NA GND P2
NA GND N25
NA GND N17
NA GND N16
NA GND N15
NA GND N14
NA GND N13
NA GND N12
NA GND N11
NA GND N10
NA GND N2
NA GND M17
NA GND M16
NA GND M15
NA GND M14
NA GND M13
NA GND M12
NA GND M11
NA GND M10
NA GND L17
NA GND L16
NA GND L15
NA GND L14
NA GND L13
NA GND L12
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
52 1-800-255-7778 Advance Product Specification
NA GND L11
NA GND L10
NA GND K17
NA GND K16
NA GND K15
NA GND K14
NA GND K13
NA GND K12
NA GND K11
NA GND K10
NA GND F21
NA GND F6
NA GND E22
NA GND E5
NA GND D23
NA GND D4
NA GND C24
NA GND C3
NA GND B25
NA GND B14
NA GND B13
NA GND B2
NA GND A26
NA GND A1
Table 8: FG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V1500 No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
54 1-800-255-7778 Advance Product Specification
BG575 Standard BGA Package
As shown in Table 9, XC2V1000, XC2V1500, and XC2V2000 Virtex-II devices are available in the BG575 BGA package.
Pins in the XC2V1000, XC2V1500, and XC2V2000 devices are the same, except for the pin differences in the XC2V1000
and XC2V1500 devices shown in the No Connect columns. Following this table are the BG575 Standard BGA Package
Specifications (1.27mm pitch).
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
0 IO_L01N_0 A3
0 IO_L01P_0 A4
0 IO_L02N_0 D5
0 IO_L02P_0 C5
0 IO_L03N_0/VRP_0 E6
0 IO_L03P_0/VRN_0 D6
0 IO_L04N_0/VREF_0 F7
0 IO_L04P_0 E7
0 IO_L05N_0 G8
0 IO_L05P_0 H9
0 IO_L06N_0 A5
0 IO_L06P_0 A6
0 IO_L19N_0 B5
0 IO_L19P_0 B6
0 IO_L21N_0 D7
0 IO_L21P_0/VREF_0 C7
0 IO_L22N_0 F8
0 IO_L22P_0 E8
0 IO_L24N_0 G9
0 IO_L24P_0 F9
0 IO_L49N_0 G10
0 IO_L49P_0 H10
0 IO_L51N_0 B7
0 IO_L51P_0/VREF_0 B8
0 IO_L52N_0 D8
0 IO_L52P_0 C8
0 IO_L54N_0 E9
0 IO_L54P_0 D9
0 IO_L67N_0 A8 NC
0 IO_L67P_0 A9 NC
0 IO_L69N_0 C9 NC
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 55
0 IO_L69P_0/VREF_0 B9 NC
0 IO_L70N_0 F10 NC
0 IO_L70P_0 E10 NC
0 IO_L72N_0 A10 NC
0 IO_L72P_0 A11 NC
0 IO_L73N_0 C10 NC NC
0 IO_L73P_0 B10 NC NC
0 IO_L91N_0/VREF_0 D11
0 IO_L91P_0 C11
0 IO_L92N_0 G11
0 IO_L92P_0 E11
0 IO_L93N_0 C12
0 IO_L93P_0 B12
0 IO_L94N_0/VREF_0 E12
0 IO_L94P_0 D12
0 IO_L95N_0/GCLK7P G12
0 IO_L95P_0/GCLK6S F12
0 IO_L96N_0/GCLK5P H11
0 IO_L96P_0/GCLK4S H12
1 IO_L96N_1/GCLK3P A13
1 IO_L96P_1/GCLK2S A14
1 IO_L95N_1/GCLK1P B13
1 IO_L95P_1/GCLK0S C13
1 IO_L94N_1 D13
1 IO_L94P_1/VREF_1 E13
1 IO_L93N_1 F13
1 IO_L93P_1 G13
1 IO_L92N_1 H13
1 IO_L92P_1 H14
1 IO_L91N_1 C14
1 IO_L91P_1/VREF_1 D14
1 IO_L73N_1 E14 NC NC
1 IO_L73P_1 G14 NC NC
1 IO_L72N_1 A15 NC
1 IO_L72P_1 A16 NC
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
56 1-800-255-7778 Advance Product Specification
1 IO_L70N_1 B15 NC
1 IO_L70P_1 C15 NC
1 IO_L69N_1/VREF_1 E15 NC
1 IO_L69P_1 F15 NC
1 IO_L67N_1 G15 NC
1 IO_L67P_1 H15 NC
1 IO_L54N_1 B16
1 IO_L54P_1 C16
1 IO_L52N_1 D16
1 IO_L52P_1 E16
1 IO_L51N_1/VREF_1 F16
1 IO_L51P_1 G16
1 IO_L49N_1 A17
1 IO_L49P_1 A19
1 IO_L24N_1 B17
1 IO_L24P_1 B18
1 IO_L22N_1 C17
1 IO_L22P_1 D17
1 IO_L21N_1/VREF_1 F17
1 IO_L21P_1 E17
1 IO_L19N_1 A20
1 IO_L19P_1 A21
1 IO_L06N_1 B19
1 IO_L06P_1 B20
1 IO_L05N_1 C18
1 IO_L05P_1 D18
1 IO_L04N_1 C20
1 IO_L04P_1/VREF_1 D20
1 IO_L03N_1/VRP_1 D19
1 IO_L03P_1/VRN_1 E19
1 IO_L02N_1 E18
1 IO_L02P_1 F18
1 IO_L01N_1 H16
1 IO_L01P_1 G17
2 IO_L01N_2 D22
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 57
2 IO_L01P_2 D23
2 IO_L02N_2/VRP_2 E21
2 IO_L02P_2/VRN_2 E22
2 IO_L03N_2 F21
2 IO_L03P_2/VREF_2 F20
2 IO_L04N_2 G20
2 IO_L04P_2 G19
2 IO_L06N_2 H18
2 IO_L06P_2 J17
2 IO_L19N_2 D24
2 IO_L19P_2 E23
2 IO_L21N_2 E24
2 IO_L21P_2/VREF_2 F24
2 IO_L22N_2 F23
2 IO_L22P_2 G23
2 IO_L24N_2 G21
2 IO_L24P_2 G22
2 IO_L43N_2 H19
2 IO_L43P_2 H20
2 IO_L45N_2 J18
2 IO_L45P_2/VREF_2 J19
2 IO_L46N_2 K17
2 IO_L46P_2 K18
2 IO_L48N_2 H23
2 IO_L48P_2 H24
2 IO_L49N_2 H21
2 IO_L49P_2 H22
2 IO_L51N_2 J24
2 IO_L51P_2/VREF_2 K24
2 IO_L52N_2 J22
2 IO_L52P_2 J23
2 IO_L54N_2 J20
2 IO_L54P_2 J21
2 IO_L67N_2 K19 NC
2 IO_L67P_2 K20 NC
2 IO_L69N_2 L17 NC
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
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58 1-800-255-7778 Advance Product Specification
2 IO_L69P_2/VREF_2 L18 NC
2 IO_L70N_2 K23 NC
2 IO_L70P_2 L24 NC
2 IO_L72N_2 K22 NC
2 IO_L72P_2 L22 NC
2 IO_L73N_2 L21 NC NC
2 IO_L73P_2 L20 NC NC
2 IO_L91N_2 M23
2 IO_L91P_2 N24
2 IO_L93N_2 M21
2 IO_L93P_2/VREF_2 M22
2 IO_L94N_2 M19
2 IO_L94P_2 M20
2 IO_L96N_2 M17
2 IO_L96P_2 M18
3 IO_L96N_3 N23
3 IO_L96P_3 N22
3 IO_L94N_3 N20
3 IO_L94P_3 N21
3 IO_L93N_3/VREF_3 N19
3 IO_L93P_3 N18
3 IO_L91N_3 N17
3 IO_L91P_3 P17
3 IO_L73N_3 P24 NC NC
3 IO_L73P_3 R24 NC NC
3 IO_L72N_3 R23 NC
3 IO_L72P_3 R22 NC
3 IO_L70N_3 P22 NC
3 IO_L70P_3 P21 NC
3 IO_L69N_3/VREF_3 P20 NC
3 IO_L69P_3 P18 NC
3 IO_L67N_3 T24 NC
3 IO_L67P_3 U24 NC
3 IO_L54N_3 T23
3 IO_L54P_3 T22
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 59
3 IO_L52N_3 T21
3 IO_L52P_3 T20
3 IO_L51N_3/VREF_3 R20
3 IO_L51P_3 R19
3 IO_L49N_3 W24
3 IO_L49P_3 W23
3 IO_L48N_3 U23
3 IO_L48P_3 V23
3 IO_L46N_3 U22
3 IO_L46P_3 U21
3 IO_L45N_3/VREF_3 V22
3 IO_L45P_3 V21
3 IO_L43N_3 U19
3 IO_L43P_3 U20
3 IO_L24N_3 T19
3 IO_L24P_3 T18
3 IO_L22N_3 R18
3 IO_L22P_3 R17
3 IO_L21N_3/VREF_3 Y24
3 IO_L21P_3 Y23
3 IO_L19N_3 AA24
3 IO_L19P_3 AB24
3 IO_L06N_3 AA23
3 IO_L06P_3 AA22
3 IO_L04N_3 Y22
3 IO_L04P_3 Y21
3 IO_L03N_3/VREF_3 W21
3 IO_L03P_3 W20
3 IO_L02N_3/VRP_3 V20
3 IO_L02P_3/VRN_3 V19
3 IO_L01N_3 U18
3 IO_L01P_3 T17
4 IO_L01N_4/DOUT AD22
4 IO_L01P_4/INIT_B AD21
4 IO_L02N_4/D0 AA20
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
60 1-800-255-7778 Advance Product Specification
4 IO_L02P_4/D1 AB20
4 IO_L03N_4/D2/ALT_VRP_4 Y19
4 IO_L03P_4/D3/ALT_VRN_4 AA19
4 IO_L04N_4/VREF_4 W18
4 IO_L04P_4 Y18
4 IO_L05N_4/VRP_4 U16
4 IO_L05P_4/VRN_4 V17
4 IO_L06N_4 AD20
4 IO_L06P_4 AD19
4 IO_L19N_4 AC20
4 IO_L19P_4 AC19
4 IO_L21N_4 AA18
4 IO_L21P_4/VREF_4 AB18
4 IO_L22N_4 AC18
4 IO_L22P_4 AC17
4 IO_L24N_4 AA17
4 IO_L24P_4 AB17
4 IO_L49N_4 Y17
4 IO_L49P_4 W17
4 IO_L51N_4 V16
4 IO_L51P_4/VREF_4 W16
4 IO_L52N_4 AD17
4 IO_L52P_4 AD16
4 IO_L54N_4 AB16
4 IO_L54P_4 AC16
4 IO_L67N_4 Y16 NC
4 IO_L67P_4 AA16 NC
4 IO_L69N_4 W15 NC
4 IO_L69P_4/VREF_4 Y15 NC
4 IO_L70N_4 U15 NC
4 IO_L70P_4 V15 NC
4 IO_L72N_4 AD15 NC
4 IO_L72P_4 AD14 NC
4 IO_L73N_4 AB15 NC NC
4 IO_L73P_4 AC15 NC NC
4 IO_L91N_4/VREF_4 AA14
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 61
4 IO_L91P_4 AB14
4 IO_L92N_4 V14
4 IO_L92P_4 Y14
4 IO_L93N_4 AB13
4 IO_L93P_4 AC13
4 IO_L94N_4/VREF_4 Y13
4 IO_L94P_4 AA13
4 IO_L95N_4/GCLK3S V13
4 IO_L95P_4/GCLK2P W13
4 IO_L96N_4/GCLK1S U14
4 IO_L96P_4/GCLK0P U13
5 IO_L96N_5/GCLK7S AD12
5 IO_L96P_5/GCLK6P AD11
5 IO_L95N_5/GCLK5S AC12
5 IO_L95P_5/GCLK4P AB12
5 IO_L94N_5 AA12
5 IO_L94P_5/VREF_5 Y12
5 IO_L93N_5 W12
5 IO_L93P_5 V12
5 IO_L92N_5 U12
5 IO_L92P_5 U11
5 IO_L91N_5 AB11
5 IO_L91P_5/VREF_5 AA11
5 IO_L73N_5 Y11 NC NC
5 IO_L73P_5 V11 NC NC
5 IO_L72N_5 AD10 NC
5 IO_L72P_5 AD9 NC
5 IO_L70N_5 AC10 NC
5 IO_L70P_5 AB10 NC
5 IO_L69N_5/VREF_5 Y10 NC
5 IO_L69P_5 W10 NC
5 IO_L67N_5 V10 NC
5 IO_L67P_5 U10 NC
5 IO_L54N_5 AC9
5 IO_L54P_5 AB9
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
62 1-800-255-7778 Advance Product Specification
5 IO_L52N_5 AA9
5 IO_L52P_5 Y9
5 IO_L51N_5/VREF_5 W9
5 IO_L51P_5 V9
5 IO_L49N_5 AD8
5 IO_L49P_5 AD6
5 IO_L24N_5 AC8
5 IO_L24P_5 AC7
5 IO_L22N_5 AB8
5 IO_L22P_5 AA8
5 IO_L21N_5/VREF_5 W8
5 IO_L21P_5 Y8
5 IO_L19N_5 AD5
5 IO_L19P_5 AD4
5 IO_L06N_5 AC6
5 IO_L06P_5 AC5
5 IO_L05N_5/VRP_5 AB7
5 IO_L05P_5/VRN_5 AA7
5 IO_L04N_5 AB5
5 IO_L04P_5/VREF_5 AA5
5 IO_L03N_5/D4/ALT_VRP_5 AA6
5 IO_L03P_5/D5/ALT_VRN_5 Y6
5 IO_L02N_5/D6 Y7
5 IO_L02P_5/D7 W7
5 IO_L01N_5/RDWR_B V8
5 IO_L01P_5/CS_B U9
6 IO_L01P_6 AB2
6 IO_L01N_6 AB1
6 IO_L02P_6/VRN_6 AA3
6 IO_L02N_6/VRP_6 AA2
6 IO_L03P_6 Y4
6 IO_L03N_6/VREF_6 Y3
6 IO_L04P_6 W4
6 IO_L04N_6 W5
6 IO_L06P_6 V5
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 63
6 IO_L06N_6 V6
6 IO_L19P_6 U7
6 IO_L19N_6 T8
6 IO_L21P_6 AA1
6 IO_L21N_6/VREF_6 Y2
6 IO_L22P_6 Y1
6 IO_L22N_6 W1
6 IO_L24P_6 W2
6 IO_L24N_6 V2
6 IO_L43P_6 V4
6 IO_L43N_6 V3
6 IO_L45P_6 U6
6 IO_L45N_6/VREF_6 U5
6 IO_L46P_6 T7
6 IO_L46N_6 T6
6 IO_L48P_6 R8
6 IO_L48N_6 R7
6 IO_L49P_6 U2
6 IO_L49N_6 U1
6 IO_L51P_6 U4
6 IO_L51N_6/VREF_6 U3
6 IO_L52P_6 T1
6 IO_L52N_6 R1
6 IO_L54P_6 T3
6 IO_L54N_6 T2
6 IO_L67P_6 T5 NC
6 IO_L67N_6 T4 NC
6 IO_L69P_6 R6 NC
6 IO_L69N_6/VREF_6 R5 NC
6 IO_L70P_6 P8 NC
6 IO_L70N_6 P7 NC
6 IO_L72P_6 R2 NC
6 IO_L72N_6 P1 NC
6 IO_L73P_6 R3 NC NC
6 IO_L73N_6 P3 NC NC
6 IO_L91P_6 P5
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
64 1-800-255-7778 Advance Product Specification
6 IO_L91N_6 P4
6 IO_L93P_6 N4
6 IO_L93N_6/VREF_6 N3
6 IO_L94P_6 N6
6 IO_L94N_6 N5
6 IO_L96P_6 N8
6 IO_L96N_6 N7
7 IO_L96P_7 N2
7 IO_L96N_7 M1
7 IO_L94P_7 M2
7 IO_L94N_7 M3
7 IO_L93P_7/VREF_7 M4
7 IO_L93N_7 M5
7 IO_L91P_7 M6
7 IO_L91N_7 M7
7 IO_L73P_7 M8 NC NC
7 IO_L73N_7 L8 NC NC
7 IO_L72P_7 L1 NC
7 IO_L72N_7 K1 NC
7 IO_L70P_7 K2 NC
7 IO_L70N_7 K3 NC
7 IO_L69P_7/VREF_7 L3 NC
7 IO_L69N_7 L4 NC
7 IO_L67P_7 L5 NC
7 IO_L67N_7 L7 NC
7 IO_L54P_7 J1
7 IO_L54N_7 H1
7 IO_L52P_7 J2
7 IO_L52N_7 J3
7 IO_L51P_7/VREF_7 J4
7 IO_L51N_7 J5
7 IO_L49P_7 K5
7 IO_L49N_7 K6
7 IO_L48P_7 F1
7 IO_L48N_7 F2
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 65
7 IO_L46P_7 H2
7 IO_L46N_7 G2
7 IO_L45P_7/VREF_7 H3
7 IO_L45N_7 H4
7 IO_L43P_7 G3
7 IO_L43N_7 G4
7 IO_L24P_7 H5
7 IO_L24N_7 H6
7 IO_L22P_7 J6
7 IO_L22N_7 J7
7 IO_L21P_7/VREF_7 K7
7 IO_L21N_7 K8
7 IO_L19P_7 E1
7 IO_L19N_7 E2
7 IO_L06P_7 D2
7 IO_L06N_7 D3
7 IO_L04P_7 E3
7 IO_L04N_7 E4
7 IO_L03P_7/VREF_7 F4
7 IO_L03N_7 F5
7 IO_L02P_7/VRN_7 G5
7 IO_L02N_7/VRP_7 G6
7 IO_L01P_7 H7
7 IO_L01N_7 J8
0 VCCO_0 J12
0 VCCO_0 J11
0 VCCO_0 J10
0 VCCO_0 F11
0 VCCO_0 C6
0 VCCO_0 B11
1 VCCO_1 J15
1 VCCO_1 J14
1 VCCO_1 J13
1 VCCO_1 F14
1 VCCO_1 C19
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
66 1-800-255-7778 Advance Product Specification
1 VCCO_1 B14
2 VCCO_2 M16
2 VCCO_2 L23
2 VCCO_2 L19
2 VCCO_2 L16
2 VCCO_2 K16
2 VCCO_2 F22
3 VCCO_3 W22
3 VCCO_3 R16
3 VCCO_3 P23
3 VCCO_3 P19
3 VCCO_3 P16
3 VCCO_3 N16
4 VCCO_4 AC14
4 VCCO_4 AB19
4 VCCO_4 W14
4 VCCO_4 T15
4 VCCO_4 T14
4 VCCO_4 T13
5 VCCO_5 AC11
5 VCCO_5 AB6
5 VCCO_5 W11
5 VCCO_5 T12
5 VCCO_5 T11
5 VCCO_5 T10
6 VCCO_6 W3
6 VCCO_6 R9
6 VCCO_6 P9
6 VCCO_6 P6
6 VCCO_6 P2
6 VCCO_6 N9
7 VCCO_7 M9
7 VCCO_7 L9
7 VCCO_7 L6
7 VCCO_7 L2
7 VCCO_7 K9
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 67
7 VCCO_7 F3
NA CCLK AB23
NA PROG_B C1
NA DONE AB21
NA M0 AC4
NA M1 AB4
NA M2 AD3
NA HSWAP_EN C2
NA TCK C23
NA TDI D1
NA TDO C24
NA TMS C21
NA PWRDWN_B AC21
NA DXN B4
NA DXP C4
NA VBATT B21
NA RSVD A22
NA VCCAUX AD13
NA VCCAUX AC22
NA VCCAUX AC3
NA VCCAUX N1
NA VCCAUX M24
NA VCCAUX B22
NA VCCAUX B3
NA VCCAUX A12
NA VCCINT U17
NA VCCINT U8
NA VCCINT T16
NA VCCINT T9
NA VCCINT R15
NA VCCINT R14
NA VCCINT R13
NA VCCINT R12
NA VCCINT R11
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
68 1-800-255-7778 Advance Product Specification
NA VCCINT R10
NA VCCINT P15
NA VCCINT P10
NA VCCINT N15
NA VCCINT N10
NA VCCINT M15
NA VCCINT M10
NA VCCINT L15
NA VCCINT L10
NA VCCINT K15
NA VCCINT K14
NA VCCINT K13
NA VCCINT K12
NA VCCINT K11
NA VCCINT K10
NA VCCINT J16
NA VCCINT J9
NA VCCINT H17
NA VCCINT H8
NA GND AD24
NA GND AD23
NA GND AD18
NA GND AD7
NA GND AD2
NA GND AD1
NA GND AC24
NA GND AC23
NA GND AC2
NA GND AC1
NA GND AB22
NA GND AB3
NA GND AA21
NA GND AA15
NA GND AA10
NA GND AA4
NA GND Y20
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 69
NA GND Y5
NA GND W19
NA GND W6
NA GND V24
NA GND V18
NA GND V7
NA GND V1
NA GND R21
NA GND R4
NA GND P14
NA GND P13
NA GND P12
NA GND P11
NA GND N14
NA GND N13
NA GND N12
NA GND N11
NA GND M14
NA GND M13
NA GND M12
NA GND M11
NA GND L14
NA GND L13
NA GND L12
NA GND L11
NA GND K21
NA GND K4
NA GND G24
NA GND G18
NA GND G7
NA GND G1
NA GND F19
NA GND F6
NA GND E20
NA GND E5
NA GND D21
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
70 1-800-255-7778 Advance Product Specification
NA GND D15
NA GND D10
NA GND D4
NA GND C22
NA GND C3
NA GND B24
NA GND B23
NA GND B2
NA GND B1
NA GND A24
NA GND A23
NA GND A18
NA GND A7
NA GND A2
Table 9: BG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in XC2V1000 No Connect in XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
72 1-800-255-7778 Advance Product Specification
BG728 Standard BGA Package
As shown in Table 10, XC2V2000 and XC2V3000 Virtex-II devices are available in the BG728 BGA package. Pins in the
XC2V2000 and XC2V3000 devices are the same, except for the pin differences in the XC2V2000 device, shown in the No
Connect column. Following this table are the BG728 Standard BGA Package Specifications (1.27mm pitch).
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
0 IO_L01N_0 B3
0 IO_L01P_0 A3
0 IO_L02N_0 B4
0 IO_L02P_0 A4
0 IO_L03N_0/VRP_0 C5
0 IO_L03P_0/VRN_0 C6
0 IO_L04N_0/VREF_0 B5
0 IO_L04P_0 A5
0 IO_L05N_0 E6
0 IO_L05P_0 D6
0 IO_L06N_0 B6
0 IO_L06P_0 A6
0 IO_L19N_0 E7
0 IO_L19P_0 D8
0 IO_L21N_0 F8
0 IO_L21P_0/VREF_0 E8
0 IO_L22N_0 C7
0 IO_L22P_0 C8
0 IO_L24N_0 B7
0 IO_L24P_0 A7
0 IO_L25N_0 H9 NC
0 IO_L25P_0 J9 NC
0 IO_L27N_0 F9 NC
0 IO_L27P_0/VREF_0 G9 NC
0 IO_L28N_0 E9 NC
0 IO_L28P_0 D9 NC
0 IO_L30N_0 C9 NC
0 IO_L30P_0 B9 NC
0 IO_L49N_0 A8
0 IO_L49P_0 A9
0 IO_L51N_0 G10
0 IO_L51P_0/VREF_0 H10
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 73
0 IO_L52N_0 F10
0 IO_L52P_0 E10
0 IO_L54N_0 D10
0 IO_L54P_0 C10
0 IO_L67N_0 B10
0 IO_L67P_0 A10
0 IO_L69N_0 G11
0 IO_L69P_0/VREF_0 H11
0 IO_L70N_0 F11
0 IO_L70P_0 F12
0 IO_L72N_0 D11
0 IO_L72P_0 C11
0 IO_L73N_0 B11
0 IO_L73P_0 A11
0 IO_L75N_0 H12
0 IO_L75P_0/VREF_0 J12
0 IO_L76N_0 E12
0 IO_L76P_0 D12
0 IO_L78N_0 B12
0 IO_L78P_0 A12
0 IO_L91N_0/VREF_0 J13
0 IO_L91P_0 H13
0 IO_L92N_0 G13
0 IO_L92P_0 F13
0 IO_L93N_0 E13
0 IO_L93P_0 D13
0 IO_L94N_0/VREF_0 B13
0 IO_L94P_0 A13
0 IO_L95N_0/GCLK7P C13
0 IO_L95P_0/GCLK6S C14
0 IO_L96N_0/GCLK5P F14
0 IO_L96P_0/GCLK4S E14
1 IO_L96N_1/GCLK3P G14
1 IO_L96P_1/GCLK2S H14
1 IO_L95N_1/GCLK1P A15
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
74 1-800-255-7778 Advance Product Specification
1 IO_L95P_1/GCLK0S B15
1 IO_L94N_1 C15
1 IO_L94P_1/VREF_1 D15
1 IO_L93N_1 E15
1 IO_L93P_1 F15
1 IO_L92N_1 G15
1 IO_L92P_1 H15
1 IO_L91N_1 J15
1 IO_L91P_1/VREF_1 J16
1 IO_L78N_1 A16
1 IO_L78P_1 B16
1 IO_L76N_1 D16
1 IO_L76P_1 E16
1 IO_L75N_1/VREF_1 F16
1 IO_L75P_1 F17
1 IO_L73N_1 H16
1 IO_L73P_1 H17
1 IO_L72N_1 A17
1 IO_L72P_1 B17
1 IO_L70N_1 C17
1 IO_L70P_1 D17
1 IO_L69N_1/VREF_1 G18
1 IO_L69P_1 G17
1 IO_L67N_1 A18
1 IO_L67P_1 B18
1 IO_L54N_1 C18
1 IO_L54P_1 D18
1 IO_L52N_1 E18
1 IO_L52P_1 F18
1 IO_L51N_1/VREF_1 H19
1 IO_L51P_1 H18
1 IO_L49N_1 A19
1 IO_L49P_1 A20
1 IO_L30N_1 B19 NC
1 IO_L30P_1 C19 NC
1 IO_L28N_1 D19 NC
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 75
1 IO_L28P_1 E19 NC
1 IO_L27N_1/VREF_1 F19 NC
1 IO_L27P_1 G19 NC
1 IO_L25N_1 J19 NC
1 IO_L25P_1 J20 NC
1 IO_L24N_1 C20
1 IO_L24P_1 C21
1 IO_L22N_1 D20
1 IO_L22P_1 E21
1 IO_L21N_1/VREF_1 E20
1 IO_L21P_1 F20
1 IO_L19N_1 A21
1 IO_L19P_1 B21
1 IO_L06N_1 A22
1 IO_L06P_1 B22
1 IO_L05N_1 C22
1 IO_L05P_1 C23
1 IO_L04N_1 D22
1 IO_L04P_1/VREF_1 E22
1 IO_L03N_1/VRP_1 A23
1 IO_L03P_1/VRN_1 B23
1 IO_L02N_1 A24
1 IO_L02P_1 B24
1 IO_L01N_1 A25
1 IO_L01P_1 B25
2 IO_L01N_2 C27
2 IO_L01P_2 D27
2 IO_L02N_2/VRP_2 D25
2 IO_L02P_2/VRN_2 D26
2 IO_L03N_2 E24
2 IO_L03P_2/VREF_2 E25
2 IO_L04N_2 E26
2 IO_L04P_2 E27
2 IO_L06N_2 F23
2 IO_L06P_2 F24
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
76 1-800-255-7778 Advance Product Specification
2 IO_L19N_2 F25
2 IO_L19P_2 F26
2 IO_L21N_2 F27
2 IO_L21P_2/VREF_2 G27
2 IO_L22N_2 G23
2 IO_L22P_2 H23
2 IO_L24N_2 G25
2 IO_L24P_2 G26
2 IO_L25N_2 H21 NC
2 IO_L25P_2 J21 NC
2 IO_L27N_2 H22 NC
2 IO_L27P_2/VREF_2 J22 NC
2 IO_L28N_2 H24 NC
2 IO_L28P_2 H25 NC
2 IO_L30N_2 H27 NC
2 IO_L30P_2 J27 NC
2 IO_L43N_2 J23
2 IO_L43P_2 J24
2 IO_L45N_2 J25
2 IO_L45P_2/VREF_2 J26
2 IO_L46N_2 K20
2 IO_L46P_2 K21
2 IO_L48N_2 K22
2 IO_L48P_2 K23
2 IO_L49N_2 K24
2 IO_L49P_2 K25
2 IO_L51N_2 K26
2 IO_L51P_2/VREF_2 K27
2 IO_L52N_2 L20
2 IO_L52P_2 M20
2 IO_L54N_2 L21
2 IO_L54P_2 L22
2 IO_L67N_2 L24
2 IO_L67P_2 L25
2 IO_L69N_2 L26
2 IO_L69P_2/VREF_2 L27
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 77
2 IO_L70N_2 M19
2 IO_L70P_2 N19
2 IO_L72N_2 M22
2 IO_L72P_2 M23
2 IO_L73N_2 M24
2 IO_L73P_2 N24
2 IO_L75N_2 M26
2 IO_L75P_2/VREF_2 M27
2 IO_L76N_2 N20
2 IO_L76P_2 N21
2 IO_L78N_2 N22
2 IO_L78P_2 N23
2 IO_L91N_2 N25
2 IO_L91P_2 P25
2 IO_L93N_2 N26
2 IO_L93P_2/VREF_2 N27
2 IO_L94N_2 P20
2 IO_L94P_2 P21
2 IO_L96N_2 P22
2 IO_L96P_2 P23
3 IO_L96N_3 R27
3 IO_L96P_3 R26
3 IO_L94N_3 R25
3 IO_L94P_3 R24
3 IO_L93N_3/VREF_3 R23
3 IO_L93P_3 T23
3 IO_L91N_3 R22
3 IO_L91P_3 R21
3 IO_L78N_3 R20
3 IO_L78P_3 R19
3 IO_L76N_3 T27
3 IO_L76P_3 T26
3 IO_L75N_3/VREF_3 T24
3 IO_L75P_3 U24
3 IO_L73N_3 T22
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
78 1-800-255-7778 Advance Product Specification
3 IO_L73P_3 U22
3 IO_L72N_3 T20
3 IO_L72P_3 T19
3 IO_L70N_3 U27
3 IO_L70P_3 U26
3 IO_L69N_3/VREF_3 U25
3 IO_L69P_3 V25
3 IO_L67N_3 U21
3 IO_L67P_3 U20
3 IO_L54N_3 V27
3 IO_L54P_3 V26
3 IO_L52N_3 V24
3 IO_L52P_3 V23
3 IO_L51N_3/VREF_3 V22
3 IO_L51P_3 W22
3 IO_L49N_3 V21
3 IO_L49P_3 V20
3 IO_L48N_3 W27
3 IO_L48P_3 Y27
3 IO_L46N_3 W26
3 IO_L46P_3 W25
3 IO_L45N_3/VREF_3 W24
3 IO_L45P_3 W23
3 IO_L43N_3 W21
3 IO_L43P_3 W20
3 IO_L28N_3 W19 NC
3 IO_L28P_3 Y19 NC
3 IO_L27N_3/VREF_3 Y25 NC
3 IO_L27P_3 Y24 NC
3 IO_L25N_3 Y23 NC
3 IO_L25P_3 AA23 NC
3 IO_L24N_3 Y22
3 IO_L24P_3 Y21
3 IO_L22N_3 AA27
3 IO_L22P_3 AB27
3 IO_L21N_3/VREF_3 AA26
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 79
3 IO_L21P_3 AA25
3 IO_L19N_3 AB26
3 IO_L19P_3 AB25
3 IO_L06N_3 AB24
3 IO_L06P_3 AB23
3 IO_L04N_3 AC27
3 IO_L04P_3 AC26
3 IO_L03N_3/VREF_3 AC25
3 IO_L03P_3 AC24
3 IO_L02N_3/VRP_3 AD27
3 IO_L02P_3/VRN_3 AE27
3 IO_L01N_3 AD26
3 IO_L01P_3 AD25
4 IO_L01N_4/DOUT AF25
4 IO_L01P_4/INIT_B AG25
4 IO_L02N_4/D0 AF24
4 IO_L02P_4/D1 AG24
4 IO_L03N_4/D2/ALT_VRP_4 AD23
4 IO_L03P_4/D3/ALT_VRN_4 AE23
4 IO_L04N_4/VREF_4 AF23
4 IO_L04P_4 AG23
4 IO_L05N_4/VRP_4 AD22
4 IO_L05P_4/VRN_4 AE22
4 IO_L06N_4 AF22
4 IO_L06P_4 AG22
4 IO_L19N_4 AC21
4 IO_L19P_4 AB21
4 IO_L21N_4 AE21
4 IO_L21P_4/VREF_4 AE20
4 IO_L22N_4 AF21
4 IO_L22P_4 AG21
4 IO_L24N_4 AB20
4 IO_L24P_4 AA20
4 IO_L25N_4 AC20 NC
4 IO_L25P_4 AD20 NC
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
80 1-800-255-7778 Advance Product Specification
4 IO_L27N_4 AG20 NC
4 IO_L27P_4/VREF_4 AG19 NC
4 IO_L28N_4 AB19 NC
4 IO_L28P_4 AA19 NC
4 IO_L30N_4 AC19 NC
4 IO_L30P_4 AD19 NC
4 IO_L49N_4 AE19
4 IO_L49P_4 AF19
4 IO_L51N_4 AA18
4 IO_L51P_4/VREF_4 Y18
4 IO_L52N_4 AB18
4 IO_L52P_4 AC18
4 IO_L54N_4 AD18
4 IO_L54P_4 AE18
4 IO_L67N_4 AF18
4 IO_L67P_4 AG18
4 IO_L69N_4 AA17
4 IO_L69P_4/VREF_4 Y17
4 IO_L70N_4 AB17
4 IO_L70P_4 AB16
4 IO_L72N_4 AD17
4 IO_L72P_4 AE17
4 IO_L73N_4 AF17
4 IO_L73P_4 AG17
4 IO_L75N_4 Y16
4 IO_L75P_4/VREF_4 W16
4 IO_L76N_4 AC16
4 IO_L76P_4 AD16
4 IO_L78N_4 AF16
4 IO_L78P_4 AG16
4 IO_L91N_4/VREF_4 W15
4 IO_L91P_4 Y15
4 IO_L92N_4 AB15
4 IO_L92P_4 AA15
4 IO_L93N_4 AC15
4 IO_L93P_4 AD15
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 81
4 IO_L94N_4/VREF_4 AE15
4 IO_L94P_4 AE14
4 IO_L95N_4/GCLK3S AF15
4 IO_L95P_4/GCLK2P AG15
4 IO_L96N_4/GCLK1S Y14
4 IO_L96P_4/GCLK0P AA14
5 IO_L96N_5/GCLK7S AC14
5 IO_L96P_5/GCLK6P AB14
5 IO_L95N_5/GCLK5S AG13
5 IO_L95P_5/GCLK4P AF13
5 IO_L94N_5 AE13
5 IO_L94P_5/VREF_5 AD13
5 IO_L93N_5 AC13
5 IO_L93P_5 AB13
5 IO_L92N_5 AA13
5 IO_L92P_5 Y13
5 IO_L91N_5 W13
5 IO_L91P_5/VREF_5 W12
5 IO_L78N_5 AG12
5 IO_L78P_5 AF12
5 IO_L76N_5 AD12
5 IO_L76P_5 AC12
5 IO_L75N_5/VREF_5 AB12
5 IO_L75P_5 AB11
5 IO_L73N_5 Y12
5 IO_L73P_5 Y11
5 IO_L72N_5 AG11
5 IO_L72P_5 AF11
5 IO_L70N_5 AE11
5 IO_L70P_5 AD11
5 IO_L69N_5/VREF_5 AA10
5 IO_L69P_5 AA11
5 IO_L67N_5 AG10
5 IO_L67P_5 AF10
5 IO_L54N_5 AE10
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
82 1-800-255-7778 Advance Product Specification
5 IO_L54P_5 AD10
5 IO_L52N_5 AC10
5 IO_L52P_5 AB10
5 IO_L51N_5/VREF_5 Y9
5 IO_L51P_5 Y10
5 IO_L49N_5 AG9
5 IO_L49P_5 AG8
5 IO_L30N_5 AF9 NC
5 IO_L30P_5 AE9 NC
5 IO_L28N_5 AD9 NC
5 IO_L28P_5 AC9 NC
5 IO_L27N_5/VREF_5 AB9 NC
5 IO_L27P_5 AA9 NC
5 IO_L25N_5 AE8 NC
5 IO_L25P_5 AE7 NC
5 IO_L24N_5 AD8
5 IO_L24P_5 AC8
5 IO_L22N_5 AB8
5 IO_L22P_5 AA8
5 IO_L21N_5/VREF_5 AG7
5 IO_L21P_5 AF7
5 IO_L19N_5 AC7
5 IO_L19P_5 AB7
5 IO_L06N_5 AG6
5 IO_L06P_5 AF6
5 IO_L05N_5/VRP_5 AE6
5 IO_L05P_5/VRN_5 AD6
5 IO_L04N_5 AG5
5 IO_L04P_5/VREF_5 AF5
5 IO_L03N_5/D4/ALT_VRP_5 AE5
5 IO_L03P_5/D5/ALT_VRN_5 AD5
5 IO_L02N_5/D6 AG4
5 IO_L02P_5/D7 AF4
5 IO_L01N_5/RDWR_B AG3
5 IO_L01P_5/CS_B AF3
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 83
6 IO_L01P_6 AE1
6 IO_L01N_6 AD1
6 IO_L02P_6/VRN_6 AD3
6 IO_L02N_6/VRP_6 AD2
6 IO_L03P_6 AC4
6 IO_L03N_6/VREF_6 AC3
6 IO_L04P_6 AC2
6 IO_L04N_6 AC1
6 IO_L06P_6 AB5
6 IO_L06N_6 AB4
6 IO_L19P_6 AB3
6 IO_L19N_6 AB2
6 IO_L21P_6 AB1
6 IO_L21N_6/VREF_6 AA1
6 IO_L22P_6 AA5
6 IO_L22N_6 AA6
6 IO_L24P_6 AA3
6 IO_L24N_6 AA2
6 IO_L25P_6 Y5 NC
6 IO_L25N_6 Y6 NC
6 IO_L27P_6 Y4 NC
6 IO_L27N_6/VREF_6 Y3 NC
6 IO_L28P_6 Y1 NC
6 IO_L28N_6 W1 NC
6 IO_L43P_6 W8
6 IO_L43N_6 W9
6 IO_L45P_6 W6
6 IO_L45N_6/VREF_6 W7
6 IO_L46P_6 W5
6 IO_L46N_6 W4
6 IO_L48P_6 W3
6 IO_L48N_6 W2
6 IO_L49P_6 V7
6 IO_L49N_6 V8
6 IO_L51P_6 V5
6 IO_L51N_6/VREF_6 V6
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
84 1-800-255-7778 Advance Product Specification
6 IO_L52P_6 V4
6 IO_L52N_6 V3
6 IO_L54P_6 V2
6 IO_L54N_6 V1
6 IO_L67P_6 U8
6 IO_L67N_6 T8
6 IO_L69P_6 U6
6 IO_L69N_6/VREF_6 U7
6 IO_L70P_6 U4
6 IO_L70N_6 U3
6 IO_L72P_6 U2
6 IO_L72N_6 U1
6 IO_L73P_6 T9
6 IO_L73N_6 R9
6 IO_L75P_6 T5
6 IO_L75N_6/VREF_6 T6
6 IO_L76P_6 T4
6 IO_L76N_6 R4
6 IO_L78P_6 T2
6 IO_L78N_6 T1
6 IO_L91P_6 R7
6 IO_L91N_6 R8
6 IO_L93P_6 R5
6 IO_L93N_6/VREF_6 R6
6 IO_L94P_6 R3
6 IO_L94N_6 P3
6 IO_L96P_6 R2
6 IO_L96N_6 R1
7 IO_L96P_7 P5
7 IO_L96N_7 P6
7 IO_L94P_7 P7
7 IO_L94N_7 P8
7 IO_L93P_7/VREF_7 N1
7 IO_L93N_7 N2
7 IO_L91P_7 N3
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 85
7 IO_L91N_7 N4
7 IO_L78P_7 N6
7 IO_L78N_7 N7
7 IO_L76P_7 N9
7 IO_L76N_7 N8
7 IO_L75P_7/VREF_7 N5
7 IO_L75N_7 M6
7 IO_L73P_7 M1
7 IO_L73N_7 M2
7 IO_L72P_7 M4
7 IO_L72N_7 M5
7 IO_L70P_7 M8
7 IO_L70N_7 M9
7 IO_L69P_7/VREF_7 L1
7 IO_L69N_7 L2
7 IO_L67P_7 L3
7 IO_L67N_7 L4
7 IO_L54P_7 K1
7 IO_L54N_7 K2
7 IO_L52P_7 K4
7 IO_L52N_7 K5
7 IO_L51P_7/VREF_7 L6
7 IO_L51N_7 L7
7 IO_L49P_7 K6
7 IO_L49N_7 K7
7 IO_L48P_7 L8
7 IO_L48N_7 K8
7 IO_L46P_7 J1
7 IO_L46N_7 H1
7 IO_L45P_7/VREF_7 J2
7 IO_L45N_7 J3
7 IO_L43P_7 K3
7 IO_L43N_7 J4
7 IO_L30P_7 H3 NC
7 IO_L30N_7 H4 NC
7 IO_L28P_7 J5 NC
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
86 1-800-255-7778 Advance Product Specification
7 IO_L28N_7 J6 NC
7 IO_L27P_7/VREF_7 H5 NC
7 IO_L27N_7 H6 NC
7 IO_L25P_7 J7 NC
7 IO_L25N_7 J8 NC
7 IO_L24P_7 G1
7 IO_L24N_7 F1
7 IO_L22P_7 G2
7 IO_L22N_7 G3
7 IO_L21P_7/VREF_7 F2
7 IO_L21N_7 F3
7 IO_L19P_7 G5
7 IO_L19N_7 G6
7 IO_L06P_7 F4
7 IO_L06N_7 F5
7 IO_L04P_7 E1
7 IO_L04N_7 E2
7 IO_L03P_7/VREF_7 D1
7 IO_L03N_7 C1
7 IO_L02P_7/VRN_7 E3
7 IO_L02N_7/VRP_7 E4
7 IO_L01P_7 D2
7 IO_L01N_7 D3
0 VCCO_0 K13
0 VCCO_0 K12
0 VCCO_0 K11
0 VCCO_0 J11
0 VCCO_0 J10
0 VCCO_0 G12
0 VCCO_0 D7
0 VCCO_0 C12
1 VCCO_1 K17
1 VCCO_1 K16
1 VCCO_1 K15
1 VCCO_1 J18
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 87
1 VCCO_1 J17
1 VCCO_1 G16
1 VCCO_1 D21
1 VCCO_1 C16
2 VCCO_2 N18
2 VCCO_2 M25
2 VCCO_2 M21
2 VCCO_2 M18
2 VCCO_2 L19
2 VCCO_2 L18
2 VCCO_2 K19
2 VCCO_2 G24
3 VCCO_3 AA24
3 VCCO_3 V19
3 VCCO_3 U19
3 VCCO_3 U18
3 VCCO_3 T25
3 VCCO_3 T21
3 VCCO_3 T18
3 VCCO_3 R18
4 VCCO_4 AE16
4 VCCO_4 AD21
4 VCCO_4 AA16
4 VCCO_4 W18
4 VCCO_4 W17
4 VCCO_4 V17
4 VCCO_4 V16
4 VCCO_4 V15
5 VCCO_5 AE12
5 VCCO_5 AD7
5 VCCO_5 AA12
5 VCCO_5 W11
5 VCCO_5 W10
5 VCCO_5 V13
5 VCCO_5 V12
5 VCCO_5 V11
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
88 1-800-255-7778 Advance Product Specification
6 VCCO_6 AA4
6 VCCO_6 V9
6 VCCO_6 U10
6 VCCO_6 U9
6 VCCO_6 T10
6 VCCO_6 T7
6 VCCO_6 T3
6 VCCO_6 R10
7 VCCO_7 M10
7 VCCO_7 M7
7 VCCO_7 M3
7 VCCO_7 L10
7 VCCO_7 L9
7 VCCO_7 K9
7 VCCO_7 G4
7 VCCO_7 N10
NA CCLK AA22
NA PROG_B C4
NA DONE AC22
NA M0 AC6
NA M1 Y7
NA M2 AE4
NA HSWAP_EN D5
NA TCK G20
NA TDI H7
NA TDO G22
NA TMS F21
NA PWRDWN_B AE24
NA DXN G8
NA DXP F7
NA VBATT D23
NA RSVD C24
NA VCCAUX AF14
NA VCCAUX AE26
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 89
NA VCCAUX AE2
NA VCCAUX P26
NA VCCAUX P2
NA VCCAUX C26
NA VCCAUX C2
NA VCCAUX B14
NA VCCINT V18
NA VCCINT V14
NA VCCINT V10
NA VCCINT U17
NA VCCINT U16
NA VCCINT U15
NA VCCINT U14
NA VCCINT U13
NA VCCINT U12
NA VCCINT U11
NA VCCINT T17
NA VCCINT T11
NA VCCINT R17
NA VCCINT R11
NA VCCINT P18
NA VCCINT P17
NA VCCINT P11
NA VCCINT P10
NA VCCINT N17
NA VCCINT N11
NA VCCINT M17
NA VCCINT M11
NA VCCINT L17
NA VCCINT L16
NA VCCINT L15
NA VCCINT L14
NA VCCINT L13
NA VCCINT L12
NA VCCINT L11
NA VCCINT K18
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
90 1-800-255-7778 Advance Product Specification
NA VCCINT K14
NA VCCINT K10
NA GND AG27
NA GND AG26
NA GND AG14
NA GND AG2
NA GND AG1
NA GND AF27
NA GND AF26
NA GND AF20
NA GND AF8
NA GND AF2
NA GND AF1
NA GND AE25
NA GND AE3
NA GND AD24
NA GND AD14
NA GND AD4
NA GND AC23
NA GND AC17
NA GND AC11
NA GND AC5
NA GND AB22
NA GND AB6
NA GND AA21
NA GND AA7
NA GND Y26
NA GND Y20
NA GND Y8
NA GND Y2
NA GND W14
NA GND U23
NA GND U5
NA GND T16
NA GND T15
NA GND T14
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 91
NA GND T13
NA GND T12
NA GND R16
NA GND R15
NA GND R14
NA GND R13
NA GND R12
NA GND P27
NA GND P24
NA GND P19
NA GND P16
NA GND P15
NA GND P14
NA GND P13
NA GND P12
NA GND P9
NA GND P4
NA GND P1
NA GND N16
NA GND N15
NA GND N14
NA GND N13
NA GND N12
NA GND M16
NA GND M15
NA GND M14
NA GND M13
NA GND M12
NA GND L23
NA GND L5
NA GND J14
NA GND H26
NA GND H20
NA GND H8
NA GND H2
NA GND G21
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
92 1-800-255-7778 Advance Product Specification
NA GND G7
NA GND F22
NA GND F6
NA GND E23
NA GND E17
NA GND E11
NA GND E5
NA GND D24
NA GND D14
NA GND D4
NA GND C25
NA GND C3
NA GND B27
NA GND B26
NA GND B20
NA GND B8
NA GND B2
NA GND B1
NA GND A27
NA GND A26
NA GND A14
NA GND A2
Table 10: BG728 BGA — XC2V2000 and XC2V3000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
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94 1-800-255-7778 Advance Product Specification
FF896 Flip-Chip Fine-Pitch BGA Package
As shown in Table 11, XC2V1000, XC2V1500, and XC2V2000 Virtex-II devices are available in the FF896 flip-chip fine-pitch
BGA package. Pins in the XC2V1000, XC2V1500, and XC2V2000 devices are the same, except for the pin differences in the
XC2V1000 and XC2V1500 devices shown in the No Connect columns. Following this table are the FF896 Flip-Chip
Fine-Pitch BGA Package Specifications (1.00mm pitch).
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
0 IO_L01N_0 B27
0 IO_L01P_0 A27
0 IO_L02N_0 F24
0 IO_L02P_0 E24
0 IO_L03N_0/VRP_0 C26
0 IO_L03P_0/VRN_0 C25
0 IO_L04N_0/VREF_0 A26
0 IO_L04P_0 A25
0 IO_L05N_0 F23
0 IO_L05P_0 F22
0 IO_L06N_0 C24
0 IO_L06P_0 D25
0 IO_L19N_0 A24
0 IO_L19P_0 B25
0 IO_L20N_0 G22
0 IO_L20P_0 G21
0 IO_L21N_0 D24
0 IO_L21P_0/VREF_0 D23
0 IO_L22N_0 B23
0 IO_L22P_0 B24
0 IO_L23N_0 H21
0 IO_L23P_0 H20
0 IO_L24N_0 E22
0 IO_L24P_0 E23
0 IO_L49N_0 A22
0 IO_L49P_0 B22
0 IO_L50N_0 F21
0 IO_L50P_0 F20
0 IO_L51N_0 C23
0 IO_L51P_0/VREF_0 C22
0 IO_L52N_0 B20
0 IO_L52P_0 B21
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 95
0 IO_L53N_0 G20
0 IO_L53P_0 G19
0 IO_L54N_0 D21
0 IO_L54P_0 D22
0 IO_L67N_0 E20 NC
0 IO_L67P_0 E21 NC
0 IO_L68N_0 H19 NC
0 IO_L68P_0 H18 NC
0 IO_L69N_0 D20 NC
0 IO_L69P_0/VREF_0 D19 NC
0 IO_L70N_0 A20 NC
0 IO_L70P_0 A21 NC
0 IO_L71N_0 F19 NC
0 IO_L71P_0 F18 NC
0 IO_L72N_0 C19 NC
0 IO_L72P_0 C20 NC
0 IO_L73N_0 B18 NC NC
0 IO_L73P_0 B19 NC NC
0 IO_L74N_0 G18 NC NC
0 IO_L74P_0 H17 NC NC
0 IO_L75N_0 E18 NC NC
0 IO_L75P_0/VREF_0 D18 NC NC
0 IO_L76N_0 A18 NC NC
0 IO_L76P_0 A19 NC NC
0 IO_L77N_0 J17 NC NC
0 IO_L77P_0 J16 NC NC
0 IO_L78N_0 E16 NC NC
0 IO_L78P_0 E17 NC NC
0 IO_L91N_0/VREF_0 B17
0 IO_L91P_0 B16
0 IO_L92N_0 F17
0 IO_L92P_0 F16
0 IO_L93N_0 D16
0 IO_L93P_0 D17
0 IO_L94N_0/VREF_0 A17
0 IO_L94P_0 A16
0 IO_L95N_0/GCLK7P H16
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
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96 1-800-255-7778 Advance Product Specification
0 IO_L95P_0/GCLK6S G16
0 IO_L96N_0/GCLK5P C17
0 IO_L96P_0/GCLK4S C16
1 IO_L96N_1/GCLK3P C15
1 IO_L96P_1/GCLK2S C14
1 IO_L95N_1/GCLK1P F15
1 IO_L95P_1/GCLK0S F14
1 IO_L94N_1 B15
1 IO_L94P_1/VREF_1 B14
1 IO_L93N_1 D14
1 IO_L93P_1 D15
1 IO_L92N_1 G15
1 IO_L92P_1 H15
1 IO_L91N_1 A14
1 IO_L91P_1/VREF_1 A13
1 IO_L78N_1 E14 NC NC
1 IO_L78P_1 E15 NC NC
1 IO_L77N_1 J15 NC NC
1 IO_L77P_1 J14 NC NC
1 IO_L76N_1 B12 NC NC
1 IO_L76P_1 B13 NC NC
1 IO_L75N_1/VREF_1 D13 NC NC
1 IO_L75P_1 E13 NC NC
1 IO_L74N_1 H14 NC NC
1 IO_L74P_1 H13 NC NC
1 IO_L73N_1 A11 NC NC
1 IO_L73P_1 A12 NC NC
1 IO_L72N_1 C11 NC
1 IO_L72P_1 C12 NC
1 IO_L71N_1 F13 NC
1 IO_L71P_1 F12 NC
1 IO_L70N_1 B10 NC
1 IO_L70P_1 B11 NC
1 IO_L69N_1/VREF_1 D12 NC
1 IO_L69P_1 D11 NC
1 IO_L68N_1 G13 NC
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 97
1 IO_L68P_1 G12 NC
1 IO_L67N_1 A9 NC
1 IO_L67P_1 A10 NC
1 IO_L54N_1 E10
1 IO_L54P_1 E11
1 IO_L53N_1 H12
1 IO_L53P_1 H11
1 IO_L52N_1 D9
1 IO_L52P_1 D10
1 IO_L51N_1/VREF_1 C9
1 IO_L51P_1 C8
1 IO_L50N_1 F11
1 IO_L50P_1 F10
1 IO_L49N_1 B8
1 IO_L49P_1 B9
1 IO_L24N_1 E8
1 IO_L24P_1 E9
1 IO_L23N_1 G11
1 IO_L23P_1 H10
1 IO_L22N_1 B7
1 IO_L22P_1 A7
1 IO_L21N_1/VREF_1 D8
1 IO_L21P_1 E7
1 IO_L20N_1 G10
1 IO_L20P_1 G9
1 IO_L19N_1 A5
1 IO_L19P_1 A6
1 IO_L06N_1 C6
1 IO_L06P_1 C7
1 IO_L05N_1 F9
1 IO_L05P_1 G8
1 IO_L04N_1 B6
1 IO_L04P_1/VREF_1 C5
1 IO_L03N_1/VRP_1 D7
1 IO_L03P_1/VRN_1 D6
1 IO_L02N_1 F8
1 IO_L02P_1 F7
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
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98 1-800-255-7778 Advance Product Specification
1 IO_L01N_1 B4
1 IO_L01P_1 A4
2 IO_L01N_2 C1
2 IO_L01P_2 B1
2 IO_L02N_2/VRP_2 H9
2 IO_L02P_2/VRN_2 H8
2 IO_L03N_2 D3
2 IO_L03P_2/VREF_2 E3
2 IO_L04N_2 D2
2 IO_L04P_2 C2
2 IO_L05N_2 G7
2 IO_L05P_2 H7
2 IO_L06N_2 F4
2 IO_L06P_2 E4
2 IO_L19N_2 E1
2 IO_L19P_2 D1
2 IO_L20N_2 G6
2 IO_L20P_2 H6
2 IO_L21N_2 F5
2 IO_L21P_2/VREF_2 G5
2 IO_L22N_2 G2
2 IO_L22P_2 F2
2 IO_L23N_2 J8
2 IO_L23P_2 J7
2 IO_L24N_2 G3
2 IO_L24P_2 F3
2 IO_L43N_2 G1
2 IO_L43P_2 F1
2 IO_L44N_2 K8
2 IO_L44P_2 L8
2 IO_L45N_2 G4
2 IO_L45P_2/VREF_2 H4
2 IO_L46N_2 J2
2 IO_L46P_2 H2
2 IO_L47N_2 J6
2 IO_L47P_2 K6
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 99
2 IO_L48N_2 J5
2 IO_L48P_2 H5
2 IO_L49N_2 J3
2 IO_L49P_2 H3
2 IO_L50N_2 K7
2 IO_L50P_2 L7
2 IO_L51N_2 J4
2 IO_L51P_2/VREF_2 K4
2 IO_L52N_2 K1
2 IO_L52P_2 J1
2 IO_L53N_2 L6
2 IO_L53P_2 M6
2 IO_L54N_2 L5
2 IO_L54P_2 K5
2 IO_L67N_2 L2 NC
2 IO_L67P_2 K2 NC
2 IO_L68N_2 M8 NC
2 IO_L68P_2 N8 NC
2 IO_L69N_2 L4 NC
2 IO_L69P_2/VREF_2 M4 NC
2 IO_L70N_2 M1 NC
2 IO_L70P_2 L1 NC
2 IO_L71N_2 M7 NC
2 IO_L71P_2 N7 NC
2 IO_L72N_2 M3 NC
2 IO_L72P_2 L3 NC
2 IO_L73N_2 N2 NC NC
2 IO_L73P_2 M2 NC NC
2 IO_L74N_2 N6 NC NC
2 IO_L74P_2 P6 NC NC
2 IO_L75N_2 N5 NC NC
2 IO_L75P_2/VREF_2 N4 NC NC
2 IO_L76N_2 P1 NC NC
2 IO_L76P_2 N1 NC NC
2 IO_L77N_2 P9 NC NC
2 IO_L77P_2 R9 NC NC
2 IO_L78N_2 R5 NC NC
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
100 1-800-255-7778 Advance Product Specification
2 IO_L78P_2 P5 NC NC
2 IO_L91N_2 R2
2 IO_L91P_2 P2
2 IO_L92N_2 P8
2 IO_L92P_2 R8
2 IO_L93N_2 P4
2 IO_L93P_2/VREF_2 R4
2 IO_L94N_2 R1
2 IO_L94P_2 T2
2 IO_L95N_2 R7
2 IO_L95P_2 R6
2 IO_L96N_2 R3
2 IO_L96P_2 P3
3 IO_L96N_3 T7
3 IO_L96P_3 T6
3 IO_L95N_3 U1
3 IO_L95P_3 V1
3 IO_L94N_3 T3
3 IO_L94P_3 U3
3 IO_L93N_3/VREF_3 T8
3 IO_L93P_3 U8
3 IO_L92N_3 U2
3 IO_L92P_3 V2
3 IO_L91N_3 T4
3 IO_L91P_3 U4
3 IO_L78N_3 U9 NC NC
3 IO_L78P_3 T9 NC NC
3 IO_L77N_3 W1 NC NC
3 IO_L77P_3 Y1 NC NC
3 IO_L76N_3 T5 NC NC
3 IO_L76P_3 U5 NC NC
3 IO_L75N_3/VREF_3 U6 NC NC
3 IO_L75P_3 V6 NC NC
3 IO_L74N_3 W2 NC NC
3 IO_L74P_3 Y2 NC NC
3 IO_L73N_3 V4 NC NC
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 101
3 IO_L73P_3 W4 NC NC
3 IO_L72N_3 W7 NC
3 IO_L72P_3 V7 NC
3 IO_L71N_3 V5 NC
3 IO_L71P_3 W6 NC
3 IO_L70N_3 W3 NC
3 IO_L70P_3 Y3 NC
3 IO_L69N_3/VREF_3 V8 NC
3 IO_L69P_3 W8 NC
3 IO_L68N_3 AA1 NC
3 IO_L68P_3 AB1 NC
3 IO_L67N_3 Y4 NC
3 IO_L67P_3 AA4 NC
3 IO_L54N_3 AA6
3 IO_L54P_3 Y6
3 IO_L53N_3 AA2
3 IO_L53P_3 AB2
3 IO_L52N_3 Y5
3 IO_L52P_3 AA5
3 IO_L51N_3/VREF_3 Y8
3 IO_L51P_3 AA8
3 IO_L50N_3 AC2
3 IO_L50P_3 AD2
3 IO_L49N_3 Y7
3 IO_L49P_3 AA7
3 IO_L48N_3 AC6
3 IO_L48P_3 AB6
3 IO_L47N_3 AD1
3 IO_L47P_3 AE1
3 IO_L46N_3 AB3
3 IO_L46P_3 AC3
3 IO_L45N_3/VREF_3 AB7
3 IO_L45P_3 AC7
3 IO_L44N_3 AB4
3 IO_L44P_3 AC4
3 IO_L43N_3 AB5
3 IO_L43P_3 AC5
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
102 1-800-255-7778 Advance Product Specification
3 IO_L24N_3 AC8
3 IO_L24P_3 AB8
3 IO_L23N_3 AE2
3 IO_L23P_3 AF3
3 IO_L22N_3 AD3
3 IO_L22P_3 AE3
3 IO_L21N_3/VREF_3 AD6
3 IO_L21P_3 AD7
3 IO_L20N_3 AF1
3 IO_L20P_3 AG1
3 IO_L19N_3 AD4
3 IO_L19P_3 AE4
3 IO_L06N_3 AD8
3 IO_L06P_3 AE7
3 IO_L05N_3 AG2
3 IO_L05P_3 AH2
3 IO_L04N_3 AD5
3 IO_L04P_3 AE5
3 IO_L03N_3/VREF_3 AC9
3 IO_L03P_3 AD9
3 IO_L02N_3/VRP_3 AH1
3 IO_L02P_3/VRN_3 AJ1
3 IO_L01N_3 AF4
3 IO_L01P_3 AG3
4 IO_L01N_4/DOUT AK2
4 IO_L01P_4/INIT_B AJ3
4 IO_L02N_4/D0 AE8
4 IO_L02P_4/D1 AF9
4 IO_L03N_4/D2/ALT_VRP_4 AH5
4 IO_L03P_4/D3/ALT_VRN_4 AH6
4 IO_L04N_4/VREF_4 AJ4
4 IO_L04P_4 AK4
4 IO_L05N_4/VRP_4 AC10
4 IO_L05P_4/VRN_4 AC11
4 IO_L06N_4 AH7
4 IO_L06P_4 AG6
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 103
4 IO_L19N_4 AK6
4 IO_L19P_4 AK5
4 IO_L20N_4 AE9
4 IO_L20P_4 AE10
4 IO_L21N_4 AF7
4 IO_L21P_4/VREF_4 AF8
4 IO_L22N_4 AK7
4 IO_L22P_4 AJ6
4 IO_L23N_4 AD10
4 IO_L23P_4 AD11
4 IO_L24N_4 AG8
4 IO_L24P_4 AG7
4 IO_L49N_4 AJ8
4 IO_L49P_4 AJ7
4 IO_L50N_4 AE11
4 IO_L50P_4 AE12
4 IO_L51N_4 AG9
4 IO_L51P_4/VREF_4 AG10
4 IO_L52N_4 AK9
4 IO_L52P_4 AJ9
4 IO_L53N_4 AH8
4 IO_L53P_4 AH9
4 IO_L54N_4 AF11
4 IO_L54P_4 AF10
4 IO_L67N_4 AJ11 NC
4 IO_L67P_4 AJ10 NC
4 IO_L68N_4 AC12 NC
4 IO_L68P_4 AC13 NC
4 IO_L69N_4 AG11 NC
4 IO_L69P_4/VREF_4 AG12 NC
4 IO_L70N_4 AK11 NC
4 IO_L70P_4 AK10 NC
4 IO_L71N_4 AD12 NC
4 IO_L71P_4 AD13 NC
4 IO_L72N_4 AH12 NC
4 IO_L72P_4 AH11 NC
4 IO_L73N_4 AJ13 NC NC
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
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104 1-800-255-7778 Advance Product Specification
4 IO_L73P_4 AJ12 NC NC
4 IO_L74N_4 AE13 NC NC
4 IO_L74P_4 AE14 NC NC
4 IO_L75N_4 AF13 NC NC
4 IO_L75P_4/VREF_4 AG13 NC NC
4 IO_L76N_4 AK13 NC NC
4 IO_L76P_4 AK12 NC NC
4 IO_L77N_4 AB14 NC NC
4 IO_L77P_4 AB15 NC NC
4 IO_L78N_4 AF15 NC NC
4 IO_L78P_4 AF14 NC NC
4 IO_L91N_4/VREF_4 AJ14
4 IO_L91P_4 AJ15
4 IO_L92N_4 AC14
4 IO_L92P_4 AC15
4 IO_L93N_4 AG15
4 IO_L93P_4 AG14
4 IO_L94N_4/VREF_4 AK14
4 IO_L94P_4 AK15
4 IO_L95N_4/GCLK3S AD15
4 IO_L95P_4/GCLK2P AE15
4 IO_L96N_4/GCLK1S AH14
4 IO_L96P_4/GCLK0P AH15
5 IO_L96N_5/GCLK7S AH16
5 IO_L96P_5/GCLK6P AH17
5 IO_L95N_5/GCLK5S AE16
5 IO_L95P_5/GCLK4P AD16
5 IO_L94N_5 AJ16
5 IO_L94P_5/VREF_5 AJ17
5 IO_L93N_5 AG17
5 IO_L93P_5 AG16
5 IO_L92N_5 AC16
5 IO_L92P_5 AC17
5 IO_L91N_5 AK17
5 IO_L91P_5/VREF_5 AK18
5 IO_L78N_5 AF17 NC NC
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 105
5 IO_L78P_5 AF16 NC NC
5 IO_L77N_5 AB16 NC NC
5 IO_L77P_5 AB17 NC NC
5 IO_L76N_5 AJ19 NC NC
5 IO_L76P_5 AJ18 NC NC
5 IO_L75N_5/VREF_5 AG18 NC NC
5 IO_L75P_5 AF18 NC NC
5 IO_L74N_5 AE17 NC NC
5 IO_L74P_5 AE18 NC NC
5 IO_L73N_5 AK20 NC NC
5 IO_L73P_5 AK19 NC NC
5 IO_L72N_5 AH20 NC
5 IO_L72P_5 AH19 NC
5 IO_L71N_5 AD18 NC
5 IO_L71P_5 AD19 NC
5 IO_L70N_5 AJ21 NC
5 IO_L70P_5 AJ20 NC
5 IO_L69N_5/VREF_5 AG19 NC
5 IO_L69P_5 AG20 NC
5 IO_L68N_5 AC18 NC
5 IO_L68P_5 AC19 NC
5 IO_L67N_5 AK22 NC
5 IO_L67P_5 AK21 NC
5 IO_L54N_5 AF21
5 IO_L54P_5 AF20
5 IO_L53N_5 AH22
5 IO_L53P_5 AH23
5 IO_L52N_5 AG22
5 IO_L52P_5 AG21
5 IO_L51N_5/VREF_5 AF22
5 IO_L51P_5 AF23
5 IO_L50N_5 AE19
5 IO_L50P_5 AE20
5 IO_L49N_5 AJ23
5 IO_L49P_5 AJ22
5 IO_L24N_5 AF24
5 IO_L24P_5 AG23
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
106 1-800-255-7778 Advance Product Specification
5 IO_L23N_5 AD20
5 IO_L23P_5 AD21
5 IO_L22N_5 AK25
5 IO_L22P_5 AK24
5 IO_L21N_5/VREF_5 AH24
5 IO_L21P_5 AH25
5 IO_L20N_5 AE21
5 IO_L20P_5 AD22
5 IO_L19N_5 AJ25
5 IO_L19P_5 AJ24
5 IO_L06N_5 AG25
5 IO_L06P_5 AG24
5 IO_L05N_5/VRP_5 AC20
5 IO_L05P_5/VRN_5 AC21
5 IO_L04N_5 AK26
5 IO_L04P_5/VREF_5 AK27
5 IO_L03N_5/D4/ALT_VRP_5 AH26
5 IO_L03P_5/D5/ALT_VRN_5 AJ27
5 IO_L02N_5/D6 AE22
5 IO_L02P_5/D7 AE23
5 IO_L01N_5/RDWR_B AJ28
5 IO_L01P_5/CS_B AK29
6 IO_L01P_6 AC22
6 IO_L01N_6 AB23
6 IO_L02P_6/VRN_6 AG28
6 IO_L02N_6/VRP_6 AF28
6 IO_L03P_6 AJ30
6 IO_L03N_6/VREF_6 AH30
6 IO_L04P_6 AD23
6 IO_L04N_6 AC23
6 IO_L05P_6 AF27
6 IO_L05N_6 AE27
6 IO_L06P_6 AG29
6 IO_L06N_6 AH29
6 IO_L19P_6 AE24
6 IO_L19N_6 AD24
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 107
6 IO_L20P_6 AE26
6 IO_L20N_6 AD26
6 IO_L21P_6 AG30
6 IO_L21N_6/VREF_6 AF30
6 IO_L22P_6 AD25
6 IO_L22N_6 AC25
6 IO_L23P_6 AE28
6 IO_L23N_6 AD28
6 IO_L24P_6 AD29
6 IO_L24N_6 AE29
6 IO_L43P_6 AC24
6 IO_L43N_6 AB24
6 IO_L44P_6 AD27
6 IO_L44N_6 AC27
6 IO_L45P_6 AC26
6 IO_L45N_6/VREF_6 AB26
6 IO_L46P_6 AA23
6 IO_L46N_6 Y23
6 IO_L47P_6 AC28
6 IO_L47N_6 AB28
6 IO_L48P_6 AD30
6 IO_L48N_6 AE30
6 IO_L49P_6 AB25
6 IO_L49N_6 AA25
6 IO_L50P_6 AA24
6 IO_L50N_6 Y24
6 IO_L51P_6 AC29
6 IO_L51N_6/VREF_6 AB30
6 IO_L52P_6 Y25
6 IO_L52N_6 W25
6 IO_L53P_6 AB27
6 IO_L53N_6 AA27
6 IO_L54P_6 AA29
6 IO_L54N_6 AB29
6 IO_L67P_6 W23 NC
6 IO_L67N_6 V23 NC
6 IO_L68P_6 AA26 NC
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
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108 1-800-255-7778 Advance Product Specification
6 IO_L68N_6 Y26 NC
6 IO_L69P_6 AA30 NC
6 IO_L69N_6/VREF_6 Y30 NC
6 IO_L70P_6 W24 NC
6 IO_L70N_6 V24 NC
6 IO_L71P_6 Y27 NC
6 IO_L71N_6 W27 NC
6 IO_L72P_6 W28 NC
6 IO_L72N_6 Y28 NC
6 IO_L73P_6 V25 NC NC
6 IO_L73N_6 U25 NC NC
6 IO_L74P_6 V26 NC NC
6 IO_L74N_6 V27 NC NC
6 IO_L75P_6 Y29 NC NC
6 IO_L75N_6/VREF_6 W29 NC NC
6 IO_L76P_6 U22 NC NC
6 IO_L76N_6 T22 NC NC
6 IO_L77P_6 U26 NC NC
6 IO_L77N_6 T26 NC NC
6 IO_L78P_6 V30 NC NC
6 IO_L78N_6 W30 NC NC
6 IO_L91P_6 U23
6 IO_L91N_6 T23
6 IO_L92P_6 U27
6 IO_L92N_6 T27
6 IO_L93P_6 V29
6 IO_L93N_6/VREF_6 U29
6 IO_L94P_6 T24
6 IO_L94N_6 T25
6 IO_L95P_6 U28
6 IO_L95N_6 T28
6 IO_L96P_6 T30
6 IO_L96N_6 U30
7 IO_L96P_7 P28
7 IO_L96N_7 R28
7 IO_L95P_7 R25
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 109
7 IO_L95N_7 R24
7 IO_L94P_7 R29
7 IO_L94N_7 T29
7 IO_L93P_7/VREF_7 R27
7 IO_L93N_7 P27
7 IO_L92P_7 R23
7 IO_L92N_7 P23
7 IO_L91P_7 N30
7 IO_L91N_7 P30
7 IO_L78P_7 P26 NC NC
7 IO_L78N_7 R26 NC NC
7 IO_L77P_7 R22 NC NC
7 IO_L77N_7 P22 NC NC
7 IO_L76P_7 N29 NC NC
7 IO_L76N_7 P29 NC NC
7 IO_L75P_7/VREF_7 N27 NC NC
7 IO_L75N_7 N26 NC NC
7 IO_L74P_7 P25 NC NC
7 IO_L74N_7 N25 NC NC
7 IO_L73P_7 L30 NC NC
7 IO_L73N_7 M30 NC NC
7 IO_L72P_7 L28 NC
7 IO_L72N_7 M28 NC
7 IO_L71P_7 N24 NC
7 IO_L71N_7 M24 NC
7 IO_L70P_7 L29 NC
7 IO_L70N_7 M29 NC
7 IO_L69P_7/VREF_7 M27 NC
7 IO_L69N_7 L27 NC
7 IO_L68P_7 N23 NC
7 IO_L68N_7 M23 NC
7 IO_L67P_7 J30 NC
7 IO_L67N_7 K30 NC
7 IO_L54P_7 K26
7 IO_L54N_7 L26
7 IO_L53P_7 M25
7 IO_L53N_7 L25
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
110 1-800-255-7778 Advance Product Specification
7 IO_L52P_7 J29
7 IO_L52N_7 K29
7 IO_L51P_7/VREF_7 K27
7 IO_L51N_7 J27
7 IO_L50P_7 L24
7 IO_L50N_7 K24
7 IO_L49P_7 H27
7 IO_L49N_7 J28
7 IO_L48P_7 H26
7 IO_L48N_7 J26
7 IO_L47P_7 K25
7 IO_L47N_7 J25
7 IO_L46P_7 H28
7 IO_L46N_7 H29
7 IO_L45P_7/VREF_7 G28
7 IO_L45N_7 F28
7 IO_L44P_7 L23
7 IO_L44N_7 K23
7 IO_L43P_7 F30
7 IO_L43N_7 G30
7 IO_L24P_7 F26
7 IO_L24N_7 G27
7 IO_L23P_7 J24
7 IO_L23N_7 H24
7 IO_L22P_7 F29
7 IO_L22N_7 G29
7 IO_L21P_7/VREF_7 G26
7 IO_L21N_7 G25
7 IO_L20P_7 H25
7 IO_L20N_7 G24
7 IO_L19P_7 D30
7 IO_L19N_7 E30
7 IO_L06P_7 E27
7 IO_L06N_7 F27
7 IO_L05P_7 J23
7 IO_L05N_7 H22
7 IO_L04P_7 C29
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 111
7 IO_L04N_7 D29
7 IO_L03P_7/VREF_7 E28
7 IO_L03N_7 D28
7 IO_L02P_7/VRN_7 H23
7 IO_L02N_7/VRP_7 G23
7 IO_L01P_7 B30
7 IO_L01N_7 C30
0 VCCO_0 K20
0 VCCO_0 K19
0 VCCO_0 K18
0 VCCO_0 K17
0 VCCO_0 K16
0 VCCO_0 J21
0 VCCO_0 J20
0 VCCO_0 J19
0 VCCO_0 J18
0 VCCO_0 C18
0 VCCO_0 B26
1 VCCO_1 K15
1 VCCO_1 K14
1 VCCO_1 K13
1 VCCO_1 K12
1 VCCO_1 K11
1 VCCO_1 J13
1 VCCO_1 J12
1 VCCO_1 J11
1 VCCO_1 J10
1 VCCO_1 C13
1 VCCO_1 B5
2 VCCO_2 R10
2 VCCO_2 P10
2 VCCO_2 N10
2 VCCO_2 N9
2 VCCO_2 N3
2 VCCO_2 M10
2 VCCO_2 M9
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
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112 1-800-255-7778 Advance Product Specification
2 VCCO_2 L10
2 VCCO_2 L9
2 VCCO_2 K9
2 VCCO_2 E2
3 VCCO_3 AF2
3 VCCO_3 AA9
3 VCCO_3 Y10
3 VCCO_3 Y9
3 VCCO_3 W10
3 VCCO_3 W9
3 VCCO_3 V10
3 VCCO_3 V9
3 VCCO_3 V3
3 VCCO_3 U10
3 VCCO_3 T10
4 VCCO_4 AJ5
4 VCCO_4 AH13
4 VCCO_4 AB13
4 VCCO_4 AB12
4 VCCO_4 AB11
4 VCCO_4 AB10
4 VCCO_4 AA15
4 VCCO_4 AA14
4 VCCO_4 AA13
4 VCCO_4 AA12
4 VCCO_4 AA11
5 VCCO_5 AJ26
5 VCCO_5 AH18
5 VCCO_5 AB21
5 VCCO_5 AB20
5 VCCO_5 AB19
5 VCCO_5 AB18
5 VCCO_5 AA20
5 VCCO_5 AA19
5 VCCO_5 AA18
5 VCCO_5 AA17
5 VCCO_5 AA16
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 113
6 VCCO_6 AF29
6 VCCO_6 AA22
6 VCCO_6 Y22
6 VCCO_6 Y21
6 VCCO_6 W22
6 VCCO_6 W21
6 VCCO_6 V28
6 VCCO_6 V22
6 VCCO_6 V21
6 VCCO_6 U21
6 VCCO_6 T21
7 VCCO_7 R21
7 VCCO_7 P21
7 VCCO_7 N28
7 VCCO_7 N22
7 VCCO_7 N21
7 VCCO_7 M22
7 VCCO_7 M21
7 VCCO_7 L22
7 VCCO_7 L21
7 VCCO_7 K22
7 VCCO_7 E29
NA CCLK AF6
NA PROG_B B28
NA DONE AG5
NA M0 AF25
NA M1 AG26
NA M2 AH27
NA HSWAP_EN C27
NA TCK D5
NA TDI A29
NA TDO B3
NA TMS C4
NA PWRDWN_B AH4
NA DXN D26
NA DXP E25
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
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114 1-800-255-7778 Advance Product Specification
NA VBATT A2
NA RSVD E6
NA VCCAUX AK28
NA VCCAUX AK16
NA VCCAUX AK3
NA VCCAUX T1
NA VCCAUX R30
NA VCCAUX A28
NA VCCAUX A15
NA VCCAUX A3
NA VCCINT AB22
NA VCCINT AB9
NA VCCINT AA21
NA VCCINT AA10
NA VCCINT Y20
NA VCCINT Y19
NA VCCINT Y18
NA VCCINT Y17
NA VCCINT Y16
NA VCCINT Y15
NA VCCINT Y14
NA VCCINT Y13
NA VCCINT Y12
NA VCCINT Y11
NA VCCINT W20
NA VCCINT W11
NA VCCINT V20
NA VCCINT V11
NA VCCINT U20
NA VCCINT U11
NA VCCINT T20
NA VCCINT T11
NA VCCINT R20
NA VCCINT R11
NA VCCINT P20
NA VCCINT P11
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 115
NA VCCINT N20
NA VCCINT N11
NA VCCINT M20
NA VCCINT M11
NA VCCINT L20
NA VCCINT L19
NA VCCINT L18
NA VCCINT L17
NA VCCINT L16
NA VCCINT L15
NA VCCINT L14
NA VCCINT L13
NA VCCINT L12
NA VCCINT L11
NA VCCINT K21
NA VCCINT K10
NA VCCINT J22
NA VCCINT J9
NA GND AK23
NA GND AK8
NA GND AJ29
NA GND AJ2
NA GND AH28
NA GND AH21
NA GND AH10
NA GND AH3
NA GND AG27
NA GND AG4
NA GND AF26
NA GND AF19
NA GND AF12
NA GND AF5
NA GND AE25
NA GND AE6
NA GND AD17
NA GND AD14
NA GND AC30
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
116 1-800-255-7778 Advance Product Specification
NA GND AC1
NA GND AA28
NA GND AA3
NA GND W26
NA GND W19
NA GND W18
NA GND W17
NA GND W16
NA GND W15
NA GND W14
NA GND W13
NA GND W12
NA GND W5
NA GND V19
NA GND V18
NA GND V17
NA GND V16
NA GND V15
NA GND V14
NA GND V13
NA GND V12
NA GND U24
NA GND U19
NA GND U18
NA GND U17
NA GND U16
NA GND U15
NA GND U14
NA GND U13
NA GND U12
NA GND U7
NA GND T19
NA GND T18
NA GND T17
NA GND T16
NA GND T15
NA GND T14
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 117
NA GND T13
NA GND T12
NA GND R19
NA GND R18
NA GND R17
NA GND R16
NA GND R15
NA GND R14
NA GND R13
NA GND R12
NA GND P24
NA GND P19
NA GND P18
NA GND P17
NA GND P16
NA GND P15
NA GND P14
NA GND P13
NA GND P12
NA GND P7
NA GND N19
NA GND N18
NA GND N17
NA GND N16
NA GND N15
NA GND N14
NA GND N13
NA GND N12
NA GND M26
NA GND M19
NA GND M18
NA GND M17
NA GND M16
NA GND M15
NA GND M14
NA GND M13
NA GND M12
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
118 1-800-255-7778 Advance Product Specification
NA GND M5
NA GND K28
NA GND K3
NA GND H30
NA GND H1
NA GND G17
NA GND G14
NA GND F25
NA GND F6
NA GND E26
NA GND E19
NA GND E12
NA GND E5
NA GND D27
NA GND D4
NA GND C28
NA GND C21
NA GND C10
NA GND C3
NA GND B29
NA GND B2
NA GND A23
NA GND A8
Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank Pin Description Pin Number No Connect in the XC2V1000 No Connect in the XC2V1500
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 119
FF896 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 7: FF896 Flip-Chip Fine-Pitch BGA Package Specifications
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
120 1-800-255-7778 Advance Product Specification
FF1152 Flip-Chip Fine-Pitch BGA Package
As shown in Tabl e 12, XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Virtex-II devices are available in the FF1152
flip-chip fine-pitch BGA package. Pins in each of these devices are the same, except for the pin differences in the XC2V3000
device shown in the No Connect column. Following this table are the FF1152 Flip-Chip Fine-Pitch BGA Package
Specifications (1.00mm pitch).
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
0 IO_L01N_0 D29
0 IO_L01P_0 C29
0 IO_L02N_0 H26
0 IO_L02P_0 G26
0 IO_L03N_0/VRP_0 E28
0 IO_L03P_0/VRN_0 E27
0 IO_L04N_0/VREF_0 F25
0 IO_L04P_0 F26
0 IO_L05N_0 H25
0 IO_L05P_0 H24
0 IO_L06N_0 E26
0 IO_L06P_0 F27
0 IO_L19N_0 B32
0 IO_L19P_0 C33
0 IO_L20N_0 J24
0 IO_L20P_0 J23
0 IO_L21N_0 C27
0 IO_L21P_0/VREF_0 C28
0 IO_L22N_0 B30
0 IO_L22P_0 B31
0 IO_L23N_0 K23
0 IO_L23P_0 K22
0 IO_L24N_0 C26
0 IO_L24P_0 D27
0 IO_L25N_0 A30
0 IO_L25P_0 A31
0 IO_L26N_0 G24
0 IO_L26P_0 G25
0 IO_L27N_0 E25
0 IO_L27P_0/VREF_0 E24
0 IO_L28N_0 D25
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 121
0 IO_L28P_0 D26
0 IO_L29N_0 H23
0 IO_L29P_0 H22
0 IO_L30N_0 F23
0 IO_L30P_0 F24
0 IO_L49N_0 B28
0 IO_L49P_0 B29
0 IO_L50N_0 J22
0 IO_L50P_0 J21
0 IO_L51N_0 A28
0 IO_L51P_0/VREF_0 A29
0 IO_L52N_0 A26
0 IO_L52P_0 B27
0 IO_L53N_0 C24
0 IO_L53P_0 D24
0 IO_L54N_0 D22
0 IO_L54P_0 D23
0 IO_L60N_0 B25 NC
0 IO_L60P_0 B26 NC
0 IO_L67N_0 B23
0 IO_L67P_0 B24
0 IO_L68N_0 G22
0 IO_L68P_0 G23
0 IO_L69N_0 F22
0 IO_L69P_0/VREF_0 F21
0 IO_L70N_0 A23
0 IO_L70P_0 A24
0 IO_L71N_0 K21
0 IO_L71P_0 K20
0 IO_L72N_0 C22
0 IO_L72P_0 C23
0 IO_L73N_0 E21
0 IO_L73P_0 E22
0 IO_L74N_0 H21
0 IO_L74P_0 H20
0 IO_L75N_0 G20
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
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122 1-800-255-7778 Advance Product Specification
0 IO_L75P_0/VREF_0 F20
0 IO_L76N_0 B21
0 IO_L76P_0 B22
0 IO_L77N_0 J20
0 IO_L77P_0 K19
0 IO_L78N_0 D20
0 IO_L78P_0 D21
0 IO_L79N_0 A21 NC
0 IO_L79P_0 A22 NC
0 IO_L80N_0 L19 NC
0 IO_L80P_0 L18 NC
0 IO_L81N_0 B19 NC
0 IO_L81P_0/VREF_0 A20 NC
0 IO_L82N_0 A18 NC
0 IO_L82P_0 B18 NC
0 IO_L83N_0 H19 NC
0 IO_L83P_0 H18 NC
0 IO_L84N_0 C20 NC
0 IO_L84P_0 C21 NC
0 IO_L91N_0/VREF_0 D19
0 IO_L91P_0 D18
0 IO_L92N_0 G18
0 IO_L92P_0 G19
0 IO_L93N_0 F18
0 IO_L93P_0 F19
0 IO_L94N_0/VREF_0 C19
0 IO_L94P_0 C18
0 IO_L95N_0/GCLK7P K18
0 IO_L95P_0/GCLK6S J18
0 IO_L96N_0/GCLK5P E19
0 IO_L96P_0/GCLK4S E18
1 IO_L96N_1/GCLK3P E17
1 IO_L96P_1/GCLK2S E16
1 IO_L95N_1/GCLK1P H17
1 IO_L95P_1/GCLK0S H16
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 123
1 IO_L94N_1 D17
1 IO_L94P_1/VREF_1 D16
1 IO_L93N_1 F16
1 IO_L93P_1 F17
1 IO_L92N_1 G16
1 IO_L92P_1 G17
1 IO_L91N_1 C16
1 IO_L91P_1/VREF_1 C15
1 IO_L84N_1 D14 NC
1 IO_L84P_1 D15 NC
1 IO_L83N_1 J17 NC
1 IO_L83P_1 K17 NC
1 IO_L82N_1 B17 NC
1 IO_L82P_1 A17 NC
1 IO_L81N_1/VREF_1 A15 NC
1 IO_L81P_1 B16 NC
1 IO_L80N_1 L17 NC
1 IO_L80P_1 L16 NC
1 IO_L79N_1 A13 NC
1 IO_L79P_1 A14 NC
1 IO_L78N_1 C13
1 IO_L78P_1 C14
1 IO_L77N_1 K16
1 IO_L77P_1 K15
1 IO_L76N_1 B13
1 IO_L76P_1 B14
1 IO_L75N_1/VREF_1 F15
1 IO_L75P_1 G15
1 IO_L74N_1 H15
1 IO_L74P_1 H14
1 IO_L73N_1 A11
1 IO_L73P_1 A12
1 IO_L72N_1 E13
1 IO_L72P_1 E14
1 IO_L71N_1 J15
1 IO_L71P_1 J14
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
124 1-800-255-7778 Advance Product Specification
1 IO_L70N_1 D12
1 IO_L70P_1 D13
1 IO_L69N_1/VREF_1 F14
1 IO_L69P_1 F13
1 IO_L68N_1 C11
1 IO_L68P_1 C12
1 IO_L67N_1 B11
1 IO_L67P_1 B12
1 IO_L60N_1 F11 NC
1 IO_L60P_1 F12 NC
1 IO_L54N_1 D10
1 IO_L54P_1 D11
1 IO_L53N_1 G12
1 IO_L53P_1 G13
1 IO_L52N_1 B9
1 IO_L52P_1 B10
1 IO_L51N_1/VREF_1 B8
1 IO_L51P_1 A9
1 IO_L50N_1 K14
1 IO_L50P_1 K13
1 IO_L49N_1 A6
1 IO_L49P_1 A7
1 IO_L30N_1 D9
1 IO_L30P_1 C9
1 IO_L29N_1 H13
1 IO_L29P_1 H12
1 IO_L28N_1 C7
1 IO_L28P_1 C8
1 IO_L27N_1/VREF_1 E11
1 IO_L27P_1 E10
1 IO_L26N_1 J13
1 IO_L26P_1 K12
1 IO_L25N_1 B6
1 IO_L25P_1 B7
1 IO_L24N_1 E8
1 IO_L24P_1 E9
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 125
1 IO_L23N_1 G10
1 IO_L23P_1 G11
1 IO_L22N_1 A4
1 IO_L22P_1 A5
1 IO_L21N_1/VREF_1 F10
1 IO_L21P_1 G9
1 IO_L20N_1 J12
1 IO_L20P_1 J11
1 IO_L19N_1 B4
1 IO_L19P_1 B5
1 IO_L06N_1 D6
1 IO_L06P_1 C6
1 IO_L05N_1 H11
1 IO_L05P_1 J10
1 IO_L04N_1 D8
1 IO_L04P_1/VREF_1 E7
1 IO_L03N_1/VRP_1 F9
1 IO_L03P_1/VRN_1 F8
1 IO_L02N_1 H10
1 IO_L02P_1 H9
1 IO_L01N_1 C2
1 IO_L01P_1 B3
2 IO_L01N_2 E2
2 IO_L01P_2 D2
2 IO_L02N_2/VRP_2 K11
2 IO_L02P_2/VRN_2 K10
2 IO_L03N_2 F5
2 IO_L03P_2/VREF_2 G5
2 IO_L04N_2 E3
2 IO_L04P_2 D3
2 IO_L05N_2 J9
2 IO_L05P_2 K9
2 IO_L06N_2 F4
2 IO_L06P_2 E4
2 IO_L19N_2 E1
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
126 1-800-255-7778 Advance Product Specification
2 IO_L19P_2 D1
2 IO_L20N_2 J8
2 IO_L20P_2 K8
2 IO_L21N_2 H7
2 IO_L21P_2/VREF_2 J7
2 IO_L22N_2 H6
2 IO_L22P_2 G6
2 IO_L23N_2 L10
2 IO_L23P_2 L9
2 IO_L24N_2 G3
2 IO_L24P_2 F3
2 IO_L25N_2 G2
2 IO_L25P_2 F2
2 IO_L26N_2 M10
2 IO_L26P_2 N10
2 IO_L27N_2 J6
2 IO_L27P_2/VREF_2 K6
2 IO_L28N_2 J5
2 IO_L28P_2 H5
2 IO_L29N_2 L7
2 IO_L29P_2 K7
2 IO_L30N_2 J4
2 IO_L30P_2 H4
2 IO_L43N_2 G1
2 IO_L43P_2 F1
2 IO_L44N_2 L8
2 IO_L44P_2 M8
2 IO_L45N_2 J1
2 IO_L45P_2/VREF_2 H2
2 IO_L46N_2 J3
2 IO_L46P_2 H3
2 IO_L47N_2 M9
2 IO_L47P_2 N9
2 IO_L48N_2 L5
2 IO_L48P_2 K5
2 IO_L49N_2 K2
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 127
2 IO_L49P_2 J2
2 IO_L50N_2 N7
2 IO_L50P_2 M7
2 IO_L51N_2 L6
2 IO_L51P_2/VREF_2 M6
2 IO_L52N_2 M3
2 IO_L52P_2 L3
2 IO_L53N_2 L4
2 IO_L53P_2 K4
2 IO_L54N_2 N4
2 IO_L54P_2 M4
2 IO_L67N_2 M2
2 IO_L67P_2 L2
2 IO_L68N_2 N8
2 IO_L68P_2 P8
2 IO_L69N_2 N6
2 IO_L69P_2/VREF_2 P6
2 IO_L70N_2 P5
2 IO_L70P_2 N5
2 IO_L71N_2 P10
2 IO_L71P_2 R10
2 IO_L72N_2 P3
2 IO_L72P_2 N3
2 IO_L73N_2 M1
2 IO_L73P_2 L1
2 IO_L74N_2 P9
2 IO_L74P_2 R9
2 IO_L75N_2 P2
2 IO_L75P_2/VREF_2 N2
2 IO_L76N_2 R4
2 IO_L76P_2 P4
2 IO_L77N_2 R8
2 IO_L77P_2 T8
2 IO_L78N_2 T3
2 IO_L78P_2 R3
2 IO_L79N_2 P1 NC
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
128 1-800-255-7778 Advance Product Specification
2 IO_L79P_2 N1 NC
2 IO_L80N_2 T11 NC
2 IO_L80P_2 U11 NC
2 IO_L81N_2 R7 NC
2 IO_L81P_2/VREF_2 R6 NC
2 IO_L82N_2 U5 NC
2 IO_L82P_2 T5 NC
2 IO_L83N_2 T10 NC
2 IO_L83P_2 U10 NC
2 IO_L84N_2 U4 NC
2 IO_L84P_2 T4 NC
2 IO_L91N_2 T2
2 IO_L91P_2 R1
2 IO_L92N_2 U7
2 IO_L92P_2 T7
2 IO_L93N_2 T6
2 IO_L93P_2/VREF_2 U6
2 IO_L94N_2 U1
2 IO_L94P_2 U2
2 IO_L95N_2 U9
2 IO_L95P_2 U8
2 IO_L96N_2 U3
2 IO_L96P_2 V4
3 IO_L96N_3 V6
3 IO_L96P_3 W6
3 IO_L95N_3 V5
3 IO_L95P_3 W5
3 IO_L94N_3 V7
3 IO_L94P_3 W7
3 IO_L93N_3/VREF_3 V10
3 IO_L93P_3 W10
3 IO_L92N_3 V1
3 IO_L92P_3 V2
3 IO_L91N_3 W3
3 IO_L91P_3 Y3
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 129
3 IO_L84N_3 V9 NC
3 IO_L84P_3 V8 NC
3 IO_L83N_3 W4 NC
3 IO_L83P_3 Y4 NC
3 IO_L82N_3 W11 NC
3 IO_L82P_3 V11 NC
3 IO_L81N_3/VREF_3 W8 NC
3 IO_L81P_3 Y8 NC
3 IO_L80N_3 W2 NC
3 IO_L80P_3 Y1 NC
3 IO_L79N_3 AA3 NC
3 IO_L79P_3 AB3 NC
3 IO_L78N_3 Y6
3 IO_L78P_3 AA6
3 IO_L77N_3 AA4
3 IO_L77P_3 AB4
3 IO_L76N_3 Y7
3 IO_L76P_3 AA8
3 IO_L75N_3/VREF_3 Y10
3 IO_L75P_3 AA10
3 IO_L74N_3 AA1
3 IO_L74P_3 AB1
3 IO_L73N_3 AA5
3 IO_L73P_3 AB5
3 IO_L72N_3 AA9
3 IO_L72P_3 Y9
3 IO_L71N_3 AA2
3 IO_L71P_3 AB2
3 IO_L70N_3 AB6
3 IO_L70P_3 AC6
3 IO_L69N_3/VREF_3 AD1
3 IO_L69P_3 AC1
3 IO_L68N_3 AC3
3 IO_L68P_3 AD3
3 IO_L67N_3 AC4
3 IO_L67P_3 AD4
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
130 1-800-255-7778 Advance Product Specification
3 IO_L54N_3 AB7
3 IO_L54P_3 AC7
3 IO_L53N_3 AC2
3 IO_L53P_3 AD2
3 IO_L52N_3 AC8
3 IO_L52P_3 AB8
3 IO_L51N_3/VREF_3 AB10
3 IO_L51P_3 AC10
3 IO_L50N_3 AD5
3 IO_L50P_3 AE5
3 IO_L49N_3 AE4
3 IO_L49P_3 AF4
3 IO_L48N_3 AB9
3 IO_L48P_3 AC9
3 IO_L47N_3 AE2
3 IO_L47P_3 AF1
3 IO_L46N_3 AD6
3 IO_L46P_3 AE6
3 IO_L45N_3/VREF_3 AD9
3 IO_L45P_3 AE9
3 IO_L44N_3 AF2
3 IO_L44P_3 AG2
3 IO_L43N_3 AF3
3 IO_L43P_3 AG3
3 IO_L30N_3 AD7
3 IO_L30P_3 AE7
3 IO_L29N_3 AF5
3 IO_L29P_3 AG5
3 IO_L28N_3 AE8
3 IO_L28P_3 AD8
3 IO_L27N_3/VREF_3 AF8
3 IO_L27P_3 AF9
3 IO_L26N_3 AH1
3 IO_L26P_3 AJ1
3 IO_L25N_3 AG4
3 IO_L25P_3 AH5
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 131
3 IO_L24N_3 AF6
3 IO_L24P_3 AG6
3 IO_L23N_3 AH3
3 IO_L23P_3 AJ3
3 IO_L22N_3 AF7
3 IO_L22P_3 AG7
3 IO_L21N_3/VREF_3 AL1
3 IO_L21P_3 AK1
3 IO_L20N_3 AH2
3 IO_L20P_3 AJ2
3 IO_L19N_3 AJ4
3 IO_L19P_3 AK4
3 IO_L06N_3 AE10
3 IO_L06P_3 AD10
3 IO_L05N_3 AK2
3 IO_L05P_3 AL2
3 IO_L04N_3 AH6
3 IO_L04P_3 AJ5
3 IO_L03N_3/VREF_3 AE11
3 IO_L03P_3 AF11
3 IO_L02N_3/VRP_3 AK3
3 IO_L02P_3/VRN_3 AL3
3 IO_L01N_3 AF10
3 IO_L01P_3 AG9
4 IO_L01N_4/DOUT AM4
4 IO_L01P_4/INIT_B AL5
4 IO_L02N_4/D0 AG10
4 IO_L02P_4/D1 AH11
4 IO_L03N_4/D2/ALT_VRP_4 AK7
4 IO_L03P_4/D3/ALT_VRN_4 AK8
4 IO_L04N_4/VREF_4 AL6
4 IO_L04P_4 AM6
4 IO_L05N_4/VRP_4 AK9
4 IO_L05P_4/VRN_4 AJ8
4 IO_L06N_4 AM8
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
132 1-800-255-7778 Advance Product Specification
4 IO_L06P_4 AM7
4 IO_L19N_4 AN3
4 IO_L19P_4 AM2
4 IO_L20N_4 AJ10
4 IO_L20P_4 AJ9
4 IO_L21N_4 AH9
4 IO_L21P_4/VREF_4 AH10
4 IO_L22N_4 AN5
4 IO_L22P_4 AN4
4 IO_L23N_4 AE12
4 IO_L23P_4 AE13
4 IO_L24N_4 AM9
4 IO_L24P_4 AL8
4 IO_L25N_4 AP5
4 IO_L25P_4 AP4
4 IO_L26N_4 AG11
4 IO_L26P_4 AG12
4 IO_L27N_4 AN7
4 IO_L27P_4/VREF_4 AN6
4 IO_L28N_4 AL10
4 IO_L28P_4 AL9
4 IO_L29N_4 AF12
4 IO_L29P_4 AF13
4 IO_L30N_4 AK10
4 IO_L30P_4 AK11
4 IO_L49N_4 AP7
4 IO_L49P_4 AP6
4 IO_L50N_4 AH13
4 IO_L50P_4 AH12
4 IO_L51N_4 AJ11
4 IO_L51P_4/VREF_4 AJ12
4 IO_L52N_4 AP9
4 IO_L52P_4 AN8
4 IO_L53N_4 AG13
4 IO_L53P_4 AG14
4 IO_L54N_4 AM11
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 133
4 IO_L54P_4 AL11
4 IO_L60N_4 AN10 NC
4 IO_L60P_4 AN9 NC
4 IO_L67N_4 AN12
4 IO_L67P_4 AN11
4 IO_L68N_4 AE14
4 IO_L68P_4 AE15
4 IO_L69N_4 AJ13
4 IO_L69P_4/VREF_4 AJ14
4 IO_L70N_4 AL13
4 IO_L70P_4 AL12
4 IO_L71N_4 AF14
4 IO_L71P_4 AF15
4 IO_L72N_4 AM13
4 IO_L72P_4 AM12
4 IO_L73N_4 AP12
4 IO_L73P_4 AP11
4 IO_L74N_4 AG15
4 IO_L74P_4 AG16
4 IO_L75N_4 AN14
4 IO_L75P_4/VREF_4 AN13
4 IO_L76N_4 AP14
4 IO_L76P_4 AP13
4 IO_L77N_4 AD16
4 IO_L77P_4 AD17
4 IO_L78N_4 AK14
4 IO_L78P_4 AK13
4 IO_L79N_4 AN16 NC
4 IO_L79P_4 AP15 NC
4 IO_L80N_4 AE16 NC
4 IO_L80P_4 AE17 NC
4 IO_L81N_4 AH15 NC
4 IO_L81P_4/VREF_4 AJ15 NC
4 IO_L82N_4 AP17 NC
4 IO_L82P_4 AN17 NC
4 IO_L83N_4 AH17 NC
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
134 1-800-255-7778 Advance Product Specification
4 IO_L83P_4 AH16 NC
4 IO_L84N_4 AL15 NC
4 IO_L84P_4 AL14 NC
4 IO_L91N_4/VREF_4 AL16
4 IO_L91P_4 AL17
4 IO_L92N_4 AJ17
4 IO_L92P_4 AJ16
4 IO_L93N_4 AM15
4 IO_L93P_4 AM14
4 IO_L94N_4/VREF_4 AM16
4 IO_L94P_4 AM17
4 IO_L95N_4/GCLK3S AF17
4 IO_L95P_4/GCLK2P AG17
4 IO_L96N_4/GCLK1S AK16
4 IO_L96P_4/GCLK0P AK17
5 IO_L96N_5/GCLK7S AK18
5 IO_L96P_5/GCLK6P AK19
5 IO_L95N_5/GCLK5S AG18
5 IO_L95P_5/GCLK4P AF18
5 IO_L94N_5 AL18
5 IO_L94P_5/VREF_5 AL19
5 IO_L93N_5 AJ19
5 IO_L93P_5 AJ18
5 IO_L92N_5 AH19
5 IO_L92P_5 AH18
5 IO_L91N_5 AM19
5 IO_L91P_5/VREF_5 AM20
5 IO_L84N_5 AL21 NC
5 IO_L84P_5 AL20 NC
5 IO_L83N_5 AM22 NC
5 IO_L83P_5 AM21 NC
5 IO_L82N_5 AN18 NC
5 IO_L82P_5 AP18 NC
5 IO_L81N_5/VREF_5 AP20 NC
5 IO_L81P_5 AN19 NC
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 135
5 IO_L80N_5 AE18 NC
5 IO_L80P_5 AE19 NC
5 IO_L79N_5 AP22 NC
5 IO_L79P_5 AP21 NC
5 IO_L78N_5 AK22
5 IO_L78P_5 AK21
5 IO_L77N_5 AD18
5 IO_L77P_5 AD19
5 IO_L76N_5 AN22
5 IO_L76P_5 AN21
5 IO_L75N_5/VREF_5 AJ20
5 IO_L75P_5 AH20
5 IO_L74N_5 AG19
5 IO_L74P_5 AG20
5 IO_L73N_5 AP24
5 IO_L73P_5 AP23
5 IO_L72N_5 AL23
5 IO_L72P_5 AL22
5 IO_L71N_5 AF20
5 IO_L71P_5 AF21
5 IO_L70N_5 AM24
5 IO_L70P_5 AM23
5 IO_L69N_5/VREF_5 AJ21
5 IO_L69P_5 AJ22
5 IO_L68N_5 AJ24
5 IO_L68P_5 AJ23
5 IO_L67N_5 AN24
5 IO_L67P_5 AN23
5 IO_L60N_5 AN26 NC
5 IO_L60P_5 AN25 NC
5 IO_L54N_5 AL25
5 IO_L54P_5 AL24
5 IO_L53N_5 AE20
5 IO_L53P_5 AE21
5 IO_L52N_5 AN27
5 IO_L52P_5 AP26
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
136 1-800-255-7778 Advance Product Specification
5 IO_L51N_5/VREF_5 AP29
5 IO_L51P_5 AP28
5 IO_L50N_5 AG21
5 IO_L50P_5 AG22
5 IO_L49N_5 AN29
5 IO_L49P_5 AN28
5 IO_L30N_5 AK24
5 IO_L30P_5 AK25
5 IO_L29N_5 AH23
5 IO_L29P_5 AH22
5 IO_L28N_5 AP31
5 IO_L28P_5 AP30
5 IO_L27N_5/VREF_5 AH24
5 IO_L27P_5 AH25
5 IO_L26N_5 AF22
5 IO_L26P_5 AF23
5 IO_L25N_5 AM27
5 IO_L25P_5 AM26
5 IO_L24N_5 AL27
5 IO_L24P_5 AL26
5 IO_L23N_5 AH26
5 IO_L23P_5 AJ25
5 IO_L22N_5 AN31
5 IO_L22P_5 AN30
5 IO_L21N_5/VREF_5 AK26
5 IO_L21P_5 AK27
5 IO_L20N_5 AG23
5 IO_L20P_5 AF24
5 IO_L19N_5 AM33
5 IO_L19P_5 AN32
5 IO_L06N_5 AJ27
5 IO_L06P_5 AJ26
5 IO_L05N_5/VRP_5 AE22
5 IO_L05P_5/VRN_5 AE23
5 IO_L04N_5 AM28
5 IO_L04P_5/VREF_5 AM29
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 137
5 IO_L03N_5/D4/ALT_VRP_5 AK28
5 IO_L03P_5/D5/ALT_VRN_5 AL29
5 IO_L02N_5/D6 AG24
5 IO_L02P_5/D7 AG25
5 IO_L01N_5/RDWR_B AL30
5 IO_L01P_5/CS_B AM31
6 IO_L01P_6 AE24
6 IO_L01N_6 AD25
6 IO_L02P_6/VRN_6 AJ30
6 IO_L02N_6/VRP_6 AH30
6 IO_L03P_6 AL32
6 IO_L03N_6/VREF_6 AK32
6 IO_L04P_6 AF25
6 IO_L04N_6 AE25
6 IO_L05P_6 AJ31
6 IO_L05N_6 AK31
6 IO_L06P_6 AH29
6 IO_L06N_6 AG29
6 IO_L19P_6 AG26
6 IO_L19N_6 AF26
6 IO_L20P_6 AL33
6 IO_L20N_6 AK33
6 IO_L21P_6 AJ32
6 IO_L21N_6/VREF_6 AH32
6 IO_L22P_6 AG28
6 IO_L22N_6 AF28
6 IO_L23P_6 AG30
6 IO_L23N_6 AF30
6 IO_L24P_6 AF29
6 IO_L24N_6 AE29
6 IO_L25P_6 AF27
6 IO_L25N_6 AE27
6 IO_L26P_6 AL34
6 IO_L26N_6 AK34
6 IO_L27P_6 AE28
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
138 1-800-255-7778 Advance Product Specification
6 IO_L27N_6/VREF_6 AD28
6 IO_L28P_6 AE26
6 IO_L28N_6 AD26
6 IO_L29P_6 AF31
6 IO_L29N_6 AG31
6 IO_L30P_6 AF32
6 IO_L30N_6 AG32
6 IO_L43P_6 AC25
6 IO_L43N_6 AB25
6 IO_L44P_6 AJ33
6 IO_L44N_6 AH33
6 IO_L45P_6 AE31
6 IO_L45N_6/VREF_6 AD32
6 IO_L46P_6 AD27
6 IO_L46N_6 AC27
6 IO_L47P_6 AJ34
6 IO_L47N_6 AH34
6 IO_L48P_6 AE30
6 IO_L48N_6 AD30
6 IO_L49P_6 AC26
6 IO_L49N_6 AB26
6 IO_L50P_6 AD29
6 IO_L50N_6 AC29
6 IO_L51P_6 AF33
6 IO_L51N_6/VREF_6 AG33
6 IO_L52P_6 AC28
6 IO_L52N_6 AB28
6 IO_L53P_6 AF34
6 IO_L53N_6 AE33
6 IO_L54P_6 AB27
6 IO_L54N_6 AA27
6 IO_L67P_6 AA25
6 IO_L67N_6 Y25
6 IO_L68P_6 AD33
6 IO_L68N_6 AC33
6 IO_L69P_6 AC32
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 139
6 IO_L69N_6/VREF_6 AB32
6 IO_L70P_6 AA26
6 IO_L70N_6 Y26
6 IO_L71P_6 AD34
6 IO_L71N_6 AC34
6 IO_L72P_6 AC31
6 IO_L72N_6 AD31
6 IO_L73P_6 Y27
6 IO_L73N_6 W27
6 IO_L74P_6 AB29
6 IO_L74N_6 AA29
6 IO_L75P_6 AB31
6 IO_L75N_6/VREF_6 AA31
6 IO_L76P_6 Y28
6 IO_L76N_6 Y29
6 IO_L77P_6 AB33
6 IO_L77N_6 AA33
6 IO_L78P_6 AA30
6 IO_L78N_6 AB30
6 IO_L79P_6 W24 NC
6 IO_L79N_6 V24 NC
6 IO_L80P_6 AB34 NC
6 IO_L80N_6 AA34 NC
6 IO_L81P_6 W33 NC
6 IO_L81N_6/VREF_6 Y34 NC
6 IO_L82P_6 W25 NC
6 IO_L82N_6 V25 NC
6 IO_L83P_6 Y32 NC
6 IO_L83N_6 AA32 NC
6 IO_L84P_6 W29 NC
6 IO_L84N_6 V29 NC
6 IO_L91P_6 W28
6 IO_L91N_6 V28
6 IO_L92P_6 V33
6 IO_L92N_6 V34
6 IO_L93P_6 Y31
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
140 1-800-255-7778 Advance Product Specification
6 IO_L93N_6/VREF_6 W31
6 IO_L94P_6 V26
6 IO_L94N_6 V27
6 IO_L95P_6 W30
6 IO_L95N_6 V30
6 IO_L96P_6 V32
6 IO_L96N_6 W32
7 IO_L96P_7 U31
7 IO_L96N_7 V31
7 IO_L95P_7 T28
7 IO_L95N_7 U28
7 IO_L94P_7 U33
7 IO_L94N_7 U34
7 IO_L93P_7/VREF_7 U29
7 IO_L93N_7 T29
7 IO_L92P_7 U27
7 IO_L92N_7 U26
7 IO_L91P_7 T30
7 IO_L91N_7 U30
7 IO_L84P_7 R32 NC
7 IO_L84N_7 T32 NC
7 IO_L83P_7 U25 NC
7 IO_L83N_7 T25 NC
7 IO_L82P_7 R34 NC
7 IO_L82N_7 T33 NC
7 IO_L81P_7/VREF_7 N34 NC
7 IO_L81N_7 P34 NC
7 IO_L80P_7 U24 NC
7 IO_L80N_7 T24 NC
7 IO_L79P_7 R31 NC
7 IO_L79N_7 T31 NC
7 IO_L78P_7 N32
7 IO_L78N_7 P32
7 IO_L77P_7 T27
7 IO_L77N_7 R27
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 141
7 IO_L76P_7 N33
7 IO_L76N_7 P33
7 IO_L75P_7/VREF_7 R29
7 IO_L75N_7 R28
7 IO_L74P_7 R26
7 IO_L74N_7 P26
7 IO_L73P_7 N31
7 IO_L73N_7 P31
7 IO_L72P_7 N30
7 IO_L72N_7 P30
7 IO_L71P_7 R25
7 IO_L71N_7 P25
7 IO_L70P_7 L34
7 IO_L70N_7 M34
7 IO_L69P_7/VREF_7 P29
7 IO_L69N_7 N29
7 IO_L68P_7 P27
7 IO_L68N_7 N27
7 IO_L67P_7 L32
7 IO_L67N_7 M32
7 IO_L54P_7 L31
7 IO_L54N_7 M31
7 IO_L53P_7 K29
7 IO_L53N_7 L30
7 IO_L52P_7 L33
7 IO_L52N_7 M33
7 IO_L51P_7/VREF_7 M29
7 IO_L51N_7 L29
7 IO_L50P_7 M28
7 IO_L50N_7 N28
7 IO_L49P_7 K30
7 IO_L49N_7 K31
7 IO_L48P_7 H32
7 IO_L48N_7 J32
7 IO_L47P_7 N26
7 IO_L47N_7 M26
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
142 1-800-255-7778 Advance Product Specification
7 IO_L46P_7 J33
7 IO_L46N_7 K33
7 IO_L45P_7/VREF_7 H33
7 IO_L45N_7 J34
7 IO_L44P_7 M27
7 IO_L44N_7 L27
7 IO_L43P_7 H31
7 IO_L43N_7 J31
7 IO_L30P_7 F32
7 IO_L30N_7 G32
7 IO_L29P_7 N25
7 IO_L29N_7 M25
7 IO_L28P_7 F34
7 IO_L28N_7 G34
7 IO_L27P_7/VREF_7 J30
7 IO_L27N_7 H30
7 IO_L26P_7 K28
7 IO_L26N_7 L28
7 IO_L25P_7 H28
7 IO_L25N_7 J29
7 IO_L24P_7 G29
7 IO_L24N_7 H29
7 IO_L23P_7 L26
7 IO_L23N_7 K26
7 IO_L22P_7 F33
7 IO_L22N_7 G33
7 IO_L21P_7/VREF_7 J28
7 IO_L21N_7 J27
7 IO_L20P_7 K27
7 IO_L20N_7 J26
7 IO_L19P_7 E31
7 IO_L19N_7 F31
7 IO_L06P_7 D32
7 IO_L06N_7 E32
7 IO_L05P_7 L25
7 IO_L05N_7 K24
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 143
7 IO_L04P_7 D34
7 IO_L04N_7 E34
7 IO_L03P_7/VREF_7 G30
7 IO_L03N_7 F30
7 IO_L02P_7/VRN_7 K25
7 IO_L02N_7/VRP_7 J25
7 IO_L01P_7 D33
7 IO_L01N_7 E33
0 VCCO_0 M22
0 VCCO_0 M21
0 VCCO_0 M20
0 VCCO_0 M19
0 VCCO_0 M18
0 VCCO_0 L23
0 VCCO_0 L22
0 VCCO_0 L21
0 VCCO_0 L20
0 VCCO_0 E20
0 VCCO_0 D28
0 VCCO_0 A25
0 VCCO_0 A19
1 VCCO_1 M17
1 VCCO_1 M16
1 VCCO_1 M15
1 VCCO_1 M14
1 VCCO_1 M13
1 VCCO_1 L15
1 VCCO_1 L14
1 VCCO_1 L13
1 VCCO_1 L12
1 VCCO_1 E15
1 VCCO_1 D7
1 VCCO_1 A16
1 VCCO_1 A10
2 VCCO_2 U12
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
144 1-800-255-7778 Advance Product Specification
2 VCCO_2 T12
2 VCCO_2 T1
2 VCCO_2 R12
2 VCCO_2 R11
2 VCCO_2 R5
2 VCCO_2 P12
2 VCCO_2 P11
2 VCCO_2 N12
2 VCCO_2 N11
2 VCCO_2 M11
2 VCCO_2 K1
2 VCCO_2 G4
3 VCCO_3 AH4
3 VCCO_3 AE1
3 VCCO_3 AC11
3 VCCO_3 AB12
3 VCCO_3 AB11
3 VCCO_3 AA12
3 VCCO_3 AA11
3 VCCO_3 Y12
3 VCCO_3 Y11
3 VCCO_3 Y5
3 VCCO_3 W12
3 VCCO_3 W1
3 VCCO_3 V12
4 VCCO_4 AP16
4 VCCO_4 AP10
4 VCCO_4 AL7
4 VCCO_4 AK15
4 VCCO_4 AD15
4 VCCO_4 AD14
4 VCCO_4 AD13
4 VCCO_4 AD12
4 VCCO_4 AC17
4 VCCO_4 AC16
4 VCCO_4 AC15
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 145
4 VCCO_4 AC14
4 VCCO_4 AC13
5 VCCO_5 AP25
5 VCCO_5 AP19
5 VCCO_5 AL28
5 VCCO_5 AK20
5 VCCO_5 AD23
5 VCCO_5 AD22
5 VCCO_5 AD21
5 VCCO_5 AD20
5 VCCO_5 AC22
5 VCCO_5 AC21
5 VCCO_5 AC20
5 VCCO_5 AC19
5 VCCO_5 AC18
6 VCCO_6 AH31
6 VCCO_6 AE34
6 VCCO_6 AC24
6 VCCO_6 AB24
6 VCCO_6 AB23
6 VCCO_6 AA24
6 VCCO_6 AA23
6 VCCO_6 Y30
6 VCCO_6 Y24
6 VCCO_6 Y23
6 VCCO_6 W34
6 VCCO_6 W23
6 VCCO_6 V23
7 VCCO_7 U23
7 VCCO_7 T34
7 VCCO_7 T23
7 VCCO_7 R30
7 VCCO_7 R24
7 VCCO_7 R23
7 VCCO_7 P24
7 VCCO_7 P23
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
146 1-800-255-7778 Advance Product Specification
7 VCCO_7 N24
7 VCCO_7 N23
7 VCCO_7 M24
7 VCCO_7 K34
7 VCCO_7 G31
NA CCLK AH8
NA PROG_B D30
NA DONE AJ7
NA M0 AH27
NA M1 AJ28
NA M2 AK29
NA HSWAP_EN E29
NA TCK F7
NA TDI C31
NA TDO D5
NA TMS E6
NA PWRDWN_B AK6
NA DXN F28
NA DXP G27
NA VBATT C4
NA RSVD G8
NA VCCAUX AM30
NA VCCAUX AM18
NA VCCAUX AM5
NA VCCAUX V3
NA VCCAUX U32
NA VCCAUX C30
NA VCCAUX C17
NA VCCAUX C5
NA VCCINT AD24
NA VCCINT AD11
NA VCCINT AC23
NA VCCINT AC12
NA VCCINT AB22
NA VCCINT AB21
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 147
NA VCCINT AB20
NA VCCINT AB19
NA VCCINT AB18
NA VCCINT AB17
NA VCCINT AB16
NA VCCINT AB15
NA VCCINT AB14
NA VCCINT AB13
NA VCCINT AA22
NA VCCINT AA13
NA VCCINT Y22
NA VCCINT Y13
NA VCCINT W22
NA VCCINT W13
NA VCCINT V22
NA VCCINT V13
NA VCCINT U22
NA VCCINT U13
NA VCCINT T22
NA VCCINT T13
NA VCCINT R22
NA VCCINT R13
NA VCCINT P22
NA VCCINT P13
NA VCCINT N22
NA VCCINT N21
NA VCCINT N20
NA VCCINT N19
NA VCCINT N18
NA VCCINT N17
NA VCCINT N16
NA VCCINT N15
NA VCCINT N14
NA VCCINT N13
NA VCCINT M23
NA VCCINT M12
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
148 1-800-255-7778 Advance Product Specification
NA VCCINT L24
NA VCCINT L11
NA GND AP33
NA GND AP32
NA GND AP27
NA GND AP8
NA GND AP3
NA GND AP2
NA GND AN34
NA GND AN33
NA GND AN20
NA GND AN15
NA GND AN2
NA GND AN1
NA GND AM34
NA GND AM32
NA GND AM25
NA GND AM10
NA GND AM3
NA GND AM1
NA GND AL31
NA GND AL4
NA GND AK30
NA GND AK23
NA GND AK12
NA GND AK5
NA GND AJ29
NA GND AJ6
NA GND AH28
NA GND AH21
NA GND AH14
NA GND AH7
NA GND AG34
NA GND AG27
NA GND AG8
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 149
NA GND AG1
NA GND AF19
NA GND AF16
NA GND AE32
NA GND AE3
NA GND AC30
NA GND AC5
NA GND AA28
NA GND AA21
NA GND AA20
NA GND AA19
NA GND AA18
NA GND AA17
NA GND AA16
NA GND AA15
NA GND AA14
NA GND AA7
NA GND Y33
NA GND Y21
NA GND Y20
NA GND Y19
NA GND Y18
NA GND Y17
NA GND Y16
NA GND Y15
NA GND Y14
NA GND Y2
NA GND W26
NA GND W21
NA GND W20
NA GND W19
NA GND W18
NA GND W17
NA GND W16
NA GND W15
NA GND W14
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
150 1-800-255-7778 Advance Product Specification
NA GND W9
NA GND V21
NA GND V20
NA GND V19
NA GND V18
NA GND V17
NA GND V16
NA GND V15
NA GND V14
NA GND U21
NA GND U20
NA GND U19
NA GND U18
NA GND U17
NA GND U16
NA GND U15
NA GND U14
NA GND T26
NA GND T21
NA GND T20
NA GND T19
NA GND T18
NA GND T17
NA GND T16
NA GND T15
NA GND T14
NA GND T9
NA GND R33
NA GND R21
NA GND R20
NA GND R19
NA GND R18
NA GND R17
NA GND R16
NA GND R15
NA GND R14
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 151
NA GND R2
NA GND P28
NA GND P21
NA GND P20
NA GND P19
NA GND P18
NA GND P17
NA GND P16
NA GND P15
NA GND P14
NA GND P7
NA GND M30
NA GND M5
NA GND K32
NA GND K3
NA GND J19
NA GND J16
NA GND H34
NA GND H27
NA GND H8
NA GND H1
NA GND G28
NA GND G21
NA GND G14
NA GND G7
NA GND F29
NA GND F6
NA GND E30
NA GND E23
NA GND E12
NA GND E5
NA GND D31
NA GND D4
NA GND C34
NA GND C32
NA GND C25
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
152 1-800-255-7778 Advance Product Specification
NA GND C10
NA GND C3
NA GND C1
NA GND B34
NA GND B33
NA GND B20
NA GND B15
NA GND B2
NA GND B1
NA GND A33
NA GND A32
NA GND A27
NA GND A8
NA GND A3
NA GND A2
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V3000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 153
FF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 8: FF1152 Flip-Chip Fine-Pitch BGA Package Specifications
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
154 1-800-255-7778 Advance Product Specification
FF1517 Flip-Chip Fine-Pitch BGA Package
As shown in Table 13 , XC2V4000, XC2V6000, and XC2V8000 Virtex-II devices are available in the FF1517 flip-chip
fine-pitch BGA package. Pins in each of these devices are the same, except for the pin differences in the XC2V4000 and
XC2V6000 devices shown in the No Connect columns. Following this table are the FF1517 Flip-Chip Fine-Pitch BGA
Package Specifications (1.00mm pitch).
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
0 IO_L01N_0 B36
0 IO_L01P_0 C36
0 IO_L02N_0 J30
0 IO_L02P_0 J29
0 IO_L03N_0/VRP_0 D33
0 IO_L03P_0/VRN_0 D34
0 IO_L04N_0/VREF_0 C34
0 IO_L04P_0 C35
0 IO_L05N_0 H30
0 IO_L05P_0 G30
0 IO_L06N_0 D32
0 IO_L06P_0 E33
0 IO_L07N_0 A35 NC
0 IO_L07P_0 A36 NC
0 IO_L08N_0 K28 NC
0 IO_L08P_0 J28 NC
0 IO_L09N_0 E32 NC
0 IO_L09P_0/VREF_0 F32 NC
0 IO_L10N_0 B34 NC
0 IO_L10P_0 B35 NC
0 IO_L11N_0 H29 NC
0 IO_L11P_0 H28 NC
0 IO_L12N_0 F31 NC
0 IO_L12P_0 G31 NC
0 IO_L19N_0 C32
0 IO_L19P_0 C33
0 IO_L20N_0 M26
0 IO_L20P_0 M25
0 IO_L21N_0 E30
0 IO_L21P_0/VREF_0 E31
0 IO_L22N_0 A33
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 155
0 IO_L22P_0 A34
0 IO_L23N_0 K27
0 IO_L23P_0 K26
0 IO_L24N_0 F29
0 IO_L24P_0 F30
0 IO_L25N_0 B32
0 IO_L25P_0 B33
0 IO_L26N_0 L26
0 IO_L26P_0 L25
0 IO_L27N_0 G28
0 IO_L27P_0/VREF_0 G29
0 IO_L28N_0 C30
0 IO_L28P_0 C31
0 IO_L29N_0 J27
0 IO_L29P_0 J26
0 IO_L30N_0 D30
0 IO_L30P_0 D31
0 IO_L31N_0 A31 NC
0 IO_L31P_0 A32 NC
0 IO_L32N_0 H27 NC
0 IO_L32P_0 H26 NC
0 IO_L33N_0 F27 NC
0 IO_L33P_0/VREF_0 F28 NC
0 IO_L34N_0 B30 NC
0 IO_L34P_0 B31 NC
0 IO_L35N_0 M24 NC
0 IO_L35P_0 M23 NC
0 IO_L36N_0 D28 NC
0 IO_L36P_0 D29 NC
0 IO_L49N_0 C28
0 IO_L49P_0 C29
0 IO_L50N_0 K25
0 IO_L50P_0 L24
0 IO_L51N_0 E27
0 IO_L51P_0/VREF_0 E28
0 IO_L52N_0 A29
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
156 1-800-255-7778 Advance Product Specification
0 IO_L52P_0 A30
0 IO_L53N_0 G26
0 IO_L53P_0 G25
0 IO_L54N_0 D26
0 IO_L54P_0 D27
0 IO_L55N_0 B27
0 IO_L55P_0 B28
0 IO_L56N_0 H25
0 IO_L56P_0 H24
0 IO_L57N_0 F25
0 IO_L57P_0/VREF_0 F26
0 IO_L58N_0 A27
0 IO_L58P_0 A28
0 IO_L59N_0 K24
0 IO_L59P_0 K23
0 IO_L60N_0 E24
0 IO_L60P_0 E25
0 IO_L67N_0 C26
0 IO_L67P_0 C27
0 IO_L68N_0 J24
0 IO_L68P_0 J23
0 IO_L69N_0 D24
0 IO_L69P_0/VREF_0 D25
0 IO_L70N_0 A25
0 IO_L70P_0 A26
0 IO_L71N_0 M22
0 IO_L71P_0 M21
0 IO_L72N_0 G23
0 IO_L72P_0 G24
0 IO_L73N_0 B25
0 IO_L73P_0 C25
0 IO_L74N_0 L22
0 IO_L74P_0 L21
0 IO_L75N_0 F23
0 IO_L75P_0/VREF_0 F24
0 IO_L76N_0 C23
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 157
0 IO_L76P_0 C24
0 IO_L77N_0 K22
0 IO_L77P_0 K21
0 IO_L78N_0 E22
0 IO_L78P_0 E23
0 IO_L79N_0 B23
0 IO_L79P_0 B24
0 IO_L80N_0 J22
0 IO_L80P_0 J21
0 IO_L81N_0 G21
0 IO_L81P_0/VREF_0 G22
0 IO_L82N_0 A23
0 IO_L82P_0 A24
0 IO_L83N_0 H22
0 IO_L83P_0 H21
0 IO_L84N_0 F21
0 IO_L84P_0 F22
0 IO_L91N_0/VREF_0 B21
0 IO_L91P_0 B22
0 IO_L92N_0 L20
0 IO_L92P_0 M20
0 IO_L93N_0 E21
0 IO_L93P_0 D22
0 IO_L94N_0/VREF_0 A21
0 IO_L94P_0 A22
0 IO_L95N_0/GCLK7P H20
0 IO_L95P_0/GCLK6S J20
0 IO_L96N_0/GCLK5P C21
0 IO_L96P_0/GCLK4S D21
1 IO_L96N_1/GCLK3P F19
1 IO_L96P_1/GCLK2S F20
1 IO_L95N_1/GCLK1P H19
1 IO_L95P_1/GCLK0S H18
1 IO_L94N_1 C19
1 IO_L94P_1/VREF_1 C20
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
158 1-800-255-7778 Advance Product Specification
1 IO_L93N_1 E19
1 IO_L93P_1 E20
1 IO_L92N_1 J19
1 IO_L92P_1 J18
1 IO_L91N_1 A18
1 IO_L91P_1/VREF_1 A19
1 IO_L84N_1 D18
1 IO_L84P_1 D19
1 IO_L83N_1 K19
1 IO_L83P_1 K18
1 IO_L82N_1 B18
1 IO_L82P_1 B19
1 IO_L81N_1/VREF_1 G18
1 IO_L81P_1 G19
1 IO_L80N_1 E18
1 IO_L80P_1 E17
1 IO_L79N_1 A16
1 IO_L79P_1 A17
1 IO_L78N_1 F17
1 IO_L78P_1 F18
1 IO_L77N_1 L19
1 IO_L77P_1 L18
1 IO_L76N_1 B16
1 IO_L76P_1 B17
1 IO_L75N_1/VREF_1 G16
1 IO_L75P_1 G17
1 IO_L74N_1 M19
1 IO_L74P_1 M18
1 IO_L73N_1 C16
1 IO_L73P_1 C17
1 IO_L72N_1 D15
1 IO_L72P_1 D16
1 IO_L71N_1 J17
1 IO_L71P_1 J16
1 IO_L70N_1 A14
1 IO_L70P_1 A15
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 159
1 IO_L69N_1/VREF_1 E15
1 IO_L69P_1 E16
1 IO_L68N_1 K17
1 IO_L68P_1 K16
1 IO_L67N_1 C15
1 IO_L67P_1 B15
1 IO_L60N_1 F15
1 IO_L60P_1 F16
1 IO_L59N_1 H16
1 IO_L59P_1 H15
1 IO_L58N_1 C13
1 IO_L58P_1 C14
1 IO_L57N_1/VREF_1 D13
1 IO_L57P_1 D14
1 IO_L56N_1 M17
1 IO_L56P_1 M16
1 IO_L55N_1 A12
1 IO_L55P_1 A13
1 IO_L54N_1 B12
1 IO_L54P_1 B13
1 IO_L53N_1 G15
1 IO_L53P_1 G14
1 IO_L52N_1 C11
1 IO_L52P_1 C12
1 IO_L51N_1/VREF_1 F13
1 IO_L51P_1 F14
1 IO_L50N_1 L16
1 IO_L50P_1 L15
1 IO_L49N_1 A10
1 IO_L49P_1 A11
1 IO_L36N_1 E12 NC
1 IO_L36P_1 E13 NC
1 IO_L35N_1 K15 NC
1 IO_L35P_1 J14 NC
1 IO_L34N_1 B9 NC
1 IO_L34P_1 B10 NC
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
160 1-800-255-7778 Advance Product Specification
1 IO_L33N_1/VREF_1 D11 NC
1 IO_L33P_1 D12 NC
1 IO_L32N_1 H14 NC
1 IO_L32P_1 H13 NC
1 IO_L31N_1 A8 NC
1 IO_L31P_1 A9 NC
1 IO_L30N_1 F11
1 IO_L30P_1 F12
1 IO_L29N_1 K14
1 IO_L29P_1 L14
1 IO_L28N_1 C9
1 IO_L28P_1 C10
1 IO_L27N_1/VREF_1 G11
1 IO_L27P_1 G12
1 IO_L26N_1 M15
1 IO_L26P_1 M14
1 IO_L25N_1 B7
1 IO_L25P_1 B8
1 IO_L24N_1 D9
1 IO_L24P_1 D10
1 IO_L23N_1 J13
1 IO_L23P_1 J12
1 IO_L22N_1 A6
1 IO_L22P_1 A7
1 IO_L21N_1/VREF_1 E9
1 IO_L21P_1 E10
1 IO_L20N_1 D8
1 IO_L20P_1 E7
1 IO_L19N_1 C7
1 IO_L19P_1 C8
1 IO_L12N_1 F9 NC
1 IO_L12P_1 F10 NC
1 IO_L11N_1 H12 NC
1 IO_L11P_1 H11 NC
1 IO_L10N_1 B5 NC
1 IO_L10P_1 B6 NC
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 161
1 IO_L09N_1/VREF_1 G9 NC
1 IO_L09P_1 G10 NC
1 IO_L08N_1 K13 NC
1 IO_L08P_1 K12 NC
1 IO_L07N_1 A4 NC
1 IO_L07P_1 A5 NC
1 IO_L06N_1 F8
1 IO_L06P_1 E8
1 IO_L05N_1 J11
1 IO_L05P_1 K11
1 IO_L04N_1 C5
1 IO_L04P_1/VREF_1 C6
1 IO_L03N_1/VRP_1 D6
1 IO_L03P_1/VRN_1 D7
1 IO_L02N_1 H10
1 IO_L02P_1 J10
1 IO_L01N_1 C4
1 IO_L01P_1 B4
2 IO_L01N_2 E3
2 IO_L01P_2 D2
2 IO_L02N_2/VRP_2 L13
2 IO_L02P_2/VRN_2 M13
2 IO_L03N_2 F4
2 IO_L03P_2/VREF_2 E4
2 IO_L04N_2 E1
2 IO_L04P_2 D1
2 IO_L05N_2 L12
2 IO_L05P_2 M11
2 IO_L06N_2 G6
2 IO_L06P_2 F5
2 IO_L07N_2 F2 NC
2 IO_L07P_2 E2 NC
2 IO_L08N_2 M12 NC
2 IO_L08P_2 N12 NC
2 IO_L09N_2 H6 NC
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
162 1-800-255-7778 Advance Product Specification
2 IO_L09P_2/VREF_2 H7 NC
2 IO_L10N_2 G3 NC
2 IO_L10P_2 F3 NC
2 IO_L11N_2 J8 NC
2 IO_L11P_2 K8 NC
2 IO_L12N_2 H5 NC
2 IO_L12P_2 G5 NC
2 IO_L19N_2 G1
2 IO_L19P_2 F1
2 IO_L20N_2 K9
2 IO_L20P_2 L10
2 IO_L21N_2 K7
2 IO_L21P_2/VREF_2 J7
2 IO_L22N_2 H2
2 IO_L22P_2 G2
2 IO_L23N_2 L9
2 IO_L23P_2 M9
2 IO_L24N_2 H4
2 IO_L24P_2 G4
2 IO_L25N_2 J3
2 IO_L25P_2 H3
2 IO_L26N_2 M10
2 IO_L26P_2 N10
2 IO_L27N_2 K6
2 IO_L27P_2/VREF_2 J6
2 IO_L28N_2 K5
2 IO_L28P_2 J5
2 IO_L29N_2 N11
2 IO_L29P_2 P11
2 IO_L30N_2 M7
2 IO_L30P_2 L7
2 IO_L31N_2 J1 NC
2 IO_L31P_2 H1 NC
2 IO_L32N_2 L8 NC
2 IO_L32P_2 M8 NC
2 IO_L33N_2 K4 NC
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 163
2 IO_L33P_2/VREF_2 J4 NC
2 IO_L34N_2 K2 NC
2 IO_L34P_2 J2 NC
2 IO_L35N_2 P12 NC
2 IO_L35P_2 R12 NC
2 IO_L36N_2 M6 NC
2 IO_L36P_2 L6 NC
2 IO_L43N_2 L3
2 IO_L43P_2 K3
2 IO_L44N_2 N9
2 IO_L44P_2 P9
2 IO_L45N_2 M4
2 IO_L45P_2/VREF_2 L4
2 IO_L46N_2 L1
2 IO_L46P_2 K1
2 IO_L47N_2 P10
2 IO_L47P_2 R10
2 IO_L48N_2 N5
2 IO_L48P_2 M5
2 IO_L49N_2 N3
2 IO_L49P_2 M3
2 IO_L50N_2 N8
2 IO_L50P_2 P8
2 IO_L51N_2 T11
2 IO_L51P_2/VREF_2 R11
2 IO_L52N_2 N2
2 IO_L52P_2 M2
2 IO_L53N_2 T12
2 IO_L53P_2 U12
2 IO_L54N_2 P6
2 IO_L54P_2 N6
2 IO_L55N_2 N1
2 IO_L55P_2 M1
2 IO_L56N_2 R8
2 IO_L56P_2 T8
2 IO_L57N_2 R7
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
164 1-800-255-7778 Advance Product Specification
2 IO_L57P_2/VREF_2 P7
2 IO_L58N_2 R3
2 IO_L58P_2 P3
2 IO_L59N_2 T10
2 IO_L59P_2 U10
2 IO_L60N_2 P4
2 IO_L60P_2 N4
2 IO_L67N_2 T6
2 IO_L67P_2 R6
2 IO_L68N_2 T9
2 IO_L68P_2 U9
2 IO_L69N_2 T5
2 IO_L69P_2/VREF_2 R5
2 IO_L70N_2 R1
2 IO_L70P_2 P1
2 IO_L71N_2 V12
2 IO_L71P_2 W12
2 IO_L72N_2 T4
2 IO_L72P_2 R4
2 IO_L73N_2 T2
2 IO_L73P_2 R2
2 IO_L74N_2 V11
2 IO_L74P_2 W11
2 IO_L75N_2 U7
2 IO_L75P_2/VREF_2 T7
2 IO_L76N_2 U3
2 IO_L76P_2 T3
2 IO_L77N_2 V10
2 IO_L77P_2 W10
2 IO_L78N_2 V6
2 IO_L78P_2 U6
2 IO_L79N_2 U1
2 IO_L79P_2 T1
2 IO_L80N_2 V9
2 IO_L80P_2 W9
2 IO_L81N_2 V5
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 165
2 IO_L81P_2/VREF_2 U5
2 IO_L82N_2 V2
2 IO_L82P_2 U2
2 IO_L83N_2 V8
2 IO_L83P_2 W8
2 IO_L84N_2 W7
2 IO_L84P_2 V7
2 IO_L91N_2 W1
2 IO_L91P_2 V1
2 IO_L92N_2 Y11
2 IO_L92P_2 Y12
2 IO_L93N_2 W4
2 IO_L93P_2/VREF_2 V4
2 IO_L94N_2 W2
2 IO_L94P_2 W3
2 IO_L95N_2 Y8
2 IO_L95P_2 Y9
2 IO_L96N_2 W5
2 IO_L96P_2 W6
3 IO_L96N_3 AB8
3 IO_L96P_3 AA8
3 IO_L95N_3 Y3
3 IO_L95P_3 AA3
3 IO_L94N_3 Y6
3 IO_L94P_3 AA6
3 IO_L93N_3/VREF_3 AB9
3 IO_L93P_3 AA9
3 IO_L92N_3 AA1
3 IO_L92P_3 AB1
3 IO_L91N_3 Y5
3 IO_L91P_3 AA5
3 IO_L84N_3 AB10
3 IO_L84P_3 AA10
3 IO_L83N_3 AA2
3 IO_L83P_3 AB2
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
166 1-800-255-7778 Advance Product Specification
3 IO_L82N_3 AA4
3 IO_L82P_3 AB4
3 IO_L81N_3/VREF_3 AB11
3 IO_L81P_3 AA11
3 IO_L80N_3 AC1
3 IO_L80P_3 AD1
3 IO_L79N_3 AA7
3 IO_L79P_3 AB7
3 IO_L78N_3 AB12
3 IO_L78P_3 AA12
3 IO_L77N_3 AC2
3 IO_L77P_3 AC3
3 IO_L76N_3 AB5
3 IO_L76P_3 AC5
3 IO_L75N_3/VREF_3 AD9
3 IO_L75P_3 AC9
3 IO_L74N_3 AD2
3 IO_L74P_3 AE2
3 IO_L73N_3 AB6
3 IO_L73P_3 AC6
3 IO_L72N_3 AD10
3 IO_L72P_3 AC10
3 IO_L71N_3 AD3
3 IO_L71P_3 AE3
3 IO_L70N_3 AC7
3 IO_L70P_3 AD7
3 IO_L69N_3/VREF_3 AE8
3 IO_L69P_3 AD8
3 IO_L68N_3 AE1
3 IO_L68P_3 AF1
3 IO_L67N_3 AD4
3 IO_L67P_3 AE4
3 IO_L60N_3 AD12
3 IO_L60P_3 AC12
3 IO_L59N_3 AF3
3 IO_L59P_3 AG3
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 167
3 IO_L58N_3 AD5
3 IO_L58P_3 AE5
3 IO_L57N_3/VREF_3 AE11
3 IO_L57P_3 AD11
3 IO_L56N_3 AG1
3 IO_L56P_3 AH1
3 IO_L55N_3 AD6
3 IO_L55P_3 AE6
3 IO_L54N_3 AF10
3 IO_L54P_3 AE10
3 IO_L53N_3 AG2
3 IO_L53P_3 AH2
3 IO_L52N_3 AF4
3 IO_L52P_3 AG4
3 IO_L51N_3/VREF_3 AG8
3 IO_L51P_3 AF8
3 IO_L50N_3 AH3
3 IO_L50P_3 AJ3
3 IO_L49N_3 AE7
3 IO_L49P_3 AF7
3 IO_L48N_3 AG9
3 IO_L48P_3 AF9
3 IO_L47N_3 AF6
3 IO_L47P_3 AG6
3 IO_L46N_3 AG5
3 IO_L46P_3 AH5
3 IO_L45N_3/VREF_3 AF12
3 IO_L45P_3 AE12
3 IO_L44N_3 AJ1
3 IO_L44P_3 AK1
3 IO_L43N_3 AH4
3 IO_L43P_3 AJ4
3 IO_L36N_3 AG11 NC
3 IO_L36P_3 AF11 NC
3 IO_L35N_3 AK2 NC
3 IO_L35P_3 AL2 NC
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
168 1-800-255-7778 Advance Product Specification
3 IO_L34N_3 AH6 NC
3 IO_L34P_3 AJ6 NC
3 IO_L33N_3/VREF_3 AJ8 NC
3 IO_L33P_3 AH8 NC
3 IO_L32N_3 AL1 NC
3 IO_L32P_3 AM1 NC
3 IO_L31N_3 AH7 NC
3 IO_L31P_3 AJ7 NC
3 IO_L30N_3 AH10
3 IO_L30P_3 AG10
3 IO_L29N_3 AK3
3 IO_L29P_3 AL3
3 IO_L28N_3 AK4
3 IO_L28P_3 AL4
3 IO_L27N_3/VREF_3 AJ9
3 IO_L27P_3 AH9
3 IO_L26N_3 AM2
3 IO_L26P_3 AN2
3 IO_L25N_3 AK5
3 IO_L25P_3 AL5
3 IO_L24N_3 AK9
3 IO_L24P_3 AK8
3 IO_L23N_3 AN1
3 IO_L23P_3 AP1
3 IO_L22N_3 AK6
3 IO_L22P_3 AL6
3 IO_L21N_3/VREF_3 AH12
3 IO_L21P_3 AG12
3 IO_L20N_3 AM3
3 IO_L20P_3 AN3
3 IO_L19N_3 AM4
3 IO_L19P_3 AN4
3 IO_L12N_3 AJ12 NC
3 IO_L12P_3 AH11 NC
3 IO_L11N_3 AP2 NC
3 IO_L11P_3 AR2 NC
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 169
3 IO_L10N_3 AK7 NC
3 IO_L10P_3 AL7 NC
3 IO_L09N_3/VREF_3 AK11 NC
3 IO_L09P_3 AJ10 NC
3 IO_L08N_3 AR1 NC
3 IO_L08P_3 AT1 NC
3 IO_L07N_3 AM5 NC
3 IO_L07P_3 AN5 NC
3 IO_L06N_3 AM7
3 IO_L06P_3 AL8
3 IO_L05N_3 AP3
3 IO_L05P_3 AP4
3 IO_L04N_3 AM6
3 IO_L04P_3 AN6
3 IO_L03N_3/VREF_3 AJ13
3 IO_L03P_3 AH13
3 IO_L02N_3/VRP_3 AR3
3 IO_L02P_3/VRN_3 AT2
3 IO_L01N_3 AP5
3 IO_L01P_3 AR4
4 IO_L01N_4/DOUT AV4
4 IO_L01P_4/INIT_B AU4
4 IO_L02N_4/D0 AM9
4 IO_L02P_4/D1 AM10
4 IO_L03N_4/D2/ALT_VRP_4 AT6
4 IO_L03P_4/D3/ALT_VRN_4 AR6
4 IO_L04N_4/VREF_4 AU6
4 IO_L04P_4 AU5
4 IO_L05N_4/VRP_4 AL10
4 IO_L05P_4/VRN_4 AL11
4 IO_L06N_4 AR8
4 IO_L06P_4 AR7
4 IO_L07N_4 AW5 NC
4 IO_L07P_4 AW4 NC
4 IO_L08N_4 AK12 NC
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
170 1-800-255-7778 Advance Product Specification
4 IO_L08P_4 AL12 NC
4 IO_L09N_4 AP9 NC
4 IO_L09P_4/VREF_4 AP8 NC
4 IO_L10N_4 AV6 NC
4 IO_L10P_4 AV5 NC
4 IO_L11N_4 AM11 NC
4 IO_L11P_4 AM12 NC
4 IO_L12N_4 AN10 NC
4 IO_L12P_4 AN9 NC
4 IO_L19N_4 AU8
4 IO_L19P_4 AU7
4 IO_L20N_4 AH14
4 IO_L20P_4 AH15
4 IO_L21N_4 AT8
4 IO_L21P_4/VREF_4 AT7
4 IO_L22N_4 AW7
4 IO_L22P_4 AW6
4 IO_L23N_4 AK13
4 IO_L23P_4 AK14
4 IO_L24N_4 AR10
4 IO_L24P_4 AR9
4 IO_L25N_4 AV8
4 IO_L25P_4 AV7
4 IO_L26N_4 AJ14
4 IO_L26P_4 AJ15
4 IO_L27N_4 AP11
4 IO_L27P_4/VREF_4 AP10
4 IO_L28N_4 AU10
4 IO_L28P_4 AU9
4 IO_L29N_4 AL13
4 IO_L29P_4 AL14
4 IO_L30N_4 AN12
4 IO_L30P_4 AN11
4 IO_L31N_4 AW9 NC
4 IO_L31P_4 AW8 NC
4 IO_L32N_4 AM13 NC
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 171
4 IO_L32P_4 AM14 NC
4 IO_L33N_4 AT10 NC
4 IO_L33P_4/VREF_4 AT9 NC
4 IO_L34N_4 AV10 NC
4 IO_L34P_4 AV9 NC
4 IO_L35N_4 AH16 NC
4 IO_L35P_4 AH17 NC
4 IO_L36N_4 AP13 NC
4 IO_L36P_4 AP12 NC
4 IO_L49N_4 AU12
4 IO_L49P_4 AU11
4 IO_L50N_4 AK15
4 IO_L50P_4 AJ16
4 IO_L51N_4 AT12
4 IO_L51P_4/VREF_4 AT11
4 IO_L52N_4 AN15
4 IO_L52P_4 AN14
4 IO_L53N_4 AR12
4 IO_L53P_4 AR13
4 IO_L54N_4 AT14
4 IO_L54P_4 AT13
4 IO_L55N_4 AW11
4 IO_L55P_4 AW10
4 IO_L56N_4 AM15
4 IO_L56P_4 AM16
4 IO_L57N_4 AP15
4 IO_L57P_4/VREF_4 AP14
4 IO_L58N_4 AV13
4 IO_L58P_4 AV12
4 IO_L59N_4 AK16
4 IO_L59P_4 AK17
4 IO_L60N_4 AR16
4 IO_L60P_4 AR15
4 IO_L67N_4 AW13
4 IO_L67P_4 AW12
4 IO_L68N_4 AL16
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
172 1-800-255-7778 Advance Product Specification
4 IO_L68P_4 AL17
4 IO_L69N_4 AT16
4 IO_L69P_4/VREF_4 AT15
4 IO_L70N_4 AU14
4 IO_L70P_4 AU13
4 IO_L71N_4 AH18
4 IO_L71P_4 AH19
4 IO_L72N_4 AN17
4 IO_L72P_4 AN16
4 IO_L73N_4 AW15
4 IO_L73P_4 AW14
4 IO_L74N_4 AJ18
4 IO_L74P_4 AJ19
4 IO_L75N_4 AP17
4 IO_L75P_4/VREF_4 AP16
4 IO_L76N_4 AV15
4 IO_L76P_4 AU15
4 IO_L77N_4 AK18
4 IO_L77P_4 AK19
4 IO_L78N_4 AR18
4 IO_L78P_4 AR17
4 IO_L79N_4 AU17
4 IO_L79P_4 AU16
4 IO_L80N_4 AL18
4 IO_L80P_4 AL19
4 IO_L81N_4 AN19
4 IO_L81P_4/VREF_4 AN18
4 IO_L82N_4 AV17
4 IO_L82P_4 AV16
4 IO_L83N_4 AM18
4 IO_L83P_4 AM19
4 IO_L84N_4 AP19
4 IO_L84P_4 AP18
4 IO_L85N_4 AW17 NC NC
4 IO_L85P_4 AW16 NC NC
4 IO_L91N_4/VREF_4 AV19
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 173
4 IO_L91P_4 AV18
4 IO_L92N_4 AH20
4 IO_L92P_4 AJ20
4 IO_L93N_4 AR19
4 IO_L93P_4 AT18
4 IO_L94N_4/VREF_4 AW19
4 IO_L94P_4 AW18
4 IO_L95N_4/GCLK3S AL20
4 IO_L95P_4/GCLK2P AM20
4 IO_L96N_4/GCLK1S AU19
4 IO_L96P_4/GCLK0P AT19
5 IO_L96N_5/GCLK7S AP21
5 IO_L96P_5/GCLK6P AP20
5 IO_L95N_5/GCLK5S AN21
5 IO_L95P_5/GCLK4P AN22
5 IO_L94N_5 AU21
5 IO_L94P_5/VREF_5 AU20
5 IO_L93N_5 AR21
5 IO_L93P_5 AR20
5 IO_L92N_5 AM21
5 IO_L92P_5 AM22
5 IO_L91N_5 AW22
5 IO_L91P_5/VREF_5 AW21
5 IO_L85N_5 AV22 NC NC
5 IO_L85P_5 AV21 NC NC
5 IO_L84N_5 AT22
5 IO_L84P_5 AT21
5 IO_L83N_5 AL21
5 IO_L83P_5 AL22
5 IO_L82N_5 AW24
5 IO_L82P_5 AW23
5 IO_L81N_5/VREF_5 AR23
5 IO_L81P_5 AR22
5 IO_L80N_5 AK21
5 IO_L80P_5 AK22
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
174 1-800-255-7778 Advance Product Specification
5 IO_L79N_5 AV24
5 IO_L79P_5 AV23
5 IO_L78N_5 AP23
5 IO_L78P_5 AP22
5 IO_L77N_5 AJ21
5 IO_L77P_5 AJ22
5 IO_L76N_5 AU24
5 IO_L76P_5 AU23
5 IO_L75N_5/VREF_5 AT25
5 IO_L75P_5 AT24
5 IO_L74N_5 AH21
5 IO_L74P_5 AH22
5 IO_L73N_5 AW26
5 IO_L73P_5 AW25
5 IO_L72N_5 AR25
5 IO_L72P_5 AR24
5 IO_L71N_5 AN23
5 IO_L71P_5 AN24
5 IO_L70N_5 AU25
5 IO_L70P_5 AV25
5 IO_L69N_5/VREF_5 AL24
5 IO_L69P_5 AL23
5 IO_L68N_5 AK23
5 IO_L68P_5 AK24
5 IO_L67N_5 AU27
5 IO_L67P_5 AU26
5 IO_L60N_5 AP25
5 IO_L60P_5 AP24
5 IO_L59N_5 AM24
5 IO_L59P_5 AM25
5 IO_L58N_5 AW28
5 IO_L58P_5 AW27
5 IO_L57N_5/VREF_5 AT27
5 IO_L57P_5 AT26
5 IO_L56N_5 AH23
5 IO_L56P_5 AH24
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 175
5 IO_L55N_5 AV28
5 IO_L55P_5 AV27
5 IO_L54N_5 AP27
5 IO_L54P_5 AP26
5 IO_L53N_5 AN25
5 IO_L53P_5 AN26
5 IO_L52N_5 AU29
5 IO_L52P_5 AU28
5 IO_L51N_5/VREF_5 AR28
5 IO_L51P_5 AR27
5 IO_L50N_5 AJ24
5 IO_L50P_5 AJ25
5 IO_L49N_5 AW30
5 IO_L49P_5 AW29
5 IO_L36N_5 AT29 NC
5 IO_L36P_5 AT28 NC
5 IO_L35N_5 AK25 NC
5 IO_L35P_5 AL26 NC
5 IO_L34N_5 AV31 NC
5 IO_L34P_5 AV30 NC
5 IO_L33N_5/VREF_5 AP29 NC
5 IO_L33P_5 AP28 NC
5 IO_L32N_5 AK26 NC
5 IO_L32P_5 AJ26 NC
5 IO_L31N_5 AW32 NC
5 IO_L31P_5 AW31 NC
5 IO_L30N_5 AM27
5 IO_L30P_5 AM26
5 IO_L29N_5 AN28
5 IO_L29P_5 AN29
5 IO_L28N_5 AU31
5 IO_L28P_5 AU30
5 IO_L27N_5/VREF_5 AT31
5 IO_L27P_5 AT30
5 IO_L26N_5 AH25
5 IO_L26P_5 AH26
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
176 1-800-255-7778 Advance Product Specification
5 IO_L25N_5 AV33
5 IO_L25P_5 AV32
5 IO_L24N_5 AR31
5 IO_L24P_5 AR30
5 IO_L23N_5 AL27
5 IO_L23P_5 AL28
5 IO_L22N_5 AW34
5 IO_L22P_5 AW33
5 IO_L21N_5/VREF_5 AN30
5 IO_L21P_5 AP30
5 IO_L20N_5 AM28
5 IO_L20P_5 AM29
5 IO_L19N_5 AU33
5 IO_L19P_5 AU32
5 IO_L12N_5 AT33 NC
5 IO_L12P_5 AT32 NC
5 IO_L11N_5 AK27 NC
5 IO_L11P_5 AK28 NC
5 IO_L10N_5 AV35 NC
5 IO_L10P_5 AV34 NC
5 IO_L09N_5/VREF_5 AP32 NC
5 IO_L09P_5 AP31 NC
5 IO_L08N_5 AL29 NC
5 IO_L08P_5 AK29 NC
5 IO_L07N_5 AW36 NC
5 IO_L07P_5 AW35 NC
5 IO_L06N_5 AR33
5 IO_L06P_5 AR32
5 IO_L05N_5/VRP_5 AM30
5 IO_L05P_5/VRN_5 AL30
5 IO_L04N_5 AU35
5 IO_L04P_5/VREF_5 AU34
5 IO_L03N_5/D4/ALT_VRP_5 AR34
5 IO_L03P_5/D5/ALT_VRN_5 AT34
5 IO_L02N_5/D6 AN31
5 IO_L02P_5/D7 AM31
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 177
5 IO_L01N_5/RDWR_B AU36
5 IO_L01P_5/CS_B AV36
6 IO_L01P_6 AJ27
6 IO_L01N_6 AH27
6 IO_L02P_6/VRN_6 AT38
6 IO_L02N_6/VRP_6 AR37
6 IO_L03P_6 AP36
6 IO_L03N_6/VREF_6 AR36
6 IO_L04P_6 AJ28
6 IO_L04N_6 AH29
6 IO_L05P_6 AT39
6 IO_L05N_6 AR39
6 IO_L06P_6 AN34
6 IO_L06N_6 AP35
6 IO_L07P_6 AH28 NC
6 IO_L07N_6 AG28 NC
6 IO_L08P_6 AR38 NC
6 IO_L08N_6 AP38 NC
6 IO_L09P_6 AM34 NC
6 IO_L09N_6/VREF_6 AM33 NC
6 IO_L10P_6 AL32 NC
6 IO_L10N_6 AK32 NC
6 IO_L11P_6 AP37 NC
6 IO_L11N_6 AN37 NC
6 IO_L12P_6 AM35 NC
6 IO_L12N_6 AN35 NC
6 IO_L19P_6 AK31
6 IO_L19N_6 AJ30
6 IO_L20P_6 AP39
6 IO_L20N_6 AN39
6 IO_L21P_6 AK33
6 IO_L21N_6/VREF_6 AL33
6 IO_L22P_6 AJ31
6 IO_L22N_6 AH31
6 IO_L23P_6 AN38
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
178 1-800-255-7778 Advance Product Specification
6 IO_L23N_6 AM38
6 IO_L24P_6 AM36
6 IO_L24N_6 AN36
6 IO_L25P_6 AH30
6 IO_L25N_6 AG30
6 IO_L26P_6 AM37
6 IO_L26N_6 AL37
6 IO_L27P_6 AK34
6 IO_L27N_6/VREF_6 AL34
6 IO_L28P_6 AG29
6 IO_L28N_6 AF29
6 IO_L29P_6 AL35
6 IO_L29N_6 AK35
6 IO_L30P_6 AH33
6 IO_L30N_6 AJ33
6 IO_L31P_6 AJ32 NC
6 IO_L31N_6 AH32 NC
6 IO_L32P_6 AM39 NC
6 IO_L32N_6 AL39 NC
6 IO_L33P_6 AK36 NC
6 IO_L33N_6/VREF_6 AL36 NC
6 IO_L34P_6 AF28 NC
6 IO_L34N_6 AE28 NC
6 IO_L35P_6 AL38 NC
6 IO_L35N_6 AK38 NC
6 IO_L36P_6 AH34 NC
6 IO_L36N_6 AJ34 NC
6 IO_L43P_6 AG31
6 IO_L43N_6 AF31
6 IO_L44P_6 AK37
6 IO_L44N_6 AJ37
6 IO_L45P_6 AH36
6 IO_L45N_6/VREF_6 AJ36
6 IO_L46P_6 AF30
6 IO_L46N_6 AE30
6 IO_L47P_6 AK39
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 179
6 IO_L47N_6 AJ39
6 IO_L48P_6 AG35
6 IO_L48N_6 AH35
6 IO_L49P_6 AG32
6 IO_L49N_6 AF32
6 IO_L50P_6 AH37
6 IO_L50N_6 AG37
6 IO_L51P_6 AD29
6 IO_L51N_6/VREF_6 AE29
6 IO_L52P_6 AD28
6 IO_L52N_6 AC28
6 IO_L53P_6 AH38
6 IO_L53N_6 AG38
6 IO_L54P_6 AF34
6 IO_L54N_6 AG34
6 IO_L55P_6 AE32
6 IO_L55N_6 AD32
6 IO_L56P_6 AH39
6 IO_L56N_6 AG39
6 IO_L57P_6 AE33
6 IO_L57N_6/VREF_6 AF33
6 IO_L58P_6 AD30
6 IO_L58N_6 AC30
6 IO_L59P_6 AF37
6 IO_L59N_6 AE37
6 IO_L60P_6 AF36
6 IO_L60N_6 AG36
6 IO_L67P_6 AD31
6 IO_L67N_6 AC31
6 IO_L68P_6 AE34
6 IO_L68N_6 AD34
6 IO_L69P_6 AD35
6 IO_L69N_6/VREF_6 AE35
6 IO_L70P_6 AB28
6 IO_L70N_6 AA28
6 IO_L71P_6 AF39
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
180 1-800-255-7778 Advance Product Specification
6 IO_L71N_6 AE39
6 IO_L72P_6 AD36
6 IO_L72N_6 AE36
6 IO_L73P_6 AB29
6 IO_L73N_6 AA29
6 IO_L74P_6 AE38
6 IO_L74N_6 AD38
6 IO_L75P_6 AC33
6 IO_L75N_6/VREF_6 AD33
6 IO_L76P_6 AB30
6 IO_L76N_6 AA30
6 IO_L77P_6 AD37
6 IO_L77N_6 AC37
6 IO_L78P_6 AB34
6 IO_L78N_6 AC34
6 IO_L79P_6 AB31
6 IO_L79N_6 AA31
6 IO_L80P_6 AD39
6 IO_L80N_6 AC39
6 IO_L81P_6 AB35
6 IO_L81N_6/VREF_6 AC35
6 IO_L82P_6 AB32
6 IO_L82N_6 AA32
6 IO_L83P_6 AC38
6 IO_L83N_6 AB38
6 IO_L84P_6 AA33
6 IO_L84N_6 AB33
6 IO_L91P_6 Y28
6 IO_L91N_6 Y29
6 IO_L92P_6 AB39
6 IO_L92N_6 AA39
6 IO_L93P_6 AA36
6 IO_L93N_6/VREF_6 AB36
6 IO_L94P_6 Y31
6 IO_L94N_6 Y32
6 IO_L95P_6 AA37
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 181
6 IO_L95N_6 AA38
6 IO_L96P_6 AA35
6 IO_L96N_6 AA34
7 IO_L96P_7 W34
7 IO_L96N_7 Y34
7 IO_L95P_7 W32
7 IO_L95N_7 V32
7 IO_L94P_7 W37
7 IO_L94N_7 Y37
7 IO_L93P_7/VREF_7 W35
7 IO_L93N_7 Y35
7 IO_L92P_7 W31
7 IO_L92N_7 V31
7 IO_L91P_7 V39
7 IO_L91N_7 W39
7 IO_L84P_7 V36
7 IO_L84N_7 W36
7 IO_L83P_7 W30
7 IO_L83N_7 V30
7 IO_L82P_7 V38
7 IO_L82N_7 W38
7 IO_L81P_7/VREF_7 V33
7 IO_L81N_7 W33
7 IO_L80P_7 W29
7 IO_L80N_7 V29
7 IO_L79P_7 T39
7 IO_L79N_7 U39
7 IO_L78P_7 U35
7 IO_L78N_7 V35
7 IO_L77P_7 W28
7 IO_L77N_7 V28
7 IO_L76P_7 U37
7 IO_L76N_7 U38
7 IO_L75P_7/VREF_7 U34
7 IO_L75N_7 V34
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
182 1-800-255-7778 Advance Product Specification
7 IO_L74P_7 U31
7 IO_L74N_7 T31
7 IO_L73P_7 R38
7 IO_L73N_7 T38
7 IO_L72P_7 T33
7 IO_L72N_7 U33
7 IO_L71P_7 U30
7 IO_L71N_7 T30
7 IO_L70P_7 R37
7 IO_L70N_7 T37
7 IO_L69P_7/VREF_7 R36
7 IO_L69N_7 T36
7 IO_L68P_7 T32
7 IO_L68N_7 R32
7 IO_L67P_7 P39
7 IO_L67N_7 R39
7 IO_L60P_7 R35
7 IO_L60N_7 T35
7 IO_L59P_7 U28
7 IO_L59N_7 T28
7 IO_L58P_7 N37
7 IO_L58N_7 P37
7 IO_L57P_7/VREF_7 R34
7 IO_L57N_7 T34
7 IO_L56P_7 T29
7 IO_L56N_7 R29
7 IO_L55P_7 M39
7 IO_L55N_7 N39
7 IO_L54P_7 N36
7 IO_L54N_7 P36
7 IO_L53P_7 R30
7 IO_L53N_7 P30
7 IO_L52P_7 M38
7 IO_L52N_7 N38
7 IO_L51P_7/VREF_7 P33
7 IO_L51N_7 R33
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 183
7 IO_L50P_7 P32
7 IO_L50N_7 N32
7 IO_L49P_7 L37
7 IO_L49N_7 M37
7 IO_L48P_7 N34
7 IO_L48N_7 P34
7 IO_L47P_7 P31
7 IO_L47N_7 N31
7 IO_L46P_7 M35
7 IO_L46N_7 N35
7 IO_L45P_7/VREF_7 L36
7 IO_L45N_7 M36
7 IO_L44P_7 R28
7 IO_L44N_7 P28
7 IO_L43P_7 K39
7 IO_L43N_7 L39
7 IO_L36P_7 L34 NC
7 IO_L36N_7 M34 NC
7 IO_L35P_7 P29 NC
7 IO_L35N_7 N29 NC
7 IO_L34P_7 J38 NC
7 IO_L34N_7 K38 NC
7 IO_L33P_7/VREF_7 L33 NC
7 IO_L33N_7 M33 NC
7 IO_L32P_7 M32 NC
7 IO_L32N_7 L32 NC
7 IO_L31P_7 H39 NC
7 IO_L31N_7 J39 NC
7 IO_L30P_7 J36
7 IO_L30N_7 K36
7 IO_L29P_7 N30
7 IO_L29N_7 M30
7 IO_L28P_7 J37
7 IO_L28N_7 K37
7 IO_L27P_7/VREF_7 J35
7 IO_L27N_7 K35
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
184 1-800-255-7778 Advance Product Specification
7 IO_L26P_7 M31
7 IO_L26N_7 L31
7 IO_L25P_7 G38
7 IO_L25N_7 H38
7 IO_L24P_7 J34
7 IO_L24N_7 K34
7 IO_L23P_7 K32
7 IO_L23N_7 K31
7 IO_L22P_7 F39
7 IO_L22N_7 G39
7 IO_L21P_7/VREF_7 G36
7 IO_L21N_7 H36
7 IO_L20P_7 N28
7 IO_L20N_7 M28
7 IO_L19P_7 G37
7 IO_L19N_7 H37
7 IO_L12P_7 J33 NC
7 IO_L12N_7 K33 NC
7 IO_L11P_7 M29 NC
7 IO_L11N_7 L28 NC
7 IO_L10P_7 E38 NC
7 IO_L10N_7 F38 NC
7 IO_L09P_7/VREF_7 G35 NC
7 IO_L09N_7 H35 NC
7 IO_L08P_7 L30 NC
7 IO_L08N_7 K29 NC
7 IO_L07P_7 D39 NC
7 IO_L07N_7 E39 NC
7 IO_L06P_7 G34
7 IO_L06N_7 H34
7 IO_L05P_7 J32
7 IO_L05N_7 H33
7 IO_L04P_7 F36
7 IO_L04N_7 F37
7 IO_L03P_7/VREF_7 E36
7 IO_L03N_7 F35
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 185
7 IO_L02P_7/VRN_7 M27
7 IO_L02N_7/VRP_7 L27
7 IO_L01P_7 D38
7 IO_L01N_7 E37
0 VCCO_0 P25
0 VCCO_0 P24
0 VCCO_0 P23
0 VCCO_0 P22
0 VCCO_0 P21
0 VCCO_0 N26
0 VCCO_0 N25
0 VCCO_0 N24
0 VCCO_0 N23
0 VCCO_0 N22
0 VCCO_0 N21
0 VCCO_0 L23
0 VCCO_0 J25
0 VCCO_0 G27
0 VCCO_0 E29
0 VCCO_0 C22
0 VCCO_0 B26
1 VCCO_1 P19
1 VCCO_1 P18
1 VCCO_1 P17
1 VCCO_1 P16
1 VCCO_1 P15
1 VCCO_1 N19
1 VCCO_1 N18
1 VCCO_1 N17
1 VCCO_1 N16
1 VCCO_1 N15
1 VCCO_1 N14
1 VCCO_1 L17
1 VCCO_1 J15
1 VCCO_1 G13
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
186 1-800-255-7778 Advance Product Specification
1 VCCO_1 E11
1 VCCO_1 C18
1 VCCO_1 B14
2 VCCO_2 W14
2 VCCO_2 W13
2 VCCO_2 V14
2 VCCO_2 V13
2 VCCO_2 V3
2 VCCO_2 U14
2 VCCO_2 U13
2 VCCO_2 U11
2 VCCO_2 T14
2 VCCO_2 T13
2 VCCO_2 R14
2 VCCO_2 R13
2 VCCO_2 R9
2 VCCO_2 P13
2 VCCO_2 P2
2 VCCO_2 N7
2 VCCO_2 L5
3 VCCO_3 AJ5
3 VCCO_3 AG7
3 VCCO_3 AF13
3 VCCO_3 AF2
3 VCCO_3 AE14
3 VCCO_3 AE13
3 VCCO_3 AE9
3 VCCO_3 AD14
3 VCCO_3 AD13
3 VCCO_3 AC14
3 VCCO_3 AC13
3 VCCO_3 AC11
3 VCCO_3 AB14
3 VCCO_3 AB13
3 VCCO_3 AB3
3 VCCO_3 AA14
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 187
3 VCCO_3 AA13
4 VCCO_4 AV14
4 VCCO_4 AU18
4 VCCO_4 AR11
4 VCCO_4 AN13
4 VCCO_4 AL15
4 VCCO_4 AJ17
4 VCCO_4 AG19
4 VCCO_4 AG18
4 VCCO_4 AG17
4 VCCO_4 AG16
4 VCCO_4 AG15
4 VCCO_4 AG14
4 VCCO_4 AF19
4 VCCO_4 AF18
4 VCCO_4 AF17
4 VCCO_4 AF16
4 VCCO_4 AF15
5 VCCO_5 AV26
5 VCCO_5 AU22
5 VCCO_5 AR29
5 VCCO_5 AN27
5 VCCO_5 AL25
5 VCCO_5 AJ23
5 VCCO_5 AG26
5 VCCO_5 AG25
5 VCCO_5 AG24
5 VCCO_5 AG23
5 VCCO_5 AG22
5 VCCO_5 AG21
5 VCCO_5 AF25
5 VCCO_5 AF24
5 VCCO_5 AF23
5 VCCO_5 AF22
5 VCCO_5 AF21
6 VCCO_6 AJ35
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
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188 1-800-255-7778 Advance Product Specification
6 VCCO_6 AG33
6 VCCO_6 AF38
6 VCCO_6 AF27
6 VCCO_6 AE31
6 VCCO_6 AE27
6 VCCO_6 AE26
6 VCCO_6 AD27
6 VCCO_6 AD26
6 VCCO_6 AC29
6 VCCO_6 AC27
6 VCCO_6 AC26
6 VCCO_6 AB37
6 VCCO_6 AB27
6 VCCO_6 AB26
6 VCCO_6 AA27
6 VCCO_6 AA26
7 VCCO_7 W27
7 VCCO_7 W26
7 VCCO_7 V37
7 VCCO_7 V27
7 VCCO_7 V26
7 VCCO_7 U29
7 VCCO_7 U27
7 VCCO_7 U26
7 VCCO_7 T27
7 VCCO_7 T26
7 VCCO_7 R31
7 VCCO_7 R27
7 VCCO_7 R26
7 VCCO_7 P38
7 VCCO_7 P27
7 VCCO_7 N33
7 VCCO_7 L35
NA CCLK AT5
NA PROG_B H31
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 189
NA DONE AP7
NA M0 AN32
NA M1 AP33
NA M2 AT35
NA HSWAP_EN E34
NA TCK G8
NA TDI D35
NA TDO E6
NA TMS F7
NA PWRDWN_B AN8
NA DXN G32
NA DXP F33
NA VBATT D5
NA RSVD H9
NA VCCAUX AV20
NA VCCAUX AT37
NA VCCAUX AT3
NA VCCAUX Y38
NA VCCAUX Y2
NA VCCAUX D37
NA VCCAUX D3
NA VCCAUX B20
NA VCCINT AG27
NA VCCINT AG20
NA VCCINT AG13
NA VCCINT AF26
NA VCCINT AF20
NA VCCINT AF14
NA VCCINT AE25
NA VCCINT AE24
NA VCCINT AE23
NA VCCINT AE22
NA VCCINT AE21
NA VCCINT AE20
NA VCCINT AE19
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
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190 1-800-255-7778 Advance Product Specification
NA VCCINT AE18
NA VCCINT AE17
NA VCCINT AE16
NA VCCINT AE15
NA VCCINT AD25
NA VCCINT AD24
NA VCCINT AD16
NA VCCINT AD15
NA VCCINT AC25
NA VCCINT AC15
NA VCCINT AB25
NA VCCINT AB15
NA VCCINT AA25
NA VCCINT AA15
NA VCCINT Y27
NA VCCINT Y26
NA VCCINT Y25
NA VCCINT Y15
NA VCCINT Y14
NA VCCINT Y13
NA VCCINT W25
NA VCCINT W15
NA VCCINT V25
NA VCCINT V15
NA VCCINT U25
NA VCCINT U15
NA VCCINT T25
NA VCCINT T24
NA VCCINT T16
NA VCCINT T15
NA VCCINT R25
NA VCCINT R24
NA VCCINT R23
NA VCCINT R22
NA VCCINT R21
NA VCCINT R20
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 191
NA VCCINT R19
NA VCCINT R18
NA VCCINT R17
NA VCCINT R16
NA VCCINT R15
NA VCCINT P26
NA VCCINT P20
NA VCCINT P14
NA VCCINT N27
NA VCCINT N20
NA VCCINT N13
NA GND AW38
NA GND AW37
NA GND AW20
NA GND AW3
NA GND AW2
NA GND AV39
NA GND AV38
NA GND AV37
NA GND AV29
NA GND AV11
NA GND AV3
NA GND AV2
NA GND AV1
NA GND AU39
NA GND AU38
NA GND AU37
NA GND AU3
NA GND AU2
NA GND AU1
NA GND AT36
NA GND AT23
NA GND AT20
NA GND AT17
NA GND AT4
NA GND AR35
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
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192 1-800-255-7778 Advance Product Specification
NA GND AR26
NA GND AR14
NA GND AR5
NA GND AP34
NA GND AP6
NA GND AN33
NA GND AN20
NA GND AN7
NA GND AM32
NA GND AM23
NA GND AM17
NA GND AM8
NA GND AL31
NA GND AL9
NA GND AK30
NA GND AK20
NA GND AK10
NA GND AJ38
NA GND AJ29
NA GND AJ11
NA GND AJ2
NA GND AF35
NA GND AF5
NA GND AD23
NA GND AD22
NA GND AD21
NA GND AD20
NA GND AD19
NA GND AD18
NA GND AD17
NA GND AC36
NA GND AC32
NA GND AC24
NA GND AC23
NA GND AC22
NA GND AC21
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 193
NA GND AC20
NA GND AC19
NA GND AC18
NA GND AC17
NA GND AC16
NA GND AC8
NA GND AC4
NA GND AB24
NA GND AB23
NA GND AB22
NA GND AB21
NA GND AB20
NA GND AB19
NA GND AB18
NA GND AB17
NA GND AB16
NA GND AA24
NA GND AA23
NA GND AA22
NA GND AA21
NA GND AA20
NA GND AA19
NA GND AA18
NA GND AA17
NA GND AA16
NA GND Y39
NA GND Y36
NA GND Y33
NA GND Y30
NA GND Y24
NA GND Y23
NA GND Y22
NA GND Y21
NA GND Y20
NA GND Y19
NA GND Y18
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
194 1-800-255-7778 Advance Product Specification
NA GND Y17
NA GND Y16
NA GND Y10
NA GND Y7
NA GND Y4
NA GND Y1
NA GND W24
NA GND W23
NA GND W22
NA GND W21
NA GND W20
NA GND W19
NA GND W18
NA GND W17
NA GND W16
NA GND V24
NA GND V23
NA GND V22
NA GND V21
NA GND V20
NA GND V19
NA GND V18
NA GND V17
NA GND V16
NA GND U36
NA GND U32
NA GND U24
NA GND U23
NA GND U22
NA GND U21
NA GND U20
NA GND U19
NA GND U18
NA GND U17
NA GND U16
NA GND U8
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 195
NA GND U4
NA GND T23
NA GND T22
NA GND T21
NA GND T20
NA GND T19
NA GND T18
NA GND T17
NA GND P35
NA GND P5
NA GND L38
NA GND L29
NA GND L11
NA GND L2
NA GND K30
NA GND K20
NA GND K10
NA GND J31
NA GND J9
NA GND H32
NA GND H23
NA GND H17
NA GND H8
NA GND G33
NA GND G20
NA GND G7
NA GND F34
NA GND F6
NA GND E35
NA GND E26
NA GND E14
NA GND E5
NA GND D36
NA GND D23
NA GND D20
NA GND D17
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
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196 1-800-255-7778 Advance Product Specification
NA GND D4
NA GND C39
NA GND C38
NA GND C37
NA GND C3
NA GND C2
NA GND C1
NA GND B39
NA GND B38
NA GND B37
NA GND B29
NA GND B11
NA GND B3
NA GND B2
NA GND B1
NA GND A38
NA GND A37
NA GND A20
NA GND A3
NA GND A2
Table 13: FF1517 BGA — XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in the XC2V4000 No Connect in the XC2V6000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 197
FF1517 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)
Figure 9: FF1517 Flip-Chip Fine-Pitch BGA Package Specifications
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
198 1-800-255-7778 Advance Product Specification
BF957 Flip-Chip BGA Package
As shown in Table 14, XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Virtex-II devices are available in the
BF957 package. Pins in each of these devices are the same, except for the pin differences in the XC2V2000 device shown
in the No Connect column. Following this table are the BF957 Flip-Chip BGA Package Specifications (1.27mm pitch).
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
0 IO_L01N_0 H23
0 IO_L01P_0 H22
0 IO_L02N_0 G24
0 IO_L02P_0 E25
0 IO_L03N_0/VRP_0 B29
0 IO_L03P_0/VRN_0 C27
0 IO_L04N_0/VREF_0 F24
0 IO_L04P_0 F23
0 IO_L05N_0 D26
0 IO_L05P_0 D25
0 IO_L06N_0 A28
0 IO_L06P_0 A27
0 IO_L19N_0 J22
0 IO_L19P_0 J21
0 IO_L20N_0 G23
0 IO_L20P_0 G22
0 IO_L21N_0 B27
0 IO_L21P_0/VREF_0 B26
0 IO_L22N_0 K20
0 IO_L22P_0 K19
0 IO_L23N_0 C26
0 IO_L23P_0 C24
0 IO_L24N_0 D24
0 IO_L24P_0 D23
0 IO_L25N_0 E24 NC
0 IO_L25P_0 E23 NC
0 IO_L26N_0 G21 NC
0 IO_L26P_0 G20 NC
0 IO_L27N_0 A26 NC
0 IO_L27P_0/VREF_0 A25 NC
0 IO_L29N_0 H21 NC
0 IO_L29P_0 H20 NC
0 IO_L30N_0 B25 NC
0 IO_L30P_0 B23 NC
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 199
0 IO_L49N_0 C23
0 IO_L49P_0 C22
0 IO_L50N_0 E22
0 IO_L50P_0 E21
0 IO_L51N_0 F21
0 IO_L51P_0/VREF_0 F20
0 IO_L52N_0 A24
0 IO_L52P_0 A23
0 IO_L53N_0 E20
0 IO_L53P_0 E19
0 IO_L54N_0 B22
0 IO_L54P_0 B21
0 IO_L67N_0 D21
0 IO_L67P_0 D20
0 IO_L68N_0 J20
0 IO_L68P_0 J19
0 IO_L69N_0 F19
0 IO_L69P_0/VREF_0 F18
0 IO_L70N_0 A22
0 IO_L70P_0 A21
0 IO_L71N_0 H19
0 IO_L71P_0 H17
0 IO_L72N_0 C21
0 IO_L72P_0 C20
0 IO_L73N_0 B20
0 IO_L73P_0 B19
0 IO_L74N_0 G18
0 IO_L74P_0 G17
0 IO_L75N_0 E18
0 IO_L75P_0/VREF_0 D17
0 IO_L76N_0 A20
0 IO_L76P_0 A19
0 IO_L77N_0 D19
0 IO_L77P_0 D18
0 IO_L78N_0 C19
0 IO_L78P_0 C17
0 IO_L91N_0/VREF_0 K18
0 IO_L91P_0 J18
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
200 1-800-255-7778 Advance Product Specification
0 IO_L92N_0 F17
0 IO_L92P_0 F16
0 IO_L93N_0 B18
0 IO_L93P_0 B17
0 IO_L94N_0/VREF_0 J17
0 IO_L94P_0 J16
0 IO_L95N_0/GCLK7P E17
0 IO_L95P_0/GCLK6S E16
0 IO_L96N_0/GCLK5P A18
0 IO_L96P_0/GCLK4S A17
1 IO_L96N_1/GCLK3P C16
1 IO_L96P_1/GCLK2S C15
1 IO_L95N_1/GCLK1P H16
1 IO_L95P_1/GCLK0S H15
1 IO_L94N_1 A15
1 IO_L94P_1/VREF_1 A14
1 IO_L93N_1 F15
1 IO_L93P_1 F14
1 IO_L92N_1 G15
1 IO_L92P_1 G14
1 IO_L91N_1 B15
1 IO_L91P_1/VREF_1 B14
1 IO_L78N_1 D15
1 IO_L78P_1 E15
1 IO_L77N_1 J15
1 IO_L77P_1 K14
1 IO_L76N_1 D14
1 IO_L76P_1 D13
1 IO_L75N_1/VREF_1 E14
1 IO_L75P_1 E13
1 IO_L74N_1 A13
1 IO_L74P_1 A12
1 IO_L73N_1 F13
1 IO_L73P_1 F12
1 IO_L72N_1 J14
1 IO_L72P_1 J13
1 IO_L71N_1 B13
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
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Advance Product Specification 1-800-255-7778 201
1 IO_L71P_1 B12
1 IO_L70N_1 C13
1 IO_L70P_1 C12
1 IO_L69N_1/VREF_1 H13
1 IO_L69P_1 H12
1 IO_L68N_1 D12
1 IO_L68P_1 D11
1 IO_L67N_1 B11
1 IO_L67P_1 B10
1 IO_L54N_1 E12
1 IO_L54P_1 E11
1 IO_L53N_1 A11
1 IO_L53P_1 A10
1 IO_L52N_1 G12
1 IO_L52P_1 G11
1 IO_L51N_1/VREF_1 K13
1 IO_L51P_1 K12
1 IO_L50N_1 C11
1 IO_L50P_1 C10
1 IO_L49N_1 B9
1 IO_L49P_1 B7
1 IO_L30N_1 F11 NC
1 IO_L30P_1 F9 NC
1 IO_L29N_1 A9 NC
1 IO_L29P_1 A8 NC
1 IO_L27N_1/VREF_1 D9 NC
1 IO_L27P_1 D8 NC
1 IO_L26N_1 J12 NC
1 IO_L26P_1 J11 NC
1 IO_L25N_1 C9 NC
1 IO_L25P_1 C8 NC
1 IO_L24N_1 E10
1 IO_L24P_1 E9
1 IO_L23N_1 H11
1 IO_L23P_1 H10
1 IO_L22N_1 A7
1 IO_L22P_1 A6
1 IO_L21N_1/VREF_1 A5
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
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1 IO_L21P_1 A4
1 IO_L20N_1 G10
1 IO_L20P_1 G9
1 IO_L19N_1 B6
1 IO_L19P_1 C5
1 IO_L06N_1 C6
1 IO_L06P_1 D6
1 IO_L05N_1 H9
1 IO_L05P_1 G8
1 IO_L04N_1 D7
1 IO_L04P_1/VREF_1 E6
1 IO_L03N_1/VRP_1 E8
1 IO_L03P_1/VRN_1 E7
1 IO_L02N_1 F8
1 IO_L02P_1 F7
1 IO_L01N_1 B5
1 IO_L01P_1 B3
2 IO_L01N_2 F5
2 IO_L01P_2 G4
2 IO_L02N_2/VRP_2 G6
2 IO_L02P_2/VRN_2 H6
2 IO_L03N_2 D3
2 IO_L03P_2/VREF_2 E4
2 IO_L04N_2 K10
2 IO_L04P_2 K9
2 IO_L05N_2 D2
2 IO_L05P_2 E3
2 IO_L06N_2 F4
2 IO_L06P_2 F3
2 IO_L19N_2 L10
2 IO_L19P_2 M10
2 IO_L20N_2 H7
2 IO_L20P_2 J8
2 IO_L21N_2 D1
2 IO_L21P_2/VREF_2 E1
2 IO_L22N_2 G5
2 IO_L22P_2 H5
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 203
2 IO_L23N_2 E2
2 IO_L23P_2 F2
2 IO_L24N_2 H4
2 IO_L24P_2 J4
2 IO_L25N_2 K8 NC
2 IO_L25P_2 L8 NC
2 IO_L27N_2 J7 NC
2 IO_L27P_2/VREF_2 K7 NC
2 IO_L43N_2 F1
2 IO_L43P_2 G1
2 IO_L44N_2 L9
2 IO_L44P_2 M9
2 IO_L45N_2 G2
2 IO_L45P_2/VREF_2 J2
2 IO_L46N_2 H3
2 IO_L46P_2 J3
2 IO_L47N_2 J6
2 IO_L47P_2 L6
2 IO_L48N_2 J5
2 IO_L48P_2 K5
2 IO_L49N_2 H1
2 IO_L49P_2 J1
2 IO_L50N_2 N10
2 IO_L50P_2 P10
2 IO_L51N_2 L7
2 IO_L51P_2/VREF_2 M7
2 IO_L52N_2 K3
2 IO_L52P_2 L3
2 IO_L53N_2 M8
2 IO_L53P_2 N8
2 IO_L54N_2 L5
2 IO_L54P_2 M5
2 IO_L67N_2 K2
2 IO_L67P_2 L2
2 IO_L68N_2 M6
2 IO_L68P_2 N6
2 IO_L69N_2 L4
2 IO_L69P_2/VREF_2 M4
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
204 1-800-255-7778 Advance Product Specification
2 IO_L70N_2 K1
2 IO_L70P_2 L1
2 IO_L71N_2 N9
2 IO_L71P_2 P9
2 IO_L72N_2 N5
2 IO_L72P_2 P5
2 IO_L73N_2 M3
2 IO_L73P_2 N3
2 IO_L74N_2 R8
2 IO_L74P_2 R9
2 IO_L75N_2 M2
2 IO_L75P_2/VREF_2 N2
2 IO_L76N_2 M1
2 IO_L76P_2 N1
2 IO_L77N_2 P7
2 IO_L77P_2 R7
2 IO_L78N_2 N4
2 IO_L78P_2 P4
2 IO_L91N_2 T8
2 IO_L91P_2 T9
2 IO_L92N_2 P6
2 IO_L92P_2 R6
2 IO_L93N_2 P2
2 IO_L93P_2/VREF_2 R2
2 IO_L94N_2 R5
2 IO_L94P_2 T5
2 IO_L95N_2 P1
2 IO_L95P_2 R1
2 IO_L96N_2 R4
2 IO_L96P_2 R3
3 IO_L96N_3 T6
3 IO_L96P_3 U5
3 IO_L95N_3 U6
3 IO_L95P_3 V6
3 IO_L94N_3 T3
3 IO_L94P_3 U3
3 IO_L93N_3/VREF_3 U1
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 205
3 IO_L93P_3 V1
3 IO_L92N_3 U8
3 IO_L92P_3 W8
3 IO_L91N_3 U2
3 IO_L91P_3 V2
3 IO_L78N_3 U7
3 IO_L78P_3 V7
3 IO_L77N_3 U4
3 IO_L77P_3 V4
3 IO_L76N_3 W1
3 IO_L76P_3 Y1
3 IO_L75N_3/VREF_3 V5
3 IO_L75P_3 W5
3 IO_L74N_3 W2
3 IO_L74P_3 Y2
3 IO_L73N_3 W6
3 IO_L73P_3 Y6
3 IO_L72N_3 Y5
3 IO_L72P_3 AA5
3 IO_L71N_3 W3
3 IO_L71P_3 Y3
3 IO_L70N_3 W4
3 IO_L70P_3 Y4
3 IO_L69N_3/VREF_3 U9
3 IO_L69P_3 V9
3 IO_L68N_3 AA1
3 IO_L68P_3 AB1
3 IO_L67N_3 Y7
3 IO_L67P_3 AA7
3 IO_L54N_3 AA6
3 IO_L54P_3 AC6
3 IO_L53N_3 AA2
3 IO_L53P_3 AB2
3 IO_L52N_3 AA4
3 IO_L52P_3 AC4
3 IO_L51N_3/VREF_3 V10
3 IO_L51P_3 W10
3 IO_L50N_3 AA3
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
206 1-800-255-7778 Advance Product Specification
3 IO_L50P_3 AB3
3 IO_L49N_3 AB5
3 IO_L49P_3 AC5
3 IO_L48N_3 W9
3 IO_L48P_3 Y9
3 IO_L47N_3 AC1
3 IO_L47P_3 AD1
3 IO_L46N_3 AC3
3 IO_L46P_3 AD3
3 IO_L45N_3/VREF_3 Y8
3 IO_L45P_3 AA8
3 IO_L44N_3 AC2
3 IO_L44P_3 AE2
3 IO_L43N_3 AB7
3 IO_L43P_3 AC7
3 IO_L27N_3/VREF_3 Y10 NC
3 IO_L27P_3 AA10 NC
3 IO_L25N_3 AE1 NC
3 IO_L25P_3 AF1 NC
3 IO_L24N_3 AF2
3 IO_L24P_3 AG2
3 IO_L23N_3 AA9
3 IO_L23P_3 AB9
3 IO_L22N_3 AD4
3 IO_L22P_3 AE4
3 IO_L21N_3/VREF_3 AD5
3 IO_L21P_3 AE5
3 IO_L20N_3 AB8
3 IO_L20P_3 AC8
3 IO_L19N_3 AG1
3 IO_L19P_3 AH1
3 IO_L06N_3 AF4
3 IO_L06P_3 AG4
3 IO_L05N_3 AB10
3 IO_L05P_3 AB11
3 IO_L04N_3 AF3
3 IO_L04P_3 AG3
3 IO_L03N_3/VREF_3 AD6
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 207
3 IO_L03P_3 AD7
3 IO_L02N_3/VRP_3 AE6
3 IO_L02P_3/VRN_3 AF5
3 IO_L01N_3 AH2
3 IO_L01P_3 AH3
4 IO_L01N_4/DOUT AD9
4 IO_L01P_4/INIT_B AD10
4 IO_L02N_4/D0 AF7
4 IO_L02P_4/D1 AG7
4 IO_L03N_4/D2/ALT_VRP_4 AK3
4 IO_L03P_4/D3/ALT_VRN_4 AJ5
4 IO_L04N_4/VREF_4 AE8
4 IO_L04P_4 AF8
4 IO_L05N_4/VRP_4 AK4
4 IO_L05P_4/VRN_4 AK5
4 IO_L06N_4 AH6
4 IO_L06P_4 AH7
4 IO_L19N_4 AC10
4 IO_L19P_4 AC11
4 IO_L20N_4 AE9
4 IO_L20P_4 AE10
4 IO_L21N_4 AL4
4 IO_L21P_4/VREF_4 AL5
4 IO_L22N_4 AB12
4 IO_L22P_4 AB13
4 IO_L23N_4 AJ6
4 IO_L23P_4 AJ8
4 IO_L24N_4 AK6
4 IO_L24P_4 AK7
4 IO_L25N_4 AG8 NC
4 IO_L25P_4 AG9 NC
4 IO_L26N_4 AF9 NC
4 IO_L26P_4 AF11 NC
4 IO_L27N_4 AH8 NC
4 IO_L27P_4/VREF_4 AH9 NC
4 IO_L28N_4 AD11 NC
4 IO_L28P_4 AD12 NC
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
208 1-800-255-7778 Advance Product Specification
4 IO_L29N_4 AL6 NC
4 IO_L29P_4 AL7 NC
4 IO_L30N_4 AJ9 NC
4 IO_L30P_4 AJ10 NC
4 IO_L49N_4 AE11
4 IO_L49P_4 AE12
4 IO_L50N_4 AG10
4 IO_L50P_4 AG11
4 IO_L51N_4 AL8
4 IO_L51P_4/VREF_4 AL9
4 IO_L52N_4 AF12
4 IO_L52P_4 AF13
4 IO_L53N_4 AK9
4 IO_L53P_4 AK10
4 IO_L54N_4 AH11
4 IO_L54P_4 AH12
4 IO_L67N_4 AC12
4 IO_L67P_4 AC13
4 IO_L68N_4 AG12
4 IO_L68P_4 AG13
4 IO_L69N_4 AL10
4 IO_L69P_4/VREF_4 AL11
4 IO_L70N_4 AD13
4 IO_L70P_4 AD15
4 IO_L71N_4 AJ11
4 IO_L71P_4 AJ12
4 IO_L72N_4 AK11
4 IO_L72P_4 AK12
4 IO_L73N_4 AE14
4 IO_L73P_4 AE15
4 IO_L74N_4 AF14
4 IO_L74P_4 AF15
4 IO_L75N_4 AL12
4 IO_L75P_4/VREF_4 AL13
4 IO_L76N_4 AB14
4 IO_L76P_4 AC14
4 IO_L77N_4 AH13
4 IO_L77P_4 AH14
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 209
4 IO_L78N_4 AJ13
4 IO_L78P_4 AK13
4 IO_L91N_4/VREF_4 AC15
4 IO_L91P_4 AC16
4 IO_L92N_4 AG14
4 IO_L92P_4 AG15
4 IO_L93N_4 AK14
4 IO_L93P_4 AK15
4 IO_L94N_4/VREF_4 AF16
4 IO_L94P_4 AG16
4 IO_L95N_4/GCLK3S AL14
4 IO_L95P_4/GCLK2P AL15
4 IO_L96N_4/GCLK1S AH15
4 IO_L96P_4/GCLK0P AJ15
5 IO_L96N_5/GCLK7S AJ16
5 IO_L96P_5/GCLK6P AH17
5 IO_L95N_5/GCLK5S AD16
5 IO_L95P_5/GCLK4P AD17
5 IO_L94N_5 AL17
5 IO_L94P_5/VREF_5 AL18
5 IO_L93N_5 AG17
5 IO_L93P_5 AF17
5 IO_L92N_5 AE17
5 IO_L92P_5 AE18
5 IO_L91N_5 AK17
5 IO_L91P_5/VREF_5 AJ17
5 IO_L78N_5 AK18
5 IO_L78P_5 AK19
5 IO_L77N_5 AC17
5 IO_L77P_5 AB18
5 IO_L76N_5 AH18
5 IO_L76P_5 AH19
5 IO_L75N_5/VREF_5 AL19
5 IO_L75P_5 AL20
5 IO_L74N_5 AC18
5 IO_L74P_5 AC19
5 IO_L73N_5 AJ19
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
210 1-800-255-7778 Advance Product Specification
5 IO_L73P_5 AJ20
5 IO_L72N_5 AG18
5 IO_L72P_5 AG19
5 IO_L71N_5 AF18
5 IO_L71P_5 AF19
5 IO_L70N_5 AK20
5 IO_L70P_5 AK21
5 IO_L69N_5/VREF_5 AH20
5 IO_L69P_5 AH21
5 IO_L68N_5 AD19
5 IO_L68P_5 AD20
5 IO_L67N_5 AL21
5 IO_L67P_5 AL22
5 IO_L54N_5 AG20
5 IO_L54P_5 AG21
5 IO_L53N_5 AB19
5 IO_L53P_5 AB20
5 IO_L52N_5 AJ21
5 IO_L52P_5 AJ22
5 IO_L51N_5/VREF_5 AF20
5 IO_L51P_5 AF21
5 IO_L50N_5 AE20
5 IO_L50P_5 AE21
5 IO_L49N_5 AK22
5 IO_L49P_5 AK23
5 IO_L30N_5 AJ23 NC
5 IO_L30P_5 AJ24 NC
5 IO_L29N_5 AC20 NC
5 IO_L29P_5 AC21 NC
5 IO_L28N_5 AL23 NC
5 IO_L28P_5 AL24 NC
5 IO_L27N_5/VREF_5 AL25 NC
5 IO_L27P_5 AL26 NC
5 IO_L26N_5 AD21 NC
5 IO_L26P_5 AD22 NC
5 IO_L25N_5 AH23 NC
5 IO_L25P_5 AH24 NC
5 IO_L24N_5 AG22
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 211
5 IO_L24P_5 AG23
5 IO_L23N_5 AE22
5 IO_L23P_5 AE23
5 IO_L22N_5 AK25
5 IO_L22P_5 AK26
5 IO_L21N_5/VREF_5 AH25
5 IO_L21P_5 AG25
5 IO_L20N_5 AB21
5 IO_L20P_5 AC22
5 IO_L19N_5 AL27
5 IO_L19P_5 AL28
5 IO_L06N_5 AK27
5 IO_L06P_5 AJ27
5 IO_L05N_5/VRP_5 AD23
5 IO_L05P_5/VRN_5 AE24
5 IO_L04N_5 AJ26
5 IO_L04P_5/VREF_5 AH26
5 IO_L03N_5/D4/ALT_VRP_5 AF23
5 IO_L03P_5/D5/ALT_VRN_5 AF24
5 IO_L02N_5/D6 AG24
5 IO_L02P_5/D7 AF25
5 IO_L01N_5/RDWR_B AK28
5 IO_L01P_5/CS_B AK29
6 IO_L01P_6 AF27
6 IO_L01N_6 AF28
6 IO_L02P_6/VRN_6 AE26
6 IO_L02N_6/VRP_6 AE27
6 IO_L03P_6 AH29
6 IO_L03N_6/VREF_6 AH30
6 IO_L04P_6 AB22
6 IO_L04N_6 AB23
6 IO_L05P_6 AG28
6 IO_L05N_6 AG29
6 IO_L06P_6 AH31
6 IO_L06N_6 AG31
6 IO_L19P_6 AA22
6 IO_L19N_6 Y22
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
212 1-800-255-7778 Advance Product Specification
6 IO_L20P_6 AD25
6 IO_L20N_6 AC24
6 IO_L21P_6 AG30
6 IO_L21N_6/VREF_6 AF30
6 IO_L22P_6 AD26
6 IO_L22N_6 AC26
6 IO_L23P_6 AF29
6 IO_L23N_6 AD29
6 IO_L24P_6 AE28
6 IO_L24N_6 AD28
6 IO_L25P_6 AB24 NC
6 IO_L25N_6 AA24 NC
6 IO_L27P_6 AC25 NC
6 IO_L27N_6/VREF_6 AB25 NC
6 IO_L43P_6 AF31
6 IO_L43N_6 AE31
6 IO_L44P_6 AA23
6 IO_L44N_6 Y23
6 IO_L45P_6 AE30
6 IO_L45N_6/VREF_6 AC30
6 IO_L46P_6 AC28
6 IO_L46N_6 AA28
6 IO_L47P_6 AD27
6 IO_L47N_6 AC27
6 IO_L48P_6 AA25
6 IO_L48N_6 Y25
6 IO_L49P_6 AC29
6 IO_L49N_6 AB29
6 IO_L50P_6 AB27
6 IO_L50N_6 AA27
6 IO_L51P_6 AA26
6 IO_L51N_6/VREF_6 Y26
6 IO_L52P_6 AD31
6 IO_L52N_6 AC31
6 IO_L53P_6 W22
6 IO_L53N_6 V22
6 IO_L54P_6 Y27
6 IO_L54N_6 W27
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 213
6 IO_L67P_6 AB30
6 IO_L67N_6 AA30
6 IO_L68P_6 W26
6 IO_L68N_6 V26
6 IO_L69P_6 AB31
6 IO_L69N_6/VREF_6 AA31
6 IO_L70P_6 AA29
6 IO_L70N_6 Y29
6 IO_L71P_6 Y24
6 IO_L71N_6 W24
6 IO_L72P_6 V25
6 IO_L72N_6 U25
6 IO_L73P_6 Y28
6 IO_L73N_6 W28
6 IO_L74P_6 W23
6 IO_L74N_6 V23
6 IO_L75P_6 Y30
6 IO_L75N_6/VREF_6 W30
6 IO_L76P_6 Y31
6 IO_L76N_6 W31
6 IO_L77P_6 V27
6 IO_L77N_6 U27
6 IO_L78P_6 W29
6 IO_L78N_6 U29
6 IO_L91P_6 U23
6 IO_L91N_6 T23
6 IO_L92P_6 U26
6 IO_L92N_6 T26
6 IO_L93P_6 V28
6 IO_L93N_6/VREF_6 U28
6 IO_L94P_6 U24
6 IO_L94N_6 T24
6 IO_L95P_6 V30
6 IO_L95N_6 U30
6 IO_L96P_6 V31
6 IO_L96N_6 U31
7 IO_L96P_7 T27
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
214 1-800-255-7778 Advance Product Specification
7 IO_L96N_7 R27
7 IO_L95P_7 R24
7 IO_L95N_7 N24
7 IO_L94P_7 T29
7 IO_L94N_7 R29
7 IO_L93P_7/VREF_7 R31
7 IO_L93N_7 P31
7 IO_L92P_7 R26
7 IO_L92N_7 P26
7 IO_L91P_7 R30
7 IO_L91N_7 P30
7 IO_L78P_7 R25
7 IO_L78N_7 P25
7 IO_L77P_7 R28
7 IO_L77N_7 P28
7 IO_L76P_7 N31
7 IO_L76N_7 M31
7 IO_L75P_7/VREF_7 R23
7 IO_L75N_7 P23
7 IO_L74P_7 N30
7 IO_L74N_7 M30
7 IO_L73P_7 P27
7 IO_L73N_7 N27
7 IO_L72P_7 P22
7 IO_L72N_7 N22
7 IO_L71P_7 N29
7 IO_L71N_7 M29
7 IO_L70P_7 N28
7 IO_L70N_7 M28
7 IO_L69P_7/VREF_7 N26
7 IO_L69N_7 M26
7 IO_L68P_7 L31
7 IO_L68N_7 K31
7 IO_L67P_7 M27
7 IO_L67N_7 L27
7 IO_L54P_7 N23
7 IO_L54N_7 M23
7 IO_L53P_7 L30
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 215
7 IO_L53N_7 K30
7 IO_L52P_7 L28
7 IO_L52N_7 J28
7 IO_L51P_7/VREF_7 M24
7 IO_L51N_7 L24
7 IO_L50P_7 L29
7 IO_L50N_7 K29
7 IO_L49P_7 M25
7 IO_L49N_7 L25
7 IO_L48P_7 L26
7 IO_L48N_7 J26
7 IO_L47P_7 J31
7 IO_L47N_7 H31
7 IO_L46P_7 J29
7 IO_L46N_7 H29
7 IO_L45P_7/VREF_7 M22
7 IO_L45N_7 L22
7 IO_L44P_7 J30
7 IO_L44N_7 G30
7 IO_L43P_7 K27
7 IO_L43N_7 J27
7 IO_L27P_7/VREF_7 L23 NC
7 IO_L27N_7 K23 NC
7 IO_L25P_7 G31 NC
7 IO_L25N_7 F31 NC
7 IO_L24P_7 F30
7 IO_L24N_7 E30
7 IO_L23P_7 K25
7 IO_L23N_7 J25
7 IO_L22P_7 H28
7 IO_L22N_7 G28
7 IO_L21P_7/VREF_7 H27
7 IO_L21N_7 G27
7 IO_L20P_7 K24
7 IO_L20N_7 J24
7 IO_L19P_7 E31
7 IO_L19N_7 D31
7 IO_L06P_7 F28
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
216 1-800-255-7778 Advance Product Specification
7 IO_L06N_7 E28
7 IO_L05P_7 K22
7 IO_L05N_7 K21
7 IO_L04P_7 F29
7 IO_L04N_7 E29
7 IO_L03P_7/VREF_7 H26
7 IO_L03N_7 H25
7 IO_L02P_7/VRN_7 G26
7 IO_L02N_7/VRP_7 F27
7 IO_L01P_7 D30
7 IO_L01N_7 D29
0 VCCO_0 C18
0 VCCO_0 C25
0 VCCO_0 F22
0 VCCO_0 H18
0 VCCO_0 L17
0 VCCO_0 L18
0 VCCO_0 L19
0 VCCO_0 L20
0 VCCO_0 M17
0 VCCO_0 M18
0 VCCO_0 M19
1 VCCO_1 C7
1 VCCO_1 C14
1 VCCO_1 F10
1 VCCO_1 H14
1 VCCO_1 L12
1 VCCO_1 L13
1 VCCO_1 L14
1 VCCO_1 L15
1 VCCO_1 M13
1 VCCO_1 M14
1 VCCO_1 M15
2 VCCO_2 G3
2 VCCO_2 K6
2 VCCO_2 M11
2 VCCO_2 N11
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
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Advance Product Specification 1-800-255-7778 217
2 VCCO_2 N12
2 VCCO_2 P3
2 VCCO_2 P8
2 VCCO_2 P11
2 VCCO_2 P12
2 VCCO_2 R11
2 VCCO_2 R12
3 VCCO_3 U11
3 VCCO_3 U12
3 VCCO_3 V3
3 VCCO_3 V8
3 VCCO_3 V11
3 VCCO_3 V12
3 VCCO_3 W11
3 VCCO_3 W12
3 VCCO_3 Y11
3 VCCO_3 AB6
3 VCCO_3 AE3
4 VCCO_4 Y13
4 VCCO_4 Y14
4 VCCO_4 Y15
4 VCCO_4 AA12
4 VCCO_4 AA13
4 VCCO_4 AA14
4 VCCO_4 AA15
4 VCCO_4 AD14
4 VCCO_4 AF10
4 VCCO_4 AJ7
4 VCCO_4 AJ14
5 VCCO_5 Y17
5 VCCO_5 Y18
5 VCCO_5 Y19
5 VCCO_5 AA17
5 VCCO_5 AA18
5 VCCO_5 AA19
5 VCCO_5 AA20
5 VCCO_5 AD18
5 VCCO_5 AF22
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
218 1-800-255-7778 Advance Product Specification
5 VCCO_5 AJ18
5 VCCO_5 AJ25
6 VCCO_6 U20
6 VCCO_6 U21
6 VCCO_6 V20
6 VCCO_6 V21
6 VCCO_6 V24
6 VCCO_6 V29
6 VCCO_6 W20
6 VCCO_6 W21
6 VCCO_6 Y21
6 VCCO_6 AB26
6 VCCO_6 AE29
7 VCCO_7 G29
7 VCCO_7 K26
7 VCCO_7 M21
7 VCCO_7 N20
7 VCCO_7 N21
7 VCCO_7 P20
7 VCCO_7 P21
7 VCCO_7 P24
7 VCCO_7 P29
7 VCCO_7 R20
7 VCCO_7 R21
NA CCLK AJ4
NA PROG_B D27
NA DONE AG6
NA M0 AH27
NA M1 AJ28
NA M2 AG26
NA HSWAP_EN E26
NA TCK K11
NA TDI C28
NA TDO C4
NA TMS J10
NA PWRDWN_B AH5
NA DXN F25
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 219
NA DXP B28
NA VBATT D5
NA RSVD B4
NA VCCAUX B16
NA VCCAUX C2
NA VCCAUX C30
NA VCCAUX T2
NA VCCAUX T30
NA VCCAUX AJ2
NA VCCAUX AJ30
NA VCCAUX AK16
NA VCCINT K15
NA VCCINT K17
NA VCCINT L11
NA VCCINT L16
NA VCCINT L21
NA VCCINT M12
NA VCCINT M16
NA VCCINT M20
NA VCCINT N13
NA VCCINT N14
NA VCCINT N15
NA VCCINT N16
NA VCCINT N17
NA VCCINT N18
NA VCCINT N19
NA VCCINT P13
NA VCCINT P19
NA VCCINT R10
NA VCCINT R13
NA VCCINT R19
NA VCCINT R22
NA VCCINT T11
NA VCCINT T12
NA VCCINT T13
NA VCCINT T19
NA VCCINT T20
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
220 1-800-255-7778 Advance Product Specification
NA VCCINT T21
NA VCCINT U10
NA VCCINT U13
NA VCCINT U19
NA VCCINT U22
NA VCCINT V13
NA VCCINT V19
NA VCCINT W13
NA VCCINT W14
NA VCCINT W15
NA VCCINT W16
NA VCCINT W17
NA VCCINT W18
NA VCCINT W19
NA VCCINT Y12
NA VCCINT Y16
NA VCCINT Y20
NA VCCINT AA11
NA VCCINT AA16
NA VCCINT AA21
NA VCCINT AB15
NA VCCINT AB17
NA GND A2
NA GND A3
NA GND A16
NA GND A29
NA GND A30
NA GND B1
NA GND B2
NA GND B8
NA GND B24
NA GND B30
NA GND B31
NA GND C1
NA GND C3
NA GND C29
NA GND C31
NA GND D4
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 221
NA GND D10
NA GND D16
NA GND D22
NA GND D28
NA GND E5
NA GND E27
NA GND F6
NA GND F26
NA GND G7
NA GND G13
NA GND G16
NA GND G19
NA GND G25
NA GND H2
NA GND H8
NA GND H24
NA GND H30
NA GND J9
NA GND J23
NA GND K4
NA GND K16
NA GND K28
NA GND N7
NA GND N25
NA GND P14
NA GND P15
NA GND P16
NA GND P17
NA GND P18
NA GND R14
NA GND R15
NA GND R16
NA GND R17
NA GND R18
NA GND T1
NA GND T4
NA GND T7
NA GND T10
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information R
Module 4 of 4 www.xilinx.com DS031-4 (v1.6) November 7, 2001
222 1-800-255-7778 Advance Product Specification
NA GND T14
NA GND T15
NA GND T16
NA GND T17
NA GND T18
NA GND T22
NA GND T25
NA GND T28
NA GND T31
NA GND U14
NA GND U15
NA GND U16
NA GND U17
NA GND U18
NA GND V14
NA GND V15
NA GND V16
NA GND V17
NA GND V18
NA GND W7
NA GND W25
NA GND AB4
NA GND AB16
NA GND AB28
NA GND AC9
NA GND AC23
NA GND AD2
NA GND AD8
NA GND AD24
NA GND AD30
NA GND AE7
NA GND AE13
NA GND AE16
NA GND AE19
NA GND AE25
NA GND AF6
NA GND AF26
NA GND AG5
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 223
NA GND AG27
NA GND AH4
NA GND AH10
NA GND AH16
NA GND AH22
NA GND AH28
NA GND AJ1
NA GND AJ3
NA GND AJ29
NA GND AJ31
NA GND AK1
NA GND AK2
NA GND AK8
NA GND AK24
NA GND AK30
NA GND AK31
NA GND AL2
NA GND AL3
NA GND AL16
NA GND AL29
NA GND AL30
Table 14: BF957 — XC2V2000, XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank Pin Description Pin Number No Connect in XC2V2000
Virtex-II 1.5V Field-Programmable Gate Arrays Pinout Information
R
DS031-4 (v1.6) November 7, 2001 www.xilinx.com Module 4 of 4
Advance Product Specification 1-800-255-7778 225
Revision History
This section records the change history for this module of the data sheet.
Virtex-II Data Sheet
The Virtex-II Data Sheet contains the following modules:
•DS031-1, Virtex-II 1.5V FPGAs: Introduction and
Ordering Information (Module 1)
•DS031-2, Virtex-II 1.5V FPGAs: Functional Description
(Module 2)
•DS031-3, Virtex-II 1.5V FPGAs: DC and Switching
Characteristics (Module 3)
•DS031-4, Virtex-II 1.5V FPGAs: Pinout Tables
(Module 4)
Date Version Revision
11/07/00 1.0 Early access draft.
11/22/00 1.1 Initial Xilinx release. Made the following corrections:
CS144 package - Table 5 on page 5:
•Added missing pin D10 in Bank 1.
•Changed dedicated pins A2 and B2 to RSVD (from DXN and DXP).
FG256 package - Table 6 on page 10:
•Changed dedicated pins A3 and A4 to RSVD (from DXN and DXP).
FG896 package - Table 11 on page 94:
•Corrected pin AG1 in Bank 4 to be AG12.
FF1152 package - Table 12 on page 120:
•Corrected pin Y3 in Bank 6 to be Y32.
12/19/00 1.2 Reverse designations were fixed for pins in every package.
01/25/01 1.3 The data sheet was divided into four modules (per the current style standard). DXN
and DXP pin information was added for the CS144 package (Table 5) and the FG256
package (Table 6).
02/07/01 1.4 DXN and DXP pin information was changed back to RSVD for the CS144 package
(Tabl e 5 ) and the FG256 package (Table 6).
04/02/01 1.5 •ALT_VRN and ALT_VRP pin information was added for each package.
•Table 8 on page 34 – added No Connect designations for the XC2V1500 device
in the FG676 package.
•Reverted to traditional double-column format.
11/07/01 1.6 •Updated list of devices supported in the FF1152, FF1517, and BF957 packages.
